SCLS005D − MARCH 1984 − REVISED AUGUST 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DOperating Voltage Range of 4.5 V to 5.5 V
DHigh-Current 3-State True Outputs Can
Drive Up To 15 LSTTL Loads
DLow Power Consumption, 80-µA Max ICC
DTypical tpd = 22 ns
D±6-mA Output Drive at 5 V
DLow Input Current of 1 µA Max
DInputs Are TTL-Voltage Compatible
DEight D-Type Flip-Flops in a Single Package
DFull Parallel Access for Loading
description/ordering information
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’HCT374 devices are
edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels that were set up at the
data (D) inputs.
An output-enable (OE) input places the eight
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the
bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER TOP-SIDE
MARKING
PDIP − N Tube of 20 SN74HCT374N SN74HCT374N
SOIC − DW
Tube of 25 SN74HCT374DW
HCT374
SOIC − DW Reel of 2000 SN74HCT374DWR HCT374
−40°C to 85°C
SOP − NS Reel of 2000 SN74HCT374NSR HCT374
−40°C to 85°CSSOP − DB Reel of 2000 SN74HCT374DBR HT374
Tube of 70 SN74HCT374PW
TSSOP − PW Reel of 2000 SN74HCT374PWR HT374
TSSOP − PW
Reel of 250 SN74HCT374PWT
HT374
CDIP − J Tube of 20 SNJ54HCT374J SNJ54HCT374J
−55°C to 125°CCFP − W Tube of 85 SNJ54HCT374W SNJ54HCT374W
−55 C to 125 C
LCCC − FK Tube of 55 SNJ54HCT374FK SNJ54HCT374FK
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
3212019
910111213
4
5
6
7
8
18
17
16
15
14
8D
7D
7Q
6Q
6D
2D
2Q
3Q
3D
4D
1D
1Q
OE
5Q
5D V
8Q
4Q
GND
CLK
SN54HCT374 . . . FK PACKAGE
(TOP VIEW)
CC
SN54HCT374 ...J OR W PACKAGE
SN74HCT374 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
VCC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
Copyright 2003, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! " #$%! " &$'(#! )!%*
)$#!" # ! "&%##!" &% !+% !%" %," "!$%!"
"!)) -!.* )$#! &#%""/ )%" ! %#%""(. #($)%
!%"!/ (( &%!%"*
&)$#!" #&(! ! 01 (( &%!%" % !%"!%)
$(%"" !+%-"% !%)* (( !+% &)$#!" &)$#!
&#%""/ )%" ! %#%""(. #($)% !%"!/ (( &%!%"*
SCLS005D − MARCH 1984 − REVISED AUGUST 2003
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description/ordering information (continued)
OE does not af fect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLK D
OUTPUT
Q
L↑H H
L↑LL
LH or L X Q0
H X X Z
logic diagram (positive logic)
OE
To Seven Other Channels
1
11
32
CLK
1D
C1
1D 1Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 69°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 60°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
SCLS005D − MARCH 1984 − REVISED AUGUST 2003
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 3)
SN54HCT374 SN74HCT374
UNIT
MIN NOM MAX MIN NOM MAX
UNIT
VCC Supply voltage 4.5 5 5.5 4.5 5 5.5 V
VIH High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
VIL Low-level input voltage VCC = 4.5 V to 5.5 V 0.8 0.8 V
VIInput voltage 0 VCC 0 VCC V
VOOutput voltage 0 VCC 0 VCC V
∆t/∆vInput transition rise/fall time 500 500 ns
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
TA = 25°C SN54HCT374 SN74HCT374
UNIT
PARAMETER
TEST CONDITIONS
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
VOH
VI = VIH or VIL
IOH = −20 µA
4.5 V
4.4 4.499 4.4 4.4
V
VOH VI = VIH or VIL IOH = −6 mA 4.5 V 3.98 4.3 3.7 3.84 V
VOL
VI = VIH or VIL
IOL = 20 µA
4.5 V
0.001 0.1 0.1 0.1
V
VOL VI = VIH or VIL IOL = 6 mA 4.5 V 0.17 0.26 0.4 0.33 V
IIVI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
IOZ VO = VCC or 0 5.5 V ±0.01 ±0.5 ±10 ±5µA
ICC VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
∆ICC†One input at 0.5 V or 2.4 V,
Other inputs at 0 or VCC 5.5 V 1.4 2.4 3 2.9 mA
Ci4.5 V
to 5.5 V 3 10 10 10 pF
†This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
VCC
TA = 25°C SN54HCT374 SN74HCT374
UNIT
V
CC MIN MAX MIN MAX MIN MAX
UNIT
fclock
Clock frequency
4.5 V 31 21 25
MHz
fclock Clock frequency 5.5 V 36 23 28 MHz
tw
Pulse duration, CLK high or low
4.5 V 16 24 20
ns
twPulse duration, CLK high or low 5.5 V 14 22 18 ns
tsu
Setup time, data before CLK↑
4.5 V 20 30 25
ns
tsu Setup time, data before CLK↑5.5 V 17 27 23 ns
th
Hold time, data after CLK↑
4.5 V 10 10 10
ns
t
h
Hold time, data after CLK↑
5.5 V 10 10 10
ns
SCLS005D − MARCH 1984 − REVISED AUGUST 2003
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HCT374 SN74HCT374
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
fmax
4.5 V 31 36 21 25
MHz
fmax 5.5 V 36 40 23 28 MHz
tpd
CLK
Any Q
4.5 V 30 36 54 45
ns
tpd CLK Any Q 5.5 V 25 32 49 41 ns
ten
OE
Any Q
4.5 V 26 30 45 38
ns
ten OE Any Q 5.5 V 23 27 41 34 ns
tdis
OE
Any Q
4.5 V 23 30 45 38
ns
tdis OE Any Q 5.5 V 22 27 41 34 ns
tt
Any Q
4.5 V 10 12 18 15
ns
t
t
Any Q
5.5 V 911 16 14
ns
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
PARAMETER
FROM
TO
VCC
TA = 25°C SN54HCT374 SN74HCT374
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
V
CC MIN TYP MAX MIN MAX MIN MAX
UNIT
tpd
CLK
Any Q
4.5 V 40 46 69 58
ns
tpd CLK Any Q 5.5 V 35 41 62 52 ns
ten
OE
Any Q
4.5 V 34 40 60 50
ns
ten OE Any Q 5.5 V 29 36 54 45 ns
tt
Any Q
4.5 V 18 42 63 53
ns
t
t
Any Q
5.5 V 16 38 57 48
ns
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance per flip-flop No load 85 pF
SCLS005D − MARCH 1984 − REVISED AUGUST 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
1.3 V
10%
90%
3 V
≈VCC
VOL
0 V
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
1.3 V
tPZL tPLZ
VOH
≈0 V
1.3 V
1.3 V
tPZH tPHZ
Output
Waveform 2
(See Note B)
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
th
tsu
1.3 V
1.3 V1.3 V 0.3 V0.3 V 2.7 V 2.7 V
3 V
3 V
0 V
0 V
trtf
Reference
Input
Data
Input
1.3 V
High-Level
Pulse 1.3 V 3 V
0 V
1.3 V 1.3 V
3 V
0 V
tw
Low-Level
Pulse
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
1.3 V1.3 V 10%10% 90% 90%
3 V
VOH
VOL
0 V
trtf
Input
In-Phase
Output
1.3 V
tPLH tPHL
1.3 V 1.3 V
10% 10% 90%90% VOH
VOL
tr
tf
tPHL tPLH
Out-of-
Phase
Output
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
Test
Point
From Output
Under Test
RL
V
CC
S1
S2
LOAD CIRCUIT
PARAMETER CL
tPZH
tpd or tt
tdis
ten tPZL
tPHZ
tPLZ
1 kΩ
1 kΩ
50 pF
or
150 pF
50 pF
Open Closed
RLS1
Closed Open
S2
Open Closed
Closed Open
50 pF
or
150 pF Open Open−−
CL
(see Note A)
NOTES: A. CL includes probe and test-fixture capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, fmax is measured when the input duty cycle is 50%.
E. The outputs are measured one at a time with one input transition per measurement.
F. tPLZ and tPHZ are the same as tdis.
G. tPZL and tPZH are the same as ten.
H. tPLH and tPHL are the same as tpd.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
5962-8550701VRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
5962-8550701VSA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
85507012A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8550701RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
JM38510/65652BRA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN54HCT374J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
SN74HCT374DBR ACTIVE SSOP DB 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374DBRE4 ACTIVE SSOP DB 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374DBRG4 ACTIVE SSOP DB 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374DW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374DWE4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374DWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HCT374N3 OBSOLETE PDIP N 20 TBD Call TI Call TI
SN74HCT374NE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN74HCT374NSR ACTIVE SO NS 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374NSRE4 ACTIVE SO NS 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374NSRG4 ACTIVE SO NS 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374PW ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374PWE4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374PWG4 ACTIVE TSSOP PW 20 70 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374PWR ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374PWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374PWRG4 ACTIVE TSSOP PW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374PWT ACTIVE TSSOP PW 20 250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
no Sb/Br)
SN74HCT374PWTE4 ACTIVE TSSOP PW 20 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN74HCT374PWTG4 ACTIVE TSSOP PW 20 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SNJ54HCT374FK ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
SNJ54HCT374J ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 15-Oct-2009
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74HCT374DBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
SN74HCT374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN74HCT374DWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1
SN74HCT374NSR SO NS 20 2000 330.0 24.4 8.2 13.0 2.5 12.0 24.0 Q1
SN74HCT374PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Nov-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74HCT374DBR SSOP DB 20 2000 346.0 346.0 33.0
SN74HCT374DWR SOIC DW 20 2000 346.0 346.0 41.0
SN74HCT374DWR SOIC DW 20 2000 346.0 346.0 41.0
SN74HCT374NSR SO NS 20 2000 346.0 346.0 41.0
SN74HCT374PWR TSSOP PW 20 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 10-Nov-2008
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°–ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65 M
0,10
0,10
0,25
0,50
0,75
0,15 NOM
Gage Plane
28
9,80
9,60
24
7,90
7,70
2016
6,60
6,40
4040064/F 01/97
0,30
6,60
6,20
80,19
4,30
4,50
7
0,15
14
A
1
1,20 MAX
14
5,10
4,90
8
3,10
2,90
A MAX
A MIN
DIM PINS **
0,05
4,90
5,10
Seating Plane
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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