Rev. 1.0/Nov. 2009 5
H5GQ1H24AFR
FEATURES
•Singleendedinterfacefordata,addressandcommand
•Quarterdata‐ratedifferentialclockinputsCK/CK#for
ADR/CMD
•Twohalfdata‐ratedifferentialclockinputsWCK/
WCK#,eachassociatedwithtwodatabytes(DQ,DBI#,
EDC)
•DoubleDataRate(DDR)data(WCK)
•SingleDataRate(SDR)command(CK)
•DoubleDataRate(DDR)addressing(CK)
•16internalbanks
•4bankgroupsfortCCDL=3tCK
•8nprefetcharchitecture:256bitperarrayreadorwrite
access
•Burstlength:8only
• ProgrammableCASlatency:5to20tCK
• ProgrammableWRITElatency:1to7tCK
•WRITEDatamaskfunctionviaaddressbus(single/
doublebytemask)
• Databusinversion(DBI)&addressbusinversion
(ABI)
• Input/outputPLLon/offmode
• Addresstraining:addressinputmonitoringbyDQ
pins
• WCK2CKclocktrainingwithphaseinformationby
EDCpins
• DatareadandwritetrainingviaREADFIFO
•READFIFOpatternpreloadbyLDFFcommand
•DirectwritedataloadtoREADFIFObyWRTR
command
•ConsecutivereadofREADFIFObyRDTRcommand
• Read/Writedatatransmissionintegritysecuredby
cyclicredundancycheck(CRC‐8)
• READ/WRITEEDCon/offmode
• ProgrammableEDCholdpatternforCDR
• ProgrammableCRCREADlatency=0to3tCK
• ProgrammableCRCWRITElatency=7to14tCK
•LowPowermodes
•RDQSmodeonEDCpin
•Optionalon‐chiptemperaturesensorwithread‐out
•Auto&selfrefreshmodes
•Autoprechargeoptionforeachburstaccess
• 32ms,autorefresh(8kcycles)
• Temperaturesensorcontrolledselfrefreshrate
•On‐dietermination(ODT);nominalvaluesof60ohm
and120ohm
•Pseudoopendrain(POD‐15)compatibleoutputs(40
ohmpulldown,60ohmpullup)
•ODTandoutputdrivestrengthauto‐calibrationwith
externalresistorZQpin(120ohm)
• Programmableterminationanddriverstrengthoffsets
• SelectableexternalorinternalVREFfordatainputs;
programmableoffsetsforinternalVREF
• SeparateexternalVREFforaddress/commandinputs
•VendorID,FIFOdepthandDensityinfofieldsfor
identification
• x32/x16modeconfigurationsetatpower‐upwithEDC
pin
•MirrorfunctionwithMFpin
• BoundaryscanfunctionwithSENpin
•1.6V/1.5V+/‐0.045Vsupplyfordeviceoperation
(VDD)
•1.6V/1.5V+/‐0.045VsupplyforI/Ointerface(VDDQ)
• 170ballBGApackage
FUNCTIONAL DESCRIPTION
TheGDDR5SGRAMisahighspeeddynamic
random‐accessmemorydesignedforapplications
requiringhighbandwidth.GDDR5devicescontain
thefollowingnumberofbits:
1Gbhas1,073,741,824bitsandsixteenbanks
TheGDDR5SGRAMusesa8nprefetch
architectureandDDRinterfacetoachievehigh‐
speedoperation.Thedevicecanbeconfiguredto
operateinx32modeorx16(clamshell)mode.The
modeisdetectedduringdeviceinitialization.The
GDDR5interfacetransferstwo32bitwidedata
wordsperWCKclockcycleto/fromtheI/Opins.
Correspondingtothe8n‐prefetchasinglewriteor
readaccessconsistsofa256bitwide,twoCKclock
cycledatatransferattheinternalmemorycoreand
eightcorresponding32bitwideone‐halfWCKclock
cycledatatransfersattheI/Opins.
TheGDDR5SGRAMoperatesfromadifferential
clockCKandCK#.Commandsareregisteredat
everyrisingedgeofCK.Addressesareregisteredat
everyrisingedgeofCKandeveryrisingedgeof
CK#.
GDDR5replacesthepulsedstrobes(WDQS&
RDQS)usedinpreviousDRAMssuchasGDDR4
withafreerunningdifferentialforwardedclock
(WCK/WCK#)withbothinputandoutputdata
registeredanddrivenrespectivelyatbothedgesof
theforwardedWCK.
ReadandwriteaccessestotheGDDR5SGRAMare
burstoriented;anaccessstartsataselectedlocation
andconsistsofatotalofeightdatawords.Accesses
beginwiththeregistrationofanACTIVEcommand,
whichisthenfollowedbyaREADorWRITE
command.Theaddressbitsregisteredcoincident
withtheACTIVEcommandandthenextrisingCK#
edgeareusedtoselectthebankandtherowtobe
accessed.Theaddressbitsregisteredcoincident
withtheREADorWRITEcommandandthenext
risingCK#edgeareusedtoselectthebankandthe
columnlocationfortheburstaccess.