32 Megabit High Speed CMOS SRAM
DPS1MK32MKV3
DESCRIPTION:
The DPS1MK32MKV3 ‘’VERSA-STACK’’ module is a
revolutionary new high speed memory subsystem using
Dense-Pac Microsystems’ ceramic Stackable Leadless Chip
Carriers (SLCC) mounted on a co-fired ceramic substrate. It offers
32 Megabits of SRAM in a package envelope of 1.190 x 1.190 x
0.360 inches.
The DPS1MK32MKV3 contains eight individual 512K x 8 SRAMs,
packaged in their own hermetically sealed SLCCs making the
module suitable for commercial, industrial and military
applications.
By using SLCCs, the ‘’Versa-Stack’’ family of modules offers a
higher board density of memory than available with conventional
through-hole, surface mount, module, or hybrid techniques.
FEATURES:
•Organizations Available:
READ: 1Meg x 32
WRITE: 1Meg x 32, 2 Meg x 16
or 4 Meg x 8
•Access Times:
20, 25, 35, 45ns
•Fully Static Operation
- No clock or refresh required
•Low Power Dissipation
•Single +5V Power Supply,
±10% Tolerance
•TTL Compatible
•Common Data Inputs and Outputs
•Low Data Retention Current
•66-Pin PGA Special ‘’VERSA-STACK’’
Package with Compatable Footprint
PIN-OUT DIAGRAM
PIN NAMES
A0 - A18 Address Inputs
I/O0 - I/O31 Data Input/Output
CE0, CE1Low Chip Enables
WE0 - WE3Write Enables
OE Output Enable
VDD Power (+5V)
VSS Ground
N.C. No Connect
FUNCTIONAL BLOCK DIAGRAM
4Mx8/2Mx16/1Mx32, 20 - 45ns, PGA
30A128-14 B
This document contains information on a product that is currently released
to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the
right to change products or specifications herein without prior notice.
30A128-14
REV. B 1
DPS1MK32MKV3 Dense-Pac Microsystems, Inc.
RECOMMENDED OPERATING RANGE 3
Symbol Characteristic Min. Typ. Max. Unit
VDD Supply Voltage 4.5 5.0 5.5 V
VIH Input HIGH Voltage 2.2 VDD+0.3 V
VIL Input LOW Voltage -0.520.8 V
TAOperating
Temperature
M-55 +25 +125
oC
I-40 +25 +85
C0+25 +70
TRUTH TABLE
Mode CE WEOE I/O Pin Supply
Current
Not Selected HX X High-Z Standby
DOUT Disable LH H High-Z Active
Read LHLDOUT Active
Write L L XDIN Active
H = HIGH L = LOW X = Don’t Care
DC OUTPUT CHARACTERISTICS
Symbol Parameter Conditions Min. Max. Unit
VOH HIGH Voltage IOH= -4.0mA 2.4 V
VOL LOW Voltage IOL=8.0mA 0.4 V
ABSOLUTE MAXIMUM RATINGS 3
Symbol Parameter Value Unit
TSTC Storage Temperature -65 to +150 °C
TBIAS Temperature Under Bias -55 to +125 °C
VDD Supply Voltage 1 -0.5 to +7.0 °C
VI/O Input/Output Voltage 1 -0.5 to VDD+0.5 V
DC OPERATING CHARACTERISTICS: Over operating ranges
Symbol Characteristics Test Conditions Typ.
(†) CIMUnit
Min. Max. Min. Max. Min. Max.
IIN Input
Leakage Current VIN = 0V to VDD --40 +40 -40 +40 -40 +40 µA
IOUT Output
Leakage Current VI/O = 0V to VDD,
CE or OE = VIH, or WE = VIL --20 +20 -20 +20 -20 +20 µA
ICC Operating
Supply Current Cycle=min., Duty=100%
IOUT = 0mA 580 920 960 960 mA
ISB1 Full Standby
Supply Current VIN ≥ VDD -0.2V or
VIN ≤ VSS +0.2V 8.0 80 80 120 mA
ISB2 Standby Current (TTL) CE = VIH 160 480 480 480 mA
IDR3 Data Retention
Supply Current (3V) VDR = 3V, CE ≥ VDR -0.2V,
VIN ≥ VDD -0.2V or VIN ≤ +0.2V 1.2 4.0 8.0 16.0 mA
IDR2 Data Retention
Supply Current (2V) VDR = 2V, CE ≥ VDR -0.2V,
VIN ≥ VDD -0.2V or VIN ≤ +0.2V 0.8 2.4 6.4 14.4 mA
VOL Output Low Voltage IOUT = 8.0mA -0.4 0.4 0.4 V
VOH Output High Voltage IOUT = -4.0mA -2.4 2.4 2.4 V
† Typical measurements made at +25oC, Cycle = min., VDD = 5.0V.
CAPACITANCE 4: TA = 25°C, F = 1.0MHz
Symbol Parameter Max. Unit Condition
CADR Address Input 75
pF VIN2 = 0V
CCE Chip Enable 45
CWE Write Enable 25
COE Output Enable 75
CI/O Data Input/Output 25
Data Retention AC Characteristics 8
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VDR VDD for Data Retention CE ≥ VDR -0.2V 2.0 - - V
VCDR Chip Disable to
Data Retention Time See Data Retention Waveform 0- - ns
tROperation Recovery Time See Data Retention Waveform 5- - ms
30A128-14
REV. B
2
Dense-Pac Microsystems, Inc. DPS1MK32MKV3
+5V
255Ω
480Ω
CL*
DOUT
Figure 1. Output Load
* Including Probe and Jig
Capacitance.
OUTPUT LOAD
Load CLParameters Measured
130pF except tLZ, tHZ, tOHZ, tOLZ, and tWHZ
25pF tLZ, tHZ, tOHZ, tOLZ, and tWHZ
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Pulse Rise and Fall Times 5ns
Input and Output
Timing Reference Levels 1.5V
AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges
No. Symbol Parameter 20ns 25ns 30ns 35ns 45ns Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
1tRC Read Cycle Time 20 25 30 35 45 ns
2tAA Address Access Time 20 25 30 35 45 ns
3tCO CE to Output Valid 20 25 30 35 45 ns
4tOE Output Enable to Output Valid 10 12 15 20 25 ns
5tLZ CE to Output in LOW-Z 4, 5 3 3 33 3 ns
6tOLZ Output Enable to Output in LOW-Z 4, 5 0 0 00 0 ns
7tHZ CE to Output in HIGH-Z 4, 5 810 15 20 25 ns
8tOHZ Output Enable to Output in HIGH-Z 4, 5 08010 015 020 025 ns
9tOH Output Hold from Address Change 4 5 55 5 ns
AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges
No. Symbol Parameter 20ns 25ns 30ns 35ns 45ns Unit
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max.
10 tWC Write Cycle Time 20 25 30 35 45 ns
11 tAW Address Valid to End of Write 13 15 20 25 35 ns
12 tCW Chip Enable to End of Write 13 15 20 25 35 ns
13 tAS Address Set-Up Time * 000 0 0ns
14 tWP Write Pulse Width 13 15 20 25 35 ns
15 tWR Write Recovery Time 000 0 0ns
16 tWHZ Write Enable to Output in HIGH-Z 4, 5 0 8 010 012 015 020 ns
17 tDW Data to Write Time Overlap 910 12 15 20 ns
18 tDH Data Hold from Write Time 000 0 0ns
19 tOW Output Active from End of Write 333 3 3ns
* Valid for both Read and Write Cycles.
DATA RETENTION WAVEFORM: CE Controlled.
VDD
4.5V
2.3V
VDR1
CE
0V
CE ≥ VDD -0.2V
30A128-14
REV. B 3
DPS1MK32MKV3 Dense-Pac Microsystems, Inc.
READ CYCLE
ADDRESS
CE
OE
DATA I/O
WRITE CYCLE 1: CE Controlled.
ADDRESS
CE
WE
DATA IN
DATA OUT
WAVEFORM KEY
Data Valid Transition from Transition from Data Undefined
HIGH to LOW LOW to HIGH or Don’t Care
30A128-14
REV. B
4
Dense-Pac Microsystems, Inc. DPS1MK32MKV3
WRITE CYCLE 2: WE Controlled. OE is HIGH. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
WRITE CYCLE 3: WE Controlled. OE is LOW. 8
ADDRESS
CE
WE
DATA IN
DATA OUT
NOTES:
1. All voltages are with respect to VSS.
2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V
at DC level).
3. Stresses greater than those under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This
is a stress rating only and functional operation of the device
at these or any other conditions above those indicated in
the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
4. This parameter is guaranteed and not 100% tested.
5. Transition is measured at the point of ±500mV from steady
state voltage.
6. When OE and CE are LOW and WE is HIGH, I/O pins are
in the output state,and input signals of opposite phase to
the outputs must not be applied.
7. The outputs are in a high impedance state when WE is
LOW.
8. CE and WE can initiate and terminate WRITE Cycle.
30A128-14
REV. B 5
DPS1MK32MKV3 Dense-Pac Microsystems, Inc.
ORDERING INFORMATION
MECHANICAL DRAWING
Dense-Pac Microsystems, Inc.
7321 Lincoln Way ¿ Garden Grove , California 92841-1431
(714) 898-0007 (800) 642-4477 (Outside CA) ¿ FAX: (714) 897-1772 ¿ http://www.dense-pac.com
30A128-14
REV. B
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