4Mx8/2Mx16/1Mx32, 20 - 45ns, PGA 30A128-14 B 32 Megabit High Speed CMOS SRAM DPS1MK32MKV3 DESCRIPTION: The DPS1MK32MKV3 `'VERSA-STACK'' module is a revolutionary new high speed memory subsystem using Dense-Pac Microsystems' ceramic Stackable Leadless Chip Carriers (SLCC) mounted on a co-fired ceramic substrate. It offers 32 Megabits of SRAM in a package envelope of 1.190 x 1.190 x 0.360 inches. The DPS1MK32MKV3 contains eight individual 512K x 8 SRAMs, packaged in their own hermetically sealed SLCCs making the module suitable for commercial, industrial and military applications. By using SLCCs, the `'Versa-Stack'' family of modules offers a higher board density of memory than available with conventional through-hole, surface mount, module, or hybrid techniques. FEATURES: * Organizations Available: READ: 1Meg x 32 WRITE: 1Meg x 32, 2 Meg x 16 or 4 Meg x 8 * Access Times: 20, 25, 35, 45ns * Fully Static Operation - No clock or refresh required * Low Power Dissipation * Single +5V Power Supply, 10% Tolerance * TTL Compatible * Common Data Inputs and Outputs * Low Data Retention Current * 66-Pin PGA Special `'VERSA-STACK'' Package with Compatable Footprint FUNCTIONAL BLOCK DIAGRAM PIN-OUT DIAGRAM PIN NAMES A0 - A18 I/O0 - I/O31 CE0, CE1 WE0 - WE3 OE VDD VSS N.C. 30A128-14 REV. B Address Inputs Data Input/Output Low Chip Enables Write Enables Output Enable Power (+5V) Ground No Connect This document contains information on a product that is currently released to production at Dense-Pac Microsystems, Inc. Dense-Pac reserves the right to change products or specifications herein without prior notice. 1 DPS1MK32MKV3 Dense-Pac Microsystems, Inc. TRUTH TABLE Mode Not Selected DOUT Disable Read Write H = HIGH CE WE OE H L L L X H H L X H L X L = LOW Symbol VDD VIH VIL Supply Current High-Z Standby High-Z Active DOUT Active DIN Active I/O Pin TA X = Don't Care RECOMMENDED OPERATING RANGE 3 Characteristic Min. Typ. Max. Unit Supply Voltage 4.5 5.0 5.5 V Input HIGH Voltage 2.2 VDD+0.3 V Input LOW Voltage -0.52 0.8 V M -55 +25 +125 Operating oC I -40 +25 +85 Temperature C 0 +25 +70 DC OUTPUT CHARACTERISTICS Symbol Parameter Conditions Min. Max. Unit VOH HIGH Voltage IOH= -4.0mA 2.4 V VOL LOW Voltage IOL=8.0mA 0.4 V Symbol TSTC TBIAS VDD VI/O ABSOLUTE MAXIMUM RATINGS 3 Parameter Value DC OPERATING CHARACTERISTICS: Over operating ranges Typ. C I Test Conditions () Min. Max. Min. Max. Symbol Characteristics IIN Input Leakage Current Output Leakage Current Operating Supply Current Full Standby Supply Current Standby Current (TTL) Data Retention Supply Current (3V) Data Retention Supply Current (2V) Output Low Voltage Output High Voltage IOUT ICC ISB1 ISB2 IDR3 IDR2 VOL VOH Unit Storage Temperature -65 to +150 C Temperature Under Bias -55 to +125 C Supply Voltage 1 -0.5 to +7.0 C Input/Output Voltage 1 -0.5 to V DD+0.5 V CAPACITANCE 4: T A = 25C, F = 1.0MHz Symbol Parameter Max. Unit Condition CADR Address Input 75 CCE Chip Enable 45 pF VIN2 = 0V CWE Write Enable 25 COE Output Enable 75 CI/O Data Input/Output 25 M Min. Max. Unit VIN = 0V to VDD - -40 +40 -40 +40 -40 +40 A VI/O = 0V to VDD, CE or OE = VIH, or WE = VIL Cycle=min., Duty=100% IOUT = 0mA VIN VDD -0.2V or VIN VSS +0.2V CE = VIH VDR = 3V, CE VDR -0.2V, VIN VDD -0.2V or VIN +0.2V VDR = 2V, CE VDR -0.2V, VIN VDD -0.2V or VIN +0.2V IOUT = 8.0mA IOUT = -4.0mA - -20 +20 -20 +20 -20 +20 A 960 960 mA 580 920 8.0 80 80 120 mA 160 480 480 480 mA 1.2 4.0 8.0 16.0 mA 0.8 2.4 6.4 14.4 mA - 0.4 0.4 0.4 V V 2.4 2.4 2.4 Typical measurements made at +25oC, Cycle = min., VDD = 5.0V. Symbol VDR VCDR tR 2 Parameter VDD for Data Retention Chip Disable to Data Retention Time Operation Recovery Time Data Retention AC Characteristics 8 Test Conditions CE VDR -0.2V Min. 2.0 Typ. - Max. - Unit V See Data Retention Waveform 0 - - ns See Data Retention Waveform 5 - - ms 30A128-14 REV. B DPS1MK32MKV3 Dense-Pac Microsystems, Inc. AC TEST CONDITIONS Input Pulse Levels 0V to 3.0V Input Pulse Rise and Fall Times 5ns Input and Output 1.5V Timing Reference Levels Figure 1. Output Load 480 DOUT CL* 255 OUTPUT LOAD Parameters Measured except t LZ, tHZ, tOHZ, tOLZ, and t WHZ tLZ, tHZ, tOHZ, tOLZ, and tWHZ CL 30pF 5pF DATA RETENTION WAVEFORM: * Including Probe and Jig Capacitance. +5V Load 1 2 CE Controlled. VDD 4.5V 2.3V VDR1 CE VDD -0.2V CE 0V AC OPERATING CONDITIONS AND CHARACTERISTICS - READ CYCLE: Over operating ranges 20ns 25ns 30ns 35ns 45ns No. Symbol Parameter Min. 1 2 3 4 5 6 7 8 9 tRC tAA tCO tOE tLZ tOLZ tHZ tOHZ tOH Read Cycle Time Address Access Time CE to Output Valid Output Enable to Output Valid CE to Output in LOW-Z 4, 5 Output Enable to Output in LOW-Z 4, 5 CE to Output in HIGH-Z 4, 5 Output Enable to Output in HIGH-Z 4, 5 Output Hold from Address Change Max. 20 Min. 25 20 20 10 3 0 0 4 Max. 0 5 Max. 30 25 25 12 3 0 8 8 Min. 0 5 Max. 35 30 30 15 3 0 10 10 Min. 0 5 Max. 45 35 35 20 3 0 15 15 Min. 45 45 25 3 0 20 20 0 5 25 25 AC OPERATING CONDITIONS AND CHARACTERISTICS - WRITE CYCLE 6, 7: Over operating ranges 20ns 25ns 30ns 35ns 45ns No. Symbol Parameter Min. 10 11 12 13 14 15 16 17 18 19 tWC tAW tCW tAS tWP tWR tWHZ tDW tDH tOW Write Cycle Time Address Valid to End of Write Chip Enable to End of Write Address Set-Up Time * Write Pulse Width Write Recovery Time Write Enable to Output in HIGH-Z 4, 5 Data to Write Time Overlap Data Hold from Write Time Output Active from End of Write 20 13 13 0 13 0 0 9 0 3 Max. 8 Min. 25 15 15 0 15 0 0 10 0 3 Max. 10 Min. 30 20 20 0 20 0 0 12 0 3 Max. 12 Min. 35 25 25 0 25 0 0 15 0 3 Max. 15 Min. 45 35 35 0 35 0 0 20 0 3 Max. 20 Unit ns ns ns ns ns ns ns ns ns Unit ns ns ns ns ns ns ns ns ns ns * Valid for both Read and Write Cycles. 30A128-14 REV. B 3 DPS1MK32MKV3 Dense-Pac Microsystems, Inc. READ CYCLE ADDRESS CE OE DATA I/O WRITE CYCLE 1: CE Controlled. ADDRESS CE WE DATA IN DATA OUT WAVEFORM KEY Data Valid 4 Transition from HIGH to LOW Transition from LOW to HIGH Data Undefined or Don't Care 30A128-14 REV. B DPS1MK32MKV3 Dense-Pac Microsystems, Inc. WRITE CYCLE 2: WE Controlled. OE is HIGH. 8 ADDRESS CE WE DATA IN DATA OUT WRITE CYCLE 3: WE Controlled. OE is LOW. 8 ADDRESS CE WE DATA IN DATA OUT NOTES: 1. All voltages are with respect to VSS . 2. -2.0V min. for pulse width less than 20ns (VIL min. = -0.5V at DC level). 3. Stresses greater than those under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 30A128-14 REV. B 4. This parameter is guaranteed and not 100% tested. 5. Transition is measured at the point of 500mV from steady state voltage. 6. When OE and CE are LOW and WE is HIGH, I/O pins are in the output state,and input signals of opposite phase to the outputs must not be applied. 7. The outputs are in a high impedance state when WE is LOW. 8. CE and WE can initiate and terminate WRITE Cycle. 5 DPS1MK32MKV3 Dense-Pac Microsystems, Inc. ORDERING INFORMATION MECHANICAL DRAWING Dense-Pac Microsystems, Inc. 7321 Lincoln Way Garden Grove , California 92841-1431 (714) 898-0007 (800) 642-4477 (Outside CA) FAX: (714) 897-1772 http://www.dense-pac.com 6 30A128-14 REV. B