IRFR320, IRFU320 Data Sheet 3.1A, 400V, 1.800 Ohm, N-Channel Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode of operation. All of these power MOSFETs are designed for applications such as switching regulators, switching convertors, motor drivers, relay drivers, and drivers for high power bipolar switching transistors requiring high speed and low gate drive power. These types can be operated directly from integrated circuits. Formerly developmental type TA17404. Ordering Information PART NUMBER July 1999 File Number 2412.3 Features * 3.1A, 400V * rDS(ON) = 1.800 * Single Pulse Avalanche Energy Rated * SOA is Power Dissipation Limited * Nanosecond Switching Speeds * Linear Transfer Characteristics * High Input Impedance * Related Literature - TB334 "Guidelines for Soldering Surface Mount Components to PC Boards" Symbol PACKAGE D BRAND IRFR320 TO-252AA IFR320 IRFU320 TO-251AA IFU320 G NOTE: When ordering, use the entire part number. Add the suffix 9A to obtain the TO-252AA variant in tape and reel, i.e., IRFR3209A. S Packaging JEDEC TO-251AA SOURCE DRAIN GATE DRAIN (FLANGE) 4-395 JEDEC TO-252AA GATE DRAIN DRAIN (FLANGE) SOURCE CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999 IRFR320, IRFU320 Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDGR Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID TC = 100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS Maximum Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Single Pulse Avalanche Energy Rating (Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG Maximum Temperature for Soldering Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg IRFR320, IRFU320 400 400 3.1 2.0 12 20 50 0.4 190 -55 to 150 UNITS V V A A A V W W/oC mJ oC 300 260 oC oC CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. TJ = 25oC to 125oC. Electrical Specifications TC = 25oC, Unless Otherwise Specified MIN TYP MAX UNITS Drain to Source Breakdown Voltage PARAMETER BVDSS ID = 250A, VGS = 0V, (Figure 10) 400 - - V Gate Threshold Voltage VGS(TH) VGS = VDS, ID = 250A Zero Gate Voltage Drain Current On-State Drain Current (Note 2) Gate to Source Leakage Current Drain to Source On Resistance (Note 2) Forward Transconductance (Note 2) Turn-On Delay Time SYMBOL IDSS ID(ON) IGSS rDS(ON) gfs td(ON) Rise Time tr Turn-Off Delay Time td(OFF) Fall Time TEST CONDITIONS 2.0 - 4.0 V VDS = Rated BVDSS, VGS = 0V - - 25 A VDS = 0.8 x Rated BVDSS, VGS = 0V, TJ = 125oC - - 250 A 3.1 - - A VDS > ID(ON) x rDS(ON)MAX, VGS = 10V, (Figure 7) VGS = 20V - - 100 nA ID = 1.7A, VGS = 10V, (Figures 8, 9) - 1.600 1.800 1.7 2.6 - S - 10 15 ns - 14 21 ns - 30 45 ns - 13 20 ns - 13 20 nC - 2.2 3.3 nC - 7.2 11 nC - 350 - pF - 64 - pF - 8.1 - pF - 4.5 - nH - 7.5 - nH - - 2.5 oC/W - - 110 oC/W VDS 10V, ID = 2.0A, (Figure 12) VDD = 200V, ID 3.1A, RGS = 18, RL = 63, VGS = 10V MOSFET Switching Times are Essentially Independent of Operating Temperature tf Total Gate Charge (Gate to Source + Gate to Drain) Qg(TOT) Gate to Source Charge Qgs Gate to Drain "Miller" Charge Qgd Input Capacitance CISS Output Capacitance COSS Reverse Transfer Capacitance CRSS VGS = 10V, ID = 3.1A, VDS = 0.8 x Rated BVDSS, IG(REF) = 1.5mA, (Figure 14) Gate Charge is Essentially Independent of Operating Temperature VDS = 25V, VGS = 0V, f = 1MHz, (Figure 11) Internal Drain Inductance LD Measured From the Drain Lead, 6.0mm (0.25in) from Package to Center of Die Internal Source Inductance LS Measured From the Source Lead, 6.0mm (0.25in) from Package to Source Bonding Pad Modified MOSFET Symbol Showing the Internal Device Inductances D LD G LS S Thermal Resistance, Junction to Case RJC Thermal Resistance, Junction to Ambient RJA 4-396 Typical Solder Mount IRFR320, IRFU320 Source to Drain Diode Specifications PARAMETER SYMBOL Continuous Source to Drain Current TEST CONDITIONS ISD Pulse Source to Drain Current (Note 3) Modified MOSFET Symbol Showing the Integral Reverse P-N Junction Rectifier ISDM D MIN TYP MAX UNITS - - 3.1 A - - 12 A - - 1.6 V G S Source to Drain Diode Voltage (Note 2) TJ = 25oC, ISD = 3.1A, VGS = 0V, (Figure 13) VSD Reverse Recovery Time Reverse Recovery Charge trr TJ = 25oC, ISD = 3.1A, dISD/dt = 100A/s 120 270 600 ns QRR TJ = 25oC, ISD = 3.1A, dISD/dt = 100A/s 0.64 1.4 3.0 C NOTES: 2. Pulse test: pulse width 300s, duty cycle 2%. 3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3). 4. VDD = 50V, starting TJ = 25oC, L = 3.1mH, RGS = 25, peak IAS = 3.1A. Typical Performance Curves Unless Otherwise Specified 4.0 ID, DRAIN CURRENT (A) 1.0 0.8 0.6 0.4 0.2 0 25 0 125 50 75 100 TC , CASE TEMPERATURE (oC) 150 3.2 2.4 1.6 0.8 0 25 175 75 50 150 125 100 TC, CASE TEMPERATURE (oC) FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE TEMPERATURE ZJC, TRANSIENT THERMAL IMPEDANCE POWER DISSIPATION MULTIPLIER 1.2 FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs CASE TEMPERATURE 10 0.5 1 0.2 PDM 0.1 0.1 0.05 0.02 0.01 t1 t2 NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJC x RJC + TC SINGLE PULSE 10-2 10-5 10-4 10-3 10-2 0.1 t1, RECTANGULAR PULSE DURATION (s) FIGURE 3. MAXIMUM TRANSIENT THERMAL IMPEDANCE 4-397 1 10 IRFR320, IRFU320 Typical Performance Curves Unless Otherwise Specified (Continued) 5 100 10s 10 100s 1ms 1 10ms TJ = MAX RATED TC = 25oC SINGLE PULSE 0.1 1 VGS = 10V PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3 VGS = 5.5V 2 VGS = 5.0V 1 VGS = 4.0V DC 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) 0 1000 0 10 120 160 200 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VDS 350V VGS = 6.0V 3 VGS = 5.5V 2 VGS = 5.0V 1 ID, DRAIN CURRENT (A) VGS = 10V 4 80 FIGURE 5. OUTPUT CHARACTERISTICS 5 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 40 VGS = 4.5V VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 4. FORWARD BIAS SAFE OPERATING AREA ID, DRAIN CURRENT (A) VGS = 6.0V 4 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) OPERATION IN THIS AREA IS LIMITED BY rDS(ON) 1 TJ = 150oC TJ = 25oC 0.1 VGS = 4.0V VGS = 4.5V 0 0 6 3 12 9 15 10-2 0 2 4 6 8 VGS, GATE TO SOURCE VOLTAGE (V) VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS 3.0 NORMALIZED DRAIN TO SOURCE ON RESISTANCE PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 8 VGS = 10V ON RESISTANCE rDS(ON), DRAIN TO SOURCE 10 6 VGS = 20V 4 2 0 2.4 3 6 9 ID, DRAIN CURRENT (A) 12 FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE VOLTAGE AND DRAIN CURRENT 4-398 15 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 10V, ID = 1.7A 1.8 1.2 0.6 0 0 10 -40 0 40 80 120 TJ , JUNCTION TEMPERATURE (oC) FIGURE 9. NORMALIZED DRAIN TO SOURCE ON RESISTANCE vs JUNCTION TEMPERATURE 160 IRFR320, IRFU320 Typical Performance Curves Unless Otherwise Specified (Continued) 1.25 750 1.15 1.05 0.95 CISS 450 COSS 300 0.85 0.75 CRSS 150 -40 0 80 40 120 0 160 1 2 TJ , JUNCTION TEMPERATURE (oC) FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE vs JUNCTION TEMPERATURE ISD, SOURCE TO DRAIN CURRENT (A) 4 TJ = 25oC TJ = 150oC 2 1 1 2 3 ID, DRAIN CURRENT (A) 4 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX VGS = 0V TJ = 150oC 5 0 0.3 0.6 0.9 1.2 VSD, SOURCE TO DRAIN VOLTAGE (V) FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE ID = 3.1A VDS = 320V VDS = 200V VDS = 80V 16 12 8 4 0 0 4 8 12 16 20 QG(TOT) , TOTAL GATE CHARGE (nC) FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE 4-399 TJ = 25oC 1 FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT 20 102 10 0.1 0 VGS, GATE TO SOURCE (V) gfs, TRANSCONDUCTANCE (S) 100 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX 3 5 10 2 5 VDS, DRAIN TO SOURCE VOLTAGE (V) FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE 5 0 VGS = 0V, f = 1MHz CISS = CGS + CGD CRSS = CGD COSS CDS + CGD 600 C, CAPACITANCE (pF) NORMALIZED DRAIN TO SOURCE BREAKDOWN VOLTAGE ID = 250A 1.5 IRFR320, IRFU320 Test Circuits and Waveforms VDS BVDSS L tP VARY tP TO OBTAIN + RG REQUIRED PEAK IAS VDS IAS VDD VDD - VGS DUT tP 0V IAS 0 0.01 tAV FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS tON tOFF td(ON) td(OFF) tf tr RL VDS 90% 90% + RG - VDD 10% 10% 0 DUT 90% VGS VGS 0 FIGURE 17. SWITCHING TIME TEST CIRCUIT 0.2F 50% PULSE WIDTH 10% FIGURE 18. RESISTIVE SWITCHING WAVEFORMS VDS (ISOLATED SUPPLY) CURRENT REGULATOR 12V BATTERY 50% VDD Qg(TOT) SAME TYPE AS DUT 50k Qgd 0.3F VGS Qgs D VDS DUT G 0 IG(REF) S 0 IG CURRENT SAMPLING RESISTOR VDS ID CURRENT SAMPLING RESISTOR FIGURE 19. GATE CHARGE TEST CIRCUIT 4-400 IG(REF) 0 FIGURE 20. GATE CHARGE WAVEFORMS IRFR320, IRFU320 All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com Sales Office Headquarters NORTH AMERICA Intersil Corporation P. O. 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