Important notice Dear Customer, On 7 February 2017 the former NXP Standard Product business became a new company with the tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS semiconductors with its focus on the automotive, industrial, computing, consumer and wearable application markets In data sheets and application notes which still contain NXP or Philips Semiconductors references, use the references to Nexperia, as shown below. Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/, use http://www.nexperia.com Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use salesaddresses@nexperia.com (email) Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on the version, as shown below: - (c) NXP N.V. (year). All rights reserved or (c) Koninklijke Philips Electronics N.V. (year). All rights reserved Should be replaced with: - (c) Nexperia B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and understanding, Kind regards, Team Nexperia 74HC00; 74HCT00 Quad 2-input NAND gate Rev. 7 -- 25 November 2015 Product data sheet 1. General description The 74HC00; 74HCT00 is a quad 2-input NAND gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of VCC. 2. Features and benefits Input levels: For 74HC00: CMOS level For 74HCT00: TTL level Complies with JEDEC standard no. 7A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C and from 40 C to +125 C 3. Ordering information Table 1. Ordering information Type number 74HC00D Package Temperature range Name Description Version 40 C to +125 C SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1 40 C to +125 C SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1 40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very SOT762-1 thin quad flat package; no leads; 14 terminals; body 2.5 3 0.85 mm 74HCT00D 74HC00DB 74HCT00DB 74HC00PW 74HCT00PW 74HC00BQ 74HCT00BQ 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 4. Functional diagram $ % < $ % < $ % < $ % < $ < % PQD Fig 1. PQD Logic symbol Fig 2. PQD IEC logic symbol Fig 3. Logic diagram (one gate) 5. Pinning information 5.1 Pinning +& +&7 $ WHUPLQDO LQGH[DUHD % % < $ < < $ $ $ < % % % < < $ % % *1' < < 9&& *1' $ 9&& +& +&7 *1' % $ DDO 7UDQVSDUHQWWRSYLHZ DDO (1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to GND. Fig 4. Pin configuration SO14 and (T)SSOP14 74HC_HCT00 Product data sheet Fig 5. Pin configuration DHVQFN14 All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 2 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 5.2 Pin description Table 2. Pin description Symbol Pin Description 1A to 4A 1, 4, 9, 12 data input 1B to 4B 2, 5, 10, 13 data input 1Y to 4Y 3, 6, 8, 11 data output GND 7 ground (0 V) VCC 14 supply voltage 6. Functional description Table 3. Function table[1] Input Output nA nB nY L X H X L H H H L [1] H = HIGH voltage level; L = LOW voltage level; X = don't care. 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions VCC supply voltage IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V [1] IOK output clamping current VO < 0.5 V or VO > VCC + 0.5 V [1] IO output current 0.5 V < VO < VCC + 0.5 V ICC IGND Tstg storage temperature Max Unit 0.5 +7 V - 20 mA - 20 mA - 25 mA supply current - 50 mA ground current 50 - mA 65 +150 C - 500 mW [2] total power dissipation Ptot Min SO14, (T)SSOP14 and DHVQFN14 packages [1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] For SO14 package: Ptot derates linearly with 8 mW/K above 70 C. For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C. For DHVQFN14 packages: Ptot derates linearly with 4.5 mW/K above 60 C. 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 3 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 8. Recommended operating conditions Table 5. Recommended operating conditions Voltages are referenced to GND (ground = 0 V) Symbol Parameter Conditions 74HC00 Min Typ 74HCT00 Max Min Typ Unit Max VCC supply voltage 2.0 5.0 6.0 4.5 5.0 5.5 V VI input voltage 0 - VCC 0 - VCC V VO output voltage 0 - VCC 0 - VCC V Tamb ambient temperature 40 +25 +125 40 +25 +125 C t/V input transition rise and fall rate VCC = 2.0 V - - 625 - - - ns/V VCC = 4.5 V - 1.67 139 - 1.67 139 ns/V VCC = 6.0 V - - 83 - - - ns/V 9. Static characteristics Table 6. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter 25 C Conditions 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max 74HC00 VIH VIL VOH VOL HIGH-level input voltage VCC = 2.0 V - 1.2 - 1.5 - 1.5 - V VCC = 4.5 V - 2.4 - 3.15 - 3.15 - V VCC = 6.0 V - 3.2 - 4.2 - 4.2 - V LOW-level input voltage VCC = 2.0 V - 0.8 - - 0.5 - 0.5 V VCC = 4.5 V - 2.1 - - 1.35 - 1.35 V VCC = 6.0 V - 2.8 - - 1.8 - 1.8 V IO = 20 A; VCC = 2.0 V - 2.0 - 1.9 - 1.9 - V IO = 20 A; VCC = 4.5 V - 4.5 - 4.4 - 4.4 - V IO = 20 A; VCC = 6.0 V - 6.0 - 5.9 - 5.9 - V IO = 4.0 mA; VCC = 4.5 V - 4.32 - 3.84 - 3.7 - V IO = 5.2 mA; VCC = 6.0 V - 5.81 - 5.34 - 5.2 - V IO = 20 A; VCC = 2.0 V - 0 - - 0.1 - 0.1 V IO = 20 A; VCC = 4.5 V - 0 - - 0.1 - 0.1 V IO = 20 A; VCC = 6.0 V - 0 - - 0.1 - 0.1 V IO = 4.0 mA; VCC = 4.5 V - 0.15 - - 0.33 - 0.4 V IO = 5.2 mA; VCC = 6.0 V - 0.16 - - 0.33 - 0.4 V HIGH-level output voltage LOW-level output voltage VI = VIH or VIL VI = VIH or VIL II input leakage current VI = VCC or GND; VCC = 6.0 V - - - - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - - - 20 - 40 A 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 4 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate Table 6. Static characteristics ...continued At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter CI 25 C Conditions input capacitance 40 C to +85 C 40 C to +125 C Unit Min Typ Max Min Max Min Max - 3.5 - - - - - pF 74HCT00 VIH HIGH-level input voltage VCC = 4.5 V to 5.5 V - 1.6 - 2.0 - 2.0 - V VIL LOW-level input voltage VCC = 4.5 V to 5.5 V - 1.2 - - 0.8 - 0.8 V VOH HIGH-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A - 4.5 - 4.4 - 4.4 - V IO = 4.0 mA - 4.32 - 3.84 - 3.7 - V LOW-level output voltage VI = VIH or VIL; VCC = 4.5 V IO = 20 A; VCC = 4.5 V - 0 - - 0.1 - 0.1 V IO = 5.2 mA; VCC = 6.0 V - 0.15 - - 0.33 - 0.4 V VOL II input leakage current VI = VCC or GND; VCC = 6.0 V - - - - 1 - 1 A ICC supply current VI = VCC or GND; IO = 0 A; VCC = 6.0 V - - - - 20 - 40 A ICC additional supply current per input pin; VI = VCC 2.1 V; IO = 0 A; other inputs at VCC or GND; VCC = 4.5 V to 5.5 V - 150 - - 675 - 735 A CI input capacitance - 3.5 - - - - - pF 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; CL = 50 pF; for test circuit see Figure 7. Symbol Parameter 25 C Conditions 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 25 - 115 135 74HC00 tpd propagation delay nA, nB to nY; see Figure 6 [1] VCC = 2.0 V VCC = 4.5 V - 9 - 23 27 ns VCC = 5.0 V; CL = 15 pF - 7 - - - ns - 7 - 20 23 ns VCC = 6.0 V tt transition time 74HC_HCT00 Product data sheet ns see Figure 6 [2] VCC = 2.0 V - 19 - 95 110 ns VCC = 4.5 V - 7 - 19 22 ns VCC = 6.0 V - 6 - 16 19 ns All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 5 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate Table 7. Dynamic characteristics ...continued GND = 0 V; CL = 50 pF; for test circuit see Figure 7. Symbol Parameter CPD 25 C Conditions power dissipation capacitance [3] per package; VI = GND to VCC 40 C to +125 C Unit Min Typ Max Max (85 C) Max (125 C) - 22 - - - pF 74HCT00 [1] propagation delay nA, nB to nY; see Figure 6 tpd transition time tt power dissipation capacitance CPD VCC = 4.5 V - 12 - 24 29 ns VCC = 5.0 V; CL = 15 pF - 10 - - - ns VCC = 4.5 V; see Figure 6 [2] - - - 29 22 ns per package; VI = GND to VCC 1.5 V [3] - 22 - - - pF [1] tpd is the same as tPHL and tPLH. [2] tt is the same as tTHL and tTLH. [3] CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD VCC2 fi N + (CL VCC2 fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in V; N = number of inputs switching; (CL VCC2 fo) = sum of outputs. 11. Waveforms 9, Q$Q%LQSXW 90 *1' W3+/ 92+ 9< 90 9; Q<RXWSXW 92/ W3/+ W7+/ W7/+ DDL Measurement points are given in Table 9. VOL and VOH are typical voltage output levels that occur with the output load. Fig 6. Table 8. Input to output propagation delays Measurement points Type Input Output VM VM VX VY 74HC00 0.5VCC 0.5VCC 0.1VCC 0.9VCC 74HCT00 1.3 V 1.3 V 0.1VCC 0.9VCC 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 6 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 9, QHJDWLYH SXOVH W: 90 90 *1' WI 9, WI SRVLWLYH SXOVH *1' WU WU 90 90 W: 9&& * 9, 92 '87 57 &/ DDK Test data is given in Table 9. Definitions test circuit: RT = termination resistance should be equal to output impedance Zo of the pulse generator. CL = load capacitance including jig and probe capacitance. Fig 7. Table 9. Test circuit for measuring switching times Test data Type Input Load Test VI tr, tf CL 74HC00 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HCT00 3.0 V 6.0 ns 15 pF, 50 pF tPLH, tPHL 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 7 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 12. Package outline 62SODVWLFVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ' ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 LQFKGLPHQVLRQVDUHGHULYHGIURPWKHRULJLQDOPPGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP LQFKHV R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPP LQFK PD[LPXPSHUVLGHDUHQRWLQFOXGHG Fig 8. 5()(5(1&(6 287/,1( 9(56,21 ,(& -('(& 627 ( 06 -(,7$ (8523($1 352-(&7,21 ,668('$7( Package outline SOT108-1 (SO14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 8 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 6623SODVWLFVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ $ $ $ SLQLQGH[ /S / GHWDLO; Z 0 ES H PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 Fig 9. 5()(5(1&(6 ,(& -('(& -(,7$ 02 (8523($1 352-(&7,21 ,668('$7( Package outline SOT337-1 (SSOP14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 9 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP ' 627 ( $ ; F \ +( Y 0 $ = 4 $ SLQLQGH[ $ $ $ /S / H GHWDLO; Z 0 ES PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ 02 (8523($1 352-(&7,21 ,668('$7( Fig 10. Package outline SOT402-1 (TSSOP14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 10 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate '+94)1SODVWLFGXDOLQOLQHFRPSDWLEOHWKHUPDOHQKDQFHGYHU\WKLQTXDGIODWSDFNDJHQROHDGV WHUPLQDOVERG\[[PP % ' 627 $ $ $ ( F GHWDLO; WHUPLQDO LQGH[DUHD WHUPLQDO LQGH[DUHD & H H Y Z E & $ % & \ \ & / (K H N 'K ; N PP VFDOH 'LPHQVLRQV PPDUHWKHRULJLQDOGLPHQVLRQV 8QLW PP PD[ QRP PLQ $ $ E F ' 'K ( (K H H N / Y Z \ \ 1RWH 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 2XWOLQH YHUVLRQ 627 5HIHUHQFHV ,(& -('(& -(,7$ VRWBSR (XURSHDQ SURMHFWLRQ ,VVXHGDWH 02 Fig 11. Package outline SOT762-1 (DHVQFN14) 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 11 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 13. Abbreviations Table 10. Abbreviations Acronym Description CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model LSTTL Low-power Schottky Transistor-Transistor Logic MM Machine Model TTL Transistor-Transistor Logic 14. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74HC_HCT00 v.7 20151125 Product data sheet - 74HC_HCT00 v.6 Modifications: 74HC_HCT00 v.6 Modifications: * Type numbers 74HC00N and 74HCT00N (SOT27-1) removed. 20111214 * Product data sheet - 74HC_HCT00 v.5 Legal pages updated. 74HC_HCT00 v.5 20101125 Product data sheet - 74HC_HCT00 v.4 74HC_HCT00 v.4 20100111 Product data sheet - 74HC_HCT00 v.3 74HC_HCT00 v.3 20030630 Product data sheet - 74HC_HCT00_CNV v.2 Product specification - - 74HC_HCT00_CNV v.2 19970826 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 12 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate 15. Legal information 15.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions Draft -- The document is a draft version only. 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Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 13 of 15 74HC00; 74HCT00 NXP Semiconductors Quad 2-input NAND gate Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 16. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com 74HC_HCT00 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 7 -- 25 November 2015 (c) NXP Semiconductors N.V. 2015. All rights reserved. 14 of 15 NXP Semiconductors 74HC00; 74HCT00 Quad 2-input NAND gate 17. Contents 1 2 3 4 5 5.1 5.2 6 7 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 17 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 1 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 2 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 3 Recommended operating conditions. . . . . . . . 4 Static characteristics. . . . . . . . . . . . . . . . . . . . . 4 Dynamic characteristics . . . . . . . . . . . . . . . . . . 5 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . 8 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12 Legal information. . . . . . . . . . . . . . . . . . . . . . . 13 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Contact information. . . . . . . . . . . . . . . . . . . . . 14 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP Semiconductors N.V. 2015. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 25 November 2015 Document identifier: 74HC_HCT00