AIC1573
5-bit DAC, Synchronous PWM Power
Regulator with Simple PWM Power Regulator,
LDO And Linear Controller
Analog Integrations Corporation 4F, 9, Industry E. 9th Rd, Science Based Industrial Park, Hsinchu Taiwan, ROC
www.analog.com.tw
DS-1573-01 Sep 10, 01 TEL: 886-3-5772500 FAX: 886-3-5772510 1
n FEATURES
l Compatible with HIP6020.
l Provides 4 Regulated Voltages for Microprocessor
Core, AGP Bus, Memory and GTL Bus Power.
l TTL Compatible 5-bit Digital-to-Analog Core Output
Voltage Selection. Range from 1.3V to 3.5V.
0.1V Steps from 2.1V to 3.5V.
0.05V Steps from 1.3V to 2.05V.
l ±1.0% PWM Output Voltage for VCORE.
l ±3% PWM Output Voltage for AGP Bus.
l ±3.0% Reference Voltage for Chipset and/or Ca-
che Memory and VGTL.
l Simple Voltage-Mode PWM Control with Built in
Internal Compensation Networks.
l N-Channel MOSFET Driver for PWM buck con-
verters.
l Linear Controller Drives Compatible with both N–
Chanel MOSFET and NPN Bipolar Series Pass
Transistor.
l Operates from +3.3V, +5V and +12V Inputs.
l Fast Transient Response.
l Full 0% to 100% Duty Ratios.
l Adjustable Current Limit without External Sense
Resistor.
l Microprocessor Core Voltage Protection against
Upper MOSFET shorted to +5V.
l Power Good Output Voltage Monitor.
l Over-Voltage and Over-Current Fault Monitors.
l 200KHz Free-Running Oscillator Programmable up
to 700KHz.
n APPLICATIONS
l Full Motherboard Power Regulation for Computers.
n DESCRIPTION
The AIC1573 combines two PWM voltage mode
controllers and two linear controllers as well as the
monitoring and protection functions in this chip. One
PWM controller regulates the microprocessor core
voltage with a synchronous rectified buck converter.
The second PWM controller provides AGP bus 1.5V
or 3.3V power with a standard buck converter. Two
linear controllers regulate power for the 1.5V GTL
bus and 1.8V power for the chip set core voltage
and/or cache memory circuits.
An integrated 5 bit D/A converter that adjusts the
microprocessor core voltage from 2.1V to 3.5V in
0.1V increments and from 1.3V to 2.05V in 0.05V
increments. The second PWM controller for AGP
bus power is selectable by means of SELECT pin
status for 1.5V or 3.3V with 3% accuracy. Two linear
controllers drive with external N-channel MOSFETs
to provide 1.5V±3% and fixed output voltage
1.8V±3%.
This chip monitors all the output voltages. Power
Good signal is issued when the core voltage is
within ±10% of the DAC setting and the other levels
are above their under-voltage levels. Over-voltage
protection for the core output uses the lower N-
channel MOSFET to prevent output voltage above
116% of the DAC setting.
The PWM over-current function monitors the output
current by using the voltage drop across the upper
MOSFET’s RDS(ON), eliminating the need for a cur-
rent sensing resistor.
AIC1573
2
n APPLICATION CIRCUIT
+
+
+
+
+
+
UGATE1
UGATE2
PHASE1
PHASE2
LGATE1
PGND
VSEN2
FB1
SELECT NC
VAUX VSEN1
DRIVE3
VID0
VSEN3 VID1
VID2
VID3
VID4
PGOOD
DRIVE4
FAULT/RT
VESN4 SS
7µH
3µH
4.7µF
8
13
7
6
5
4
3
1nF 1nF
C7 C5
1000µF*3
1000µF*7
20
0.22µF
C6
680K
10K
R2
R1
10V
680µF*7
CIN
R3
L1
VOUT1
21
L3
22
COUT1
OCSET1
23
24
25
26
27 GND
+5VIN
1µH
Q2
Q1
9
3.3V or 1.5V
VOUT2
Q5
Q4
Q3
COUT3
COUT4
COUT2
14
CssGND
1.8V
VOUT4
15
11
16
VOUT3 19
18
1.5V
+3.3VIN
28
1
+12VIN
OCSET2
L2
10
2
VCC
17 12
AIC1573
3
n ORDERING INFORMATION
ORDER NUMBER PIN CONFIGURATION
AIC1573-CX
AIC1573CS
(SO28)
PACKAGING TYPE
S: SMALL OUTLINE
1
3
4
2
5
7
6
8
9
10
VID
1
PHASE2
VID
4
VID
3
UGATE2
VID
2
VSEN2
VID0
OCSET2
PGOOD
11
12
SS
SELECT
PHASE1
VCC
UGATE1
OCSET1
LGATE1
PGND
20
1
9
VSEN1
VSEN
3
FB
1
NC
28
26
27
25
24
23
21
22
1
8
1
7
GND
DRIVE3
13
1
4
VSEN4
FAULT/RT
1
6
15
DRIVE4
VAUX
n ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC ...............…………….....………….........…..……..................... +15V
PGOOD, FAULT and GATE Voltage .....……….....………..….... GND -0.3V to VCC +0.3V
Input, Output , or I/O Voltage ......…...………………………..……............ GND -0.3V to 7V
Recommended Operating Conditions
Supply Voltage; VCC……..…………...........…................... +12V±10%
Ambient Temperature Range ……..……..………................. 0°C~70°C
Junction Temperature Range ……....… .……….................. 0°C~125°C
Thermal Information
Thermal Resistance, θJA
SOIC package …………………………………..…..….............. 70°C/W
SOIC package (with 3in2 of copper) …...… ..…….......…......... 50°C/W
Maximum Junction Temperature (Plastic Package) …………………..……...... 150°C
Maximum Storage Temperature Range ……………………..……….... -65°C ~ 150°C
Maximum Lead Temperature (Soldering 10 sec) …………………………..…... 300°C
AIC1573
4
n ELECTRICAL CHARACTERISTICS (Vcc=12V, TA=25°C, Unless otherwise specified)
PARAMETER TEST CONDITIONS SYMBOL MIN. TYP. MAX. UNIT
VCC SUPPLY CURRENT
Supply Current UGATE1, LGATE1, UGATE2,
DRIVE3 and DRIVE4 open ICC 3 mA
POWER ON RESET
Rising VCC Threshold VOCSET=4.5V V
CCTHR
10.4 V
Falling VCC Threshold VOCSET=4.5V V
CCTHF
8.2 V
Rising VAUX Threshold VAUX
THR
2.5 V
VAUX Threshold Hysteresis VAUX
HYS
500 mV
Rising VOCSET1 Threshold V
OCSETH
1.26 V
OSCILLATOR
Free Running Frequency RT=Open F 170 200 230 KHz
Total Variation 6kΩ<RT to GND<200kΩ -15 +15 %
Ramp. Amplitude RT=open ∆VOSC 1.5 VP-P
DAC AND STANDARD BUCK REGULATOR REFERENCE
DAC (VID0~VID4) Input Low
Voltage VIDL 0.8 V
DAC (VID0~VID4) Input High
Voltage VIDH 2.0 V
DACOUT Voltage Accuracy VDAC=1.8V~3.5V -1.0 +1.0 %
PWM2 Reference Voltage Select < 0.8V 1.5 V
PWM2 Reference Voltage Select > 2.0V 3.3 V
PWM2 Reference Voltage
Tolerance 3 %
1.5V AND 1.8V LINEAR REGULATORS ( OUT3, OUT4)
Regulation 3 %
VSEN3 Regulation Voltage VREG3 1.5 V
VSEN4 Regulation Voltage VREG4 1.8 V
Under-Voltage Level
( VSEN/VREG ) VSEN Rising V
SENUV
75 %
Under-Voltage Hysteresis
(VSEN/VREG ) VSEN Falling 5 %
Output Drive Current ( All
Linears ) VAUX-VDRIVE > 0.6V 20 30 mA
AIC1573
5
n ELECTRICAL CHARACTERISTICS (Continued)
PARAMETER TEST CONDITIONS SYMBOL MIN. TYP. MAX. UNIT
SYNCHRONOUS PWM CONTROLLER AMPLIFIER
DC Gain (G.B.D.) 80 dB
Gain-Bandwidth Product (G.B.D.) GBWP 13 MHz
Slew Rate (G.B.D.) note 1. SR 6 V/µs
PWM CONTROLLER GATE DRIVERS
UGATE1,2 Upper Drive Source VCC=12V, VUGATE = 6V IUGH 0.9 A
UGATE1,2 Upper Drive Sink VUGATE=1V RUGL 2.8 3.5 Ω
Lower Drive Source VCC=12V, VLGATE =1V ILGH 1 A
Lower Drive Sink VLGATE=1V RLGL 2.2 3.0 Ω
PROTECTION
VSEN1 Over-Voltage
( VSEN1/DACOUT) VSEN1 Rising OVP 116 120 %
FAULT Sourcing Current VCC-VFAULT/RT =2.0V IOVP 20 mA
OCSET1,2 Current Source VOCSET=4.5VDC I
OCSET
170 200 230 µA
Soft-Start Current ISS 25 µA
POWER GOOD
VSEN1 Upper Threshold
( VSEN1/DACOUT ) VSEN1 Rising 108 111 %
VSEN1 Under-Voltage
( VSEN1/DACOUT ) VSEN1 Falling 92 95 %
VSEN1 Hysteresis
(VSEN1/DACOUT) Upper and Lower Threshold 2 %
PGOOD Voltage Low IPGOOD=-4mA V
PGOOD
0.4 0.8 V
Note 1. Without internal compensation network, the gain bandwidth product is 13MHz. Being associated with
internal compensation networks, the Bode Plot is shown in Fig. 3, “Internal Compensation Gain of
PWM Error Amplifier”.
AIC1573
6
n TYPICAL PERFORMANCE CHARACTERISTICS
Fig. 1 Soft Start Interval with 4 Outputs and PGOOD
PGOOD
SS
V
OUT3
V
OUT2
V
OUT1
V
OUT4
SS
VDAC=3.5V
VDAC=2V
VDAC=1.3V
Fig. 2 Soft Start Initiates PWM Output
1k 10k 100k 1M
-5
0
5
10
15
20
25
30 90°C
Gain (dB)
Frequency (Hz)
Fig 3. Internal Compensation Gain of PWM Error Amplifier
-40°C
22°C
10k 100k 1M
1k
10k
100k
1M
10M
RT Pull Up to 12V
Resistance (Ω)
Switching Frequency (Hz)
RT Pull Down to GND
Fig. 4
R
T
Resistance vs. Frequency
Switching Frequency (Hz)
200k
30
0
k
400k
500k
600k
700k
8
0
0k
900k
1M
0
20
40
60
80
100
120
140
160
ICC (mA)
VCC=12V
CUG1=CLG1=CUG2=C C=4.7nF
C=3.3nF
C=1.5nF
C=650pF
C=0
Fig. 5 Supply Current vs. Frequency
SS
Inductor
Current 5A/div
Over Load
Applied
Fault
Fig. 6 Over Current ON Inductor
AIC1573
7
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
Fig. 7 Load Transient of Linear Controller
-40
-20
0
20
40
60
80
100
120
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
FSW=200KHz
Fig. 8 Temperature vs. Switching Frequency Drift
Switching Frequency Drift (%)
Temperature (
°
C)
-40
-20
0
20
40
60
80
100
120
-8
-7
-6
-5
-4
-3
-2
-1
0
1
2
3
4
5
6
OCSET Current = 200µA
Fig.
9
Temperature vs. OCSET Current
Drift
OCSET Current Drift (%)
Temperature
(
°
C)
-40 -20 0 20 40 60 80 100 120
-0.8
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-
0
.
1
0.0
0.1
0.2
0.3
0.4
Fig.
10
Temperature Drift of 9 Different Parts
VREG2=3.3V
VSEN2 Voltage Drift (%)
Temperature (
°
C)
-40 -20 020 40 60 80 100 120
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
Fig. 11 Temperature Drift of 13 Different Parts
DACOUT=1.
6
V
PWM Output Voltage Drift (%)
Temperature (°C)
-40
-20
0
20
40
60
80
100
120
-0.7
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
0.3
0.4
Fig. 12 Temperature Drift of 9 Different Parts
VREG4=1.8V
VSEN4 Voltage Drift (%)
Temperature (°C)
AIC1573
8
n TYPICAL PERFORMANCE CHARACTERISTICS (Continued)
VOUT1
0 to 20A Load Step
Fig. 13 Load Transient of PWM Output
0 to 20A Load Step
VOUT1
Fig. 14 Stringent Load Transient of PWM Output
Fig. 15 FB Voltage Accuracy
Number of Parts
Accuracy (%)
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0
10
20
30
40
50
60
70
Ta=25°C
DACOUT=1.6V
3 std.=0.56%
Mean= -0.006%
Fig. 16 VSEN3 Voltage Accuracy
Number of Parts
-1.0 -0.5 0.0 0.5 1.0
0
10
20
30
40
50
60
70
80
Ta = 25°C
Mean = 0.16%
3 std.=1%
Accuracy (%)
AIC1573
9
n BLOCK DIAGRAM
OFF
RAMP2
RAMP1
DACOUT
INHB
OV
VSEN1
POR
SS
RESET
OC1
OC1
UP
LUV
SS
RAMP2
POR
RT
FAULT /
INHB
INHB
VAUX
GATE
CONTROL
VCC
4.5V
25uA
VCC
3 P, 2 Z
Comp.
NC
COMP1
FB1
VCC
VCC
DRV-H
PGND
CONTROL
GATE
DRV-L
RR
R
0.2V
4V
1.5V or 3.3V
VAUX
VAUX
SELECT
DRIVE4
DRIVE3
LOGIC
SOFT START
VSEN4
VSEN3
OCSET2
OCSET1
VCC
PHASE2
UGATE2
VSEN2 PHASE1 UGATE1 LGATE1
GND
SS
VID4
VID3
VID2
VID1
VID0
x 75%
COMP2
DRV2
AMP2
ERROR
CONVERTER
TTL D/A
x 115%
LATCH
CURRENT
200uA
200uA
X 75%
OSCILLATOR
AMP1
ERROR
RESET
POWER ON
x 110%
X 90%
VSEN1 PGOOD
VCC
(3)
COUNTER LATCH
FAULT
OVER
AIC1573
10
n PIN DESCRIPTIONS
Pin 1: UGATE2: External high-side N-MOSFET
gate drive pin. Connect UGATE2
to gate of the external high-side
N-MOSFET .
Pin 2: PHASE2:
Over-current detection pin. Con-
nect the PHASE2 pin to source
of the external high-side N-
MOSFET. This pin detects the
voltage drop across the high-side
N-MOSFET RDS(ON) for over-
current protection.
Pin 7: VID4:
Pin 6: VID3:
Pin 5: VID2:
Pin 4: VID1:
Pin 3: VID0: 5bit DAC voltage select pin. TTL-
compatible inputs used to set the
internal voltage reference VDAC.
When left open, these pins are
internally pulled up to 5V and
provide logic ones. The level of
VDAC sets the converter output
voltage as well as the PGOOD
and OVP thresholds.
Table 1 specifies the VDAC volt-
age for the 32 combinations of
DAC inputs.
Pin 8: PGOOD: Power good indicator pin.
PGOOD is an open drain output.
This pin is pulled low when the
converter output is ±10% out of
the VDAC reference voltage or
the other outputs are below their
under-voltage thresholds. The
PGOOD output is open for VID
codes that inhibit operation. See
Table 1.
Pin 9: OCSET2: Current limit sense pin. Connect
a resistor R
OCSET from this pin to
the drain of the external high-side
N-MOSFET. R
OCSET, an internal
200µA current source (IOCSET),
and the upper N-MOSFET on-
resistance (RDS(ON)) set the over-
current trip point according to the
following equation:
DS(ON)
OCSETOCSET
PEAK RRI
I×
=
Pin 10: VSEN2: Connect this pin to the output of
the standard buck PWM regula-
tor. The voltage at this pin is
regulated to the 1.5V/3.3V prede-
termined by the logic Low/High
level status of the SELECT pin.
This pin is also monitored by the
PGOOD comparator circuit.
Pin 11: SELECT: This pin determines the output
voltage of the AGP bus switching
regulator. A low TTL input sets
the output voltage to 1.5V, while
a high input sets the output volt-
age to 3.3V.
Pin 12: SS: Soft-start pin. Connect a capaci-
tor from this pin to ground. This
capacitor, along with an internal
25µA (typically) current source,
sets the soft-start interval of the
converter. Pulling this pin low will
shut down the IC.
Pin 13: FAULT/RT: Frequency adjustment pin.
Connecting a resistor (RT) from
this pin to GND, increasing the
frequency. Connecting a resistor
(RT) from this pin to VCC, de-
AIC1573
11
creasing the frequency by the
following figure (Fig.3).
This pin is 1.26V during normal
operation, but it is pulled to VCC
in the event of an over-voltage or
over-current condition.
+= T
RK.
ff 225
1
0,
RT pulled to GND
×
−
−= T
RVVCC
ff 526.1
1
0,
RT pulled to VCC,
where 0
fis free run frequency.
Pin14: VSEN4: Connect this pin to the 1.8V
linear regulator’s output. This pin
is monitored for under-voltage
events.
Pin15: DRIVE4: Connect this pin to the gate of
the external N-MOS to supply
1.8V power for Memorey re-
quirement.
Pin 16: VAUX: The +3.3V input voltage at this
pin is monitored for power-on –
reset (POR) purpose. Connect to
+5V provides boost current for
the linear regulator’s output.
Pin 17: GND: Signal GND for IC. All voltage
levels are measured with respect
to this pin.
Pin 18: DRIVE3: Connect this pin to the Gate of
the external N-MOS for providing
1.5V power to GTL bus.
Pin 19: VSEN3: Connect this pin to the 1.5V
linear regulator’s output. This pin
is monitored for under-voltage
events.
Pin 20: COMP1: External compensation pin of the
synchronous PWM converter.
This pin is connected to error
amplifier output and PWM com-
parator. A RC network is con-
nected to FB1 in to compensate
the voltage control feedback loop
of the converter.
Pin 21: FB1: The error amplifier inverting input
pin of the synchronous PWM
converter. The FB1 pin and
COMP1 pin are used to compen-
sate the voltage-control feedback
loop.
Pin 22: VSEN1: Synchronous PWM converter’s
output voltage sense pin. Con-
nect this pin to the converter out-
put. The PGOOD and OVP com-
parator circuits use this signal to
report output voltage status and
for over-voltage protection func-
tion.
Pin 23: OCSET1: Current limit sense pin. Connect
a resistor ROCSET from this pin to
the drain of the external high-side
N-MOSFET. R
OCSET, an internal
200µA current source (IOCSET),
and the upper N-MOSFET on-
resistance (RDS(ON)) set the over-
current trip point according to the
following equation:
DS(ON)
OCSETOCSET
PEAK RRI
I×
=
The voltage at this pin is also
moni tored for power-on reset
(POR) purpose.
Pin 24: PGND: Driver power GND pin. PGND
should be connected to a low im-
pedance ground plane in close to
lower N-MOSFET source.
Pin 25: LGATE1: Lower N-MOSFET gate drive pin
of the synchronous PWM con-
verter.
Pin 26: PHASE1:
Over-current detection pin. Con-
AIC1573
12
nect the PHASE1 pin to source
of the external high-side N-
MOSFET. This pin detects the
voltage drop across the high-side
N-MOSFET RDS(ON) for over-
current protection.
Pin 27: UGATE1:External high-side N-MOSFET
gate drive pin. Connect UGATE1
to the synchronous PWM con-
verter’s gate of the external high-
side N-MOSFET .
Pin 28: VCC: The chip power supply pin. It also
provides the gate bias charge for
all the MOSFETs controlled by
the IC. Recommended supply
voltage is 12V. The voltage at this
pin is monitored for Power-On-
Reset purpose.
n APPLICATIONS INFORMATION
The AIC1573 is designed for microprocessor com-
puter applications with 3.3V and 5V power, and
12V bias input. This IC has two PWM controller
and two linear controllers. The first PWM (PWM1)
controller is designed to regulate the microproces-
sor core voltage (VOUT1) by driving 2 MOSFETs
(Q1 and Q2) in a synchronous rectified buck con-
verter configuration. The core voltage is regulated to
a level programmed by the 5 bit D/A converter. The
second PWM (PWM2) controller is designed to
regulate the advanced graphics port (AGP) bus
voltage (VOUT2). PWM2 One of the linear control-
lers is designed to regulate the advanced graphic
port (AGP) bus voltage (VOUT2). PWM2 controller
drives a MOSFET (Q3) in a standard buck converter
and regulates the output voltage to a digitally-
programmable level of 1.5V or 3.3V.Selection of
either output voltage is achieved by applying the
proper logic level at the SELECT pin. The two linear
controllers supply the 1.5V GTL bus power (VOUT3)
and 1.8V memory power (VOUT4).
The Power-On-Reset (POR) function continually
monitors the input supply voltage +12V at VCC pin,
the 5V input voltage at OCSET pin, and the 3.3V
input at VAUX pin. The POR function initiates soft-
start operation after all three input supply voltage
exceeds their POR thresholds.
Soft-Start
The POR function initiates the soft-start sequence.
An internal 25µA current source charges an exter-
nal capacitor (CSS) on the SS pin to 4.5V. The
PWM error amplifier reference input (Non-inverting
terminal) and output (COMP1 pin) is clamped to a
level proportional to the SS pin voltage. As the SS
pin voltage slew from 1V to 4V, the output clamp
generates PHASE pulses of increasing width that
charge the output capacitors. After the output volt-
age increases to approximately 70% of the set
value, the reference-input clamp slows the output
voltage rate-of-rise and provides a smooth transition
to the final set voltage. Additionally, all linear regu-
lator’s reference inputs are clamped to a voltage
proportional to the SS pin voltage. This method
provides a rapid and controlled output voltage rise.
Fig.1 and Fig.2 show the soft-start sequence for the
typical application. The internal oscillator’s triangu-
lar waveform is compared to the clamped error am-
plifier output voltage. As the SS pin voltage in-
creases, the pulse width on PHASE pin increases.
The interval of increasing pulse width continues un-
til output reaches sufficient voltage to transfer con-
trol to the input reference clamp.
AIC1573
13
Each linear output initially follows a ramp. When
each output reaches sufficient voltage the input ref-
erence clamp slows the rate of output voltage rise.
The PGOOD signal toggles ‘high’ when all output
voltage levels have exceeded their under-voltage
levels.
Fault Protection
All four outputs are monitored and protected
against extreme overload. A sustained overload on
any output or over-voltage on PWM1 output dis-
ables all outputs and drive the FAULT/RT pin to
VCC.
+
+
0.15V
OV
Over Current
Latch
4.0V
SS
OC1
R
LUV
Q
S
Fault
VCC
Fault Latch
POR
Q
R
S
R
S
Counter
INHIBIT
OC2
Fig. 17 Simplified Schematic of Fault Logic
A simplified schematic is shown in figure 17. An
over-voltage detected on VSEN1 immediately sets
the fault latch. A sequence of three over-current
fault signals also sets the fault latch. The over-
current latch is set dependent on the status of the
over-current (OC1 and OC2), linear under-voltage
(LUV) and the soft-start signal. An under-voltage
event on either linear output (VSEN3, VSEN4) is
ignored until the soft-start interval. Cycling the bias
input voltage (+12V off then on) resets the counter
and the fault latch.
Gate Drive Overlap Protection
The Overlap Protection circuit ensures that the Bot-
tom MOSFET does not turn on until the Upper
MOSFET source has reached a voltage low enough
to ensure that shoot-through will not occur.
Over-Voltage Protection
During operation, a short on the upper PWM1
MOSFET (Q1) causes VOUT1 to increase. When
the output exceed the over-voltage threshold of
116% of DACOUT, the FAULT pin is set to fault
latch and turns Q2 on as required in order to regu-
late VOUT1 to 116% of DACOUT. The fault latch
raises the FAULT/RT pin close to VCC potential.
A separate over-voltage circuit provides protection
during the initial application of power. For voltage on
VCC pin below the power-on reset (and above ~4V),
Should VSEN1 exceed 1.0V, the lower MOSFET
(Q2) is driven on as needed to regulate VOUT1 to
1.0V.
AIC1573
14
Over-Current Protection
All outputs are protected against excessive over-
current. Both PWM controller uses upper
MOSFET’s on-resistance, RDS(ON) to monitor the
current for protection against shorted outputs. All
linear controllers monitor VSEN for under-voltage to
protect against excessive current.
When the voltage across Q1 (ID•RDS(ON)) exceeds
the level (200µA•ROCSET), this signal inhibit all
outputs. Discharge soft-start capacitor (Css) with
28µA current sink, and increments the counter.
Css recharges and initiates a soft-start cycle again
until the counter increments to 3. This sets the fault
latch to disable all outputs. Fig. 6 illustrates the
over-current protection until an over load on OUT1.
Should excessive current cause VSEN to fall below
the linear under-voltage threshold, the LUV signal
sets the over-current latch if Css is fully charged.
Cycling the bias input power (off then on reset the
counter and the fault latch.
The over-current function for PWM controller will trip
at a peak inductor current (IPEAK) determined by:
IIR
R
PEAK OCSET OCSET
DS(ON)
=×
The OC trip point varies with MOSFET’s tempera-
ture. To avoid over-current tripping in the normal op-
erating load range, determine the R
OCSET resistor
from the equation above with:
1. The maximum RDS(ON) at the highest junction.
2. The minimum IOCSET from the specification table.
3. Determine IPEAK > IOUT(MAX) + (inductor ripple
current) /2.
OUT1 Voltage Program
The output voltage of the PWM1 converter is pro-
grammed to discrete levels between 1.3V to 3.5V.
The VID pins program an internal voltage reference
(DACOUT) through a TTL compatible 5 bit digital to
analog converter. The VID pins can be left open for
a logic 1 input, because they are internally pulled
up to 5V by a 70kΩ resistor. Changing the VID in-
puts during operation is not recommended. ‘11111’
VID pin combinations disable the IC and open the
PGOOD pin.
OUT2 Voltage Selection
The AGP regulator output voltage is internally set to
one of two discrete levels, based on the SELECT
pin status. Left SELECT pin open, internal pulled
high, the output voltage is 3.3V. Grounding SE-
LECT pin will get the 1.5V output voltage.
The status of the SELECT pin can not be changed
during operation of the IC without immediatelly
causing a fault condition.
Shutdown
Neither PWM output switches until the soft-start
voltage exceeds the oscillator’s vally voltage. Addi-
tional, the reference on each linear’s amplifier is
clamped to the soft-start voltage. Holding the SS
pin low turns of all four regulators.
The VID codes resulting in an INHIBIT as shown in
Table 1 also shut down the IC.
Oscillator Synchronization
The AIC1573 avoids the problem of cross talk be-
tween the converters by way of phase control
method. Therefore, for both output voltage settings
less than 2.4V or both greater than 2.4V, PWM1
operates out of phase with PWM2. For one PWM
output voltage setting below 2.4V and the other
PWM output voltage setting of 2.4V and above,
PWM1 operates in phase with PWM2.
AIC1573
15
UGATE1
UGATE2
@VOUT2=3.3V
@VOUT1=1.7V
Fig. 18 PWM1 operates in phase with PWM2
UGATE1
UGATE2
@VOUT1=1.7V
@VOUT2=1.5V
Fig. 19 PWM1 operates out of phase with PWM2
Table 1 VOUT1 Voltage Program ( 0=connected to GND, 1=open or connected to 5V )
For all package version
PIN NAME PIN NAME
VID4 VID3 VID2 VID1 VID0
DACOUT
VOLTAGE VID4 VID3 VID2 VID1 VID0
DACOUT
VOLTAGE
0 1 1 1 1 1.30V 1 1 1 1 1 INHIBIT
0 1 1 1 0 1.35V 1 1 1 1 0 2.1 V
0 1 1 0 1 1.40V 1 1 1 0 1 2.2 V
0 1 1 0 0 1.45V 1 1 1 0 0 2.3 V
0 1 0 1 1 1.50V 1 1 0 1 1 2.4 V
0 1 0 1 0 1.55V 1 1 0 1 0 2.5 V
0 1 0 0 1 1.60V 1 1 0 0 1 2.6 V
0 1 0 0 0 1.65V 1 1 0 0 0 2.7 V
0 0 1 1 1 1.70V 1 0 1 1 1 2.8 V
0 0 1 1 0 1.75V 1 0 1 1 0 2.9 V
0 0 1 0 1 1.80 V 1 0 1 0 1 3.0 V
0 0 1 0 0 1.85 V 1 0 1 0 0 3.1 V
0 0 0 1 1 1.90 V 1 0 0 1 1 3.2 V
0 0 0 1 0 1.95 V 1 0 0 1 0 3.3 V
0 0 0 0 1 2.00 V 1 0 0 0 1 3.4 V
0 0 0 0 0 2.05 V 1 0 0 0 0 3.5 V
AIC1573
16
Layout Considerations
Any inductance in the switched current path gener-
ates a large voltage spike during the switching in-
terval. The voltage spikes can degrade efficiency,
radiate noise into the circuit, and lead to device
over-voltage stress. Careful component selection
and tight layout of critical components, and short,
wide metal trace minimize the voltage spike.
A ground plane should be used. Locate the input
capacitors (CIN) close to the power switches.
Minimize the loop formed by C
IN, the upper
MOSFET (Q1) and the lower MOSFET (Q2) as
possible. Connections should be as wide as short
as possible to minimize loop inductance.
The connection between Q1, Q2 and output induc-
tor should be as wide as short as practical. Since
this connection has fast voltage transitions will ea-
sily induce EMI.
The output capacitor (COUT) should be located as
close the load as possible. Because minimize the
transient load magnitude for high slew rate requires
low inductance and resistance in circuit board
The AIC1573 is best placed over a quiet ground
plane area. The GND pin should be connected to
the groundside of the output capacitors. Under no
circumstances should GND be returned to a ground
inside the C
IN, Q1, Q2 loop. The GND and PGND
pins should be shorted right at the IC. This help to
minimize internal ground disturbances in the IC and
prevents differences in ground potential from dis-
rupting internal circuit operation.
The wiring traces from the control IC to the MOS-
FET gate and source should be sized to carry 1A
current. The traces for OUT2 need only be sized
for 0.5A. Locate COUT2 close to the AIC1573.
The Vcc pin should be decoupled directly to GND
by a 2.2µF ceramic capacitor, trace lengths
should be as short as possible.
A multi-layer-printed circuit board is recommended.
Figure 11 shows the connections of the critical
components in the converter. The C
IN and C
OUT
could each represent numerous physical capacitors.
Dedicate one solid layer for a ground plane and
make all critical component ground connections
with vias to this layer.
PWM Output Capacitors
The load transient for the microprocessor core re-
quires high quality capacitors to supply the high
slew rate (di/dt) current demand.
The ESR (equivalent series resistance) and ESL
(equivalent series inductance) parameters rather
than actual capacitance determine the buck ca-
pacitor values. For a given transient load magnitude,
the output voltage transient change due to the out-
put capacitor can be note by the following equation:
∆ ∆ ∆
∆
VESR IESL IT
OUT OUT OUT
= × + × , where
∆
I
OUT is transient load current step.
After the initial transient, the ESL dependent term
drops off. Because the strong relationship between
output capacitor ESR and output load transient, the
output capacitor is usually chosen for ESR, not for
capacitance value. A capacitor with suitable ESR
will usually have a larger capacitance value than is
needed for energy storage.
A common way to lower ESR and raise ripple cur-
rent capability is to parallel several capacitors. In
most case, multiple electrolytic capacitors of small
case size are better than a single large case ca-
pacitor.
AIC1573
17
Output Inductor Selection
Inductor value and type should be chosen based on
output slew rate requirement, output ripple require-
ment and expected peak current. Inductor value is
primarily controlled by the required current respon-
se time. The AIC1573 will provide either 0% or
100% duty cycle in response to a load transient.
The response time to a transient is different for the
application of load and remove of load.
tLI
V V
RISE OUT
IN OUT
=×
−
∆
,
t=LI
V
FALL OUT
OUT
×∆
. Where
∆
I
OUT is transient
load current step.
In a typical 5V input, 2V output application, a 3µH
inductor has a 1A/µS rise time, resulting in a 5µS
delay in responding to a 5A load current step. To
optimize performance, different combinations of in-
put and output voltage and expected loads may re-
quire different inductor value. A smaller value of in-
ductor will improve the transient response at the
expense of increase output ripple voltage and in-
ductor core saturation rating.
Peak current in the inductor will be equal to the
maximum output load current plus half of inductor
ripple current. The ripple current is approximately
equal to:
I=(V V)V
LV
RIPPLE IN OUT OUT
IN
−
×
× ×f;
f = AIC1573 oscillator frequency.
The inductor must be able to withstand peak cur-
rent without saturation, and the copper resistance
in the winding should be kept as low as possible to
minimize resistive power loss
Input Capacitor Selection
Most of the input supply current is supplied by the
input bypass capacitor, the resulting RMS current
flow in the input capacitor will heat it up. Use a mix
of input bulk capacitors to control the voltage over-
shoot across the upper MOSFET. The ceramic ca-
pacitance for the high frequency decoupling should
be placed very close to the upper MOSFET to sup-
press the voltage induced in the parasitic circuit
impedance. The buck capacitors to supply the
RMS current is approximate equal to:
I(1 D) DI1
12 VD
fL
RMS 2OUT IN 2
= − × × + × ×
×
, where DV
V
OUT
IN
=
The capacitor voltage rating should be at least 1.25
times greater than the maximum input voltage.
PWM MOSFET Selection
In high current PWM application, the MOSFET
power dissipation, package type and heatsink are
the dominant design factors. The conduction loss is
the only component of power dissipation for the
lower MOSFET, since it turns on into near zero
voltage. The upper MOSFET has conduction loss
and switching loss. The gate charge losses are
proportional to the switching frequency and are dis-
sipated by the AIC1573. However, the gate charge
increases the switching interval, tSW, which increase
the upper MOSFET switching losses. Ensure that
both MOSFETs are within their maximum junction
temperature at high ambient temperature by calcu-
lating the temperature rise according to package
thermal resistance specifications.
PIR D IVt f
2
UPPER OUT2DS(ON) OUT IN SW
= × × + × × ×
PIRD)LOWER OUT2DS(ON)= × × −(1
The equations above do not model power loss due
to the reverse recovery of the lower MOSFET’s bo-
dy diode.
The RDS(ON) is different for the two previous equa-
tions even if the type devices is used for both. This
AIC1573
18
is because the gate drive applied to the upper
MOSFET is different than the lower MOSFET.
Logic level MOSFETs should be selected based on
on-resistance considerations, RDS(ON) should be
chosen base on input and output voltage, allowable
power dissipation and maximum required output
current. Power dissipation should be calculated
based primarily on required efficiency or allowable
thermal dissipation.
Rectifier Schottky diode is a clamp that prevent the
loss parasitic MOSFET body diode from conducting
during the dead time between the turn off of the
lower MOSFET and the turn on of the upper
MOSFET. The diode’s rated reverse breakdown
voltage must be greater than twice the maximum
input voltage.
Linear Controller MOSFET Selection
The power dissipated in a linear regulator is:
)V(VIPOUTIN OUTLINEAR −×=
Select a package and heatsink that maintains junc-
tion temperature below the maximum rating while
operation at the highest expected ambient tempera-
ture.
Linear Output Capacitor
The output capacitors for the linear regulator and
linear controller provide dynamic load current. The
linear controller uses dominant pole compensation
integrated in the error amplifier and is insensitive to
output capacitor selection. COUT3 and COUT4
should be selected for transient load regulation. The
output capacitor for the linear regulator provides
loop stability.
PWM Feedback Analysis
+
VDAC VOUT
VEA
PWM COMP.
Networks
Compensation
ERROR AMP.
R
ESR
LO
∆
VOSC
CO
Q2
Q1
VIN
Modulation
Gain
Fig 20. Control Loop
The compensation network consists of the error
amplifier and built in compensation networks. The
goal of the compensation network is to provide for
fast response and adequate phase margin. Phase
Margin is the difference between the closed loop
phase at 0dB and 180 degree.
Closed Loop Gain(dB) = Modulation Gain(dB) +
Compensation Gain (dB)
Modulation Gain(dB)
++
∆
≈2
1log10log20 ESROSC
IN FF
V
V
AIC1573
19
×
+
−− 2
2
2
1log10 QFF
FF
LCLC
where
OO
LC CL
Fπ21
=;
OESR
ESR CR
F××
=π21;
LOADO
O
ESR
O
ORC
L
R
L
C
Q11 ×+×=
The break frequency of Internal Compensation Gain
are given by
KHzFZ6.2
1=;
KHzFZ24
2=;
KHzFP30
1=;
KHzFP400
2=
100 1k 10k 100k 1M 10M
-20
0
20
40
60
F
Frequency (KHz)
FOdB
20log(V
IN
/δV
OSC
)
FESR
FLC
FZ1 FZ2
FP2
FP1
Modulation
Gain
Compensation Gain
Closed Loop
Gain
Gain (dB)
Fig. 21 Bode Plot of Converter Gain
Bode Plot of Converter Gain
Sampling theory shows that F0dB must be less that
half the switching frequency for the loop stables.
But it must be considerably less than that, or there
will be large amplitude switching frequency ripple at
the output. Thus, the usual practices is to fix F0dB
at 1/4 to 1/5 the switching frequency.
n PHYSICAL DIMENSIONS
l 28 LEAD PLASTIC SO (unit: mm)
SYMBOL MIN MAX
A2.35 2.65
A1 0.10 0.30
B0.33 0.51
C0.23 0.32
D17.70 18.10
E7.40 7.60
e1.27 (TYP)
H10.00 10.65
L0.40 1.27
D
CL
E
H
e
B
A
A1
