1Gb: x8, x16 NAND Flash Memory Features 1Gb NAND Flash Memory MT29F1GxxABB Features Figure 1: * Organization - Page size x8: 2,112 bytes (2,048 + 64 bytes) - Page size x16: 1,056 words (1,024 + 32 words) - Block size: 64 pages (128K + 4K bytes) - Device size: 1Gb: 1,024 blocks * READ performance - Random READ: 25s (MAX) - Sequential READ: 50ns (MIN) * WRITE performance - PROGRAM PAGE: 250s (TYP) - BLOCK ERASE: 2.0ms (TYP) * Endurance: 100,000 PROGRAM/ERASE cycles * Data retention: 10 years * The first block (block address 00h) is guaranteed to be valid without ECC (up to 1,000 PROGRAM/ ERASE cycles) * VCC: 1.65-1.95V * Automated PROGRAM and ERASE * Basic NAND Flash command set - PAGE READ, RANDOM DATA READ, READ ID, READ STATUS, PROGRAM PAGE, RANDOM DATA INPUT, PROGRAM PAGE CACHE MODE, INTERNAL DATA MOVE, INTERNAL DATA MOVE with RANDOM DATA INPUT, BLOCK ERASE, RESET * New commands - PAGE READ CACHE MODE - READ ID2 (contact factory) - READ UNIQUE ID (contact factory) - Programmable I/O - OTP - BLOCK LOCK * Operation status byte: Provides a software method for detecting: - Operation completion - Pass/fail condition - Write-protect status * Ready/busy# signal (R/B#): Provides a hardware method of detecting operation completion * LOCK signal: Protects selectable ranges of blocks PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__1.fm - Rev. E 1/08 EN 63-Ball VFBGA x8 * WP# signal: Write-protects the entire device * Reset required after power-up Options1 * Configuration - x8 - x16 * Package - 63-ball VFBGA 13mm x 10.5mm x 1.0mm * Operating temperature - Commercial temperature (0 to +70C) - Extended temperature (-40C to +85C) Notes: 1. For part numbers and device markings, see Figure 2 on page 2. 1 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1Gb: x8, x16 NAND Flash Memory Part Numbering Information Part Numbering Information Micron NAND Flash devices are available in several configurations and densities. Figure 2: Part Number Chart MT 29F 1G 08 A B B HC xx xx xx ES :B Micron Technology Die Revision Product Family B = Second generation 29F = Single-Supply NAND Flash Memory Production Status Density Blank = Production 1G = 1Gb ES = Engineering Sample QS = Qualification Sample Device Width 08 = 8 bits Operating Temperature Range 16 = 16 bits Blank = Commercial (0C to +70C) ET = Extended (-40 to +85C) Classification # of die # of CE# # of R/B# I/O A 1 1 1 Block Option Common Reserved for Future Use Flash Performance Operating Voltage Range Reserved for Future Use B = 1.8V (1.65V-1.95V) Package Codes Feature Set HC = 63-pin VFBGA (lead-free) A = Feature set A B = Feature set B Valid Part Number Combinations After building the part number from the part numbering chart, verify that the part number is offered and valid by using the Micron Parametric Part Search Web site at www.micron.com/products/parametric. If the device required is not on this list, contact the factory. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__1.fm - Rev. E 1/08 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Table of Contents Table of Contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 READY/BUSY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 RANDOM READ 05h-E0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh. . . . . . . . . . . . . . . 25 READ ID 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ONFI READ ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ONFI READ PARAMETER PAGE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RANDOM DATA INPUT 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PROGRAM PAGE CACHE MODE 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 INTERNAL DATA MOVE Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 READ FOR INTERNAL DATA MOVE 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 INTERNAL DATA MOVE 85h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 BLOCK ERASE 60h-D0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 One-Time Programmable (OTP) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 OTP DATA PROGRAM A0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 OTP DATA PROTECT A5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 OTP DATA READ AFh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 BLOCK LOCK Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 WP# and BLOCK LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 UNLOCK 23h-24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 LOCK 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 LOCK-TIGHT 2Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 BLOCK LOCK READ STATUS 7Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Programmable Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 PROGRAMMABLE I/O DRIVE STRENGTH B8h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 WRITE PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48aTOC.fm - Rev. E 1/08 EN 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory List of Figures List of Figures Figure 1: Figure 2: Figure 3: Figure 4: Figure 5: Figure 6: Figure 7: Figure 8: Figure 9: Figure 10: Figure 11: Figure 12: Figure 13: Figure 14: Figure 15: Figure 16: Figure 17: Figure 18: Figure 19: Figure 20: Figure 21: Figure 22: Figure 23: Figure 24: Figure 25: Figure 26: Figure 27: Figure 28: Figure 29: Figure 30: Figure 31: Figure 32: Figure 33: Figure 34: Figure 35: Figure 36: Figure 37: Figure 38: Figure 39: Figure 40: Figure 41: Figure 42: Figure 43: Figure 44: Figure 45: Figure 46: Figure 47: Figure 48: Figure 49: Figure 50: Figure 51: Figure 52: Figure 53: Figure 54: Figure 55: Figure 56: 63-Ball VFBGA x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional Block Diagram: 1Gb NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Ball Assignment (x8), 63-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Ball Assignment (x16), 63-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Array Organization for MT29F1G08 (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Array Organization for MT29F1G16 (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Memory Map (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Memory Map (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 PAGE READ CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 ONFI READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 ONFI READ PARAMETER PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Status Register Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 OTP DATA PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 OTP DATA PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 OTP DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Flash Array Protected: Inverted Area Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Flash Array Protected: Invert Area Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 UNLOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 LOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 LOCK-TIGHT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 PROGRAM/ERASE Issued to Locked or Locked-Tight Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 LOCKED-TIGHT BLOCKS to LOCKED BLOCKS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 BLOCK LOCK READ STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 BLOCK LOCK Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Programmable I/O Drive Strength Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 AC Waveforms During Power Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 SERIAL ACCESS Cycle after READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 READ Operation with CE# "Don't Care" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 PAGE READ CACHE MODE Operation, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 PAGE READ CACHE MODE Operation, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48aLOF.fm - Rev. E 1/08 EN 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory List of Figures Figure 57: Figure 58: Figure 59: Figure 60: Figure 61: Figure 62: Figure 63: Figure 64: Figure 65: Figure 66: Figure 67: PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PROGRAM Operation with CE# "Don't Care" . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 INTERNAL DATA MOVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PROGRAM PAGE CACHE MODE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 PROGRAM PAGE CACHE MODE Operation Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 63-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48aLOF.fm - Rev. E 1/08 EN 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory List of Tables List of Tables Table 1: Table 2: Table 3: Table 4: Table 5: Table 6: Table 7: Table 8: Table 9: Table 10: Table 11: Table 12: Table 13: Table 14: Table 15: Table 16: Table 17: Table 18: Table 19: Table 20: Table 21: Table 22: Table 23: Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Array Addressing: MT29F1G08 (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Array Addressing: MT29F1G16 (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Operational Example (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Operational Example (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Device ID and Configuration Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Status Register Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 BLOCK LOCK Address Cycle Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 BLOCK LOCK Status Register Bit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Status Register Contents After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 I/O Drive Strength Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Programmable I/O Drive Strength Register READ/WRITE Timing . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Absolute Maximum Ratings by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 DC and Operating Characteristics, VCC = 1.65-1.95V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 AC Characteristics - Command, Data, and Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 AC Characteristics - Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48aLOT.fm - Rev. E 1/08 EN 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory General Description General Description The MT29F1G08 and MT29F1G16 are both 1Gb NAND Flash memory devices. NAND Flash technology provides a cost-effective solution for applications requiring high-density, solid-state storage. The MT29F1Gxx devices include standard NAND Flash features as well as new features designed to enhance system-level performance. The MT29F1Gxx devices use a multiplexed 8- or 16-bit bus (I/O[7:0] or I/O[15:0]) to transfer data, address, and instruction information. The five control signals (CLE, ALE, CE#, RE#, WE#) control the NAND Flash command bus interface protocol. Additional signals control hardware write protection (WP#), monitor the device ready/busy (R/B#) state, and enable BLOCK LOCK functions (LOCK). This hardware interface creates a low-ball-count device with a standard ball arrangement that is the same from one density to another, enabling future upgrades to higher densities without any board redesign. MT29F1Gxx devices contain 1,024 erasable blocks. Each block is subdivided into 64 programmable pages. Each page consists of 2,112 bytes (x8), or 1,056 words (x16). The pages are further divided into a 2,048-byte data storage region with a separate 64-byte area on the x8 device; and on the x16 device, separate 1,024-word and 32-word areas. The 64byte and 32-word areas are typically used for error correction functions. On-chip control logic automates PROGRAM and ERASE operations to maximize cycle endurance. PROGRAM/ERASE endurance is specified at 100,000 cycles when using appropriate error correction code (ECC) and bad-block-management software. Figure 1: Functional Block Diagram: 1Gb NAND Flash VCC I/O [7:0] I/O [15:0] I/O Control VSS Address Register Status Register Command Register CE# Column Decode CLE ALE Control Logic Row Decode WE# RE# WP# LOCK Data Register Cache Register R/B# PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory General Description Figure 2: Ball Assignment (x8), 63-Ball VFBGA 1 2 A NC NC B NC 3 4 5 6 7 8 C WP# ALE Vss CE# WE# R/B# D NC RE# CLE NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC LOCK NC NC NC H NC I/O0 NC NC NC Vcc I NC I/O1 NC Vcc I/O5 I/O7 J Vss I/O2 I/O3 I/O4 I/O6 Vss 9 10 NC NC NC NC K NC NC NC NC L NC NC NC NC Top View, Ball Down Notes: 1. For package dimensions, see Figure 65 on page 69. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory General Description Figure 3: Ball Assignment (x16), 63-Ball VFBGA 1 2 A NC NC B NC 3 4 5 6 7 8 C WP# ALE Vss CE# WE# R/B# D NC RE# CLE NC NC NC E NC NC NC NC NC NC F NC NC NC NC NC NC G NC NC LOCK I/O5 I/O7 NC H I/O8 I/O1 I/O10 I/O12 I/O14 Vcc I I/O0 I/O9 I/O3 Vcc I/O6 I/O15 J Vss I/O2 I/O11 I/O4 I/O13 Vss 9 10 NC NC NC NC K NC NC NC NC L NC NC NC NC Top View, Ball Down Notes: 1. For package dimensions, see Figure 65 on page 69. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory General Description Table 1: Ball Descriptions Symbol Type Ball Function ALE Input CE# Input CLE Input LOCK Input RE# WE# WP# Input Input Input I/O[7:0] (x8) I/O Address latch enable: During the time ALE is HIGH, address information is transferred from I/O[7:0] into the on-chip address register. Upon a LOW to HIGH transition on WE#--when address information is not being loaded--the ALE signals should be driven LOW. Chip enable: Gates transfers between the host system and the NAND Flash device. After the device becomes busy or starts a PROGRAM or ERASE operation, CE# can be de-asserted. See "Bus Operation" on page 16 for additional operational details. Command latch enable: When CLE is HIGH, information is transferred from I/O [7:0] to the on-chip command register on the rising edge of WE#. When command information is not being loaded, the CLE signals should be driven LOW. When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled. To disable BLOCK LOCK, connect LOCK to VSS during power-up, or leave it unconnected (internal pull-down). Read enable: Gates transfers from the NAND Flash device to the host system. Write enable: Gates transfers from the host system to the NAND Flash device. Write protect: Protects against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when WP# is LOW. Data inputs/outputs: Bidirectional I/O signals transfer address, data and instruction information. Data is output only during READ operations; at other times the I/O signals are inputs. I/O[15:0] (x16) R/B# Output VCC VSS NC Supply Supply - PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Ready/busy: The ready/busy signal is an open-drain, active-LOW output, that uses an external pull-up resistor. The signal is used to indicate when the chip is processing a PROGRAM or ERASE operation. The signal is also used during READ operations to indicate when data is being transferred from the array into the serial data register. When these operations have completed, the ready/busy signal returns to the highimpedance state. VCC: The VCC ball is the power supply. VSS: The VSS ball is the ground connection. No connect: NC balls are not internally connected. These balls can be driven or left unconnected. 10 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Architecture Architecture The MT29F1G08 and MT29F1G16 use NAND Flash electrical and command interfaces. Data, commands, and addresses are multiplexed onto the same signals. This provides a memory device with a low ball count. The internal memory array is accessed on a page basis. When performing READs, a page of data is copied from the memory array into the data register. Once copied to the data register, data is output sequentially, byte by byte on the x8 device, or word by word on the x16 device. The memory array is programmed on a page basis. After the starting address is loaded into the internal address register, data is sequentially written to the internal data register up to the end of a page. After all page data has been loaded into the data register, array programming is started. In order to increase programming bandwidth, this device incorporates a cache register. In the cache programming mode, data is first copied into the cache register and then into the data register. Once the data is copied into the data register, programming begins. After the data register has been loaded and programming has started, the cache register becomes available for loading additional data. Loading the next page of data into the cache register takes place while page programming is in process. The INTERNAL DATA MOVE command also uses the internal cache register. Normally, moving data from one area of external memory to another uses a large number of external memory cycles. By using the internal cache register and data register, array data can be copied from one page and then programmed into another without using external memory cycles. Addressing The MT29F1G08 and MT29F1G16 devices do not have dedicated address balls. Addresses are loaded using a 4-cycle sequence as shown in Tables 2 and 3 on pages 12 and 13. Table 2 presents address functions internal to the MT29F1G08 device; Table 3 presents address functions internal to the MT29F1G16. See Figures 6 and 7 on pages 14 and 15 for additional memory mapping and addressing details. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Addressing Figure 4: Array Organization for MT29F1G08 (x8) 2,112 bytes I/O 0 Cache register 2,048 64 Data register 2,048 64 1 page = (2K + 64 bytes) 1 block = (2K + 64) bytes x 64 pages = (128K + 4K) bytes 1 block 1,024 blocks per device Table 2: I/O 7 1 device = (2K + 64) bytes x 64 pages x 1,024 blocks = 1,056 Mbits Array Addressing: MT29F1G08 (x8) Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 First Second Third Fourth CA7 LOW BA7 BA15 CA6 LOW BA6 BA14 CA5 LOW PA5 BA13 CA4 LOW PA4 BA12 CA3 CA11 PA3 BA11 CA2 CA10 PA2 BA10 CA1 CA9 PA1 BA9 CA0 CA8 PA0 BA8 Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. Note that the 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8 device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page are "out of bounds," do not exist in the device, and cannot be addressed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Addressing Figure 5: Array Organization for MT29F1G16 (x16) 1,056 words I/O 0 Cache register 1,024 32 Data register 1,024 32 Cycle First Second Third Fourth 1 page = (1K + 32) words 1 block = (1K + 32) words x 64 pages = (64K + 2K) words 1 block 1,024 blocks per device Table 3: I/O 15 1 device = (1K + 32) words x 64 pages x 1,024 blocks = 1,056 Mbits Array Addressing: MT29F1G16 (x16) I/O[15:8] I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 LOW LOW LOW LOW CA7 LOW BA7 BA15 CA6 LOW BA6 BA14 CA5 LOW PA5 BA13 CA4 LOW PA4 BA12 CA3 LOW PA3 BA11 CA2 CA10 PA2 BA10 CA1 CA9 PA1 BA9 CA0 CA8 PA0 BA8 Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address. 2. I/O[15:8] are not used during addressing sequence and should be driven LOW. 3. Note that the 11-bit column address is capable of addressing from 0 to 2,047 words on a x16 device; however, only words 0 through 1,055 are valid. Words 1,056 through 2,047 of each page are "out of bounds," do not exist in the device, and cannot be addressed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 13 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Addressing Memory Mapping Figure 6: Memory Map (x8) Blocks BA[15:6] 0 1 2 * * * * * * * * * * * * 1,023 Pages PA[5:0] 0 1 2 * * * Bytes CA[11:0] 0 1 2 * * * * * * * * * * * * * * * * * * * 63 2,047 *** 2,111 Spare area Table 4: Operational Example (x8) Block Page Min Address in Page Max Address in Page Out of Bounds Addresses in Page 0 0 0 ... 1,023 1,023 0 1 2 ... 62 63 0x00000000 0x00010000 0x00020000 ... 0xFFFE0000 0xFFFF0000 0x0000083F 0x0000183F 0x0000283F ... 0xFFFE083F 0xFFFF083F 0x00000840-0x00000FFF 0x00010840-0x00010FFF 0x00020840-0x00020FFF 0xFFFE0840-0xFFFE0FFF 0xFFFF0840-0xFFFF0FFF Notes: 1. As shown in Table 2 on page 12, the high 4 bits of the second ADDRESS cycle have no assigned address bits. However, these 4 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in the second ADDRESS cycle even though they have no address bits assigned to them. 2. Note that the 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8 device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each page are "out of bounds," do not exist in the device, and cannot be addressed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Addressing Figure 7: Memory Map (x16) Blocks BA[15:6] 0 1 2 * * * * * * * * * * * * 1,023 Pages PA[5:0] 0 1 2 * * * Words CA[10:0] 0 1 2 * * * * * * * * * * * * * * * * * * * 63 1,023 *** 1,055 Spare area Table 5: Operational Example (x16) Block Page Min Address in Page Max Address in Page Out of Bounds Addresses in Page 0 0 0 ... 1,023 1,023 0 1 2 ... 62 63 0x00000000 0x00010000 0x00020000 ... 0xFFFE0000 0xFFFF0000 0x0000041F 0x0001041F 0x0002041F ... 0xFFFE041F 0xFFFF041F 0x00000420-0x00000FFF 0x00010420-0x00010FFF 0x00020420-0x00020FFF 0xFFFE0420-0x00020FFF 0xFFFF0420-0xFFFF0FFF Notes: 1. As shown in Table 3 on page 13, the high 5 bits of ADDRESS cycle 2 have no assigned address bits. However, these 5 bits must be held LOW during the ADDRESS cycle to ensure that the address is interpreted correctly by the NAND Flash device. These extra bits are accounted for in ADDRESS cycle 2 even though they have no address bits assigned to them. 2. Note that the 11-bit column address is capable of addressing from 0 to 2,047 words on a x16 device; however, only words 0 through 1,055 are valid. Words 1,056 through 2,047 of each page are "out of bounds," do not exist in the device, and cannot be addressed. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Bus Operation Bus Operation The bus on the MT29F1Gxx devices is multiplexed. Data I/O, addresses and commands all share the same balls. I/O[15:8] are used only for data in the x16 configuration. Addresses and commands are always supplied on I/O[7:0]. The command sequence normally consists of a COMMAND LATCH cycle, ADDRESS LATCH cycle and a DATA cycle--either READ or WRITE. Control Signals CE#, WE#, RE#, CLE, ALE, LOCK, and WP control NAND Flash READ and WRITE operations. CE# is used to enable the device. When CE# is LOW and the device is not in the BUSY state, the NAND Flash memory will accept command, data, and address information. When the device is not performing an operation, CE# is typically driven HIGH and the device enters standby mode. The memory will enter standby if CE# goes HIGH while data is being transferred and the device is not busy. This helps reduce power consumption (see Figure 57 on page 64). The CE# "Don't Care" operation enables the NAND Flash to reside on the same asynchronous memory bus as other Flash or SRAM devices. Other devices on the memory bus can then be accessed while the NAND Flash is busy with internal operations. This capability is important for designs that require multiple NAND Flash devices on the same bus. One device can be programmed while another is being read. A HIGH CLE signal indicates that a COMMAND cycle is taking place. A HIGH ALE signal signifies that an ADDRESS INPUT cycle is occurring. Commands Commands are written to the command register on the rising edge of WE# when all of these conditions are met: * CE# and ALE are LOW * CLE is HIGH * the device is not busy The READ STATUS and RESET commands are different because they can be written to the device while it is busy. Commands are transferred to the command register on the rising edge of WE# (see Figure 26 on page 37). Commands are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be written with zeros when issuing a command. Address Input Addresses are written to the address register on the rising edge of WE# when all of these conditions are met: * CE# and CLE are LOW * ALE is HIGH Addresses are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be written with zeros when issuing an address. Generally, all 4 address cycles are written to the device. An exception is the BLOCK ERASE command, which requires only 2 address cycles (see "BLOCK ERASE Operation" on page 33 for details). PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 16 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Bus Operation RANDOM DATA INPUT and OUTPUT commands need only column addresses, so only 2 address cycles are required. Refer to the command descriptions to determine the addressing requirements for each command. Data Input Data is written to the data register on the rising edge of WE# when these conditions are met: * CE#, CLE, and ALE are LOW * the device is not busy Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure 46 on page 57 for additional data input details. READ After a READ command is issued, data is transferred from the memory array to the data register on the rising edge of WE#. R/B# goes LOW for tR and transitions HIGH after the transfer is complete. When data is available in the data register, it is clocked out of the part by RE# going LOW (see Figure 12 on page 21 for timing details). The READ STATUS (70h) command or the READY/BUSY signal can be used to determine when the device is ready (see the READ STATUS command section starting on page 28 for details). READY/BUSY# The R/B# output provides a hardware method of indicating the completion of a PROGRAM/ERASE/READ operation. The signal is typically HIGH, and transitions to LOW after the appropriate command is written to the device. The signal's open-drain driver enables multiple R/B# outputs to be OR-tied. The signal requires a pull-up resistor for proper operation. The READ STATUS command can be used in place of R/B#. Typically, R/B# would be connected to an interrupt ball on the system controller (see Figure 8 on page 18). The combination of Rp and the capacitive loading of the R/B# circuit determine the R/B# rise time. The actual value used for Rp depends on the system timing requirements. Large Rp values delay R/B# significantly. At the 10 percent/90 percent points on the R/B# waveform, rise time is approximately two time constants (TC). TC = R x C Where R = Rp (resistance of pull-up resistor), and C = total capacitive load. The R/B# fall time is determined mainly by the output impedance of R/B# and the total load capacitance. Refer to Figures 9 and 10 on page 18, which depict approximate Rp values using a circuit load of 100pF. The minimum value for Rp is determined by the R/B# output drive capability, the output voltage swing, and VCC. 1.85V V CC ( MAX ) - V OL ( MAX )= -------------------------Rp ( MIN, 1.8V part ) = --------------------------------------------------------------I OL + I L 3mA + I L Where I L is the sum of the input currents of all devices tied to the R/B# pin. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Bus Operation Figure 8: READY/BUSY# Open Drain Rp VCC R/B# Open drain output IOL GND Device Figure 9: t Fall and tRise 3.50 3.00 2.50 V tRise tFall 2.00 1.50 1.00 0.50 0.00 -1 0 2 4 0 2 4 TC Notes: 1. 2. 3. 4. Figure 10: 6 VCC 1.8 t Fall and tRise are calculated at 10 percent and 90 percent points. Rise is primarily dependent on external pull-up resistor and external capacitive loading. tFall 7ns at 1.8V. See TC values in Figure 11 on page 19 for approximate Rp value and TC. t IOL vs. Rp 3.50mA 3.00mA 2.50mA 2.00mA I 1.50mA 1.00mA 0.50mA 0.00mA 0 2,000 4,000 6,000 8,000 10,000 12,000 Rp IOL at 1.95V (MAX) Note: PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN To calculate Rp value, see page 17. 18 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Bus Operation Figure 11: TC vs. Rp 1.20s 1.00s T 800ns 600ns 400ns 200ns 0ns 0 2k 4k 6k 8k 10k 12k Rp IOL at 1.95V (MAX) RC = TC C = 100pf Table 6: Mode Selection CLE ALE CE# RE# WP# H L L WE# H X L H L H X H L L H H L H L H H L L L H H Data input L L L H X Sequential read and data output L X X X X L X X X X L X X X H H X X X X H X X X X Mode Read mode Command input Address input Write mode Command input Address input X H H L 0V/VCC2 During READ (busy) During PROGRAM (busy) During ERASE (busy) Write protect Standby Notes: 1. Mode selection settings for this table: H = Logic level HIGH L = Logic level LOW X = VIH or VIL 2. WP# should be biased to CMOS HIGH or LOW for standby. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 19 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Command Definitions Table 7: Command Set Command BLOCK ERASE BLOCK LOCK BLOCK LOCK READ STATUS BLOCK LOCK TIGHT BLOCK UNLOCK OTP DATA PROGRAM OTP DATA PROTECT OTP DATA READ PAGE READ PAGE READ CACHE MODE START PAGE READ CACHE MODE LAST PROGRAM for INTERNAL DATA MOVE PROGRAM PAGE PROGRAM PAGE CACHE MODE PROGRAMMABLE DRIVE STRENGTH RANDOM DATA INPUT RANDOM DATA READ READ for INTERNAL DATA MOVE READ ID READ ID (ONFI) READ PARAMETER PAGE (ONFI) READ STATUS RESET First Cycle Second Cycle Valid During Busy 60h 2Ah 7Ah 2Ch 23h-24h A0h A5h AFh 00h 31h 3Fh 85h 80h 80h B8h 85h 05h 00h 90h 90h ECh 70h FFh D0h - - - - 10h 10h 30h 30h - - 10h 10h 15h - - E0h 35h - - - - - No No No No No No No No No No No No No No No No No No No No No Yes Yes Notes 1 2 Notes: 1. RANDOM DATA INPUT command is limited to use within a single page. 2. RANDOM DATA READ command is limited to use within a single page. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 20 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions READ Operations PAGE READ 00h-30h To enter READ mode, write a 00h command to the device, then specify the starting address via the ADDRESS cycles, and finally, issue the 30h command. At this point, the device enters a busy state while it retrieves data from the NAND Flash array. During this time, the ready/busy status of the device can be monitored using the R/B# or the READ STATUS (70h) command. The R/B# signal is LOW when the device is busy retrieving data from the NAND Flash array. When R/B# returns to HIGH, data is ready for output. Pulsing the RE# line results in data output on the I/O lines. Note that the first byte or word of data output is that which was specified in the ADDRESS cycle. Each pulse of the RE# signal increases the address counter by one, so additional address cycles are not required when reading sequential data. If the system does not have a R/B# signal, NAND Flash device status can be monitored by issuing a READ STATUS (70h) command, then reading bit 5 or 6 from the status register (0 = busy; 1 = ready). If the READ STATUS command is used to monitor the data transfer, the user must re-issue the READ (00h) command to initiate data output from the data register. The user can issue 00h only after R/B# goes HIGH or the status register value is E0h. See Figure 54 on page 62 and Figure 55 on page 63 for examples. Figure 12: PAGE READ Operation CLE CE# WE# ALE tR R/B# RE# I/Ox 00h Address (4 cycles) 30h Data output (Serial access) Don`t Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions RANDOM READ 05h-E0h The RANDOM READ command enables the user to specify a new column address so data at single or multiple addresses can be read. The random read mode is enabled after a normal PAGE READ (00h-30h sequence). Random data can be output after the initial PAGE READ by writing an 05h-E0h command sequence along with the new column address (2 cycles). The RANDOM READ command can be issued without limit within the page. Only data on the current page can be read. Pulsing RE# outputs data in the same manner as a serial PAGE READ (see Figure 13). Figure 13: RANDOM DATA READ Operation tR R/B# RE# I/Ox 00h Address (4 cycles) 30h Data output 05h Address (2 cycles) E0h Data output PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh Micron NAND Flash devices have a cache register that can be used to increase READ operation speed when accessing sequential pages in a block. A normal PAGE READ (00h-30h) command sequence is issued (see Figure 14 on page 23 for details). The R/B# signal goes LOW for tR during the time it takes to transfer the first page of data from the memory to the data register. After R/B# returns to HIGH, the PAGE READ CACHE MODE START (31h) command is latched into the command register. R/B# goes LOW for tDCBSYR1 while data is being transferred from the data register to the cache register. When the data register contents are transferred to the cache register, another PAGE READ is automatically started as part of the 31h command. Data is transferred from the memory array to the data register at the same time data is being output (pulsing of RE#) from the cache register. If the total time to output data exceeds tR, then the PAGE READ is hidden. The second and subsequent pages of data are transferred to the cache register by issuing additional 31h commands. R/B# will stay LOW up to tDCBSYR2. This time can vary, depending on whether the previous memory-to-data-register transfer was completed before issuing the next 31h command. If the data transfer from memory to the data register is not completed before the 31h command is issued, R/B# stays LOW until the transfer is complete. It is not necessary to output a whole page of data before issuing another 31h command. R/B# will stay LOW until the previous PAGE READ is complete and the data has been transferred to the cache register. To read out the last page of data, the PAGE READ CACHE MODE START LAST (3Fh) command is issued. This command transfers data from the data register to the cache register without another PAGE READ (see Figure 14 on page 23 for details). PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. CLE CE# WE# PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 23 Data output 3fh Data output 31h Data output (Serial access) (Serial access) 1Gb: x8, x16 NAND Flash Memory Command Definitions Don`t Care Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. (Serial access) tDCBSYR2 tDCBSYR2 tDCBSYR1 tR 31h 30h Address (4 cycles) 00h I/Ox PAGE READ CACHE MODE Figure 14: ALE R/B# RE# 1Gb: x8, x16 NAND Flash Memory Command Definitions READ ID 90h The READ ID command is used to read the identifier codes from the MT29F1G08 and MT29F1G16 devices. The READ ID command reads a 5-byte table that includes the manufacturer ID, device configuration, and part-specific information. Table 8 on page 25 shows a complete listing of configuration details. Issuing a 90h command to the command register and a 00h command to the address register puts the device in read ID mode. The device will remain in this mode until another valid command and address are issued (see Figure 15). If a 90h command is issued without an address, the device will remain in read ID mode. Figure 15: READ ID Operation CLE CE# WE# tAR ALE RE# tWHR I/Ox 90h 00h Address, 1 cycle tREA Byte 0 Byte 1 Byte 21 Byte 31 Byte 4 Manufacturer ID1 Device ID1 Notes: 1. See Table 8 on page 25 for byte definitions. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Table 8: Device ID and Configuration Codes Options Byte 0 Byte 1 MT29F1G08ABB MT29F1G16ABB Byte 2 Number of die Cell type Number of simultaneously programmed pages Interleaved operations between multiple die Cache programming Byte value MT29F1GxxABB Byte 3 Page size Spare area size (bytes) Block size (w/o spare) Organization Serial access (MIN) Byte value MT29F1G08ABB MT29F1G16ABB Byte 4 Reserved Planes per die Plane size Reserved Byte value MT29F1GxxABB Manufacturer ID Micron Device ID 1Gb, x8, 1.8V 1Gb, x16, 1.8V I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 0 0 1 0 1 1 0 0 2Ch 1 1 0 0 1 1 0 1 0 0 0 0 0 0 1 1 A1h B1h 0 0 0 0 00b 00b 00b 1 SLC 1 Not supported (1Gb) Supported 2KB 64 128KB x8 x16 50ns x8 x16 Value1 Notes I/O7 0 1 1 0 0 0b 0 1b 80h 0 0 0 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 0 1 1 0 1 0 1 1 1 1Gb 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 01b 01b 01b 0b 1b 0xxx0b 95h D5h 00b 00b 000b 0b 00h Notes: 1. b = binary; h = hex. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions ONFI READ ID The ONFI READ ID function identifies that the device supports the ONFI specification. If the device supports the ONFI specification, then the ONFI signature will be returned. The ONFI signature is the ASCII encoding of ONFI: * O = 4Fh * N = 4Eh * F = 46h * I = 49h. Reading beyond these four values yields indeterminate data. Figure 16 defines the ONFI READ ID behavior and timings. Issuing a 90h command to the command register and a 20h command to the address register puts the device into ONFI read ID mode. The device will remain in this mode until another valid command and address are issued. If a 90h command is issued without an address, the device will remain in the ONFI read ID mode. Figure 16: ONFI READ ID Operation CLE WE# ALE RE# I/O0-7 90h PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 20h 4Fh 26 4Eh 46h 49h Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions ONFI READ PARAMETER PAGE Operation The READ PARAMETER PAGE function retrieves the data structure that describes the device organization, features, timings, and other behavioral parameters. Figure 17 defines the READ PARAMETER PAGE behavior. Figure 17: ONFI READ PARAMETER PAGE Operation CLE WE# ALE RE# I/O0-7 ECh I/O0-7 00h P0 P1 ... P1022 P1023 tR R/B# Parameter Page Data Structure Definition For parameters that span multiple bytes, the least significant byte of the parameter corresponds to the first byte. For example, if bytes 8-9 contain a 16-bit parameter, then bits 7:0 are contained in byte 8. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions READ STATUS 70h The MT29F1G08 and MT29F1G16 devices have an 8-bit status register the software can read during device operation. On the x16 device, I/O[15:8] are "0" when reading the status register. Table 9 on page 29 describes the status register. After a READ STATUS (70h) command, all READ cycles will be from the status register until a new command is issued. Changes in the status register will be seen on 1/O[7:0] as long as CE# and RE# are LOW. It is not necessary to start a new READ cycle to see these changes. During monitoring of the status register to determine when the tR (transfer from NAND Flash array to data register) is complete, the READ (00h) command must be re-issued to make the change from STATUS READs to DATA READs. After the READ command has been re-issued, pulsing the RE# line will result in outputting data, starting from the specified column address. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Table 9: Status Register Bit Definition SR Bit Program Page Program Page Cache Mode Page Read Page Read Cache Mode Block Erase 0 Pass/fail Pass/fail (N) - - Pass/fail 1 - Pass/fail (N - 1) 2 3 4 5 - - - Ready/busy - - - Ready/busy 6 Ready/busy 7 Write protect - Ready/busy cache Write protect [15:8] - Definition Notes 0 = Successful PROGRAM/ERASE 1 = Error in PROGRAM/ERASE - - - 0 = Successful PROGRAM 1 = Error in PROGRAM - - - 0 - - - 0 - - - 0 Ready/busy Ready/busy Ready/busy 0 = Busy 1 = Ready Ready/busy Ready/busy Ready/busy 0 = Busy cache 1 = Ready Write Write protect Write 0 = Protected protect protect 1 = Not protected - - - 0 1 2 3 Notes: 1. Status register bit 5 is "0" during the actual programming operation. If cache mode is used, this bit will be "1" when all internal operations are complete. 2. Status register bit 6 is "1" when the cache is ready to accept new data. R/B# follows bit 6. See Figure 19 on page 30, and Figure 25 on page 36. 3. Status register bit 7 typically mirrors the status of WP#. However, when BLOCK LOCK is used, status register bit 7 returns "0" if PROGRAM or ERASE operations are performed on a locked block. Additionally, when using the OTP PROGRAM DATA command, status register bit 7 returns "0" if the page is protected. This bit is not modified until the next PROGRAM or ERASE command is issued. Figure 18: Status Register Operation CE# tCLR CLE WE# tREA RE# I/Ox Status 70h Status Status Toggle RE# as required PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions PROGRAM Operations PROGRAM PAGE 80h-10h Micron NAND Flash devices are inherently page-programmed devices. Pages must be programmed consecutively within a block, from the least significant page address to most significant page address (that is, 0, 1, 2, ..., 63). Random page address programming is prohibited. Micron NAND Flash devices also support partial-page programming operations. This means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned so that a maximum of eight programming operations are supported before an erase is required. SERIAL DATA INPUT 80h PROGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command into the command register, followed by the ADDRESS cycles, then the data. Serial data is loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h) command is written after the data input is complete. The internal control logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operation. Write verification only detects "1s" that are not successfully written to "0." R/B# goes LOW for the duration of array programming time, tPROG. The READ STATUS REGISTER (70h) command and the RESET (FFh) command are the only commands valid during the programming operation. Bit 6 of the status register will reflect the state of R/B#. When the device reaches ready, read bit 0 of the status register to determine if the program operation passed or failed (see Figure 19). The command register stays in read status register mode until another valid command is written to it. RANDOM DATA INPUT 85h After the initial data set is input, additional data can be written to a new column address with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT command can be used any number of times in the same page prior to issuing the PAGE WRITE (10h) command. See Figure 20 for the proper command sequence. Figure 19: PROGRAM and READ STATUS Operation tPROG R/B# I/Ox 80h Address PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN DIN 70h 10h 30 Status Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 20: RANDOM DATA INPUT tPROG R/B# I/Ox 80h Address DIN 85h Address (2 cycles) DIN 10h 70h Status PROGRAM PAGE CACHE MODE 80h-15h Cache programming is actually a buffered programming mode of the standard page programming command. Programming is started by loading the SERIAL DATA INPUT (80h) command to the command register, followed by 4 cycles of address, and a full or partial page of data. The data is initially copied into the cache register, and the CACHE WRITE (15h) command is then latched to the command register. Data is transferred from the cache register to the data register on the rising edge of WE#. R/B# goes LOW during this transfer time. After the data has been copied into the data register and R/B# returns to HIGH, memory array programming begins. When R/B# returns to HIGH, new data can be written to the cache register by issuing another PROGRAM PAGE CACHE MODE command sequence. The time that R/B# stays LOW will be controlled by the actual programming time. The first time through equals the time it takes to transfer the cache register contents to the data register. On the second and subsequent programming passes, transfer from the cache register to the data register is held off until current data register content has been programmed into the array. The PROGRAM PAGE CACHE MODE command can cross block address boundaries; it must not cross die address boundaries. RANDOM DATA INPUT (85h) commands are permitted with PROGRAM PAGE CACHE MODE operations. Bit 6 (cache R/B#) of the status register can be read by issuing the READ STATUS (70h) command to determine when the cache register is ready to accept new data. R/B# always follows bit 6. Bit 5 (R/B#) of the status register can be polled to determine when the actual programming of the array is complete for the current programming cycle. If R/B# is used to determine programming completion, the last page of the program sequence must use the PROGRAM PAGE (10h) command instead of the CACHE PROGRAM (15h) command. If the CACHE PROGRAM (15h) command is used every time, including the last page of the programming sequence, status register bit 5 must be used to determine when programming is complete. Bit 1 of the status register returns the pass/fail for the previous page when bit 6 of the status register is a "1" (ready state). The pass/fail status of the current PROGRAM operation is returned with bit 0 of the status register when bit 5 of the status register is a "1" (ready state) (see Figure 21 on page 32). PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 21: PROGRAM PAGE CACHE MODE Example tCBSY tCBSY tLPROG1 tCBSY R/B# I/Ox 80h Address/ data input 15h 80h Address/ data input 15h 80h Address/ data input 15h 80h Address/ data input 10h A: Without status reads tCBSY tPROG R/B# I/Ox 80h Address/ data input 15h 70h Status output2 80h Address/ data input 10h 70h Status output1 B: With status reads Notes: 1. For definition of tLPROG, see note 3, Table 23 on page 55. 2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass/fail. RE# can remain LOW or pulse multiple times after a 70h command. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions INTERNAL DATA MOVE Operations An internal data move requires two command sequences. Issue a READ for INTERNAL DATA MOVE (00h-35h) command first, then the INTERNAL DATA MOVE (85h-10h) command. Data moves are only supported within the die from which data is read. READ FOR INTERNAL DATA MOVE 00h-35h This READ command is used in conjunction with the INTERNAL DATA MOVE (85h-10h) command. First, 00h is written to the command register, then the internal source address is written (4 cycles). After the address is input, the READ for INTERNAL DATA MOVE (35h) command writes to the command register. This transfers a page from memory into the cache register. The written column addresses are ignored even though all 4 address cycles are required. The memory device is now ready to accept the INTERNAL DATA MOVE (85h-10h) command. INTERNAL DATA MOVE 85h-10h After the READ for INTERNAL DATA MOVE command has been issued and R/B# goes HIGH, the INTERNAL DATA MOVE command can be written to the command register. This command transfers the data from the cache register to the data register and programming of the new destination page begins. After the INTERNAL DATA MOVE command and address sequence are written to the device, R/B# goes LOW while the internal control logic automatically programs the new page. The READ STATUS command and bit 6 of the status register can be used instead of the R/B# line to determine when the WRITE is complete. Bit 0 of the status register indicates if the operation was successful. The RANDOM DATA INPUT (85h) command can be used during the INTERNAL DATA MOVE command sequence to modify a word or multiple words in the original data. First, data is copied into the cache register using the 00h-35h command sequence; then the RANDOM DATA INPUT (85h) command is written, along with the address of the data to be modified next. New data is input on the external data balls. This copies the new data into the cache register. When 10h is written to the command register, the original data plus the modified data is transferred to the data register, and programming of the new page is started. The RANDOM DATA INPUT command can be issued as many times as necessary before starting the programming sequence with 10h (see Figure 22 and Figure 23 on page 34 for details). Because the INTERNAL DATA MOVE operation does not utilize external memory, ECC cannot be used to check for errors before programming the data to a new page. This can lead to a data error if the source page contains a bit error due to charge loss or charge gain. If multiple INTERNAL DATA MOVE operations are performed, these bit errors may accumulate without correction. For this reason, it is highly recommended that systems utilizing the INTERNAL DATA MOVE operation use a robust ECC scheme that can correct two or more bits per sector. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 22: INTERNAL DATA MOVE tR tPROG R/B# I/Ox 00h Figure 23: Address 35h 85h Address 10h 70h Status INTERNAL DATA MOVE with RANDOM DATA INPUT tPROG tR R/B# I/Ox 00h Address 35h 85h Address Data 85h Address (2 cycles) Data 10h 70h Unlimited number of repetitions BLOCK ERASE 60h-D0h Erasing occurs at the block level. The MT29F1G08 and the MT29F1G16 have 1,024 erase blocks organized as 64 pages per block. The BLOCK ERASE command operates on one block at a time (see Figure 24). Two cycles of addresses BA[15:6] are required for the x8 device, and 2 cycles of BA[15:6] for the x16 device. Although addresses PA[5:0] (x8) and PA[5:0] (x16) are loaded, they are a "Don't Care" and are ignored for BLOCK ERASE operations. See Figures 6 and 7 on pages 14 and 15 for addressing details. The actual BLOCK ERASE command sequence is a two-step process. First, write the ERASE SETUP (60h) command to the command register. Then write 2 cycles of addresses to the device. Next, write the ERASE CONFIRM (D0h) command to the command register. At the rising edge of WE#, R/B# goes LOW and the internal control logic automatically controls the timing and erase-verify operations. R/B# stays LOW for the entire tBERS erase time. The READ STATUS REGISTER command can be used to check the status of the ERASE operation. When bit 6 = 1, the ERASE operation is complete. Bit 0 indicates a pass/fail condition where 0 = pass. See BLOCK ERASE, and Table 9 on page 29 for details. Figure 24: BLOCK ERASE Operation tBERS R/B# I/Ox PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 60h Address D0h 34 70h Status Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions One-Time Programmable (OTP) Area This Micron NAND Flash device offers a protected, one-time programmable NAND Flash memory area. Ten full pages (2,112 bytes or 1,056 words per page) of OTP data is available on the device, and the entire range is guaranteed to be good. The OTP area is accessible only through the OTP commands. Customers can use the OTP area in any way they desire; typical uses include programming serial numbers or other data for permanent storage. In Micron NAND Flash devices, the OTP area leaves the factory in an unwritten state (each OTP bit is "1"). Programming or partial-page programming enables the user to program only "0" bits in the OTP area. The OTP area cannot be erased, even if it is not protected. Protecting the OTP area simply prevents further programming of the OTP area. While the OTP area is referred to as "one-time programmable," Micron provides a unique way to program and verify data--before permanently protecting it and preventing future changes. OTP programming and protection are accomplished in two discrete operations. First, using the OTP DATA PROGRAM (A0h-10h) command, an OTP page is programmed entirely in one operation, or in up to four partial-page programming sequences. Programming can occur on other pages within the OTP area in a similar manner. Second, the OTP area is permanently protected from further programming using the OTP DATA PROTECT (A5h-10h) command. The pages within the OTP area can always be read using the OTP DATA READ (AFh-30h) command, whether or not it is protected. OTP DATA PROGRAM A0h-10h The OTP DATA PROGRAM (A0h-10h) command is used to write data to the pages within the OTP area. An entire page can be programmed at one time, or a page can be partially programmed up to four times. There is no ERASE operation for the OTP pages. The OTP DATA PROGRAM enables programming into an offset of an OTP page, using the two bytes of column address (CA[11:0]). The OTP DATA PROGRAM command will not execute if the OTP area has been protected. If the OTP area is protected, the busy time for the OTP DATA PROGRAM operation is tOBSY and not tPROG. To use the OTP DATA PROGRAM command, issue the A0h command. Issue 4 ADDRESS cycles: the first 2 ADDRESS cycles are the column address, and for the remaining 2 cycles select a page in the 02h-0Bh range. Next, write the data: from 1 to 2,112 bytes (x8 device), or from 1 to 1,056 words (x16 device). After data input is complete, issue the 10h command. The internal control logic automatically executes the proper programming algorithm and controls the necessary timing for programming and verification. Program verification only detects "1"s that are not successfully written to "0"s. RANDOM DATA INPUT (85h) commands are supported during OTP DATA PROGRAM operations only if the OTP area is unprotected. R/B# goes LOW during the duration of the array programming time (tPROG). The READ STATUS (70h) command is the only command valid during the OTP DATA PROGRAM operation. For this operation, bits 5 and 6 of the status register will reflect the state of R/B#. If bit 7 is "0," then the OTP area has been protected; otherwise, it will be a "1." When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 9 on page 29). PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 25: OTP DATA PROGRAM CLE CE# tWC WE# tWB tPROG ALE RE# I/Ox A0h Col add 1 OTP DATA INPUT command Col add 2 OTP page1 OTP address1 00h DIN N DIN M 1 up to m bytes serial input 10h 70h PROGRAM command READ STATUS command Status R/B# x8 device: m = 2,112 bytes x16 device: m = 1,056 words OTP data written (following "good" status confirmation) Don't Care Notes: 1. The OTP page must be within the 02h-0Bh range. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions OTP DATA PROTECT A5h-10h The OTP DATA PROTECT (A5h-10h) command is used to protect all the data in the OTP area. After the data is protected, it cannot be programmed further. When the OTP area is protected, the pages within the area are no longer programmable and cannot be unprotected. To use the OTP DATA PROTECT command, issue the A5h command. Next, issue the following 4 ADDRESS cycles: 00h-00h-01h-00h. Finally, issue the 10h command. R/B# goes LOW while the OTP area is being protected. The protect command duration is similar to a normal page programming operation, tPROG. The READ STATUS (70h) command is the only command valid during the OTP DATA PROTECT operation. For this operation, bits 5 and 6 of the status register will reflect the state of R/B#. When the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see Table 9 on page 29). Figure 26: OTP DATA PROTECT CLE CE# tWC WE# tWB tPROG ALE RE# I/Ox Col 00h A5h OTP DATA PROTECT command Col 00h 01h 00h OTP address 10h 70h PROGRAM command READ STATUS command R/B# Status OTP data protected1 Don't Care Notes: 1. OTP data is protected following "good" status confirmation. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 37 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions OTP DATA READ AFh-30h The OTP DATA READ (AFh-30h) command is used to read data from a page within the OTP area. An OTP page within the OTP area is available for reading data whether or not the area is protected. To use the OTP DATA READ command, issue the AFh command. Next, issue 4 ADDRESS cycles: the first 2 ADDRESS cycles are the column address, and for the remaining 2 cycles, select a page in the range of 02h-0Bh. Finally, issue the 30h command. RANDOM DATA READ (05h-E0h) commands are supported during OTP DATA READ operations. R/B# goes LOW (tR) while the data is moved from the OTP page to the data register. The READ STATUS (70h) command and the RESET (FFh) command are the only commands valid during the OTP DATA READ operation. For this operation, bits 5 and 6 of the status register will reflect the state of R/B#. For details, refer to Table 9 on page 29. Normal READ operation timings apply to OTP read accesses (see Figure 27). Additional pages within the OTP area can be selected by repeating the OTP DATA READ command. Note that if OTP DATA READ is followed by PAGE READ CACHE MODE, a RESET (FFh) must be issued prior to issuing the PAGE READ CACHE MODE command. The maximum RESET time will not exceed 5s. Figure 27: OTP DATA READ Operation CLE CE# WE# ALE tR RE# I/Ox AFh Col add 1 Col add 2 OTP page1 DOUT N 30h 00h OTP address DOUT N+1 DOUT M Busy R/B# Don't Care Notes: 1. The OTP page must be within the range 02h-0Bh. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 38 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions BLOCK LOCK Feature The BLOCK LOCK feature provides the ability to protect the entire device or ranges of blocks from PROGRAM and ERASE operations. Using this BLOCK LOCK feature offers increased functionality and flexibility over using just WP# to prevent PROGRAM and ERASE operations. BLOCK LOCK features are enabled and disabled at power-on through the use of the LOCK signal. At power-on, if LOCK is LOW, all BLOCK LOCK commands are disabled. However, at power-on, if LOCK is HIGH, the BLOCK LOCK commands are enabled and, by default, all of the blocks on the device are protected, or locked, from PROGRAM and ERASE operations, even if WP# is HIGH. Before the contents of the device can be modified, the device must first be unlocked. Either a range of blocks or the entire device can be unlocked. PROGRAM and ERASE operations complete successfully only in the block ranges that have been unlocked. Blocks, once unlocked, can be locked again to protect them from further PROGRAM and ERASE operations. Blocks that are locked can be protected further, or locked tight. When locked tight, the device's blocks can no longer be locked or unlocked until WP# is pulled LOW for more than 100ns. After WP# goes LOW for this period, the entire device is locked from PROGRAM and ERASE operations until unlocked again. WP# and BLOCK LOCK When the BLOCK LOCK feature is enabled, it interacts with WP# as follows: * WP# must be driven HIGH and remain HIGH when UNLOCK and LOCK-TIGHT commands are issued. * Holding WP# LOW locks all blocks. * If WP# is held LOW to lock blocks, and then returned to HIGH, a new UNLOCK command must be issued to unlock blocks. UNLOCK 23h-24h By default at power-on, if LOCK is HIGH, all of the blocks in the NAND Flash device are locked, meaning that they are protected from PROGRAM and ERASE operations. The UNLOCK (23h) command is used to unlock a range of blocks. Unlocked blocks have no protection and can be programmed or erased. The UNLOCK command uses two registers--a lower boundary block address register and an upper boundary block address register--and the invert area bit to determine which range of blocks is unlocked. When the invert area bit = 0, the range of blocks within the lower and upper boundary address registers is unlocked. When the invert area bit = 1, the range of blocks outside the boundaries of the lower and upper boundary address registers are unlocked. The lower boundary block address must be less than the upper boundary block address. Figures 28 and 29 on page 40 show examples of how the lower and upper boundary address registers work with the invert area bit. To unlock a range of blocks, issue the UNLOCK (23h) command followed by the appropriate ADDRESS cycles that indicate the lower boundary block address. Then issue the 24h command followed by the appropriate ADDRESS cycles that indicate the upper boundary block address. The least significant page address bit, PA0, should be set to "1" if setting the invert area bit; otherwise, it should be "0." The other page address bits should be "0" (see Figure 30 on page 41). PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 39 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Only one range of blocks can be specified in the lower and upper boundary block address registers. If, after unlocking a range of blocks, the UNLOCK command is again issued, the new block address range determines which blocks are unlocked. The previous unlocked block address range is not retained. The UNLOCK (23h-24h) command is disabled if LOCK is LOW at power-on or if the device is locked tight (see page 42). Figure 28: Flash Array Protected: Inverted Area Bit = 0 Block 1023 Block 1022 Block 1021 Block 1020 Block 1019 Block 1018 Block 1017 Block 1016 Block. 1015 .. .. .. .. .. .. . Block 0002 Block 0001 Block 0000 Figure 29: Protected area 3FCh Upper block boundary 3F8h Lower block boundary Unprotected area Protected area Flash Array Protected: Invert Area Bit = 1 Block 1023 Block 1022 Block 1021 Block 1020 Block 1019 Block 1018 Block 1017 Block 1016 Block 1015 .. .. .. .. .. .. .. Block 0002 Block 0001 Block 0000 PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Unprotected area 3FCh Upper block boundary 3F8h Lower block boundary Protected area Unprotected area 40 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Table 10: ALE Cycle First Second BLOCK LOCK Address Cycle Assignments I/O[15:8]1 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 LOW LOW BA7 BA15 BA6 BA14 LOW BA13 LOW BA12 LOW BA11 LOW BA10 LOW BA9 Invert Area Bit2 BA8 Notes: 1. I/O[15:8] is applicable only for x16 devices. 2. Invert area bit is applicable for 24h command; it can be HIGH or LOW for the 23h command. Figure 30: UNLOCK Operation CLE CE# WE# ALE RE# I/Ox 23h UNLOCK Block add 1 Block add 2 Lower boundary 24h Block add 1 Block add 2 Upper boundary LOCK 2Ah By default at power-on, if LOCK is HIGH, all of the blocks in the NAND Flash device are locked and protected from PROGRAM and ERASE operations. If portions of the device are unlocked using the UNLOCK (23h) command, they can be locked again using the LOCK (2Ah) command. The LOCK command locks all of the blocks in the device. Locked blocks are write-protected from PROGRAM and ERASE operations. To lock all of the blocks in the device, issue the LOCK (2Ah) command. When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h) command reports bit 7 as "0," indicating that the block is protected. The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is locked tight (see page 42). PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 41 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 31: LOCK Operation CLE CE# WE# I/Ox 2Ah LOCK command LOCK-TIGHT 2Ch The LOCK-TIGHT (2Ch) command prevents locked blocks from being unlocked and also prevents unlocked blocks from being locked. When this command is issued, the UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional level of protection to locked blocks from inadvertent PROGRAM and ERASE operations. To implement the lock-tight state in all of the locked blocks in the device, verify that WP# is HIGH and then issue the LOCK-TIGHT (2Ch) command. When a PROGRAM or ERASE operation is issued to a locked block that has also been locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h) command reports bit 7 as "0," indicating that the block is protected. PROGRAM and ERASE operations complete successfully to blocks that were not locked at the time the LOCK-TIGHT command was issued. Once the LOCK-TIGHT command is issued, it cannot be disabled via a software command. The only way to disable the lock-tight status is either to hold WP# LOW for greater than 100ns or to power cycle the device. When the lock-tight status is disabled, all of the blocks become locked, the same as if the LOCK (2Ah) command were issued. The LOCK-TIGHT (2Ch) command is disabled if LOCK is LOW at power-on. Figure 32: LOCK-TIGHT Operation WP# CLE CE# WE# I/Ox 2Ch LOCK-TIGHT command PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 42 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 33: PROGRAM/ERASE Issued to Locked or Locked-Tight Block tLBSY R/B# I/Ox Address/data input PROGRAM or ERASE 70h CONFIRM Locked or locked-tight block Figure 34: 60h READ STATUS LOCKED-TIGHT BLOCKS to LOCKED BLOCKS Operation LOCK CE# > 100ns WP# Note: The device ensures exit from lock-tight mode if the WP# pulse is greater than 100ns. The device may exit lock-tight mode if WP# pulse is less than 100ns, however, this is not guaranteed. BLOCK LOCK READ STATUS 7Ah The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection status of individual blocks. The ADDRESS cycles have the same format as shown in Table 10 on page 41; the invert area bit should be set LOW. On the falling edge of RE#, the I/O outputs the block-lock status register which contains the information on the protection status of the block. Table 11 shows how to interpret the block-lock status register bits. The BLOCK LOCK READ STATUS (7Ah) command is disabled if LOCK is LOW at power-on. Table 11: BLOCK LOCK Status Register Bit Definitions BLOCK LOCK Status Register Definitions Block is locked and device is locked-tight Block is locked and device is not locked-tight Block is unlocked and device is locked-tight Block is unlocked and device is not locked-tight PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN I/O[7:3] I/O2 (Lock#) I/O1 (LT#) I/O0 (LT) X X X X 0 0 1 1 0 1 0 1 1 0 1 0 43 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 35: BLOCK LOCK READ STATUS CLE CE# WE# tWHRIO ALE RE# I/Ox 7Ah Add 1 Add 2 Status BLOCK LOCK Block address READ STATUS PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 36: BLOCK LOCK Flow Chart Power-up Power-up with LOCK HIGH Power-up with LOCK LOW (default) Entire NAND Flash array locked BLOCK LOCK function disabled LOCK-TIGHT command with WP# and LOCK HIGH Entire NAND Flash array locked tight WP# LOW >100ns UNLOCK command with invert area bit = 1 UNLOCK command with invert area bit = 0 Locked range Unlocked range LOCK command LOCK command Locked range Unlocked range UNLOCK command with invert area bit = 0 UNLOCK command with invert area bit = 1 Unlocked range UNLOCK command with invert area bit = 1 UNLOCK command invert area bit = 0 Locked range LOCK-TIGHT command with WP# and LOCK HIGH LOCK-TIGHT command with WP# and LOCK HIGH Unlocked range Locked-tight range Locked-tight range Unlocked range Unlocked range Locked-tight range WP# LOW > 100ns PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN WP# LOW > 100ns 45 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions RESET Operation RESET FFh The RESET command is used to put the memory device into a known condition and to abort a command sequence in progress. READ, PROGRAM, and ERASE commands can be aborted while the device is in the busy state. The contents of the memory location being programmed or the block being erased are no longer valid. The command register is cleared and is ready for the next command. The status register contains the value E0h when WP# is HIGH; otherwise, it is written with a 60h value. R/B# goes LOW for tRST after the RESET command is written to the command register. See Figure 37 and Table 12 for details. The RESET command must be issued after power-on and before any other command is issued to the device. The device will be busy for a maximum of 1ms at this time. Figure 37: RESET Operation CLE CE# tWB WE# tRST R/B# I/Ox FFh RESET command Table 12: Status Register Contents After Reset Condition Status WP# HIGH WP# LOW Ready Ready and write protected PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 E0h 60h 46 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Programmable Drive Strength PROGRAMMABLE I/O DRIVE STRENGTH B8h The B8h command is used to change the default I/O drive strength as shown in Figure 38. Drive strength should be selected based on expected memory bus loading. There are four allowable settings for the output drive strength. The settings and the default drive strength are shown in Table 13. The device returns to the default drive strength mode after it is power-cycled. Figure 38 shows how to write and read the drive strength. Refer toTable 14 on page 48 for unique timing parameters associated with the PROGRAMMABLE I/O DRIVE STRENGTH command. Note that the AC timing characteristics documented in Table 21 on page 54 and Table 22 on page 54 may need to be relaxed if the I/O drive strength is not set to "full." Figure 38: Programmable I/O Drive Strength Command Sequence tCLSIO tCLHIO CLE tWHIO CE# tWCIO tWPIO WE# tWHRIO tRPIO ALE tREAIO RE# tDSIO I/Ox tDHIO I/O[7:0]1 B8h I/O[7:0]2 Notes: 1. WRITE operation. 2. READ operation. Table 13: I/O Drive Strength Settings Drive Strength Full (default) Three-quarters One-half One-quarter I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 X X X X X X X X X X X X X X X X 0 0 1 1 0 1 0 1 X X X X X X X X Notes: 1. For WRITE operation, X = "Don't Care." For READ operation, X = "Undefined." 2. Timing parameters shown in Table 21 on page 54 and Table 22 on page 54 represent full drive setting. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 47 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Table 14: Programmable I/O Drive Strength Register READ/WRITE Timing Parameter Symbol Min Max Unit CLE hold time CLE setup time Data hold time Data setup time RE# access time RE# pulse width WRITE cycle time WE# pulse width HIGH WE# HIGH to RE# LOW WE# pulse width tCLHIO 15 25 15 30 - 250 100 50 100 50 - - - - 250 - - - - - ns ns ns ns ns ns ns ns ns ns t CLSIO t DHIO tDSIO t REAIO t RPIO t WCIO t WHIO tWHRIO t WPIO Notes WRITE PROTECT The WRITE PROTECT feature protects the device against inadvertent PROGRAM and ERASE operations. All PROGRAM and ERASE operations are disabled when WP# is LOW. For WRITE PROTECT timing details, see Figures 39 through 42. Figure 39: ERASE Enable WE# tWW I/Ox 60h D0h WP# R/B# Figure 40: ERASE Disable WE# tWW I/Ox 60h D0h WP# R/B# PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 48 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Command Definitions Figure 41: PROGRAM Enable WE# tWW I/Ox 80h 10h WP# R/B# Figure 42: PROGRAM Disable WE# tWW I/Ox 80h 10h WP# R/B# PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 49 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Error Management Error Management Micron MT29F1Gxx NAND Flash devices are specified to have a minimum of 1,004 valid blocks (NVB) out of 1,024 total available blocks. This means the devices may have blocks that are invalid when they are shipped. An invalid block is one that contains one or more bad bits. Additional bad blocks may develop with use. However, the total number of available blocks will not fall below NVB. Although NAND Flash memory devices may contain bad blocks, they can be used quite reliably in systems that provide bad-block mapping, replacement, and error correction algorithms. This type of software environment ensures data integrity. Internal circuitry isolates each block from other blocks, so the presence of a bad block does not affect the operation of the rest of the NAND Flash device. The first block (physical block address 00h) for each CE# in Micron NAND Flash devices is guaranteed to be free of defects (up to 1,000 PROGRAM/ERASE cycles) when shipped from the factory. This provides a reliable location for storing boot code and critical boot information. Before NAND Flash devices are shipped from Micron, they are erased. The factory identifies invalid blocks before shipping by programming data other than FFh (x8) or FFFFh (x16) into the first spare location (column address 2,048 for x8 devices, or 1,024 for x16 devices) of the first or second page of each bad block. System software should check the first spare address on the first and second page of each block prior to performing any erase or formatting operations on the NAND Flash device. A bad-block table can then be created, enabling system software to map around these areas. Factory testing is performed under worst-case conditions. Because blocks marked "bad" may be marginal, it may not be possible to recover this information if the block is erased. If the NAND Flash device is erased before these operations are performed, system software must determine which blocks are bad by writing and verifying valid information in each memory location in the device. After writing and verifying all locations, the device must be fully erased and checked to verify that each block has erased properly. Over time, some memory locations may fail to program or erase properly. In order to ensure that data is stored properly over the life of the NAND Flash device, certain precautions must be taken, including: * Always check status after a WRITE or ERASE operation. * Under typical use conditions, utilize a minimum of 1-bit ECC for each 528 bytes of data. * Use a bad-block replacement algorithm. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 50 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics Electrical Characteristics Stresses greater than those listed under Absolute Maximum Ratings by Device (see Table 15) may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Table 15: Absolute Maximum Ratings by Device Device Symbol MT29F1GxxABB MT29F1GxxABB MT29F1GxxABB Short circuit output current, I/Os Table 16: VIN VCC TSTG Supply voltage on any ball relative to VSS Storage temperature Min Max Unit -0.6 -0.6 -65 +2.45 +2.45 +150 5 V V C mA Recommended Operating Conditions Parameter/Condition Operating temperature VCC supply voltage Supply voltage PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Commercial Extended MT29F1GxxABB Symbol Min Typ Max Units TA TA VCC VSS 0 -40 1.65 0 - - 1.8 0 70 85 1.95 0 oC 51 oC V V Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics VCC Power Cycling Micron NAND Flash devices are designed to prevent data corruption during power transitions. VCC is internally monitored. (The WP# signal permits additional hardware protection during power transitions.) When VCC reaches 1.5V, a minimum of 100s should be allowed for the Flash device to initialize before any commands are executed (see Figure 43 for the states of signals during VCC power cycling). The RESET command must be issued to all CE#s after the NAND Flash device is powered on. Each CE# will be busy for a maximum of 1ms after a RESET command is issued. Figure 43: AC Waveforms During Power Transitions 1.8V device: 1.5V 1.8V device: 1.5V VCC CLE tCS CE# WP# LOCK1 WE# 100s (MIN) ALE RE# FFh I/Ox 1ms (MAX) R/B# Don't Care Undefined Notes: 1. If the system requires the LOCK features to be enabled, then the LOCK signal must be HIGH during power-up. If the LOCK features are to be disabled, then the LOCK signal should be held LOW during power-up. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 52 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics Table 17: DC and Operating Characteristics, VCC = 1.65-1.95V Parameter Sequential READ current PROGRAM current ERASE current Standby current (TTL) Standby current (CMOS) Input leakage current Output leakage current Input high voltage Input low voltage, all inputs Output high voltage Output low voltage Output low current (R/B#) Table 18: Conditions Symbol Min Typ Max Unit CYCLE = 50ns; CE# = VIL; IOUT = 0mA - - CE# = VIH; WP# = 0V/VCC CE# = VCC - 0.2V; WP# = 0V/VCC VIN = 0V to VCC VOUT = 0V to VCC I/O [7:0], I/O [15:0], CE#, CLE, ALE, WE#, RE#, WP#, R/B#, LOCK - IOH = -100A IOL = 100A VOL = 0.1V ICC1 - 10 20 mA ICC2 ICC3 ISB1 ISB2 - - - - 10 10 - 10 20 20 1 50 mA mA mA A ILI ILO VIH - - 0.8 x VCC - - - 10 10 VCC + 0.3 A A V VIL VOH VOL IOL -0.3 VCC - 0.1 - 3 - - - 4 0.2 x VCC - 0.1 - V V V mA t Valid Blocks Parameter Valid block number Symbol Device Min Typ Max Unit Notes NVB MT29F1GxxABB 1,004 - 1,024 blocks 1, 2 Notes: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad blocks after shipping. Additional bad blocks may develop over time; however, the total number of available blocks will not drop below NVB during the endurance life of the device. Do not erase or program blocks marked "invalid" by the factory. 2. Block 00h (the first block) is guaranteed to be valid, and does not require error correction for up to 1,000 PROGRAM/ERASE cycles. Table 19: Capacitance Description Input capacitance Input/output capacitance (I/O) Symbol Device Max Unit Notes CIN CIO MT29F1GxxABB MT29F1GxxABB 10 10 pF pF 1, 2 1, 2 Notes: 1. These parameters are verified in device characterization and are not 100 percent tested. 2. Test conditions: TC = 25C; f = 1 MHz; VIN = 0V. Table 20: Test Conditions Parameter Input pulse levels Input rise and fall times Input and output timing levels Output load MT29F1GxxABA MT29F1GxxABA Value Notes 0.0V to 1.8V 5ns VCC/2 1 TTL GATE and CL = 30pF 1, 2 Notes: 1. Verified on device characterization; not 100 percent tested. 2. Outputs tested at full drive strength. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 53 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics Table 21: AC Characteristics - Command, Data, and Address Input Parameter Symbol Min Max Unit Notes ALE to data start ALE hold time ALE setup time CE# hold time CLE hold time CLE setup time CE# setup time Data hold time Data setup time WRITE cycle time WE# pulse width HIGH WE# pulse width WP# setup time tADL 100 10 25 10 10 25 25 10 20 45 15 25 30 - - - - - - - - - - - - - ns ns ns ns ns ns ns ns ns ns ns ns ns 1 t ALH t ALS tCH t CLH t CLS t CS t DH tDS t WC tWH tWP tWW Notes: 1. Timing for tADL begins in the ADDRESS cycle, on the final rising edge of WE#, and ends with the first rising edge of WE# data output. Table 22: AC Characteristics - Normal Operation Parameter Symbol ALE to RE# delay CE# access time CE# HIGH to output High-Z CLE to RE# delay CE# HIGH to output hold Cache busy in PAGE READ CACHE MODE (first 31h) Cache busy in PAGE READ CACHE MODE (next 31h and 3Fh) Ouput High-Z to RE# LOW Data transfer from Flash array to data register READ cycle time RE# access time RE# HIGH hold time RE# HIGH to output hold RE# HIGH to WE# LOW RE# HIGH to output High-Z RE# pulse width Ready to RE# LOW Reset time (READ/PROGRAM/ERASE/power-up) tAR t RR RST WE# HIGH to busy WE# HIGH to RE# LOW t WB tCEA tCHZ tCLR tCOH tDCBSYR1 tDCBSYR2 tIR tR tRC tREA tREH t RHOH tRHW tRHZ tRP t tWHR Min Max Unit Notes 10 - - 10 15 - tDCBSYR1 0 - 50 - 15 15 100 - 25 20 - - 45 45 - - 3 25 - 25 - 30 - - - 100 - - 5/10/500/ 1,000 100 - ns ns ns ns ns s s ns s ns ns ns ns ns ns ns ns s 1 1 1,2 1 1 1 1 1,2 1 1, 3 1 1 1 1 1, 2 1 1 1, 4 ns ns 1, 4, 5 1 - 80 Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full. 2. Transition is measured 200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested. 3. When VCC is less than 1.7V down to 1.65V, tRC MIN is 60ns. 4. If RESET (FFh) command is loaded at ready state, the device goes busy for maximum 5s. 5. Do not issue a new command during tWB, even if R/B# is ready. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 54 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Electrical Characteristics Table 23: PROGRAM/ERASE Characteristics Parameter Symbol Number of partial page programs Block erase time Busy time for cache program Busy time for PROGRAM ERASE on locked block Busy time for OTP DATA PROGRAM operation if OTP is protected Last page program time Page program time Notes: 1. 2. 3. NOP BERS t CBSY tLBSY t OBSY t tLPROG t PROG Typ Max Unit Notes - 2 3 8 3 700 3 30 cycle ms s s s 1 2 - 250 - 700 - s 3 4 Eight total to the same page. CBSY MAX time depends on timing between internal program completion and data in. tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) address load time (last page) - data load time (last page). 4. More than 50 percent of the pages will meet typical tPROG at 1.8V and 25C. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN t 55 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Timing Diagrams Figure 44: COMMAND LATCH Cycle tCLS tCLH tCS tCH CLE CE# tWP WE# tALS tALH ALE tDH tDS I/Ox COMMAND Don`t Care Note: Figure 45: The x16 devices must have I/O[15:8] set to "0." ADDRESS LATCH Cycle CLE tCLS tCS tWC CE# tWH tWP WE# tALS tALH tDS tDH ALE I/Ox Address Don`t Care Note: PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Undefined The x16 devices must have I/O[15:8] set to "0." 56 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 46: INPUT DATA LATCH Cycle CLE tCLH CE# tALS tCH ALE tWC tWP tWP tWP WE# tWH tDS tDH tDS DIN 0 I/Ox tDH DIN 1 tDS tDH DIN Final1 Don`t Care Note: Figure 47: DIN Final = 2,112 (x8) or 1,056 (x16). SERIAL ACCESS Cycle after READ tCEA CE# tREA tCHZ1 tREA1 tREA tRP tREH tCOH RE# tRHZ1 DOUT I/Ox tRR DOUT tRHZ1 tRHOH DOUT tRC R/B# Don`t Care Note: PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Transition is measured 200mV from steady-state voltage with load. This parameter is sampled and not 100 percent tested. 57 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 48: READ STATUS Cycle tCLR CLE tCLS tCLH tCS CE# tWP tCH WE# tCEA tWHR tCHZ tRP RE# tCOH tRHZ tDS tDH tIR 70h I/Ox tREA tRHOH Status output Don`t Care Figure 49: PAGE READ Operation CLE CE# WE# ALE tR R/B# RE# I/Ox 00h Address (4 cycles) 30h Data output (Serial access) Don`t Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 58 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 50: READ Operation with CE# "Don't Care" CLE CE# RE# ALE tR R/B# WE# I/Ox 00h Address (4 cycles) 30h Data output tCEA CE# tREA RE# I/Ox Figure 51: Out Don`t Care RANDOM DATA READ Operation CLE tCLR CE# WE# tWB tAR tWHR ALE tREA tRC RE# tRR I/Ox 00h Col add 1 Col add 2 Column address N R/B# Row add 1 Row add 2 DOUT N 30h tR DOUT N+1 05h Col add 1 Col add 2 E0h DOUT M DOUT M+1 Column address M Busy Don't Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 59 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Figure 52: PAGE READ CACHE MODE Operation, Part 1 of 2 CLE tCLS tCLH tCS tCH CE# tWC WE# tCEA ALE tRC RE# tWB tR tDS tDH I/Ox 00h tRR Col add 1 Col add 2 Column address 00h Row add 1 Row add 2 Page address M 30h tREA DOUT 0 31h tDCBSYR1 DOUT 1 DOUT 0 31h DOUT tDCBSYR2 Page address M Page address M+1 R/B# 60 Column address 0 Column address 0 1 Continued to 1 of next page Don't Care 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Figure 53: PAGE READ CACHE MODE Operation, Part 2 of 2 CLE tCLH tCLS tCS tCH CE# WE# tCEA ALE tRC RE# tWB tDS tDH I/Ox tRR DOUT 0 31h DOUT tREA tDCBSYR2 DOUT 1 Page address M+1 DOUT DOUT 0 31h tDCBSYR2 DOUT 1 Page address M+2 DOUT DOUT 0 3Fh tDCBSYR2 DOUT 1 DOUT Page address M+x R/B# 61 Column address 0 1 Column address 0 Column address 0 Don't Care Continued from 1 of previous page 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Figure 54: PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2 CLE tCLS tCLH tCS tCH CE# tWC WE# tCEA ALE tRC RE# tREA tDS tDH I/Ox 00h Col add 1 Col add 2 Column address 00h Row add 1 Row add 2 Page address M 30h 70h Status 31h I/O 5 = 0, Cache busy = 1, Cache ready 70h Status 00h I/O 6 = 0, Cache busy = 1, Cache ready DOUT 0 DOUT 1 31h DOUT Page address M 70h Status 00h DOUT 0 I/O 6 = 0, Cache busy = 1, Cache ready 62 Column address 0 Page address M+1 Column address 0 1 Continued to 1 of next page Don't Care 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Figure 55: PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2 CLE tCLS tCLH tCS tCH CE# WE# tCEA ALE tRC RE# tDS tDH I/Ox 31h DOUT tREA 70h Status 00h DOUT 0 I/O 6 = 0, Cache busy = 1, Cache ready DOUT 1 Page address M+1 63 Column address 0 1 DOUT 31h 70h Status 00h I/O 6 = 0, Cache busy = 1, Cache ready DOUT 0 DOUT 1 Page address M+2 Column address 0 DOUT 3Fh 70h Status 00h DOUT 0 I/O 6 = 0, Cache busy = 1, Cache ready DOUT 1 DOUT Page address M+x Column address 0 Don't Care Continued from 1 of previous page 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 56: READ ID Operation CLE CE# WE# tAR ALE RE# tWHR 90h I/Ox 00h tREA Byte 1 Byte 0 Byte 21 Byte 31 Byte 4 Manufacturer ID1 Device ID1 Address, 1 cycle Notes: 1. See Table 8 on page 25 for byte definitions. Figure 57: PROGRAM Operation with CE# "Don't Care" CLE CE# WE# ALE I/Ox 80h Address (4 cycles) Data input tCS Data input 10h tCH CE# tWP WE# PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Don`t Care 64 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 58: PROGRAM PAGE Operation CLE CE# tWC tADL WE# tWB tPROG ALE RE# I/Ox 80h Col add 1 Col add 2 Row add 1 DIN N Row add 2 SERIAL DATA INPUT command DIN M 1 up to m Byte serial input 10h 70h PROGRAM command READ STATUS command Status R/B# x8 device: m = 2,112 bytes x16 device: m = 1,056 words Figure 59: Don`t Care PROGRAM PAGE Operation with RANDOM DATA INPUT CLE CE# tWC tADL tADL WE# tWB tPROG ALE RE# I/Ox 80h Col Col Row Row add 1 add 2 add 1 add 2 SERIAL DATA INPUT command DIN N DIN N+1 Serial input 85h Col add 1 Col add 2 RANDOM DATA Column address INPUT command DIN N DIN N+1 Serial input 10h 70h PROGRAM command READ STATUS command Status R/B# Don`t Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 65 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 60: INTERNAL DATA MOVE Operation CLE CE# tADL tWC WE# tWB tWB tPROG ALE RE# I/Ox 00h Col add 1 Col add 2 Row add 1 Row add 2 35h 85h tR Col Row Row Data Col add 1 add 2 add 1 add 2 1 Data N 10h 70h Status READ STATUS Busy command Busy R/B# INTERNAL DATA MOVE Figure 61: Don`t Care PROGRAM PAGE CACHE MODE Operation CLE CE# tADL tWC tADL WE# tWB tPROG tWBtCBSY ALE RE# I/Ox 80h Col Col add 1 add 2 Row add 1 Row add 2 SERIAL DATA INPUT command DIN N DIN M Serial input 80h 15h Col Col add 1 add 2 Row Row add 1 add 2 DIN N PROGRAM DIN M 10h 70h Status PROGRAM R/B# Last page input and programming tCSBY: Max 700s Don`t Care PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 66 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN Figure 62: PROGRAM PAGE CACHE MODE Operation Ending on 15h CLE CE# tADL tWC WE# ALE RE# I/Ox 80h Serial data input Col Col add 1 add 2 Row add 1 Row add 2 DIN N DIN M 15h 70h Status 80h Col Col Row Row Row add 1 add 2 add 1 add 2 add 3 Serial input PROGRAM Last page -1 DIN N DIN M 15h 70h Status 70h Status PROGRAM Last page Poll status until: I/O6 = 1, Ready To ensure PROGRAM success, last 2 pages: I/O5 = 1, Ready I/O0 = 0, Last page PROGRAM successful I/O1 = 0, Last page -1 PROGRAM successful 67 Don`t Care 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Timing Diagrams Figure 63: BLOCK ERASE Operation CLE CE# tWC WE# tWB tBERS ALE# RE# I/Ox 60h Row add 1 Row add 2 Row address D0h 70h ERASE command Status READ STATUS command Busy R/B# Figure 64: ERASE SETUP command Don`t Care RESET Operation CLE CE# tWB WE# tRST R/B# I/Ox FFh RESET command PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 68 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Package Dimensions Package Dimensions Figure 65: 63-Ball VFBGA Package 0.65 0.05 Seating plane Solder ball material: 96.5% Sn, 3%Ag, 0.5% Cu A 0.10 A Substrate material: Plastic laminate Mold compound: Epoxy novolac 7.20 63X O0.45 Dimensions apply to solder balls post reflow. Pre-reflow ball is O0.42 on a O0.4 SMD ball pad. 0.80 TYP Ball A1 ID Ball A1 ID Ball A1 Ball A10 0.80 TYP CL 8.80 13.00 0.10 4.40 6.50 0.05 CL 3.60 1.00 MAX 5.25 0.05 10.50 0.10 Note: All dimensions are in millimeters. (R) 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 prodmktg@micron.com www.micron.com Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. 09005aef8191f6ca alt pdf/ 09005aef8191f5ec sourcePDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 69 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved. 1Gb: x8, x16 NAND Flash Memory Revision History Revision History Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1/08 * "OTP DATA READ AFh-30h" on page 38: Added comment regarding OTP DATA READ followed by PAGE READ CACHE MODE. Rev. D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/07 * "PROGRAM PAGE CACHE MODE 80h-15h" on page 31: Revised last paragraph. Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/07 * Figure 2: Ball Assignment (x8), 63-Ball VFBGA on page 8: Renumbered ball assignments. * Figure 3: Ball Assignment (x16), 63-Ball VFBGA on page 9: Renumbered ball assignments. * Former Figure 10: Time Constants on page 17: Converted figure to equation format. * Former Figure 11: Minimum Rp on page 18: Converted figure to equation format. * "OTP DATA PROGRAM A0h-10h" on page 35: Revised RANDOM DATA INPUT (85h) discussion. * "Error Management" on page 50: Modified second bullet point wording. * VCC Power Cycling and Figure 43: AC Waveforms During Power Transitions on page 52: Changed 10s to 100s. * Table 22: AC Characteristics - Normal Operation on page 54: Removed tRLOH. Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11/06 * "Features" on page 4: Added required RESET after power-up; changed ready/busy pin to ready/busy signal. * Table 22: AC Characteristics - Normal Operation on page 54: Deleted tLBSY and t OBSY MIN values and notes; changed tOBSY (MAX) to 30s; moved tLBSY and tOBSY to table 23. * Table 23: PROGRAM/ERASE Characteristics on page 55: Changed tPROG (TYP) to 250s and added note 4. Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/06 * Initial release. PDF: 09005aef81dc05df / Source: 09005aef821d5f08 1gb_nand_m48a__2.fm - Rev. E 1/08 EN 70 Micron Technology, Inc., reserves the right to change products or specifications without notice. (c)2006 Micron Technology, Inc. All rights reserved.