MT29F1G08ABBHC-ET:B - Micron Technology, Inc.

Products and specifications discussed herein are subject to change by Micron without notice.

1Gb: x8, x16 NAND Flash Memory

Features

PDF: 09005aef81dc05df / Source: 09005aef821d5f08 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

1Gb NAND Flash Memory

MT29F1GxxABB

Features

• Organization

–Page size x8: 2,112 bytes (2,048 + 64 bytes)

–Page size x16: 1,056 words (1,024 + 32 words)

–Block size: 64 pages (128K + 4K bytes)

–Device size: 1Gb: 1,024 blocks

•READ performance

–Random READ: 25µs (MAX)

–Sequential READ: 50ns (MIN)

•WRITE performance

–PR OGRAM PAGE: 250µs (TYP)

–BLOCK ERASE: 2.0ms (TYP)

• Endurance: 100,000 PROGRAM/ERASE cycles

• Data retention: 10 years

• The first block (block address 00h) is guaranteed to

be valid without ECC (up to 1,000 PROGRAM/

ERASE cycles)

•V

CC: 1.65–1.95V

• Automated PROGRAM and ERASE

• Basic NAND Flash command set

–PAGE READ, RANDOM DATA READ, READ ID,

READ STATUS, PROGRAM PAGE, RANDOM DATA

INPUT, PROGRAM PAGE CACHE MODE, INTER-

NAL DATA MOVE, INTERNAL DATA MOVE with

RANDOM DATA INPUT, BLOCK ERASE, RESET

• New commands

–PAGE READ CACHE MODE

–READ ID2 (contact factory)

–READ UNIQUE ID (contact factory)

–Programmable I/O

–OTP

–BLOCK LOCK

• Operation status byte: Provides a software method

for detecting:

–Operation completion

–Pass/fail condition

–Write-protect status

• Ready/busy# signal (R/B#): Provides a hardware

method of detecting operation completion

• LOCK signal: Protects selectable ranges of bloc ks

Figure 1: 63-Ball VFBGA x8

• WP# signal: Write-protects the entire device

• Reset required after power-up

N otes: 1. For part numbers and device markings, see

Figure 2 on page 2.

Options1

• Configuration

–x8

–x16

•Package

–63-ball VFBGA

13mm x 10.5mm x 1.0mm

• Operating temperature

–Commercial temperature (0 to +70°C)

–Extended temperature (–40°C to +85°C)

PDF: 09005aef81dc05df / Source: 09005aef821d5f08 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

1Gb: x8, x16 NAND Flash Memory

Part Numbering Information

Micron NAND Flash devices are available in several configurations and

densities.

Figure 2: Part Number Chart

Valid Part Number Combinations

After building the part number from the part numbering chart, verify that the part

number is offered and valid by using the Micron Param etric Part Search Web site at

www.micron.com/products/parametric. If the device required is not on this list, contact

the factory.

MT 29F 1G 08 A B B HC xx xx xx ES :B

Micron Technology

Product Family

29F = Single-Supply NAND Flash Memory

Density

1G = 1Gb

Device Width

08 = 8 bits

16 = 16 bits

Operating Voltage Range

B = 1.8V (1.65V–1.95V)

Feature Set

A = Feature set A

B = Feature set B

Die Revision

B = Second generation

Production Status

Blank = Production

ES = Engineering Sample

QS = Qualification Sample

Operating Temperature Range

Blank = Commercial (0°C to +70°C)

ET = Extended (–40° to +85°C)

Block Option

Reserved for Future Use

Flash Performance

Reserved for Future Use

Package Codes

HC = 63-pin VFBGA (lead-free)

Classification

# of die # of CE# # of R/B# I/O

A 1 1 1 Common

PDF: 09005aef81dc05df / Source: 09005aef821d5f08 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

1Gb: x8, x16 NAND Flash Memory

Table of Contents

Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Part Numbering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Valid Part Number Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Memory Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

READ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

READY/BUSY# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Command Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

READ Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

PAGE READ 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

RANDOM READ 05h-E0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

PAGE READ CACHE MODE START 31h; PAGEREAD CACHE MODE START LAST 3Fh. . . . . . . . . . . . . . . 25

READ ID 90h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

ONFI READ ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

ONFI READ PARAMETER PAGE Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

READ STATUS 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

PROGRAM Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PROGRAM PAGE 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SERIAL DATA INPUT 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

RANDOM DATA INPUT 85h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

PROGRAM PAGE CACHE MODE 80h-15h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

INTERNAL DATA MOVE Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

READ FOR INTERNAL DATA MOVE 00h-35h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

INTERNAL DATA MOVE 85h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

BLOCK ERASE 60h-D0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

One-Time Programmable (OTP) Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

OTP DATA PROGRAM A0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

OTP DATA PROTECT A5h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

OTP DATA READ AFh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

BLOCK LOCK Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

WP# and BLOCK LOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

UNLOCK 23h-24h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

LOCK 2Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

LOCK-TIGHT 2Ch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

BLOCK LOCK READ STATUS 7Ah . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

RESET FFh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Programmable Drive Strength. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

PROGRAMMABLE I/O DRIVE STRENGTH B8h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

WRITE PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Error Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

VCC Power Cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Timing Diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

PDF: 09005aef81dc05df / Source: 09005aef821d5f08 Micron Technology, Inc., reserves the right to change products or specifica tions without notice.

1Gb: x8, x16 NAND Flash Memory

List of Figur es

List of Figures

Figure 1: 63-Ball VFBGA x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

Figure 2: Part Number Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3: Functional Block Diagram: 1Gb NAND Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 4: Ball Assignment (x8), 63-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Figure 5: Ball Assignment (x16), 63-Ball VFBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 6: Array Organization for MT29F1G08 (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 7: Array Organization for MT29F1G16 (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 8: Memory Map (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Figure 9: Memory Map (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Figure 10: READY/BUSY# Open Drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11: tFall and tRise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 12: Iol vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 13: TC vs. Rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 14: PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 15: RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 16: PAGE READ CACHE MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Figure 17: READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 18: ONFI READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 19: ONFI READ PARAMETER PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Figure 20: Status Regist er Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Figure 21: PROGRAM and READ STATUS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Figure 22: RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Figure 23: PROGRAM PAGE CACHE MODE Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Figure 24: INTERNAL DATA MOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 25: INTERNAL DATA MOVE with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 26: BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 27: OTP DATA PROGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 28: OTP DATA PROTECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 29: OTP DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 30: Flash Array Protected: Inverted Area Bit = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 31: Flash Array Protected: Invert Area Bit = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 32: UNLOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 33: LOCK Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 34: LOCK-TIGHT Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 35: PROGRAM/ERASE Issued to Locked or Locked-Tight Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 36: LOCKED-TIGHT BLOCKS to LOCKED BLOCKS Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Figure 37: BLOCK LOCK READ STATUS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Figure 38: BLOCK LOCK Flow Chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Figure 39: RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Figure 40: Programmable I/O Drive Strength Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Figure 41: ERASE Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 42: ERASE Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 43: PROGRAM Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 44: PROGRAM Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 45: AC Waveforms During Power Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 46: COMMAND LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 47: ADDRESS LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59

Figure 48: INPUT DATA LATCH Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 49: SERIAL ACCESS Cycle after READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 50: READ STATUS Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 51: PAGE READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 52: READ Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 53: RANDOM DATA READ Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 54: PAGE READ CACHE MODE Operation, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 55: PAGE READ CACHE MODE Operation, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 56: PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

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1Gb: x8, x16 NAND Flash Memory

List of Figur es

Figure 57: PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Figure 58: READ ID Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 59: PROGRAM Operation with CE# “Don’t Care” . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Figure 60: PROGRAM PAGE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 61: PROGRAM PAGE Operation with RANDOM DATA INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Figure 62: INTERNAL DATA MOVE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 63: PROGRAM PAGE CACHE MODE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

Figure 64: PROGRAM PAGE CACHE MODE Operation Ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

Figure 65: BLOCK ERASE Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 66: RESET Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Figure 67: 63-Ball VFBGA Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

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1Gb: x8, x16 NAND Flash Memory

List of Tables

Table 1: Ball Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 2: Array Addressing: MT29F1G08 (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 3: Array Addressing: MT29F1G16 (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 4: Operational Example (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 5: Operational Example (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 6: Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 7: Command Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 8: Device ID and Configuration Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 9: Status Register Bit Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 10: BLOCK LOCK Address Cycle Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Table 11: BLOCK LOCK Status Register Bit Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Table 12: Status Register Contents After Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 13: I/O Drive Strength Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Table 14: Programmable I/O Drive Strength Register READ/WRITE Timing. . . . . . . . . . . . . . . . . . . . . . . . . . 51

Table 15: Absolute Maximum Ratings by Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 16: Recommended Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Table 17: DC and Operating Characteristics, VCC = 1.65–1.95V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 18: Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 19: Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 20: Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Table 21: AC Characteristics – Command, Data, and Address Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 22: AC Characteristics – Normal Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Table 23: PROGRAM/ERASE Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

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1Gb: x8, x16 NAND Flash Memory

General Description

The MT29F1G08 and MT29F1G16 are both 1Gb NAND Flash memory devices. NAND

Flash technolog y provides a cost-effective solution for applications requiring high-de n -

sity, solid-state storage. The MT29F1Gxx devices include standard NAND Flash features

as well as new features designed to enhanc e system-level performance.

The M T29F1Gx x d evices u s e a m ult i p l e x e d 8- or 16-bit bus (I/O[7:0] or I/O[15:0]) to

transfer data, address, and instruction information. The five control signals (CLE, ALE,

CE#, RE#, WE#) control the NAND Flash command bus interface protocol. Additional

signals control hardware write protection (WP#), monitor the device ready/busy (R/B#)

state, and enable BLOCK LOCK functions (LOCK).

This hardware interface creates a low-ball-count device with a standard ball arrange-

ment that is the same from one density to another, enabling future upgrades to higher

densities with out any board redesign.

MT29F1Gxx devices contain 1,024 erasable blocks. Each block is subdivided into 64 pro-

grammable pages. Each page consists of 2,112 b ytes (x8), or 1,056 wor ds (x16). The pages

are further divided into a 2,048-byte data storage region with a separate 64-byte ar ea on

the x8 device; and on the x16 device, separate 1,024-word and 32-wor d areas. The 64-

byte and 32-word areas are typically used for error correction functions.

On-chip control logic automates PROGRAM and ERASE o per ations to maxim ize cycle

endu rance. PROGRAM/ERASE endurance is specified at 100,000 cycles when using

appropriate error correction code (ECC) and bad-bl ock-management softw are.

Figure 1: Functional Block Diagram: 1Gb NAND Flash

Address Register

Data Register

Cache Register

Status Register

Command Register

CE#

CLE

ALE

WE#

RE#

WP#

LOCK

R/B#

I/O [7:0]

I/O [15:0]

Control

Logic

I/O

Control

Row Decode

Column Decode

VCC VSS

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1Gb: x8, x16 NAND Flash Memory

General Description

Figure 2: Ball Assignment (x8), 63-Ball VFBGA

Notes: 1. For package dimensions, see Figure 65 on page 69.

WP#

Vss

ALE

RE#

I/O0

I/O1

I/O2

21 8

R/B#

Vcc

I/O7

Vss

CLE

LOCK

I/O3

WE#

I/O5

I/O6

9106

CE#

Vcc

I/O4

Top View, Ball Down

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1Gb: x8, x16 NAND Flash Memory

General Description

Figure 3: Ball Assignment (x16), 63-Ball VFBGA

Notes: 1. For package dimensions, see Figure 65 on page 69.

WP#

I/O8

I/O0

Vss

ALE

RE#

I/O1

I/O9

I/O2

21 8

R/B#

Vcc

I/O15

Vss

CLE

LOCK

I/O10

I/O3

I/O11

WE#

I/O7

I/O14

I/O6

I/O13

9106

CE#

I/O5

I/O12

Vcc

I/O4

Top View, Ball Down

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1Gb: x8, x16 NAND Flash Memory

General Description

Table 1: Ball Descriptions

Symbol Type Ball Function

ALE Input Address latch enable: During the time ALE is HIGH, address information is

transferred from I/O[7:0] into the on-chip addre ss register. Upon a LOW to HIGH

transition on WE#—when address information is not being loaded—t he ALE signals

should be driven LOW.

CE# Input Chip enable: Gates transfers between the host system and the NAND Flash device.

After the device becomes busy or starts a PROGRAM or ERASE operation, CE# can be

de-asserted. See “Bus Operation” on page 16 for additional operational details.

CLE Input Command latch enab le: When CLE is HIGH, inf ormation i s tr a ns ferred from

I/O [7:0] to the on-chip command register on the rising edge of WE#. When

command information is not being loaded, the CLE signals should be driven LOW.

LOCK Input When LOCK is HIGH during power-up, the BLOCK LOCK function is enabled.

To disable BLOCK LOCK, connect LOCK to VSS during power-up, or leave it

unconnected (in t ernal pull-down).

RE# Input Read enable: Gates transfers from the NAND Flash device to the host syst em.

WE# Input Write enable: Gates transfers from the host system to the NAND Flash device.

WP# Input W r it e pr ot e ct: Protects ag ainst inadvertent PROGRAM and ERASE operations. All

PROGRAM an d ERASE operat ions are disabled when WP# is LOW.

I/O[7:0]

(x8)

I/O[15:0]

(x16)

I/O Data inputs/outputs: Bidirectional I/O signals transfer address, data and instruction

information. Data is output only during READ operations; at other times the I/O

signals are inputs.

R/B# Output Ready/busy: The ready/busy signal is an open-drain, active-LOW output, that uses an

external pull-up resistor. The signal is used to indicate when the chip is processing a

PROGRAM or ERASE operation. The signal is also used during READ operations to

indicate when data is being transferred from the array into the serial data register.

When these operations have completed, the ready/ bu sy signal retur ns to th e high-

impedance state.

VCC Supply VCC: The VCC ball is the power supply.

VSS Supply VSS: The VSS ball is the ground connection.

NC – No connect: NC balls are not internally connected. These balls can be driven or left

unconnected.

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1Gb: x8, x16 NAND Flash Memory

Architecture

Architecture The MT29F1G08 and MT29F1G16 use NAND Flash electrical and command interfaces.

Data, commands, and addresses are multiplexed onto the same signals. This provides a

memory device with a low ball count.

The internal memory array is accessed on a page basis. When performing READs, a pag e

of data is copied from the memory array into the data register. Once copied to the data

the x16 device.

The memory array is programmed on a page basis. After the starting address is loaded

into the internal add r ess r egister, data is sequentially written to the internal data r egis ter

up to the end of a page. After all page data has been loaded into the data register, array

programm ing is started.

In order to increase programming bandwidth, this device incorporates a cache register.

In the cache programming mode, data is first copied into the cache register and then

into the data register. Once the data is copied into the data register, programming

begins . After the data register has been loaded and programming has started, the cache

into the cache register takes place while page programming is in process.

The INTERNAL DATA MOVE command also uses the internal cache register. Normally,

moving data from one area of external memory to another uses a large number of exter-

nal memory cy cles. By using th e internal cache r egister and data register, array data can

be copied from one page and then programmed into another without using external

memory cycles.

Addressing The MT29F1G08 and MT29F1G16 devices do not have dedicated address balls.

Addresses are loaded using a 4-cycle sequence as shown in Tables 2 and 3 on pages 12

and 13. Table 2 presents ad dress functions internal to the MT29F1G08 device; Table 3

presents address functions internal to the MT29F1G16. See Figures 6 and 7 on pages 14

and 15 for additional memory mapping and addressing details.

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1Gb: x8, x16 NAND Flash Memory

Addressing

Figure 4: Array Organization for MT29F1G08 (x8)

Notes: 1. Block address concatenated with page address = actual page address. CAx = column

address; PAx = page address; BAx = block address.

2. Note that the 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8

device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each

page are “out of bounds,” do not exist in the device, and cannot be addressed.

Table 2: Array Addressing: MT29F1G08 (x8)

Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second LOW LOW LOW LOW CA11 CA10 CA9 CA8

Third BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

Cache register

Data register

1,024 blocks

per device 1 block

642,048

2,112 bytes

I/O 7

I/O 0

1 page = (2K + 64 bytes)

1 block = (2K + 64) bytes x 64 pages

= (128K + 4K) bytes

1 device = (2K + 64) bytes x 64 pages

x 1,024 blocks

= 1,056 Mbits

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1Gb: x8, x16 NAND Flash Memory

Addressing

Figure 5: Array Organization for MT29F1G16 (x16)

Notes: 1. Block address concatenated with page address = actual page address. CAx = column

address; PAx = page address; BAx = block address.

2. I/O[15:8] are not used during addressing sequence and should be driven LOW.

3. Note that the 11-bit column address is capable of addressing from 0 to 2,047 words on a

x16 device; however, only words 0 through 1,055 are valid. Words 1,056 through 2,047 of

each page are “out of bounds,” do not exist in the device, and cannot be addressed .

Table 3: Array Addressing: MT29F1G16 (x16)

Cycle I/O[15:8] I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

First LOW CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0

Second LOW LOW LOW LOW LOW LOW CA10 CA9 CA8

Third LOW BA7 BA6 PA5 PA4 PA3 PA2 PA1 PA0

Fourth LOW BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8

Cache register

Data register

1,024 blocks

per device 1 block

321,024

1,056 words

I/O 15

I/O 0

1 page = (1K + 32) words

1 block = (1K + 32) words x 64 pages

= (64K + 2K) words

1 device = (1K + 32) words x 64 pages

x 1,024 blocks

= 1,056 Mbits

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1Gb: x8, x16 NAND Flash Memory

Addressing

Memory Mapping

Figure 6: Memory Map (x8)

Notes: 1. As shown in Table 2 on page 12, the high 4 bits of the second ADDRESS cycle have no

assigned address bits. However, these 4 bits must be held LOW during the ADDRESS cycle

to ensure that the address is interpreted correctly by the NAND Flash device. These extra

bits are accounted for in the second ADDRESS cycle even though they have no address bits

assigned to them.

2. Note that the 12-bit column address is capable of addressing from 0 to 4,095 bytes on a x8

device; however, only bytes 0 through 2,111 are valid. Bytes 2,112 through 4,095 of each

page are “out of bounds,” do not exist in the device, and cannot be addressed.

Table 4: Operational Example (x8)

Block Page Min Address in Page Max Address in Page Out of Bounds Addresses in Page

0 0 0x00000000 0x0000083F 0x00000840–0x00000FFF

0 1 0x00010000 0x0000183F 0x00010840–0x00010FFF

0 2 0x00020000 0x0000283F 0x00020840–0x00020FFF

…… … …

1,023 62 0xFFFE0000 0xFFFE083F 0xFFFE0840–0xFFFE0FFF

1,023 63 0xFFFF0000 0xFFFF083F 0xFFFF0840–0xFFFF0FFF

• • • • • • • • • • • •

• • •

• • • • • • • • • • • • • • • • • • •

Blocks

BA[15:6]

Pages

PA[5:0]

Bytes

CA[11:0]

012

012 63

0 1 2 2,047 • • • 2,111

1,023

Spare area

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1Gb: x8, x16 NAND Flash Memory

Addressing

Figure 7: Memory Map (x16)

Notes: 1. As shown in Table 3 on page 13, the high 5 bits of ADDRESS cycle 2 have no assigned

address bits. However, these 5 bits must be held LOW during the ADDRESS cycle to ensure

that the address is interpreted correct ly by the NAND Flash device. These extra bits are

accounted for in ADDRESS cycle 2 even though they have no address bits assigned to them.

2. Note that the 11-bit column address is capable of addressing from 0 to 2,047 words on a

x16 device; however, only words 0 through 1,055 are valid. Words 1,056 through 2,047 of

each page are “out of bounds,” do not exist in the device, and cannot be addressed .

Table 5: Operational Example (x16)

Block Page Min Address in Page Max Address in Page Out of Bounds Addresses in Page

0 0 0x00000000 0x0000041F 0x00000420–0x00000FFF

0 1 0x00010000 0x0001041F 0x00010420–0x00010FFF

0 2 0x00020000 0x0002041F 0x00020420–0x00020FFF

…… … …

1,023 62 0xFFFE0000 0xFFFE041F 0xFFFE0420–0x00020FFF

1,023 63 0xFFFF0000 0xFFFF041F 0xFFFF0420–0xFFFF0FFF

• • • • • • • • • • • •

• • •

• • • • • • • • • • • • • • • • • • •

Blocks

BA[15:6]

Pages

PA[5:0]

Words

CA[10:0]

012

012 63

0 1 2 1,023 • • • 1,055

1,023

Spare area

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1Gb: x8, x16 NAND Flash Memory

Bus Operation

Bus Operation The bus on the MT29F1Gxx devices is multiplexed. D a ta I/O, addre sses and commands

all share the same balls. I/O[15:8] are used only for data in the x16 configuration.

Addresses and commands are always supplied on I/O[7:0].

The command sequence normally consists of a COMMAND LATCH cycle, ADDRESS

LATCH cycle and a DATA cycle—either READ or WRITE.

Control Signals

CE#, WE#, RE#, CLE, ALE, LOCK, and WP control NAND Flash READ and WRITE opera-

tions.

CE# is used to enable the device. When CE# is LOW and the dev ice is not in the BUS Y

st a t e, th e N A N D Fl a s h m e m o ry will accept command, data, and address information.

When the device is not performing an operation, CE# is typically driven HIGH and the

device enters standby mode. The memory will enter standby if CE# goes HIGH while

data is being transferr ed and the de v i c e i s n o t b u s y. T h i s h elps red u c e p ower c o n s u m p t i o n

(see Figure 57 on page 64).

The CE# “Don’t Care” operati on enables the NAND Flash to reside on the same asyn-

chronous memory bus as other Flash or SRAM devices. Other devices on the memory

bus can then be accessed while the NAND Flash is busy with internal operations. This

capability is important for designs that require multiple NAND Flash device s on the

same bus. One device ca n be programmed while another is being read.

A HIGH CLE signal indicates that a COMMAND cycle is taking place. A HIGH ALE signal

signifies that an ADDRESS INPUT cycle is occurring.

Commands

Commands are written to the command register on the rising edge of WE# when all of

these conditions are met:

• CE# and ALE are LOW

•CLE is HIGH

• the device is not busy

The READ STATUS and RESET commands are different because they can be written to

the device while it is busy. Commands are transferr ed to the command r egister on the

rising edge of WE# (see Figure 26 on page 37).

Commands ar e input on I/O[7:0] only. F or devices with a x16 interface, I/O[15:8] must be

written with zeros when issuing a command.

Address Input

Addresses are written to the address register on the rising edge of WE# when all of these

conditions are met:

• CE# and CLE are LOW

•ALE is HIGH

Addresses are input on I/O[7:0] only. For devices with a x16 interface, I/O[15:8] must be

written with zeros when issuing an address.

Generally, all 4 address cycles are written to the device. An exception is the BLOCK

ERASE command, which requires only 2 address cycles (see “BLOCK ERASE Operation”

on page 33 for details).

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1Gb: x8, x16 NAND Flash Memory

Bus Operation

RANDOM DATA INPUT and OUTPUT commands need only column addr esses, s o only 2

address cycles are required. Refer to the command descriptions to determine the

addressing requirements for each command.

Data Input

Data is written to the data register on the rising edge of WE# when these conditions are

met:

• CE#, CLE, and ALE are LOW

• the device is not busy

Data is input on I/O[7:0] for x8 devices, and I/O[15:0] on x16 devices. See Figure46 on

page 57 for additional data input details.

READ

After a READ command is issued, data is transferred from the memory array to the data

transfer is complete. When data is available in the data register, it is clocked out of the

part by RE# going LOW (see Figure 12 on page 21 for timing details).

The READ STATUS (70h) command or the READ Y/B USY signal can be used to determine

when the device is ready (see the READ STATUS command section starting on page 28

for details).

READY/BUSY#

The R/B# output provides a hardware method of indicating the completion of a PRO-

GRAM/ERASE/READ operation. The signal is typically HIGH, and transitions to LOW

after the appropriate command is written to the device. The signal’s open-drain driver

enables multiple R/B# outputs to be OR-tied. The signal requires a pull-up resi stor for

proper operation. The READ STATUS command can be used in place of R/B#. Typically,

R/B# would be connected to an interrupt ball on the system controller (see Figure8 on

page 18).

The combination of Rp and the capacitive loading of the R/B# circuit determine the

R/B# rise time. The actual value used for Rp depends on the system timing requi re-

ments. Large Rp values delay R/B# signifi cantly. At the 10 percent/90 percent points on

the R/B# waveform, rise time is approximately two time constants (TC).

The R/B# fall time is determined mainly by the output impedance of R/B# and the total

load capacitance. Refer to Figures 9 and 10 on page 18, which depict approximate Rp

values using a circuit load of 100pF.

The minimum valu e for Rp is determined b y the R/B# output drive capability, the output

voltage swing, and VCC.

TC R C×=

Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.

Rp MIN, 1.8V part()

VCC MAX()VOL MAX()–

IOL ΣIL+

---------------------------------------------------------------=1.85V

3mA ΣIL+

---------------------------=

Where ΣILis the sum of the input currents of all devices tied to the R/B# pin.

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1Gb: x8, x16 NAND Flash Memory

Bus Operation

Figure 8: READY/BUSY# Open Drain

Figure 9: tFall and tRise

Notes: 1. tFall and tRise are calculated at 10 percent and 90 percent points.

2. tRise is primarily dependent on external pull-up resistor and external capacitive loading.

3. tFall ≈ 7ns at 1. 8V.

4. See TC values in Figure 11 on page 19 for approximate Rp value and TC.

Figure 10: IOL vs. Rp

Note: To calculate Rp value, see page 17.

R/B#

Open drain output

VCC

GND

Device

IOL

3.50

3.00

2.50

2.00

1.50

1.00

0.50

0.00 -1 0 2 4 0 2 4 6

tFall tRise

VCC 1.8

3.50mA

3.00mA

2.50mA

2.00mA

1.50mA

1.00mA

0.50mA

0.00mA0 2,000 4,000 6,000 8,000 10,000 12,000

IOL at 1.95V (MAX)

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1Gb: x8, x16 NAND Flash Memory

Bus Operation

Figure 11: TC vs. Rp

Notes: 1. Mode selection settings for this table:

H = Logic level HIGH

L = Logic level LOW

X = VIH or VIL

2. WP# should be biased to CMOS HIGH or LOW for standby.

Table 6: Mode Selection

CLE ALE CE# WE# RE# WP# Mode

HLL HX

Read mode Command input

LHL HX Address input

HLL HH

Write mode Command input

LHL HH Addre s s input

LLL HH

Data input

LLLH X

Sequential read and data output

LLLHHX

During READ (busy)

XXXXXH

During PROGRAM (busy)

XXXXXH

During ERASE (busy)

XXXXXL

Write protect

XXHXX0V/V

CC2Standby

1.20µs

1.00µs

800ns

600ns

400ns

200ns

0ns 0 2kΩ 4kΩ 6kΩ 8kΩ 10kΩ 12kΩ

IOL at 1.95V (MAX)

RC = TC

C = 100pf

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Notes: 1. RANDOM DATA INPUT command is limited to use within a single page.

2. RANDOM DATA READ command is limited to use within a single page.

Table 7 : Command Set

Command First Cycle Second Cycle Valid During Busy Notes

BLOCK ERASE 60h D0h No

BLOCK LOCK 2Ah – No

BLOCK LOCK READ STATUS 7Ah – No

BLOCK LOCK TIGHT 2Ch – No

BLOCK UNLOCK 23h-24h – No

OTP DATA PROGRAM A0h 10h No

OTP DATA PROTECT A5h 10h No

OTP DATA READ AFh 30h No

PAGE READ 00h 30h No

PAGE READ CACHE MODE START 31h – No

PAGE READ CACHE MODE LAST 3Fh – No

PROGRAM for INTERNAL DATA MOVE 85h 10h No

PROGRAM P AGE 80h 10h No

PROGRAM P AGE CACHE MODE 80h 15h No

PROGRAMMABLE DRIVE STRENGTH B8h – No

RANDOM DATA INPUT 85h – No 1

RANDOM DATA READ 05h E0h No 2

READ for INTERNAL DATA MOVE 00h 35h No

READ ID 90h – No

READ ID (ONFI) 90h – No

READ PARAMETER PAGE (ONFI) ECh – No

READ STATUS 70h – Yes

RESET FFh – Yes

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

READ Operations

PAGE READ 00h-30h

To enter READ mode, write a 00h command to the device, then specify the starting

address via the ADDRESS cycles, and finally, issue the 30h command. At this point, the

device enters a busy state while it retrieves data from the NAND Flash array. During this

time, the ready/busy status of the device can be monitored using the R/B# or the READ

STATUS (70h) command.

The R/B# signal is LOW when the device is busy retrieving data from the NAND Flash

array. When R/B# re turns to HIGH, data is ready for output . Pulsing the RE# line results

in data output on the I/O lines. Note that the first byte or word of data output is that

which was specified in the ADDRESS cycle. Each pulse of the RE# signal increases the

address counter by one, so additional address cycles are not requir ed when reading

sequential data .

If the system does not have a R/B# signal, NAND Flash device status can be monitored

b y issuing a READ STATUS (70h) command, then reading bit 5 or 6 from the status regis-

ter (0 = busy; 1 = ready). If the READ STATUS command is used to monitor the data

transfer, the user must re-issue the READ (00h) command to initiate data output from

the data register. The user can issue 00h only after R/B# goes HIGH or the status register

value is E0h. See Figure 54 on page 62 and Figure55 on page 63 for examples.

Figure 12: PAGE READ Operation

RE#

CE#

ALE

CLE

I/Ox 00h Address (4 cycles) Data output

(Serial access)

30h

R/B#

WE#

Don‘t Care

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

RANDOM READ 05h-E0h

The RANDOM READ command enables the user to specify a new column address so

data at single or multiple addresses can be read . The r andom read mode is e nabled after

a normal PAGE READ (00h-30h sequence).

Random data can be output after the initial PAGE READ by writing an 05h-E0h com-

mand sequence along wit h th e ne w colum n add ress (2 cycles).

The RANDOM READ command can be issued without limit within the page.

Only data on the curre nt page can be read. P ulsing RE# outputs data in the same manner

as a serial PAGE READ (see Figure13).

Figure 13: RANDOM DATA READ Operation

PAGE READ CACHE MODE START 31h; PAGE READ CACHE MODE START LAST 3Fh

Micron NAND Flash devices have a cache register that can be used to increase READ

operation speed when accessing sequential pages in a block.

A normal PAGE READ (00h-30h) command sequence is issued (see Figure 14 on page 23

for details). The R/B# signal goes LOW for tR during the time it takes to transfer the first

page of data from the memory to the data r egister. After R/B# r e turns to HIGH, the PAGE

READ CACHE MODE STAR T (31h) command is latched into the command register. R/B#

goes LOW for tDCBSYR1 while data is being transferred from the data register to the

cache register. Whe n the data register con t ents are transferred to the cache register,

another PAGE READ is automatically started as part of the 31h command. Data is trans-

ferred from the memory array to the data register at the same time data is being output

(pulsing of RE#) from the cache register. If the total time to output da ta exceeds tR, then

the PAGE READ is hidden.

The second and subsequent pages of data are transferr ed to the cache r egister b y issui ng

additional 31h commands. R/B# will stay LOW up to tDCBSYR2. This time can vary,

depending on whether the previous memory-to-data-register transfer was completed

before issuing the next 31h command. If the data transfer from memory to the data reg-

ister is not completed before the 31h command is issued, R/B# stays LOW until the

transfer is complete.

I t is not necessary to output a whole page of data before issuing another 31h command.

R/B# will stay LOW until the previous PAGE READ is complete and the data has been

transferred to the cache register.

To read out the last page of data, the P AGE READ CA CHE MODE START LAST (3Fh) com-

mand is issued. This command tr ansfe rs data fr om the data register to the ca che r e gister

without another PAGE READ (see Figure 14 on page 23 for details).

RE#

I/Ox 00h Address

(4 cycles) Data output Data output

30h 05h Address

(2 cycles) E0h

R/B#

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 14: PAGE READ CACHE MODE

RE#

CE#

ALE

CLE

I/Ox Address (4 cycles) 31h

30h 31h 3fh

R/B#

WE#

tR tDCBSYR1 tDCBSYR2 tDCBSYR2

Don‘t Care

Data output

(Serial access)

Data output

(Serial access)

Data output

(Serial access)

00h

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

READ ID 90h

The READ ID command is used to read the identifier codes from the MT29F1G08 and

MT29F1G16 devices. The READ ID command r eads a 5-b yte table that includes the man-

ufacturer ID, device configuration, and part-specific information. Tab le 8 on page 25

shows a complete listing of configuration details.

Iss uing a 90h command to the command register and a 00h command to the address

another valid command and address are issued (see Figure 15). If a 90h comma nd is

issued without an address, the device will remain in read ID mode.

Figure 15: READ ID Operation

Notes: 1. See Table 8 on page 25 for byte definitions.

Device ID1

WE#

CE#

ALE

CLE

RE#

I/Ox

Address, 1 cycle

90h 00h

Manufacturer ID1

Byte 21

Byte 0 Byte 1 Byte 31Byte 4

tAR

tREA

tWHR

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Notes: 1. b = binary; h = hex.

Table 8: Device ID and Configuration Codes

Options I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 Value1Notes

Byte 0 Manufactur er ID

Micron 001011002Ch

Byte 1 Device ID

MT29F1G08ABB 1Gb, x8, 1.8V 10100001A1h

MT29F1G16ABB 1Gb, x16, 1.8V 10110001B1h

Byte 2

Number of die 1 0 000b

Cell type SLC 0000b

Number of simultaneously

programmed pages 10000b

Interleaved operations

between multiple die Not supported

(1Gb) 00b

Cache programming Supported 11b

Byte value MT29F1GxxABB 1000000080h

Byte 3

Page size 2KB 0101b

Spare area size (bytes) 64 101b

Block size (w/o spare) 128KB 0 1 01b

Organization x8 00b

x16 11b

Serial access (MIN) 50ns 00 0xxx0b

Byte value MT29F1G08ABB x8 1001010195h

MT29F1G16ABB x16 11010101D5h

Byte 4

Reserved 0000b

Planes per die 10000b

Plane size 1Gb 000 000b

Reserved 00b

Byte value MT29F1GxxABB 0000000000h

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

ONFI READ ID

The ONFI READ ID function identifies that the device supports the ONFI specification. If

the device supports the ONFI specification, then the ONFI signature will be returned .

The ONFI signature is the ASCII encoding of ONFI:

•O = 4Fh

•N = 4Eh

•F = 46h

• I = 49h.

Re ading bey ond these four v alue s yiel ds indeterminate data. F igure 16 defines the ONFI

READ ID behavior and timings.

Iss uing a 90h command to the command register and a 20h command to the address

until another valid command and address are issued. If a 90h command is issued with-

out an address, the device will remain in the ONFI read ID mode.

Figure 16: ONFI READ ID Operation

WE#

ALE

CLE

RE#

I/O0-7 90h 20h 4Fh 4Eh 46h 49h

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

ONFI READ PARAMETER PAGE Operation

The READ PARAMETER PAGE function retrieves the data structure that describes the

device organization, features, timings, and other behavioral parameters. Figure17

defines the READ PARAMETER PAGE behavior.

Figure 17: ONFI READ PARAMETER PAGE Operation

Parameter Page Data Structure Definition

For parameters that span multiple bytes, the least significant byte of the parameter cor-

responds to the first b yte. For example, if bytes 8–9 contain a 16-bit parameter, then bits

7:0 are contained in byte 8.

WE#

ALE

CLE

RE#

R/B#

ECh 00h

P0 P1 … P1022 P1023

I/O0-7

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

READ STATUS 70h

The MT29F1G08 and MT29F1G16 devices have an 8-bit status register the softwar e can

read during device operation. On the x16 devic e, I/O[15:8] are “0” when reading the sta-

tus register. Table 9 on page 29 describes the status registe r.

After a READ STATUS (70h) command, all READ cycles w ill be from the s tatus register

until a new command is issued. Changes in the status register will be seen on 1/O[7:0] as

long as CE# and RE# are LOW. It is not necessar y to st art a new READ cycle to see these

changes.

During monitoring of the status register to determine when the tR (transfer from NAND

Flash array to data register) is complete , th e READ (0 0h) command must be re-issued to

make the change from STATUS READs to DATA READs. After the READ command has

been re-issued, pulsing the RE# line will result in outputting data, starting from the spec-

ified column address.

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Notes: 1. Status register bit 5 is “0” during the actual programming operation. If cache mode is

used, this bit will be “1” when all internal operations are complete.

2. Status register bit 6 is “1” when the cache is ready to accept new data. R/B# follow s bit 6.

See Figure 19 on page 30, and Figure 25 on page 36.

3. Status register bit 7 typically mir rors the status of WP#. However, when BLOCK LOCK is

used, status register bit 7 ret urns “0” if PROGRAM or ERASE operati on s are performed on

a locked block. Additionally, when using the OTP PROGRAM DATA command, status regis-

ter bit 7 returns “0” if the page is protected. This bit is not modified until the next PRO-

GRAM or ERASE command is issued.

Figure 18: Status Register Operation

Table 9: Status Register Bit Definition

Bit Program

Page Program Page

Cache Mode Page

Read Page Read

Cache Mode Block

Erase Definition Notes

0 Pass/fail Pass/fail (N) – – Pass/fail 0 = Successful PROGRAM/ERASE

1 = Error in PROGRAM/ERASE

1 – Pass/fail (N - 1) – – – 0 = Successful PROGRAM

1 = Error in PROGRAM

2– – – – –

3– – – – –

4– – – – –

5 Ready/busy Ready/busy Ready/busy Ready/busy Ready/busy 0 = Busy

1 = Ready 1

6 Ready/busy Ready/busy

cache Ready/busy Ready/busy

cache Ready/busy 0 = Busy

1 = Ready 2

7 Write

protect Write protect Write

protect 0 = Protected

1 = Not protected 3

[15:8] – – – – – 0

70h

CE#

CLE

WE#

RE#

I/Ox Status

Status

Toggle RE# as required

Status

tREA

tCLR

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

PROGRAM Operations

PROGRAM PAGE 80h-10h

Micron NAND Flash devices are inherently page-programmed devices. Pages must be

programmed consecutively within a block, from the least significant page address to

most significant page address (that is, 0, 1, 2, …, 63). Random page address program-

ming is prohibited.

Micron NAND Flash devices also support partial-page programming operations. This

means that any single bit can only be programmed one time b efore an erase is r equire d;

however, the page can be partitioned so that a maximum of eight programming opera-

tions are supported before an erase is required.

SERIAL DATA INPUT 80h

PR OGRAM PAGE operations require loading the SERIAL DATA INPUT (80h) command

into the command r egister, followed by the ADDRESS cycles, then the data. S erial data is

loaded on consecutive WE# cycles starting at the given address. The PROGRAM (10h)

command is written after the data input is complete. The internal control logic automat-

ically executes the prope r algorithm and controls all the necessary timing to program

and verify the operation. Write verification only detects “1s” that are not successfully

written to “0.”

R/B# goes LOW for the duration of array programming time, tPR OG. The READ STATUS

during the programming operation. Bit 6 of the status register will reflect the state of

R/B#. When the device reaches ready, read bit 0 of the status register to determine if the

program operation passed or failed (see Figure 19). The command register stays in read

status re gister mode until another valid command is written to it.

RANDOM DATA INPUT 85h

After the initial data set is input, additional data can be written to a new column address

with the RANDOM DATA INPUT (85h) command. The RANDOM DATA INPUT com-

mand can be used any number of times in the same page prior to issuing the PAGE

WRITE (10h) command. See Figure 20 for the proper command sequence.

Figure 19: PROGRAM and READ STATUS Operation

I/Ox 80h Address 10h 70h

R/B#

tPROG

Status

DIN

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 20: RANDOM DATA INPUT

PROGRAM PAGE CACHE MODE 80h-15h

Cache pr og r amming is act ually a buffered programming mode of the s tandar d page pr o-

gramming command. Programming is started b y loading the SERIAL DATA INPUT (80h)

command to the c ommand register, followed by 4 cycles of address, and a full or partial

page of data. The data is initially copied into the cache register, and the CACHE WRITE

(15h) command is then latched to the command register. Data is transferred from the

cache register to the data register on the r ising edge of WE#. R/B# goes LOW during this

transfer time. After the data has been copied into the data register and R/B# returns to

HIGH, memory array programming begins.

When R/B# returns to HIGH, new data can be written to the cache register by issuing

another PROGRAM PAGE CACHE MODE command sequence. The time that R/B# stays

LOW will be contr olled by the actual programming time. The first time through equals

the time it takes to transfer the cache register contents to the data register. On the sec-

ond and subsequent programming passes, transfer from the cache register to the data

array.

The PROGRAM PAGE CACHE MODE command can cross block address boundaries; it

must not cross die address boundaries. RANDOM DATA INPUT (85h) commands are

permitted with PROGRAM PAGE CACHE MODE operations.

Bit 6 (cache R/B#) of the status register can be read by issuing the READ STATUS (70h)

command to determine when the cache register is ready to accept new data. R/B#

always follows bit 6.

Bit 5 (R/B#) of the status register can be polled to determine when the actual program-

ming of the array is complete for the current progr amming cycle.

If R/B# is used to deter mine programming comp le tion, the last page of the program

sequence must use the PROGRAM PAGE (10h) command inst ead of the CACHE PRO-

GRAM (15h) command. If the CACHE PROGRA M (15h) command is used every time,

including the last page of the programming sequence, status register bit 5 mus t be used

to determine when programming is complete.

Bit 1 of the status register returns the pass/fail for the previous page when bit 6 of the

status register is a “1” (ready state). The pass/fail status of the current PROGRAM opera-

tion is returned with bit 0 of the status register when bit 5 of the status register is a “1”

(ready state) (see Figure 21 on page 32).

I/Ox 80h

Address

85h

Address (2 cycles)

10h 70h

R/B#

tPROG

DIN

DIN Status

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 21: PROGRAM PAGE CACHE MODE Example

Notes: 1. For definition of tLPROG, see note 3, Table 23 on page 55.

2. Check I/O[6:5] for internal ready/busy. Check I/O[1:0] for pass/fail. RE# can remain LOW or

pulse multiple times after a 70h command.

tCBSY

R/B#

I/Ox

R/B#

I/Ox

Address/

data input

80h 15h Address/

data input

80h 15h Address/

data input

80h 15h Address/

data input

80h 10h

tCBSY tCBSY tLPROG1

tCBSY

Address/

data input

80h 15h Address/

data input

80h 10h

Status

output2

70h

tPROG

Status

output1

70h

A: Without status reads

B: With status reads

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

INTERNAL DATA MOVE Operations

An internal data move r equires two command sequences. Issue a READ for INTERNAL

DATA MOVE (00h-35h) command first, then the INTERNAL DATA MOVE (85h-10h)

command. Data moves are only supported within the die from which data is read.

READ FOR INTERNAL DATA MOVE 00h-35h

This READ command is used in conjunction with the INTERNAL DA TA MOVE (85h-10h)

command. First, 00h is written to the command register, then the internal source

address is written (4 cycles). After the addr ess is input, the READ for INTERNAL DATA

MOVE (35h) command writes to the command register. This transfer s a page from m em-

ory into the cache register. The written column addresses are ignored even though all 4

address cycles are required. The memory device is now ready to accept the INTERNA L

DATA MOVE (85h-10h) command.

INTERNAL DATA MOVE 85h-10h

After the READ for INTERNAL DATA MOVE command has been issued and R/B# goes

HIGH, the INTERNAL DATA MOVE command can be written to the command register.

This command transfers the data from the cache register to the data r egister and program-

ming of the new destination page begins. After the INTERNAL DATA MOVE command

and address sequence are written to the devic e, R/B# goes LOW while the internal con-

trol logic automatically programs the new page. The READ STATUS command and bit 6

of the status register can be used instead of the R/B# line to determine when the WRITE

is complete. Bit 0 of the status register indica tes if the operation was successful.

The RANDOM DATA INPUT (85h) command can be used during the INTERNAL DATA

MOVE command sequence to modify a word or multiple words in the original data.

First, data is copied into the cache register using the 00h-35h command sequence; then

the RANDOM DATA INPUT (85h) command is written, along with the address of the

data to be modified next. New data is input on the external data balls. This copies the

new data into the cache register.

When 10h is writte n to the command register, the original data plus the modified data i s

transferred to the data register, and programming of the new page is started. The RAN-

DOM DATA INPUT command can be issued as many times as necessary before starting

the programming sequence with 10h (see F igure22 and Figure 23 on page 34 for details).

Because the INTERNAL DATA MOVE operation does not utilize external memory, ECC

cannot be used to check for errors before progra mming the data to a new page. This can

lead to a data error if the source page contains a bit error due to charge loss or charge

gain. If mult iple INTERNAL DATA MOVE operations are performed, these bit er r ors may

accumulate without correction. For this reason, it is highly recommended that systems

utilizing the INTERNAL DATA MOVE ope ration use a robust ECC scheme that can cor-

rect two or more bits per sector.

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 22: INTERNAL DATA MOVE

Figure 23: INTERNAL DATA MOVE with RANDOM DATA INPUT

BLOCK ERASE 60h-D0h

Erasing occurs at the block level. The MT29F1G08 and the MT29F1G16 have 1,024 erase

blocks organized as 64 pages per block. The BLOCK ERASE command operates on one

block at a time (see Figure 24).

Two cycles of addresses BA[15:6] are required for the x8 device, and 2 cycles of BA[15:6]

for the x16 device . Although addr esses PA[5:0] (x8) and P A[5:0] (x16) are loaded, t he y ar e a

“Don’t Care” and are ignor ed for BLOCK ERASE operations . See Figur es6 and 7 on pages14

and 15 for addr essing details.

The actual BLOCK ERASE command sequence is a two-step process. First, write the

ERASE SETUP (60h) command to the command register. Then write 2 cycles of

addresses to the device. Next, write the ERASE CON FIRM (D0h) command to the com-

mand r egister. At the rising edge of WE#, R/B# goes L OW and the internal control logic

automatically controls the timing and er ase- v erify oper at io ns. R/B# st ays L OW for the

entire tBERS erase time .

The READ STATUS REGISTER command can be used to check the status of the ERASE

operation. When bit 6 = 1, the ERASE operation is complete. Bit 0 indicates a pass/fail

condition where 0 = pass. See BLOCK ERASE, and Table 9 on page 29 for details.

Figure 24: BLOCK ERASE Operation

I/Ox 00h Address 35h 85h Address 10h 70h

R/B#

tPROG

Status

I/Ox 00h Address 35h 85h Address Data Data85h Address

(2 cycles)

Unlimited number of repetitions

10h 70h

R/B#

tPROG

I/Ox 60h Address D0h 70h

R/B#

tBERS

Status

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

One-Time Programmable (OTP) Area

This Micron NAND Flash device offers a protected, one-time programmable NAND

Flash memory area. Ten full pages (2,112 bytes or 1,056 words per page) of O T P data is

available on the device, and the entire range is guaranteed to be good. The OTP area is

accessible only through the O TP com mands. C ustomers can use the O TP ar ea in any way

they desire; typical uses include programming serial numbers or other data for per ma -

nent storage.

In Micron NAND Flash devices, the OTP area leaves the factory in an unwritten state

(each OTP bit is “1”). Programming or partial-page programmi ng enables the user to

program only “0” bits in the OT P area. The OTP area cannot be eras ed, even if it is not

protected. Protecting the OTP area simply prevents further programming of the OTP

area.

While the OTP area is referr ed to as “one-time programmable,” Micron provides a

unique way to program and verify data—before permanently protecting it and prevent-

ing future changes.

OTP programming and protection are accomplished in two discr ete operations. First,

using the OTP DATA PROGRAM (A0h-10h) command, an OTP page is programmed

entirely in one operation, or in up to four partial-page programming sequences. Pro-

gramming can occur on other pages within the OTP area in a similar manner. Second,

the OTP area is permanently protected from further programming using the OTP DATA

PR O TECT (A 5h-10h) command. The pages within the O TP ar ea c an always be read using

the OTP DATA READ (AFh-30h) command, whether or not it is protected.

OTP DATA PROGRAM A0h-10h

The O TP DATA PROGRAM (A0h-10h) command is used to write data to the pages within

the OTP area. An entire page can be progr a mmed at one time, or a page can be partially

programmed up to four times. There is no ERASE operation for the OTP pages.

The O TP DATA PROGRAM enables pr ogramming into an offset of an O TP page , using the

two bytes of column addr ess (CA[11:0]). The OTP DATA PROGRAM command will not

execute if the OTP area has been protected. If the O TP area is protected, the busy time

for the OTP DATA PROGRAM operation is tOBSY and not tPROG.

To use the OTP DATA PROGRAM command, issue the A0h command. I ssue 4 ADDRESS

cycles: the first 2 ADDRESS cycles ar e the column addr ess, and for the r emaining 2 cycles

select a page in the 02h–0Bh r ange. N ext, write the data: from 1 to 2,112 b ytes (x8 device),

or from 1 to 1,056 words (x16 device). After data input is complete, issue the 10h com-

mand. The internal control logic au tom a ti ca lly executes the proper programm ing algo-

rithm and controls the necessary timing for programming and verification. Program

verification only detects “1”s that are not successfully written to “0”s.

RANDOM DATA INPUT (85h) commands are supported during OTP DATA PROGRAM

operations only if the OTP are a is unprotec ted.

R/B# goes LOW during the duration of the array programming time (tPROG). The READ

STATUS (70h) command is the only command valid during the OTP DATA PROGRAM

operation. For this operation, bits 5 and 6 of the st atus reg ister will reflect the state of

R/B#. If bit 7 is “0,” then the OTP area has been protected; otherwise, it will be a “1.”

When the device is ready, read bit 0 of the status register to determine if the operation

passed or failed (see Table 9 on page 29).

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 25: OTP DATA PROGRAM

Notes: 1. The OTP page must be within the 02h–0Bh range.

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Don’t Care

OTP data written

(following "good" status confirmation)

tWC

tWB tPROG

OTP DATA INPUT

command PROGRAM

command READ STATUS

command

1 up to m bytes

serial input

x8 device: m = 2,112 bytes

x16 device: m = 1,056 words

A0h Col

add 1 Col

add 2 DIN

NDIN

00h 10h 70h Status

OTP

page1

OTP address1

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

OTP DATA PROTEC T A5h-10h

The OTP DATA PROTECT (A5h-10h) command is used to protect all the data in the OT P

area. After the data is protected, it cannot be programmed further. When the OTP ar ea is

protected, the pages within the area are no longer programmable and cannot be unpro-

tected.

To use the OTP DATA PROTECT command, issue the A5h command. Next, issue the fol-

lowing 4 ADDRESS cycles: 00h-00h-01h-00h. Finally, issue the 10h command.

R/B# goes LO W while the O TP ar ea is being protected. The pr otect command duration is

similar to a normal page programming operation, tPROG. The READ STATUS (70h) com-

mand is the only command valid during the OTP DATA PR OTECT operation. For this

operation, bits 5 and 6 of the status register will reflect the state of R/B#.

When the device is ready, read bit 0 of the status register to determine if the operation

passed or failed (see Table 9 on page 29).

Figure 26: OTP DATA PROTECT

Notes: 1. OTP data is protected followin g “good” status co nfirmation.

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Don’t Care

tWC

tWB tPROG

OTP DATA

PROTECT command OTP address

OTP data protected1

PROGRAM

command READ STATUS

command

A5h Col

00h Col

00h 10h 70h Status

01h 00h

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

OTP DATA READ AFh-30h

The OTP DATA READ (AFh-30h) command is used to read data from a page within the

OTP area. An OTP page within the OTP area is available for reading data whether or not

the area is protected.

To use the OT P DATA READ comm and, issue the AFh command. Next, issue 4 ADDRESS

cycles: the first 2 ADDRESS cycles are the column address, and for the remaining 2

cycles, select a page in the range of 02h–0Bh. Finally, issue the 30h command.

RANDOM DATA READ (05h-E0h) commands are supported during OTP DATA READ

operations.

R/B# goes LOW (tR) while the data is moved from the OTP page to the data regi ster. The

READ STATUS (70h) command and the RESET (FFh) command are the only commands

valid during the OTP DATA READ oper ati on. For this operation, bits 5 and 6 of the status

Normal READ operation timings apply to OTP read accesses (see Figure 27). Additional

pages within the OTP area can be selected by repeating the OTP DATA READ command.

Note that if OTP DATA READ is followed by PAGE READ CACHE MODE, a RESET (FFh)

must be issued prior to issuing the PAGE READ CACHE MODE command. The maxi-

mum RESET time will not exceed 5µs.

Figure 27: OTP DATA READ Operation

Notes: 1. The OTP page must be within the range 02h–0Bh.

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Busy

AFh 00h 30h

Col

add 1 Col

add 2

Don’t Care

OTP

page1

OTP address

DOUT

NDOUT

N + 1 DOUT

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

BLOCK LOCK Feature

The BLOCK LOCK feature provides the ability to protect the entire device or ranges of

blocks from PROGRAM and ERASE operations. Using this BLOCK LOCK feature offers

increased functionality and flexibility over using just WP# to prevent PROGRAM and

ERASE operations .

BLOCK L OCK features are enabled and disabl ed at power-on through the use of the

LOCK signal. At po wer -on, if LOCK is LOW, all BLOCK LOCK commands are disabled.

H owever, at power-on, if LOCK is HIGH, the BLOCK LOCK commands are enabled and,

b y default, all of the blocks on the device are protected, or locked, from PROGRAM and

ERASE operations, even if WP# is HIGH.

Before the contents of the device can be modified, the device must first be unlocked.

Either a ra nge of blocks or the entire device can be unlocked. PROGRAM and ERASE

operations complete success f ully only in the block ranges that have been unlocked.

Blocks , once unlocked, can be locked again to protec t them from further PROGRAM and

ERASE operations .

Blocks that are locked can be protected further, or locked tight. When locked tight, the

device’s blocks can no longer be locked or unlocked until WP# is pulled LOW for more

than 100ns. After WP# goes LOW for this period, the entire device is locked from PRO-

GRAM and ERASE operations until unlocked again.

WP# and BLOCK LOCK

When the BLOCK LOCK feature is enabled, it interacts with WP# as follows:

• WP# must be driven HIGH and remain HIGH when UNLOCK and LOCK-TIGHT com-

mands are issued.

• Holding WP# LOW locks all blocks.

• If WP# is held LOW to lock blocks, and then returned to HIGH, a new UNLOCK com-

mand must be issued to unlock blocks.

UNLOCK 23h-24h

By default at power-on, if LOCK is HIGH, all of the blocks in the NAND Flash device are

locked, meaning that they are protected from PROGRAM and ERASE operations. The

UNLOCK (23h) command is used to unlock a range of blocks. Unlocked blocks have no

protection and can be programmed or erased.

The UNLOCK command uses two registers—a lower boundary block address register

and an upper boundary block address register—and the invert area bit to determine

which range of blocks is unlocked. When the invert area bit = 0, the r a nge of blocks

within the lower and upper boundary address registers is unlocked. When the invert

area bit = 1, the r ange of blocks outside the boundaries of the lower and upper boundary

address registers are unlocked. The lower boundary block address must be less than the

upper boundary block addre ss. Figures28 and 29 on page 40 show examples of how the

lower and upper boundary address registers work with the invert area bit.

To unlock a range of blocks, issue the UNL OCK (23h) comm and followed by the appro-

priate ADDRESS cycles that indicate the lower boundary block address. Then issue the

24h command followed by the appropriate ADDRESS cycles that ind ic ate the upper

boundary block address. The least significant page address bit, PA0, should be set to “1”

if setting the invert area bit; otherwise, it should be “0.” The other page address bits

should be “0” (see Figure 30 on page 41).

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Only one range of blocks can be sp ec ified in the lower and upper boundary block

addre ss registers. If, after unlocking a ra nge of blocks, the UNLOCK command is again

issued, the new block address range determines which blocks are unlocked. The previ-

ous unlocked block address range is not retained.

The UNLOCK (23h-24h) command is dis ab le d if LOCK is LOW at power-on or if the

device is locked tight (see page42).

Figure 28: Flash Array Protected: Inverted Area Bit = 0

Figure 29: Flash Array Protected: Invert Area Bit = 1

Block 1023

Block 1022

Block 1021

Block 1020

Block 1019

Block 1018

Block 1017

Block 1016

Block 1015

Block 0002

Block 0001

Block 0000

3FCh

3F8h

Unprotected

area

Protected

area

Protected

area

Upper block boundary

Lower block boundary

3FCh

3F8h

Protected

area

Upper block boundary

Lower block boundary

Unprotected

area

Unprotected

area

Block 1023

Block 1022

Block 1021

Block 1020

Block 1019

Block 1018

Block 1017

Block 1016

Block 1015

Block 0002

Block 0001

Block 0000

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Notes: 1. I/O[15:8] is applicable only for x16 devices.

2. Invert area bit is applicable for 24h command; it can be HIGH or LOW for the 23h com-

mand.

Figure 30: UNLOCK Operation

LOCK 2Ah

By default at power-on, if LOCK is HIGH, all of the blocks in the NAND Flash device are

locked and protected from PROGRAM and ERASE operations. If portions of the device

are unlocked using the UNLOCK (23h) command, they can be locked again using the

LOCK (2Ah) command. The LOCK command locks all of the blocks i n the device . L ocked

blocks are write-protected from PROGRAM and ERASE operations.

To lock all of the blocks in the device, issue the LOCK (2Ah) command.

When a PROGRAM or ERASE operation is issued to a locked block, R/B# goes LOW for

tLBSY. The PROGRAM or ERASE operation does not complete. The READ STATUS (70h)

command reports bit 7 as “0,” indicating that the block is protected.

The LOCK (2Ah) command is disabled if LOCK is LOW at power-on or if the device is

locked tight (see page 42).

Table 10: BLOCK LOCK Address Cycle Assignments

ALE Cycle I/O[15:8]1I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

First LOW BA7 BA6 LOW LOW LOW LOW LOW Invert Area Bit2

Second LOW BA15BA14BA13BA12BA11BA10 BA9 BA8

UNLOCK Lower boundary Upper boundary

CLE

CE#

WE#

ALE

RE#

I/Ox 23h 24h

Block

add 1 Block

add 2 Block

add 1 Block

add 2

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 31: LOCK Operation

LOCK-TIGHT 2Ch

The LOCK-TIGHT (2Ch) command prevents locked blocks from being unlocked and

also prevents unlocked blocks from being locke d. When thi s command is issued, the

UNLOCK (23h) and LOCK (2Ah) commands are disabled. This provides an additional

level of protection to locked blocks from inadvertent PROGRAM and ERASE operations.

To implement the lock-tight stat e in all of the lo cked blocks in the dev ice, verify that WP#

is HIGH and then issue the LOCK-TIGHT (2Ch) command.

When a PROGRAM or ERASE operation is issued to a locked block that has also been

locked tight, R/B# goes LOW for tLBSY. The PROGRAM or ERASE operation does not

complete. The READ STATUS (70h) command reports bit 7 as “0,” indicating that the

block is protected. PROGRAM and ERASE operations complete successfully to blocks

that were not locked at the time the LOCK-TIGHT command was issued.

Once the LOCK-TIGHT command is issued, it cannot be dis ab le d via a softw are com-

mand. The only way to disable the lock-tight st atus is either to hold WP# LOW for greater

than 100ns or to power cycle the device. When the lock-tight status is disabled, all of the

blocks become locked, the same as if the LOCK (2Ah) command were issued.

The LOCK-TIGHT (2Ch) command is disabled if LOCK is LOW at power-on.

Figure 32: LOCK-TIG HT Operation

LOCK

command

CLE

CE#

WE#

I/Ox 2Ah

LOCK-TIGHT

command

WP#

CLE

CE#

WE#

I/Ox 2Ch

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 33: PROGRAM/ERASE Issued to Locked or Locked-Tight Block

Figure 34: LOCKED-TIGHT BLOCKS to LOCKED BLOCKS Operation

Note: The device ensures exit from lock-tight mode if the WP# pulse is greater than 100ns. The

device may exit lock-tight mode if WP# pulse is less than 100ns, however, this is not guar-

anteed.

BLOCK LOCK READ STATUS 7Ah

The BLOCK LOCK READ STATUS (7Ah) command is used to determine the protection

status of individual blocks . The ADDRESS cycles have the same format as shown in

Table 10 on page 41; the invert area bit should be s et LO W. On the falling edge of RE#, the

I/O outputs the block-lock status register which co ntains the information on the protec-

tion status of the block. Table 11 shows how to interpret the block-lock status register

bits.

The BLOCK LOCK READ STATUS (7Ah) command is disabled if LOCK is LOW at

power-on.

Table 11: BLOCK LOCK Status Register Bit Definitions

BLOCK LOCK Status Register Definitions I/O[7:3] I/O2 (Lock#) I/O1 (LT#) I/O0 (LT)

Block is locked and device is locked-tigh t X001

Block is locked and device is not locked-tight X010

Block is unlocked and device is locked-ti gh t X101

Block is unlocked and devic e is not locked-tight X110

R/B#

I/Ox PROGRAM or ERASE Address/data input CONFIRM 70h 60h

tLBSY

Locked or locked-tight block READ STATUS

LOCK

CE#

WP#

> 100ns

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 35: BLOCK LOCK READ STATUS

BLOCK LOCK

READ STATUS Block address

CLE

CE#

WE#

ALE

RE#

I/Ox 7Ah Add 1 Add 2 Status

tWHRIO

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 36: BLOCK LOCK Flow Chart

Power-up

Power-up with

LOCK HIGH

LOCK-TIGHT command

with WP# and

LOCK HIGH

LOCK-TIGHT command

with WP# and LOCK HIGH LOCK-TIGHT command

with WP# and LOCK HIGH

WP# LOW

>100ns

WP# LOW > 100ns WP# LOW > 100ns

UNLOCK command with

invert area bit = 1

LOCK commandLOCK

command

UNLOCK command with

invert area bit = 0

UNLOCK command with

invert area bit = 0

UNLOCK command

with invert area

bit = 1

UNLOCK command with invert area bit = 1

UNLOCK command invert area bit = 0

Entire NAND Flash

array locked

Entire NAND Flash

array locked tight

BLOCK LOCK function

disabled

Unlocked range

Locked range

Unlocked range

Locked-tight range

Unlocked range

Locked-tight range

Unlocked range

Locked-tight range

Power-up with

LOCK LOW

(default)

Locked range

Unlocked range

Locked range

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

RESET Operation

RESET FFh

The RESET command is used to put the memory device into a known condition and to

abort a command sequence in progress.

READ, PROGRAM, and ERASE commands can be aborted while the devi ce is in the bus y

state. The contents of the me mory location being progr ammed or the block being erase d

are no longer valid. The command regi ste r is cleared and is r eady for the next command.

The status register contains the value E0h when WP# is HIGH; otherwise, it is written

with a 60h value . R/B# goes LOW for tRST after the RESET command is written to the

command regis te r. Se e Figure 37 and Table 12 for details.

The RESET command must be issued after power-on and before any other command is

issued to the de vic e. The device will be bus y for a ma xi m u m of 1ms at this time.

Figure 37: RESET Operation

Table 12: Status Register Contents After Reset

Condition Status Bit 7 Bit 6 Bit 5 Bi t 4 Bit 3 Bit 2 Bit 1 Bit 0 Hex

WP# HIGH Ready 11100000E0h

WP# LOW Ready and write protected 0110000060h

WE#

CE#

CLE

R/B#

I/Ox

tRST

tWB

FFh

RESET

command

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Programmable Drive Strength

PROGRAMMABLE I/O DRIVE STRENGTH B8h

The B8h command is used to chang e th e de faul t I/O drive strength as shown in

Figure 38. Drive strength should be selected based on expected memory bus loading.

There are four allowable settings for the output drive strength. The settings and the

default drive strength are shown in Table 13 . Th e de vic e returns to the de fault drive

strength mode after it is power-cycled. Figure38 shows how to write and read the drive

strength. Refer toTa ble 14 on page 48 for unique timing parameters associated with the

PR OGRAMMABLE I/O DRIVE STRENGTH command. Note that the AC timing charac-

teristics doc u m ent ed in Table 21 on page 54 and Table 22 on page 54 m ay nee d to be

relaxed if the I/O drive strength is not set to “full.”

Figure 38: Programmable I/O Drive Strength Command Sequence

Notes: 1. WRITE operation.

2. READ operatio n.

Notes: 1. For WRITE operati on, X = “Don’t Care.” For READ operation, X = “Undefined.”

2. T iming parameters shown in Table 21 on page 54 and Table 22 on page 54 represent full

drive setting.

Table 13: I/O Drive Strength Settings

Drive Strength I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0

Full (default) XXXX00XX

Three-quarters XXXX01XX

One-half XXXX10XX

One-quarter XXXX11XX

CLE

CE#

WE#

ALE

RE#

I/Ox B8h I/O[7:0]1 I/O[7:0]2

tWHRIO tRPIO

tDSIO

tWHIO

tWCIO

tWPIO

tDHIO

tCLSIO tCLHIO

tREAIO

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

WRITE PROTECT

The WRITE PROTECT feature protects the device against inadvertent PROGRAM and

ERASE operations . All PROGRAM and ERASE operations are disabled when WP# is L OW.

For WRITE PROTECT timing detail s, see Figures 39 through 42.

Figure 39: ERASE Enable

Figure 40: ERASE Disable

Table 14: Programmable I/O Drive Strength Register READ/WRITE Timing

Parameter Symbol Min Max Unit Notes

CLE hold time tCLHIO 15 – ns

CLE setup time tCLSIO 25 – ns

Data hold time tDHIO 15 – ns

Data setup time tDSIO 30 – ns

RE# access time tREAIO – 250 ns

RE# pulse width tRPIO 250 – ns

WRITE cycle time tWCIO 100 – ns

WE# pulse width HIGH tWHIO 50 – ns

WE# HIGH to RE# LOW tWHRIO 100 – ns

WE# pulse width tWPIO 50 – ns

tWW

60h D0h

WE#

I/Ox

WP#

R/B#

tWW

60h D0h

WE#

I/Ox

WP#

R/B#

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1Gb: x8, x16 NAND Flash Memory

Command Definitions

Figure 41: PROGRAM Enable

Figure 42: PROGRAM Disable

tWW

80h 10h

WE#

I/Ox

WP#

R/B#

tWW

80h 10h

WE#

I/Ox

WP#

R/B#

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1Gb: x8, x16 NAND Flash Memory

Error Management

Micron MT29F1Gxx NAND Flash devices are specified to have a minimum of 1,004 valid

blocks (NVB) out of 1,024 total available blocks. This means the devices may have blocks

that ar e inva lid when they ar e s hipped. An in valid block is one that contains one or mor e

bad bits. Additional bad blocks may de vel o p with us e. However, the total number of

available blocks will not fall below NVB.

Although NAND Flash memory devices may contain bad blocks, they can be used quite

reliably in systems that provide bad-block mapping, replacement, and error correction

algorithms. This type of software environment ensures data integrity.

Internal circuitry isolates ea ch block from other blocks, so the presence of a bad block

does not affect the operation of the rest of the NAND Flash device.

The first block (physical block address 00h) for each CE# in Micron NAND Flash devices

is guaranteed to be free of defects (up to 1,000 PROGRAM/ERASE cycles) when shipped

from the factory. This provides a reliable location for storing boot code and critical boot

information.

Before NAND Flash devices are shippe d from Micron, they are erased. The factory iden-

tifies invalid blocks before shipping by programming data other than FFh (x8) or FFFFh

(x16) into the first spare location (column address 2,048 for x8 devices, or 1,024 for x16

devices) of the first or second page of each bad block.

System software should check the first spare address on the first and second page of

each block prior to perfor ming any erase or formatting operations on the NAND Flash

device. A bad-block table can then be created , enabling system software to map around

these areas. Factory testing is performed under worst-case conditions. Because blocks

marked “bad” may be marginal, it may not be possible to recover this information if the

block is erased.

If the NAND Flash device is erased before these operations are performed, system soft-

ware mus t determine which blocks are bad b y writing and ve rifying va lid information in

each memory location in the device. After writing and verifying all locations, the device

must be fully erased and checked to verify that each block has erased properly.

Over time, some memory locations may fail to program or erase properly. In order to

ensure that data is stored properly over the life of the NAND Flash device, certain pre-

cautions must be taken, inc lud ing :

• Always check status after a WRITE or ERASE operation.

• Under typical use conditions, utilize a minimum of 1-bit ECC for each 528 bytes of

data.

• Use a bad-block replacement algorithm.

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1Gb: x8, x16 NAND Flash Memory

Electrical Characteristics

S t resses greater than those listed under Absolute Maximum Ratings by Device (see

Table 15) may cause permanent damage to the device. This is a stress rating onl y, and

functional operation of the device at these or any other conditions above those indi-

cated in the operational sections of this specification is not guaranteed. Exposure to

absolute maximum rating condit ions for extended periods may affect reliability.

Table 15: Absolute Maximum Ratings by Device

Device Symbol Min Max Unit

MT29F1GxxABB VIN Supply voltage on any ball relative to VSS –0.6 +2.45 V

MT29F1GxxABB VCC –0.6 +2.45 V

MT29F1GxxABB TSTG Storage temperature –65 +150 °C

Short circuit output cur r e nt , I/Os 5mA

Table 16: Recommended Operating Conditions

Parameter/Condition Symbol Min Typ Max Units

Operating temperature Commercial TA0–70

Extended TA–40 – 85 oC

VCC supply voltage MT29F1GxxABB VCC 1.65 1.8 1.95 V

Supply voltage VSS 000V

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1Gb: x8, x16 NAND Flash Memory

Electrical Characteristics

VCC Power Cycling

Micron NAND Flash devices are designed to prevent data corruption duri ng power tran-

sitions. VCC is internally monitored. (The WP# signal permits additional hardware pro-

tection during power transitions.) When VCC reaches 1.5V, a minimum of 100µs should

be allowed for the Flash device to initia lize before any commands are executed (see

Figure43 for the states of signals during VCC power cycling).

The RESET command must be issued to all CE#s after the NAND Flash device is powered

on. Each CE# will be busy for a maximum of 1ms after a RESET command is issued.

Figure 43: AC Waveforms During Power Transitions

Notes: 1. If the system requires the LOCK features to be enabled, then the LOCK signal must be

HIGH during power-up. If the LOCK features are to be disabled, then the LOCK signal

should be held LOW during power-up.

100µs

(MIN)

Undefined

Don’t Care

FFh

1ms

(MAX)

1.8V device: ≈ 1.5V 1.8V device: ≈ 1.5V

tCS

VCC

CLE

CE#

WP#

LOCK1

WE#

ALE

RE#

I/Ox

R/B#

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1Gb: x8, x16 NAND Flash Memory

Electrical Characteristics

Notes: 1. Invalid blocks are blocks that contain one or more bad bits. The device may contain bad

blocks after shippi ng . Additio nal bad bl oc ks may develop over time; however, the total

number of avail a ble blocks will not drop below NVB during the endurance life of the

device. Do not eras e or program blocks mark ed “invalid” by the fact ory.

2. Block 00h (the first block) is guaranteed to be valid, and does not require error correction

for up to 1,000 PROGRAM/ERASE cycles.

Notes: 1. These parameters are verified in device characterization and are not 100 percent tested.

2. Test conditions: TC = 25°C; f = 1 MHz; VIN = 0V.

Notes: 1. Verified on device characterization; not 100 percent tested.

2. Outputs tested at full drive strength.

Table 17: DC and Operati ng Characteristics, VCC = 1.65–1.95V

Parameter Conditions Symbol Min Typ Max Unit

Sequential READ current tCYCLE = 50ns; CE# = VIL;

IOUT = 0mA ICC1 – 10 20 mA

PROGRAM curre nt –I

CC2 – 10 20 mA

ERASE current –I

CC3 – 10 20 mA

Standby current (TTL) CE# = VIH; WP# = 0V/VCC ISB1– – 1mA

Standby current (CMOS) CE# = VCC - 0.2V;

WP# = 0V/VCC ISB2 – 10 50 µA

Input leakage current VIN = 0V to VCC ILI – – ±10 µA

Output leakage current VOUT = 0V to VCC ILO – – ±10 µA

Input high volt ag e I/O [7:0], I/O [15:0], CE#, CLE, ALE,

WE#, RE#, WP#, R/B#, LOCK VIH 0.8 x VCC –VCC + 0.3 V

Input low voltage, all inputs –V

IL –0.3 – 0.2 x VCC V

Output high voltage IOH = –100µA VOH VCC - 0.1 – – V

Output low voltage IOL = 100µA VOL ––0.1V

Output low current (R/B#) VOL = 0.1V IOL 34–mA

Table 18: Valid Blocks

Parameter Symbol Device Min Typ Max Unit Notes

Valid blo ck number NVB MT 29 F1 G xxA BB 1,004 – 1,024 bloc k s 1, 2

Table 19: Capacitance

Description Symbol Device Max Unit Notes

Input capacitance CIN MT29F1GxxABB 10 pF 1, 2

Input/output capacitance (I/O) CIO MT29F1GxxABB 10 pF 1, 2

Table 20: Te st Conditions

Parameter Value Notes

Input pulse levels MT29F1GxxABA 0.0V to 1.8V

Input ris e an d fa ll times 5ns

Input and outp ut timing levels VCC/2

Output load MT29F1GxxABA 1 TTL GATE and CL = 30pF 1, 2

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1Gb: x8, x16 NAND Flash Memory

Electrical Characteristics

Notes: 1. Timing for tADL begins in the ADDRESS cycle, on the final rising edge of WE#, and ends

with the first rising edge of WE# data output.

Notes: 1. AC characteristics may need to be relaxed if I/O drive strength is not set to full.

2. Transition is measured ±200mV from steady-state voltage with load. This parameter is sam-

pled and not 100 percent tested.

3. When VCC is less than 1.7V down to 1.65V, tRC MIN is 60ns.

4. If RESET (FFh) command is loaded at ready state, the device goes busy for maximum 5µs.

5. Do not issue a new command during tWB, even if R/B# is ready.

Table 21: AC Characteristics – Command, Data, and Address Input

Parameter Symbol Min Max Unit Notes

ALE to data start tADL 100 – ns 1

ALE hold time tALH 10 – ns

ALE setup time tALS 25 – ns

CE# hold time tCH 10 – ns

CLE hold time tCLH 10 – ns

CLE setup time tCLS 25 – ns

CE# setup time tCS 25 – ns

Data hold time tDH 10 – ns

Data setup time tDS 20 – ns

WRITE cycle time tWC 45 – ns

WE# pulse width HIGH tWH 15 – ns

WE# pulse width tWP 25 – ns

WP# setup time tWW 30 – ns

Table 22: AC Characteristics – Normal Operation

Parameter Symbol Min Max Unit Notes

ALE to RE# delay tAR 10 – ns 1

CE# access time tCEA –45ns1

CE# HIGH to output High-Z tCHZ –45ns1,2

CLE to RE# delay tCLR 10 – ns 1

CE# HIGH to output hold tCOH 15 – ns 1

Cache busy in PAGE READ CACHE MODE (first 31h) tDCBSYR1 –3µs1

Cache busy in PAGE READ CACHE MODE (next 31h and 3Fh) tDCBSYR2 tDCBSYR1 25 µs 1

Ouput High-Z to RE# LOW tIR 0–ns1,2

Data transfer from Flash ar ray to data register tR–25µs1

READ cycle time tRC 50 – ns 1, 3

RE# access time tREA –30ns1

RE# HIGH hold time tREH 15 – ns 1

RE# HIGH to output hold tRHOH 15 – ns 1

RE# HIGH to WE# LOW tRHW 100 – ns 1

RE# HIGH to output High-Z tRHZ – 100 ns 1, 2

RE# pulse width tRP 25 – ns 1

Ready to RE# LOW tRR 20 – ns 1

Reset time (READ/PROGRAM/ERASE/power-up) tRST – 5/10/500/

1,000 µs 1, 4

WE# HIGH to busy tWB – 100 ns 1, 4, 5

WE# HIGH to RE# LOW tWHR 80 – ns 1

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1Gb: x8, x16 NAND Flash Memory

Electrical Characteristics

Notes: 1. Eight total to the same page.

2. tCBSY MAX time depends on timing between internal program complet ion and data in.

3. tLPROG = tPROG (last page) + tPROG (last - 1 page) - command load time (last page) -

address load time (last page) - data load time (last page).

4. More than 50 percent of the pages will meet typical tPROG at 1.8V and 25°C.

Table 23: PROGRAM/ERASE Characteristics

Parameter Symbol Typ Max Unit Notes

Number of partial page programs NOP –8cycle1

Block erase time tBERS 23ms

Busy time for cache program tCBSY 3700µs2

Busy time for PROGRAM ERASE on locked block tLBSY 3µs

Busy time for OTP DATA PROGRAM operation if

OTP is protected

tOBSY 30 µs

Last page program time tLPROG –––3

Page program time tPROG 250 700 µs 4

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 44: COMMAND LATCH Cycle

Note: The x16 devices must have I/O[15:8] set to “0.”

Figure 45: ADDRESS LATCH Cycle

Note: The x16 devices must have I/O[15:8] set to “0.”

WE#

CE#

ALE

CLE

I/Ox COMMAND

tWP

tCH

tCS

tALH

tDH

tDS

tALS

tCLH

tCLS

Don‘t Care

WE#

CE#

ALE

CLE

I/Ox Address

tWP tWH

tCS

tDH

tDS

tALS tALH

tCLS

Don‘t Care Undefined

tWC

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 46: INPUT DATA LATCH Cycle

Note: DIN Final = 2,112 (x8) or 1,056 (x16).

Figure 47: SERIAL ACCESS Cycle after READ

Note: Transition is measured ±200mV from steady-state voltage with load.

This parameter is sampled and not 100 percent tested.

CE#

ALE

CLE

I/Ox DIN 0

tWP tWP tWP

tWH

tALS

tDH

tDS tDH

tDS

tCLH

tCH

DIN 1 DIN Final1

Don‘t Care

tWC

CE#

RE#

I/Ox

tREH

tRP

tRR tRC

tCEA

tREA tREA tREA

Don‘t Care

tRHZ

tCHZ

tRHZ

tRHOH

R/B#

tCOH

OUT

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 48: READ STATUS Cycle

Figure 49: PAGE READ Operation

RE#

CE#

WE#

CLE

I/Ox

tRHZ

tWP

tWHR

tCEA

tCLR

tCH

tCLS

tCS

tCLH

tDH

tCOH

tRP

tCHZ

tDS tREA tRHOH

tIR

70h Status output

Don‘t Care

RE#

CE#

ALE

CLE

I/Ox 00h Address (4 cycles) Data output

(Serial access)

30h

R/B#

WE#

Don‘t Care

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 50: READ Operation with CE# “Don’t Care”

Figure 51: RANDOM DATA READ Operation

RE#

CE# tREA

tCEA

RE#

CE#

ALE

CLE

I/Ox

I/Ox Out

R/B#

Data output

Don‘t Care

Address (4 cycles)00h 30h

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Busy

Col

add 1 Col

add 2 Row

add 1 Row

add 2

00h

tAR

tRR

Don’t Care

tRC

DOUT

MDOUT

M + 1

Col

add 1 Col

add 2

05h E0h

tREA

tWHR

tCLR

DOUT

NDOUT

N + 1

30h

tWB

Column address N Column address M

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 52: PAGE READ CACHE MODE Operation, Part 1 of 2

tWC

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox 30h DOUT

Column address 0

DOUT

1 DOUT

Column address

00h Page address

M Page address

M + 1

Page address

tCEA

tDS

tCLH

tCLS

tCS tCH

tDH

Don’t Care

tRR

31h

tWB tR

31h

Column address 0

Continued to 1

of next page

Col

add 1 Col

add 2 Row

add 1 Row

add 2

00h

tRC

tREA

tDCBSYR2

tDCBSYR1

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 53: PAGE READ CACHE MODE Operation, Part 2 of 2

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

Page address

M + 1

Don’t Care

Page address

M + 2

Column address 0

Continued from 1

of previous page

Page address

M + x

Column address 0

tCLH

tCH

tREA

tCEA

tDS tDH tRR

tWB

Column address 0

OUT

0 D

OUT

1 31h D

OUT

0 D

OUT

3Fh

OUT

1 D

OUT

0 D

OUT

tCS

tRC

31h

tCLS

tDCBSYR2 tDCBSYR2

tDCBSYR2

OUT

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 54: PAGE READ CACHE MODE Operation without R/B#, Part 1 of 2

tWC

WE#

CE#

ALE

CLE

RE#

I/Ox

30h 70h Status D

OUT

Column address 0

OUT

1 D

OUT

Column address

00h Page address

M Page address

M + 1

Page address

tCEA

tDS

tCLH

tCLS

tCS tCH

tDH

Don’t Care

31h 31h

Column address 0

70h Status

I/O 6 = 0, Cache busy

= 1, Cache ready

I/O 5 = 0, Cache busy

= 1, Cache ready

Continued to 1

of next page

Col

add 1 Col

add 2 Row

add 1 Row

add 2

00h 00h 00h

tRC

tREA

70h Status

I/O 6 = 0, Cache busy

= 1, Cache ready

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 55: PAGE READ CACHE MODE Operation without R/B#, Part 2 of 2

WE#

CE#

ALE

CLE

RE#

I/Ox

Page address

M + 1

Don’t Care

Page address

M + 2

Column address 0

Continued from 1

of previous page

Page address

M + x

Column address 0

tCLH

tCH

tREA

tCEA

tDS tDH

Column address 0

OUT

1 31h D

OUT

0 D

OUT

3Fh

OUT

1 D

OUT

tCLS

tCS

tRC

OUT

31h 70h Status

I/O 6 = 0, Cache busy

= 1, Cache ready

70h Status

I/O 6 = 0, Cache busy

= 1, Cache ready

70h Status

I/O 6 = 0, Cache busy

= 1, Cache ready

00h 00h 00h D

OUT

0 D

OUT

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 56: READ ID Operation

Notes: 1. See Table 8 on page 25 for byte definitions.

Figure 57: PROGRAM Operation with CE# “Don’t Care”

Device ID1

WE#

CE#

ALE

CLE

RE#

I/Ox

Address, 1 cycle

90h 00h

Manufacturer ID1

Byte 21

Byte 0 Byte 1 Byte 31Byte 4

tAR

tREA

tWHR

CLE

CE#

WE#

ALE

I/Ox Address (4 cycles) Data input 10h

WE#

CE#

tWP

tCH

tCS

Don‘t Care

Data input80h

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 58: PROGRAM PAGE Operation

Figure 59: PROGRAM PAGE Operation with RA NDOM DATA INPUT

CE#

ALE

CLE

RE#

R/B#

I/Ox

tWC

tWB

SERIAL DATA

INPUT command

x8 device: m = 2,112 bytes

x16 device: m = 1,056 words

PROGRAM

command READ STATUS

command

1 up to m Byte

serial input

80h Col

add 1 Col

add 2 Row

add 1 Row

add 2 DIN

NDIN

M70h Status

10h

tPROG

Don‘t Care

tADL

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox

tWC

SERIAL DATA

INPUT command Serial input

80h Col

add 1 Col

add 2 Row

add 1 DIN

N+1

tADL tADL

RANDOM DATA

INPUT command Column address PROGRAM

command READ STATUS

command

Serial input

85h Col

add 1 DIN

N+1 70h Status10h

tPROG

tWB

Don‘t Care

Row

add 2 DIN

NCol

add 2 DIN

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 60: INTERNAL DATA MOVE Operation

Figure 61: PROGRAM PAGE CACHE MODE Operation

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox Col

add 1

00h 35h

Col

add 2 Row

add 1 Row

add 2 Col

add 1 Col

add 2 Row

add 1 Row

add 2

tWB tPROG

tWB

85h Data

170h10h Status

Busy Busy READ STATUS

command

Data

tWC

INTERNAL

DATA MOVE Don‘t Care

tADL

WE#

CE#

ALE

CLE

RE#

R/B#

I/Ox 80h 15h

tCBSY

tWB tWBtPROG

Col

add 1

80h 10h 70h Status

Col

add 2 Row

add 2

Row

add 1

Col

add 1 Col

add 2 Row

add 2

Row

add 1 DIN

DIN

Last page input and programming

tCSBY: Max 700µs

SERIAL DATA

INPUT command Serial input PROGRAM

PROGRAM

tWC

Don‘t Care

tADL tADL

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 62: PROGRAM PAGE CACHE MODE Operation Ending on 15h

WE#

CE#

ALE

CLE

RE#

I/Ox Col

add 1 Status 70h Status

70h Status Col

add 2 Row

add 2

Row

add 1 Row

add 3

Col

add 1 Col

add 2 Row

add 2

Row

add 1

Last pageLast page -1

Serial input PROGRAM PROGRAM

tWC

Don‘t Care

80h

Poll status until:

I/O6 = 1, Ready T o ensure PROGRAM success, last 2 pages:

I/O5 = 1, Ready

I/O0 = 0, Last page PROGRAM successful

I/O1 = 0, Last page -1 PROGRAM successful

tADL

70h15h

80h

15h

Serial data

input

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1Gb: x8, x16 NAND Flash Memory

Timing Diagrams

Figure 63: BLOCK ERASE Operation

Figure 64: RESET Operation

WE#

CE#

ALE#

CLE

RE#

R/B#

I/Ox

ERASE SETUP

command

ERASE

command READ STATUS

command

Busy

Row address

60h Row

add 1 Row

add 2 70h Status

D0h

tWC

tBERS

tWB

Don‘t Care

WE#

CE#

CLE

R/B#

I/Ox

tRST

tWB

FFh

RESET

command

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

prodmktg@micron.com www.micron.com Customer Comment Line: 800-932- 4992

Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks ar e the property of

their respective owners.

This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range

for production devices. Although considered final, these specifications are subject to change, as further product develop-

ment and data characterization sometimes occur.

1Gb: x8, x16 NAND Flash Memory

Package Dimensions

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Package Dimensions

Figure 65: 63-Ball VFBGA Package

Note: All dimensions are in millimeters.

Ball A1 ID

1.00 MAX

Mold compound: Epoxy novolac

Substrate material: Plastic laminate

Solder ball material:

96.5% Sn, 3%Ag, 0.5% Cu

13.00 ±0.10

Ball A10

Ball A1 ID

0.80 TYP

6.50 ±0.05

10.50 ±0.10

5.25 ±0.053.60

4.40

0.65 ±0.05

Seating

plane

8.80

7.20

0.10 A

Ball A1

63X Ø0.45

Dimensions

apply to solder

balls post reflow.

Pre-reflow ball

is Ø0.42 on a Ø0.4

SMD ball pad.

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1Gb: x8, x16 NAND Flash Memory

Revision History

Rev. E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1/08

• “OTP DATA READ AFh-30h” on page 38: Added comment regarding OTP DATA READ

followed by PAGE READ CACHE MODE.

Rev. D. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6/07

• “PROGRAM PAGE CACHE MODE 80h-15h” on page 31: Revised last paragraph.

Rev. C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 /07

• Figure 2: Ball Assignment (x8), 63-Ball VFBGA on page 8: Renumbered ball assign-

ments.

• Figure 3: Ball Assignment (x16), 63-Ball VFBGA on page9: Renumbered ball assign-

ments.

• Former Figure10: Time Constants on page 17: Converted figure to equation format.

• Former Figure11: Minimum Rp on page 18: Converted figure to equation format.

• “OTP DATA PROGRAM A0h-10h” on page 35: Re vised RANDOM DATA INPUT (85h)

discussion.

• “Error Management” on page 50: Modified second bullet point wording.

•V

CC Power Cycling and Figur e43: AC Waveforms During Power Transitions on

page 52: Changed 10µs to 100µs.

• Table 22: AC Characteristics – Normal Operation on page 54: Removed tRLOH.

Rev. B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11/06

• “Features” on page 4: Added r equired RESET after power-up; changed ready/ busy pin

to ready/busy signal.

• Table 22: AC Characteristics – Normal Operation on page 54: Deleted tLBSY and

tOBSY MIN values and notes; changed tOBSY (MAX) to 30µs; moved tLBSY and tOBSY

to table 23.

• Table 23: PROGRAM/ERASE Characteristics on page 55: Changed tPR OG (TYP) to

250µs and added note 4.

Rev. A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10/06

•Initial release.