ASYNCHRONOUS
ULTRA LOW POWER 128K x 8 SRAM
LOW POWER SUPPLY VOLTAGE
LOW STANDBY CURRENT
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
Galvantech, Inc. reserves the right to change
products or specifications without notice.
Rev. 8/99
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699 Web Site http://www.galvantech.com
FULL CMOS SRAM
FEATURE
•Low standby current: 5ua (max.)
•Low operating current: 1.5mA/MHz (typ.)
•Wide power supply voltage range:
3.0V to 3.6V for GVT73024UL8XX family
2.7V to 3.3V for GVT73024UL8XXB family
2.3V to 2.7V for GVT73024UL8XXC family
1.8V to 2.2V for GVT73024UL8XXD family
•Low data retention voltage: 1.5V (Min)
•Full CMOS 6-transistor memory cell
•Fully static -- no clock or timing strobes necessary
•All inputs and outputs are TTL-compatible
•Three state outputs
•Easy memory expansion with CE1#, CE2 and OE# options
•Automactic power-down when deselected
OPTIONSMARKING
•Power supply voltage
3.3V + 0.3V -None
3.0V + 0.3V -B
2.5V + 0.2V -C
2.0V + 0.2V -D
•Timing
55ns access -55
70ns access -70
85ns access -85
100ns access -100
300ns access -300
•Packages
32-pin SOJ (300 mil) SJ
32-pin TSOP (type I) TS
32-pin sTSOP (type I) ST
•Temperature
Commercial None (0°C to 70°C)
Industrial I (-40°C to 85°C)
GENERAL DESCRIPTION
The GVT73024UL8 is organized as a 131,072 x 8 SRAM
using a six-transistor full CMOS memory cell along with low-
power CMOS process, using double-layer polysilicon,
double-layer metal technology.
Static design eliminates the need for external clocks or
timing strobes. For increased system flexibility and
eliminating bus contention problems, this device offers two
chip enables (CE1# and CE2) along with output enable (OE#)
for this organization.
The chip is enabled when CE1# is LOW and CE2 is
HIGH. With chip being enabled, writing to this device is
accomplished when write enable (WE#) is LOW and reading
is accomplished when (OE#) go LOW with (WE#) remaining
HIGH. The device offers a low power standby mode when
chip is not selected. This allows system designers to meet low
standby power requirements.
1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
22
21
20
11
12
13
14
15
16
19
18
17
A15
CE2
A10
CE1#
DQ8
DQ7
DQ6
DQ5
DQ4
WE#
A13
A8
A9
A11
OE#
A16
A14
A2
A1
A0
DQ1
DQ2
DQ3
VSS
A12
A7
A6
A5
A4
A3
VCCNC
PIN ASSIGNMENT
32-Pin SOJ
32-Pin DIP
1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
22
21
20
11
12
13
14
15
16
19
18
17
A15
CE2
A10
CE1#
DQ8
DQ7
DQ6
DQ5
DQ4
WE#
A13
A8
A9
A11 OE#
A16
A14
A2
A1
A0
DQ1
DQ2
DQ3
VSS
A12
A7
A6
A5
A4 A3
VCC
NC
PIN ASSIGNMENT
32-Pin TSOP (Type I)
32-PIN TSOP/sTSOP (TYPE I)
August 16, 19992Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
PIN DESCRIPTIONS
MODECE1#CE2WE#OE#DQPOWER
READLH H LQACTIVE
WRITELHLXDACTIVE
OUTPUT DISABLELH H H HIGH-ZACTIVE
STANDBYHX X X HIGH-ZSTANDBY
STANDBY X LX X HIGH-ZSTANDBY
SOJ Pin
NumbersTSOP & sTSOP
Pin NumbersSYMBOLTYPEDESCRIPTION
12, 11, 10, 9, 8, 7,
6, 5, 27, 28, 23,
25, 4, 28, 3, 31, 2
20, 19, 18, 17, 16,
15, 14, 13, 3, 2, 31,
1, 12, 4, 11, 7, 10
A0-A16InputAddress Inputs: These inputs determine which cell is addressed.
29 5 WE#InputWrite Enable: This input determines if the cycle is a READ or WRITE cycle. WE#
is LOW for a WRITE cycle and HIGH for a READ cycle.
22, 3030, 6CE1#, CE2InputChip Enables: These inputs are used to enable the device. When CE1# is LOW
and CE2 is HIGH, the chip is selected. When either CE1# is HIGH or CE2 is
LOW, the chip is disabled and automatically goes into standby power mode.
24 32 OE#InputOutput Enable: This active LOW input enables the output drivers.
13, 14, 15, 17,
18, 19, 20, 2121, 22, 23, 25,
26, 27, 28, 29DQ1-DQ8Input/
OutputSRAM Data I/O: Data inputs and data outputs.
32 8 VCCSupplyPower Supply: 1.8V to 3.6V, depending upon the product family.
16 24 VSS SupplyGround
CE1#
ADDRESS BUFFER
ROW DECODER
COLUMN DECODER
MEMORY ARRAY
512 ROWS X 256 X 8
COLUMNS
I/O CONTROL
WE#
OE#
DQ8
DQ1
POWER
DOWN
A16
A0
VCC
VSS
CE2
ABSOLUTE MAXIMUM RATINGS*
Voltage on VCC Supply Relative to VSS........-0.3V to +4.0V
VIN ..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ......................-65oC to +150oC
Power Dissipation ...........................................................0.7W
Soldering Temperature (10s) ........................................260oC
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
August 16, 19993Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
RECOMMENDED DC OPERATING CONDITIONS
DC AND OPERATING ELECTRICAL CHARACTERISTICS
(All Temperature Ranges; VCC = 1.8 V to 3.6V. unless otherwise noted, VLC=0.2V, VHC=VCC-0.2V)
CAPACITANCE
DESCRIPTIONSYMBOLPRODUCTMINTYPMAXUNITSNOTES
Supply VoltageVCCGVT73024UL8XX 3.03.33.6V1
GVT73024UL8XXB 2.73.03.3
GVT73024UL8XXC2.32.52.7
GVT73024UL8XXD1.82.02.2
Input High (Logic 1) voltageVIHGVT73024UL8XX 2.2-VCC+0.2V1, 2
GVT73024UL8XXB 2.2
GVT73024UL8XXC2.0
GVT73024UL8XXD1.6
Input Low (Logic 0) VoltageVIl-0.20.4V1, 2
DESCRIPTIONSYMCONDITIONSMIN.TYP.MAX.UNITSNOTES
Input Leakage Current ILI0V < VIN < VCC-1 1 uA
Output Leakage Current ILOOutput(s) disabled,
0V < VOUT < VCC-1 1 uA
Operating Power
Supply CurrentIcc1Cycle Time=1us; CE1# = VIL & CE2 = VIH;Other
Inputs = VIH/VIL; IOUT = 0mA -1.53mA3, 14
Icc2Cycle Time=Min; CE1# = VIL
& CE2 = VIH;Other Inputs =
VIH/VIL; IOUT = 0mA
VCC=3.6V@55ns- - 55 mA3
VCC=3.3V@70ns- - 50
VCC=2.7V@85ns- - 30
VCC=2.2V@300ns- - 15
TTL Standby Current ISB CE1# > VIH or CE2 < VIL; Other Inputs=VIH or VIL;
f= 0- - 0.3mA
CMOS Standby Current ISB1CE1# > VHC or CE2< VLC; Other Inputs=VHC or VLC;
f= 0- - 5 uA
Output Low VoltageVOLIOL = 2.1mA @ VCC=2.7V
IOL = 0.5mA @ VCC=2.3V
IOL = 0.33mA @ VCC=1.8V
- - 0.4V1
Output High VoltageVOHIOH = -1.0mA @ VCC=3.0V 2.4- - V1
IOH = -0.5mA @ VCC=2.5V 2.0- -
IOH = -0.44mA @ VCC=2.0V 1.6- -
DESCRIPTIONCONDITIONSSYMBOLMAXUNITSNOTES
Input CapacitanceTA = 25oC; f = 1 MHz
VCC = 3VCI6 pF4
Input/Output Capacitance (DQ)CI/O8 pF4
August 16, 19994Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
PRODUCT LIST
AC ELECTRICAL CHARACTERISTICS (Note 5)
(All Temperature Ranges; VCC = 3.0V to 3.6V for GVT73024ULXX family; VCC = 2.7V to 3.3V for GVT73024ULXXB
family; VCC = 2.3V to 2.7V for GVT73024ULXXC family; VCC = 1.8V to 2.2V for GVT73024ULXX family))
Part NameVoltage Range & Speed Grade
GVT73024UL8XX3.3V + 0.3V; 55ns, 70ns, 85ns and 100ns
GVT73024UL8XXB3.0V + 0.3V; 55ns, 70ns, 85ns and 100ns
GVT73024UL8XXC2.5V + 0.2V; 70ns, 85ns and 100ns
GVT73024UL8XXD2.0V + 0.2V; 300ns
DESCRIPTION- 55- 70- 85- 100- 300
SYMMINMAXMINMAXMINMAXMINMAXMINMAXUNITSNOTES
READ Cycle
READ cycle timetRC 55 70 85 100 300 ns
Address access timetAA 55 70 85 100 300 ns13
Chip Enable access timetACE55 70 85 100 300 ns13
Output hold from address changetOH10 10 15 15 30 ns
Chip Enable to output in Low-ZtLZCE10 10 10 10 50 ns4, 7
Chip disable to output in High-ZtHZCE20 25 25 25 60 ns 4, 6, 7
Output Enable access timetAOE20 30 40 50 150 ns13
Output Enable to output in Low-ZtLZOE5 5 5 5 30 ns4, 7
Output Enable to output in High-ZtHZOE20 25 25 25 60 ns4, 6, 7
Chip Enable to power-up timetPU0 0 0 0 0 ns4
Chip disable to power-down timetPD55 70 85 100 300 ns4
WRITE Cycle
WRITE cycle timetWC55 70 85 100 300 ns
Chip Enable to end of writetCW40 45 50 60 300 ns
Address valid to end of write, with OE#
HIGH
tAW40 45 50 60 300 ns
Address setup timetAS 0 0 0 0 0 ns
Address hold from end of writetAH0 0 0 0 0 ns
WRITE pulse widthtWP2 40 45 50 60 200 ns
WRITE pulse width, with OE# HIGHtWP1 40 45 50 60 200 ns
Data setup timetDS25 30 35 40 120 ns
Data hold timetDH 0 0 0 0 0 ns
Write disable to output in Low-ZtLZWE5 5 5 5 20 ns 4, 7
Write Enable to output in High-ZtHZWE20 25 25 25 60 ns4, 6, 7
AC TEST CONDITIONS
Input pulse levels0.4V to 2.4V for VCC=3.3V &3.0V;
0.4V to 2.2V for VCC=2.5V;
0.4V to 1.8V for VCC=2.0V
Input rise and fall times5ns
Input and output
reference levels1.5V for VCC=3.3V and 3.0V;
1.1V for VCC=2.5V;
0.9V for VCC=2.0V
Output loadCL = 100pF and 1 TTL Gate
August 16, 19995Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
NOTES
1. All voltages referenced to VSS (GND).
2. Undershoot:VIL ≤ -1.0V for t ≤ 20ns
Overshoot:VIH > VCC+1.0V for t ≤ 20ns
3. Icc is given with no output current. Icc increases with greater
output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in
the table of AC Test Conditions unless otherwise noted.
6. High-Z is defined as the time at which the outputs achieve the
open circuit conditions and are not referenced to output voltage
levels.
7. At any given temperature and voltage condition, tHZCE is less
than tLZCE and tHZWE is less than tLZWE.
8. WE# is HIGH for READ cycle.
9. Device is continuously selected. Chip enable and output enables
are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip
enable.
11. tRC = Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a
WRITE cycle.
13. Capacitance derating applies to capacitance different from the
load capacitance shown in AC Test Condition table.
14. Typical values are measured at 3.3V and 25oC.
DATA RETENTION ELECTRICAL CHARACTERISTICS
DESCRIPTIONCONDITIONSSYMBOLMINTYPMAXUNITSNOTES
Vcc for Retention DataVDR1.5-3.6V1
Data Retention CurrentCE1# >VCC -0.2 or CE2< VSS +0.2;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0;Vcc = 3.0V
ICCDR- - 5 uA
Chip Deselect to
Data Retention TimetCDR0- - ns4
Operation Recovery TimetRtRC- - ns4, 11
August 16, 19996Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
LOW VCC DATA RETENTION WAVEFORM
READ CYCLE NO. 1(8, 9)
READ CYCLE NO. 2(7, 8, 10, 12)
VCC
CE#
DATA RETENTION MODE
VDR
VIH
VIL
tRC
tCDR
ADDR VALID
t
RC
DATA VALID
t
OH
t
AA
PREVIOUS DATA VALID
Q
CE1#
tRC
DATA VALID
tLZCE
tACE
OE#
HIGH Z
tAOE
tLZOE
tHZCE
tHZOE
CE2
Q
UNDEFINED
DON'T CARE
August 16, 19997Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
WRITE CYCLE NO. 1(7, 12)
(Write Enable Controlled with Output Enable OE# active LOW))
WRITE CYCLE NO. 2(12)
(Write Enable Controlled with Output Enable OE# inactive HIGH)
ADDR
t
WC
t
AH
t
DS
DATA VALID
CE2
CE1#
WE#
D
Q
t
DH
t
WP2
t
AS
t
AW
t
CW
HIGH Z
t
HZWE
t
LZWE
ADDR
t
WC
t
AH
t
DS
DATA VALID
HIGH Z
CE2
CE1#
WE#
D
Q
t
DH
t
WP1
t
AS
t
AW
t
CW
UNDEFINED
DON'T CARE
August 16, 19998Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
WRITE CYCLE NO. 3(12)
(Chip Enable Controlled)
ADDR
tWC
tAH
tDS
DON'T CARE
DATA VALID
CE2
CE1#
WE#
D
Q
tDH
tWP1
tAS
tAW tCW
HIGH Z
August 16, 19999Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
Package Dimensions
Note: All dimensions in inches (millimeters)
.825 (20.96)
.810 (20.57)
.305 (7.75)
.292 (7.42)
PIN #1 INDEX .050 (1.27) TYP
.020 (0.51)
.015 (0.38)
MAX
MIN or typical, min where noted.
SEATING PLANE
.274 (6.95)
.254 (6.44)
.095 (2.41)
.080 (2.03)
.140 (3.55)
.120 (3.04)
.025 (0.63)
MIN
32-pin 300 Mil Plastic SOJ (SJ)
.340 (8.64)
.330 (8.38)
.319 (8.10)
.311 (7.90)
.012 (0.30)
.006 (0.15)
.728 (18.50)
.720 (18.30)
.020 (0.50) TYP
.047 (1.20) MAX
.795 (20.20)
.780 (19.80)
.041 (1.05)
.037 (0.95)
Note: All dimensions in inches (millimeters)MAX
MIN or typical, max where noted.
32-pin Plastic TSOP (TS)
August 16, 199910 Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 8/99
GVT73024UL8
ULTRA LOW POWER 128K X 8 SRAM
GALVANTECH, INC.
PRELIMINARY
Package Dimensions (continued)
Ordering Information
GVT 73024UL8 XX X - XXX X
.319 (8.10)
.311 (7.90)
.012 (0.30)
.006 (0.15)
.469 (11.90)
.461 (11.70)
.020 (0.50) TYP
.047 (1.20) MAX
.536 (13.60)
.520 (13.20)
.041 (1.05)
.037 (0.95)
Note: All dimensions in inches (millimeters) MAX
MIN or typical, max where noted.
32-pin Plastic STSOP (ST)
Galvantech Prefix
Part Number
TS= TSOP TYPE I,
Package (SJ = 300 mil SOJ,
Temperature (Blank = Commercial
Speed (55 = 55ns, 70= 70ns,
85 = 85ns, 100 = 100ns,
I = Industrial),
ST= sTSOP TYPE I)
300 = 300ns)
B = 2.7V to 3.3V,
C = 2.3V to 2.7V,
D = 1.8V to 2.2V)
Voltage (Blank = 3.0V to 3.6V,
