Vishay Siliconix
SiC402A, SiC402BCD
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
www.vishay.com
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This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
10 A microBUCK® SiC402A/B
Integrated Buck Regulator with Programmable LDO
DESCRIPTION
The Vishay Siliconix SiC402A/B an advanced stand-alone
synchronous buck regulator featuring integrated power
MOSFETs, bootstrap switch, and a programmable LDO in a
space-saving PowerPAK MLP55-32L pin packages.
The SiC402A/B are capable of operating with all ceramic
solutions and switching frequencies up to 1 MHz. The
programmable frequency, synchronous operation and
selectable power-save allow operation at high efficiency
across the full range of load current. The internal LDO may
be used to supply 5 V for the gate drive circuits or it may be
bypassed with an external 5 V for optimum efficiency and
used to drive external n-channel MOSFETs or other loads.
Additional features include cycle-by-cycle current limit,
voltage soft-start, under-voltage protection, programmable
over-current protection, soft shutdown and selectable
power-save. The Vishay Siliconix SiC402A/B also provides
an enable input and a power good output.
FEATURES
• High efficiency > 95 %
• 10 A continuous output current capability
• Integrated bootstrap switch
• Programmable 200 mA LDO with bypass logic
• Temperature compensated current limit
• Pseudo fixed-frequency adaptive on-time
control
• All ceramic solution enabled
• Programmable input UVLO threshold
• Independent enable pin for switcher and LDO
• Selectable ultra-sonic power-save mode (SiC402A)
• Selectable power-save mode (SiC402B)
• Programmable soft-start and soft-shutdown
• 1 % internal reference voltage
• Power good output
• Over-voltage and under-voltage protections
• Material categorization: For definitions of compliance
please see www.vishay.com/doc?99912
APPLICATIONS
• Notebook, desktop, and server computers
• Digital HDTV and digital consumer applications
• Networking and telecommunication equipment
• Printers, DSL, and STB applications
• Embedded applications
• Point of load power supplies
TYPICAL APPLICATION CIRCUIT AND PACKAGE OPTIONS
PRODUCT SUMMARY
Input Voltage Range 3 V to 28 V
Output Voltage Range 0.6 V to 5.5 V
Operating Frequency 200 kHz to 1 MHz
Continuous Output Current 10 A
Peak Efficiency 95 %
Package PowerPAK MLP55-32L
Typical Application Circuit for SiC402A/B (PowerPAK MLP55-32L)
PAD 1
A
GND
LX
PAD 3
LX
PAD 2
V
IN
P
GND
LX
P
GND
P
GND
P
GND
P
GND
P
GND
17
18
19
20
21
T
ON
A
GND
EN\PSV
LX
I
LIM
P
GOOD
BST
V
IN
FBL
A
GND
V
DD
V
OUT
FB
1
2
3
4
5
7
6
8
SS
P
GND
V
IN
V
IN
V
IN
NC
LX
NC
9
10
11
12
13
14
15
16
24
LX
23
22
ENL
V
IN
V
OUT
V
OUT
P
GOOD
3.3 V
EN/PSV (Tri-State)
LDO_EN
P
GND
31 30 29 2526
27
28
32
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Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
PIN CONFIGURATION (Top View)
SiC402A/B Pin Configuration (Top View)
PAD 1
AGND
LX
PAD 3
LX
PAD 2
VIN
PGND
LX
PGND
PGND
PGND
PGND
PGND
17
18
19
20
21
tON
AGND
EN\PSV
LX
ILIM
PGOOD
BST
VIN
FBL
AGND
VDD
VOUT
FB 1
2
3
4
5
7
6
8
SS
PGND
VIN
VIN
VIN
NC
LX
NC
9
10
11
12
13
14
15
16
PGND
24 LX
23
22
ENL
31 30 29 25262728
32
PIN DESCRIPTION
Pin Number Symbol Description
1FB
Feedback input for switching regulator used to program the output voltage - connect to an external
resistor divider from VOUT to AGND.
2V
OUT
Switcher output voltage sense pin - also the input to the internal switch-over between VOUT and
VLDO. The voltage at this pin must be less than or equal to the voltage at the VDD pin.
3V
DD
Bias supply for the IC - when using the internal LDO as a bias power supply, VDD is the LDO output.
When using an external power supply as the bias for the IC, the LDO output should be disabled.
4, 30, PAD 1 AGND Analog ground
5FBL
Feedback input for the internal LDO - used to program the LDO output. Connect to an external
resistor divider from VDD to AGND.
6, 9 to 11, PAD 2 VIN Input supply voltage
7 SS The soft start ramp will be programmed by an internal current source charging a capacitor on this pin.
8 BST Bootstrap pin - connect a capacitor of at least 100 nF from BST to LX to develop the floating supply
for the high-side gate drive.
12, 14 NC No connection
13 LXBST LX Boost - connect to the BST capacitor.
23 to 25, PAD 3 LX Switching (phase) node
15 to 22 PGND Power ground
26 PGOOD
Open-drain power good indicator - high impedance indicates power is good. An external pull-up
resistor is required.
27 IILIM Current limit sense pin - used to program the current limit by connecting a resistor from ILIM to LXS.
28 LXS LX sense - connects to RILIM
29 EN/PSV
Enable/power-save input for the switching regulator - connect to AGND to disable the switching
regulator, connect to VDD to operate with power-save mode and float to operate in forced continuous
mode.
31 tON On-time programming input - set the on-time by connecting through a resistor to AGND.
32 ENL Enable input for the LDO - connect ENL to AGND to disable the LDO. Drive with logic signal for logic
control, or program the VIN UVLO with a resistor divider between VIN, ENL, and AGND.
ORDERING INFORMATION
Part Number Package Marking
(Line 1: P/N)
SiC402ACD-T1-GE3 PowerPAK
MLP55-32L
SiC402A
SiC402BCD-T1-GE3 SiC402B
SiC402DB Reference Board
Format:
Line 1: Dot
Line 2: P/N
Line 3: Siliconix Logo + LOT Code + ESD Symbol
Line 4: Factory Code + Year Code + Work Week Code
P/N
Fyww
II
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
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Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
FUNCTIONAL BLOCK DIAGRAM
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating/conditions for extended periods may affect device reliability.
SiC402A/B Functional Block Diagram
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted)
Electrical Parameter Conditions Limits Unit
VIN to PGND - 0.3 to + 30
V
VIN to VDD - 0.4 max.
LX to PGND - 0.3 to + 30
LX (transient < 100 ns) to PGND - 2 to + 30
VDD to PGND - 0.3 to + 6
EN/PSV, PGOOD, ILIM Reference to PGND - 0.3 to + (VDD + 0.3)
tON to PGND - 0.3 to + (VDD - 1.5)
BST to LX - 0.3 to + 6
to PGND - 0.3 to + 35
ENL - 0.3 to VIN
AGND to PGND - 0.3 to + 0.3
Temperature
Maximum Junction Temperature 150 °C
Storage Temperature - 65 to 150
Power Dissipation
Junction to Ambient Thermal Impedance (RthJA)bIC Section 50 °C/W
Maximum Power Dissipation Ambient Temperature = 25 °C 3.4 W
Ambient Temperature = 100 °C 1.3
ESD Protection
HBM 2 kV
NC
NC
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Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
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THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
RECOMMENDED OPERATING RANGE (all voltages referenced to GND = 0 V)
Parameter Min. Typ. Max. Unit
VIN 328
VVDD to PGND 35.5
VOUT 0.6 5.5
Temperature
Operating Junction Temperature - 40 to 125 °C
Recommended Ambient Temperature - 40 to 85
ELECTRICAL SPECIFICATIONS
Parameter Symbol
Test Conditions Unless Specified
VIN = 12 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C, VDD = + 5 V,
typical application circuit
Limits
Unit
Min. Typ. Max.
Input Supplies
Input Supply Voltage VIN 328
V
VDD VDD 35.5
VIN UVLO ThresholdaVUVLO
Sensed at ENL pin, rising 2.4 2.6 2.95
Sensed at ENL pin, falling 2.23 2.4 2.57
VIN UVLO Hysteresis VUVLO, HYS 0.25
VDD UVLO Threshold VUVLO
Measured at VDD pin, rising 2.5 3
Measured at VDD pin, falling 2.4 2.9
VDD UVLO Hysteresis VUVLO, HYS 0.2
VIN Supply Current IIN
EN/PSV, ENL = 0 V, VIN = 28 V 10 20
µAStandby mode: ENL = VDD, EN/PSV = 0 V 160
VDD Supply Current IDD
EN/PSV, ENL = 0 V 190 300
SiC402A, EN/PSV = V5V, no load
(fSW = 25 kHz), VFB > 0.6 Vb0.3
mA
SiC402B, EN/PSV = V5V, no load
VFB > 0.6 Vb0.7
VDD = 5 V, fSW = 250 kHz,
EN/PSV = floating, no loadb8
VDD = 3 V, fSW = 250 kHz,
EN/PSV = floating, no loadb5
FB On-Time Threshold Static VIN and load 0.594 0.600 0.606 V
Frequency Range fsw
Continuous mode operation 1000 kHz
Minimum fSW, (SiC402A only) 25
Bootstrap Switch Resistance 10
Timing
On-Time tON
Continuous mode operation VIN = 15 V,
VOUT = 5 V, fSW = 300 kHz, RtON = 133 k999 1110 1220
ns
Minimum On-TimebtON min. 80
Minimum Off-TimebtOFF min.
VDD = 5 V 250
VDD = 3 V 370
Soft Start
Soft Start CurrentbISS 3µA
Soft Start VoltagebVSS When VOUT reaches regulation 1.5 V
Analog Inputs/Outputs
VOUT Input Resistance 500 k
Current Sense
Zero-Crossing Detector Threshold Voltage LX-PGND - 3 + 3 mV
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
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Vishay Siliconix
SiC402A, SiC402BCD
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Power Good
Power Good Threshold Voltage
PG_VTH_UPPER
Upper limit, VFB > internal 600 mV
reference + 20
%
PG_VTH_LOWER
Lower limit, VFB < internal 600 mV
reference - 10
Start-Up Delay Time
(between PWM enable and PGOOD high) PG_Td
VDD = 5 V, Css = 10 nF 12 ms
VDD = 3 V, Css = 10 nF 7
Fault (noise-immunity) Delay TimebPG_ICC 5µs
Leakage Current PG_ILK 1µA
Power Good On-Resistance PG_RDS-ON 10
Fault Protection
Vally Current LimitcILIM
VDD = 5 V, RILIM = 4460,
TJ = 0 °C to + 125 °C 8.5 10 11.5 A
VDD = 3 V, RILIM = 4460 8.5
ILIM Source Current 10 µA
ILIM Comparator Offset Voltage VILM-LK With respect to AGND - 10 0 + 10 mV
Output Under-Voltage Fault VOUV_Fault
VFB with respect to Internal 600 mV
reference, 8 consecutive clocks - 25
%
Smart Power-Save Protection
ThresholdbPSAVE_VTH
VFB with respect to internal 600 mV
reference + 10
Over-Voltage Protection Threshold VFB with respect to internal 600 mV
reference + 20
Over-Voltage Fault DelaybtOV-Delay 5µs
Over Temperature ShutdownbTShut 10 °C hysteresis 150 °C
Logic Inputs/Outputs
Logic Input High Voltage VIH 1
V
Logic Input Low Voltage VIL 0.4
EN/PSV Input for PSAVE OperationbVDD = 5 V 2.2 5
EN/PSV Input for Forced Continuous
Operationb12
EN/PSV Input for Disabling Switcher 00.4
EN/PSV Input Bias Current IEN EN/PSV = VDD or AGND - 10 + 10
µAENL Input Bias Current ENL = VIN = 28 V 10 18
FBL, FB Input Bias Current FBL_ILK FBL, FB = VDD or AGND - 1 + 1
ELECTRICAL SPECIFICATIONS
Parameter Symbol
Test Conditions Unless Specified
VIN = 12 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C, VDD = + 5 V,
typical application circuit
Limits
Unit
Min. Typ. Max.
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Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
Notes:
a. VIN UVLO is programmable using a resistor divider from VIN to ENL to AGND. The ENL voltage is compared to an internal reference.
b. Typical value measured on standard evaluation board.
c. SiC402A/B has first order temperature compensation for over current. Results vary based upon the PCB thermal layout.
d. The switch-over threshold is the maximum voltage differential between the VDD and VOUT pins which ensures that VLDO will internally
switch-over to VOUT. The non-switch-over threshold is the minimum voltage differential between the VLDO and VOUT pins which ensures that
VLDO will not switch-over to VOUT.
e. The LDO drop out voltage is the voltage at which the LDO output drops 2 % below the nominal regulation point.
Linear Dropout Regulator
FBLbVLDO ACC 0.75 V
LDO Current Limit LDO_ILIM
Short-circuit protection,
VIN =12 V, VDD < 0.75 V 65
mA
Start-up and foldback, VIN = 12 V,
0.75 < VDD < 90 % of final VDD value 115
Operating current limit, VIN = 12 V,
VDD > 90 % of final VDD value 135 200
VLDO to VOUT Switch-Over ThresholddVLDO-BPS - 130 + 130
mV
VLDO to VOUT Non-Switch-Over ThresholddVLDO-NBPS - 500 + 500
VLDO to VOUT Switch-Over Resistance RLDO VOUT = 5 V 2
LDO Drop Out VoltageeFrom VIN to VDD, VDD = + 5 V,
IVLDO = 100 mA 1.2 V
ELECTRICAL SPECIFICATIONS
Parameter Symbol
Test Conditions Unless Specified
VIN = 12 V, TA = + 25 °C for typ.,
- 40 °C to + 85 °C for min. and max.,
TJ = < 125 °C, VDD = + 5 V,
typical application circuit
Limits
Unit
Min. Typ. Max.
Vishay Siliconix
SiC402A, SiC402BCD
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
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This document is subject to change without notice.
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For technical questions, contact: powerictechsupport@vishay.com
ELECTRICAL CHARACTERISTICS
Figure 1 - PSM Effiency - VIN vs. Load
(VDD = 3.3 V, VOUT = 1.5 V)
Figure 2 - PSM Effiency - VIN vs. Load
(VDD = 5 V, VOUT = 1.5 V)
Figure 3 - PSM Effiency - VIN vs. Load
(VDD = 5 V, VOUT = 1.5 V)
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
0 1 2 3 4 5 6 7 8 9 10
Efficiency (% )
IOUT (A)
V
IN
= 5 V
V
IN
= 12 V
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
0 1 2 3 4 5 6 7 8 9 10
Eciency (%)
IO U T (A )
VIN = 5 V
VIN = 12 V
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
0 1 2 3 4 5 6 7 8 9 10
E fficiency (% )
IO U T (A)
VIN = 12 V
VIN = 18 V
Figure 4 - Efficiency - PSM vs. CCM
(VDD = 3.3 V, VOUT = 1.5 V, VIN = 12 V)
Figure 5 - Efficiency - PSM vs. CCM
(VDD = 5 V, VOUT = 1.5 V, VIN = 12 V)
Figure 6 - PSM Efficiency - VDD 3.3 V vs. 5 V
(VOUT = 1.5 V, VIN = 12 V)
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
0 1 2 3 4 5 6 7 8 9 10
Eciency (%)
IO U T (A )
PSM
CCM
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
0 1 2 3 4 5 6 7 8 9 10
Eciency (%)
IO U T (A )
PSM
CCM
50%
55%
60%
65%
70%
75%
80%
85%
90%
95%
100%
0 1 2 3 4 5 6 7 8 9 10
Eciency (%)
IO U T (A )
V
DD
= 3.3 V
V
DD
= 5 V
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Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
Figure 7 - Load Regulation - FCM
(VDD = 5 V, VOUT = 1.5 V)
Figure 8 - Load Regulation - PSM
(VDD = 5 V, VOUT = 1.5 V)
Figure 9 - Switching Frequency - PSM vs. FCM
(VDD = 5 V, VOUT = 1.5 V, VIN = 12 V)
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
V
OUTOUT
(V) (V)
I
OUTOUT
(A) (A)
9
,1
9
9
,1
9
9
,1
9
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V
OUTOUT
(V) (V)
I
OUTOUT
(A) (A)
9
,1
9
9
,1
9
9
,1
9
0
50
100
150
200
250
300
350
400
0 1 2 3 4 5 6 7 8 9 1 0
Frequency (KHz)
FCM
PSM
IO UT (A)
Figure 10 - Load Regulation - FCM
(VDD = 3.3 V, VOUT = 1.5 V)
Figure 11 - Load Regulation - PSM
(VDD = 3.3 V, VOUT = 1.5 V)
Figure 12 - Switching Frequency - PSM vs. FCM
(VDD = 5 V, VIN = 12 V)



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

V
OUTOUT
(V) (V)
I
OUTOUT
(A) (A)
9
,1
9
9
,1
9
1.47
1.48
1.49
1.50
1.51
1.52
1.53
1.54
012345678910
V
OUT
OUT
(V)
(V)
I
OUT
OUT
(A)
(A)
9
,1
9
9
,1
9
75
80
85
90
95
100
0 1 2 3 4 5 6 7 8 9 1 0
VOUT = 5 V
VOUT =3.3 V
VOUT =2.5 V
VOUT =1.5 V
VOUT = 1 V
E fficiency (%)
IO UT (A)
Vishay Siliconix
SiC402A, SiC402BCD
Document Number: 63729
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Figure 13 - Start-Up - EN/PSV
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A)
Figure 14 - Start-Up (Pre-Bias) - EN/PSV
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A)
Figure 15 - Start-Up (Pre-Bias) - EN/PSV
(VDD = 5 V, VIN = 1.5 V, IOUT = 0 A)
Figure 16 - Shutdown - EN/PSV
(VDD = 5 V, VIN = 1.5 V, IOUT = 0 A)
Figure 17 - Ultra-sonic PSM - SiC402ACD
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 0 A)
Figure 18 - Forced Continuous Mode - SiC402ACD
(VDD = 5 V, VIN = 12 V, VOUT = 1.5 V, IOUT = 10 A)
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Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
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Figure 19 - Transient Response - PSM Rising (VDD = 5 V,
VIN = 12 V, VOUT = 1.5 V, IOUT = 0.5 to 8.5 A, dI/dt = 1 A/µs)
Figure 20 - Transient Response - FCM (VDD = 5 V,
VIN = 12 V, VOUT = 1.5 V, IOUT = 2.5 to 10 A, dI/dt = 1 A/µs)
Figure 21 - Transient Response - PSM Falling (VDD = 5 V,
VIN = 12 V, VOUT = 1.5 V, IOUT = 8.5 to 0.5 A, dI/dt = 1 A/µs)
Figure 22 - Thermal Shutdown - 146 °C
(VIN = 12 V, VOUT = 2.5 to 10 A, dI/dt = 1 A/µs)
Vishay Siliconix
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Document Number: 63729
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OPERATIONAL DESCRIPTION
Device Overview
The SiC402A/B is a step down synchronous DC/DC buck
converter with integrated power MOSFETs and a 200 mA
capable programmable LDO. The device is capable of
10 A operation at very high efficiency. A space saving
5 x 5 (mm) 32-pin package is used. The programmable
operating frequency of up to 1 MHz enables optimizing
the configuration for PCB area and efficiency.
The buck controller uses a pseudo-fixed frequency adaptive
on-time control. This control method allows fast transient
response which permits the use of smaller output capacitors.
Input Voltage Requirements
The SiC402A/B requires two input supplies for normal
operation: VIN and VDD. VIN operates over a wide range from
3 V to 28 V. VDD requires a 3 V to 5.5 V supply input that can
be an external source or the internal LDO configured to
supply 3 V to 5.5 V from VIN.
Power Up Sequence
When the SiC402A/B uses an external power source at the
VDD pin, the switching regulator initiates the start up when
VIN, VDD and EN/PSV are above their respective thresholds.
When EN/PSV is at logic high, VDD needs to be applied after
VIN rises. It is also recommended to use a 10 resistor
between an external power source and the VDD pin. To start
up by using the EN/PSV pin when both VDD and VIN are
above their respective thresholds, apply EN/PSV to enable
the start-up process. For SiC402A/B in self-biased mode,
refer to the LDO section for a full description.
Shutdown
The SiC402A/B can be shut-down by pulling either VDD or
EN/PSV below its threshold. When using an external power
source, it is recommended that the VDD voltage ramps down
before the VIN voltage. When VDD is active and EN/PSV at
logic low, the output voltage discharges into the VOUT pin
through an internal FET.
Pseudo-Fixed Frequency Adaptive On-Time Control
The PWM control method used for the SiC402A/B is
pseudo-fixed frequency, adaptive on-time, as shown in
figure 23. The ripple voltage generated at the output
capacitor ESR is used as a PWM ramp signal. This ripple is
used to trigger the on-time of the controller.
The adaptive on-time is determined by an internal one-shot
timer. When the one-shot is triggered by the output ripple, the
device sends a single on-time pulse to the highside
MOSFET. The pulse period is determined by VOUT and VIN;
the period is proportional to output voltage and inversely
proportional to input voltage. With this adaptive on-time
arrangement, the device automatically anticipates the
on-time needed to regulate VOUT for the present VIN
condition and at the selected frequency.
The advantages of adaptive on-time control are:
• Predictable operating frequency compared to other
variable frequency methods.
• Reduced component count by eliminating the error
amplifier and compensation components.
• Reduced component count by removing the need to sense
and control inductor current.
• Fast transient response - the response time is controlled
by a fast comparator instead of a typically slow error
amplifier.
• Reduced output capacitance due to fast transient
response.
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in figure 24. The FB
comparator output goes high when VFB is less than the
internal 600 mV reference. This feeds into the gate drive and
turns on the high-side MOSFET, and also starts the one-shot
timer. The one-shot timer uses an internal comparator and a
capacitor. One comparator input is connected to VOUT, the
other input is connected to the capacitor. When the on-time
begins, the internal capacitor charges from zero volts
through a current which is proportional to VIN. When the
capacitor voltage reaches VOUT, the on-time is completed
and the high-side MOSFET turns off.
Figure 23 - PWM Control Method, VOUT Ripple
V
IN
C
IN
V
LX
Q1
Q2
L
ESR
+
FB
V
LX
t
ON
V
FB
C
OUT
V
OUT
FB threshold
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Document Number: 63729
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Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
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This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN. Under
steady-state conditions, the switching frequency can be
determined from the on-time by the following equation.
The SiC402A/B uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can be
programmed to provide an operating frequency up to 1 MHz
using a resistor between the tON pin and ground. The resistor
value is selected by the following equation.
The constant, k, equals 1, when VDD is greater than 3.6 V.
If VDD is less than 3.6 V and VIN is greater than
(VDD - 1.75) x 10, k is shown by the following equation.
The maximum RtON value allowed is shown by the following
equation.
VOUT Voltage Selection
The switcher output voltage is regulated by comparing VOUT
as seen through a resistor divider at the FB pin to the internal
600 mV reference voltage, see figure 25.
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
Enable and Power-Save Inputs
The EN/PSV input is used to enable or disable the switching
regulator. When EN/PSV is low (grounded), the switching
regulator is off and in its lowest power state. When off, the
output of the switching regulator soft-discharges the output
into a 500 k internal resistor via the VOUT pin. When
EN/PSV is allowed to float, the pin voltage will float to 33 %
of the voltage at VDD. The switching regulator turns on with
power-save disabled and all switching is in forced continuous
mode.
When EN/PSV is high (above 44 % of the voltage at VDD),
the switching regulator turns on with power-save enabled.
The SiC402A/B PSAVE operation reduces the switching
frequency according to the load for increased efficiency at
light load conditions.
Forced Continuous Mode Operation
The SiC402A/B operates the switcher in FCM (Forced
Continuous Mode) by floating the EN/PSV pin (see figure
26). In this mode one of the power MOSFETs is always on,
with no intentional dead time other than to avoid
cross-conduction. This feature results in uniform frequency
across the full load range with the trade-off being poor
efficiency at light loads due to the high-frequency switching
of the MOSFETs. DH is gate signal to drive upper MOSFET.
DL is lower gate signal to drive lower MOSFET.
Figure 24 - On-Time Generation
Figure 25 - Output Voltage Selection
FB
VREP
-
+
VOUT
VIN
Rton On-time = K x Rton x (VOUT/VIN)
FB comparator
One-shot
timer
Gate
drives
DH
DL
Q1
Q2
L
Q1
ESR FB
VOUT
COUT
VLX
+
VIN
f
SW
=V
OUT
t
ON
x V
IN
Rton = k
25 pF x fsw
k = (VDD - 1.75) x 10
VIN
Rton_MAX. =VIN_MIN.
15 µA
V
OUT
R
1
R
2
to FB pin
V
OUT = 0.6 x 1 + +
R1
R22
VRIPPLE
Figure 26 - Forced Continuous Mode Operation
V
OUT = 0.6 x 1 + + x
R1
R22
VRIPPLE 1 + (R1ωCTOP)2
1 + ωCTOP
R2 x R1
R2 + R1
2
FB ripple
voltage (VFB)
Inductor
current
DC load current
FB threshold
DH
DL
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
DL drives high when on-time is completed.
DL remains high until VFB falls to the FB threshold.
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Ultrasonic Power-Save Operation (SiC402A)
The SiC402A provides ultrasonic power-save operation at
light loads, with the minimum operating frequency fixed at
slightly under 25 kHz. This is accomplished by using an
internal timer that monitors the time between consecutive
high-side gate pulses. If the time exceeds 40 µs, DL drives
high to turn the low-side MOSFET on. This draws current
from VOUT through the inductor, forcing both VOUT and VFB
to fall. When VFB drops to the 600 mV threshold, the next DH
(the drive signal for the high side FET) on-time is triggered.
After the on-time is completed the high-side MOSFET is
turned off and the low-side MOSFET turns on. The low-side
MOSFET remains on until the inductor current ramps down
to zero, at which point the low-side MOSFET is turned off.
Because the on-times are forced to occur at intervals no
greater than 40 µs, the frequency will not fall far below
25 kHz. Figure 27 shows ultrasonic power-save operation.
Power-Save Operation (SiC402B)
The SIC402B provides power-save operation at light loads
with no minimum operating frequency. With power-save
enabled, the internal zero crossing comparator monitors the
inductor current via the voltage across the low-side MOSFET
during the off-time. If the inductor current falls to zero for 8
consecutive switching cycles, the controller enters MOSFET
on each subsequent cycle provided that the power-save
operation. It will turn off the low-side MOSFET on each
subsequent cycle provided that the current crosses zero. At
this time both MOSFETs remain off until VFB drops to the
600 mV threshold. Because the MOSFETs are off, the load
is supplied by the output capacitor.
If the inductor current does not reach zero on any switching
cycle, the controller immediately exits power-save and
returns to forced continuous mode.
Figure 28 shows power-save operation at light loads
Smart Power-Save Protection
Active loads may leak current from a higher voltage into the
switcher output. Under light load conditions with power-save
enabled, this can force VOUT to slowly rise and reach the
over-voltage threshold, resulting in a hard shut-down. Smart
power-save prevents this condition. When the FB voltage
exceeds 10 % above nominal, the device immediately
disables power-save, and DL drives high to turn on the
low-side MOSFET. This draws current from VOUT through
the inductor and causes VOUT to fall. When VFB drops back
to the 600 mV trip point, a normal tON switching cycle begins.
This method prevents a hard OVP shut-down and also
cycles energy from VOUT back to VIN. It also minimizes
operating power by avoiding forced conduction mode
operation. Figure 29 shows typical waveforms for the smart
power-save feature.
Figure 27 - Ultrasonic Power-Save Operation
FB ripple
voltage (VFB)
Inductor
current
(0 A)
FB threshold
(600 mV)
DH
DL
On-time
(tON)
DH on-time is triggered when
VFB reaches the FB threshold
After the 40 µs time-out, DL drives high if VFB
has not reached the FB threshold.
minimum fSW ~ 25 kHz
40 μs time-out
Figure 28 - Power-Save Mode
Figure 29 - Smart Power-Save
VOUT drifts up to due to leakage
current flowing into COUT
Smart power save
threshold
FB
threshold
DH and DL off
High-side
drive (DH)
Low-side
drive (DL)
Normal VOUT ripple
VOUT discharges via inductor
and low-side MOSFET
Single DH on-time pulse
after DL turn-off
Normal DL pulse after DH
on-time pulse
DL turns on when smart
PSAVE threshold is reached
DL turns off FB
threshold is reached
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Document Number: 63729
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Vishay Siliconix
SiC402A, SiC402BCD
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SmartDriveTM
For each DH pulse the DH driver initially turns on the high
side MOSFET at a lower speed, allowing a softer, smooth
turn-off of the low-side diode. Once the diode is off and the
LX voltage has risen 0.5 V above PGND, the SmartDrive
circuit automatically drives the high-side MOSFET on at a
rapid rate. This technique reduces switching losses while
maintaining high efficiency and also avoids the need for
snubbers for the power MOSFETs.
Current Limit Protection
The device features programmable current limiting, which is
accomplished by using the RDS(on) of the lower MOSFET for
current sensing. The current limit is set by RILIM resistor. The
RILIM resistor connects from the ILIM pin to the LXS pin which
is also the drain of the low-side MOSFET. When the low-side
MOSFET is on, an internal ~ 10 µA current flows from the
ILIM pin and through the RILIM resistor, creating a voltage
drop across the resistor. While the low-side MOSFET is on,
the inductor current flows through it and creates a voltage
across the RDS(on). The voltage across the MOSFET is
negative with respect to ground. If this MOSFET voltage drop
exceeds the voltage across RILIM, the voltage at the ILIM pin
will be negative and current limit will activate. The current
limit then keeps the low-side MOSFET on and will not allow
another high-side on-time, until the current in the low-side
MOSFET reduces enough to bring the ILIM voltage back up
to zero. This method regulates the inductor valley current at
the level shown by ILIM in figure 30.
Setting the valley current limit to 10 A results in a peak
inductor current of 10 A plus peak ripple current. In this
situation, the average (load) current through the inductor is
10 A plus one-half the peak-to-peak ripple current.
The internal 10 µA current source is temperature
compensated at 4100 ppm in order to provide tracking with
the RDS(on).
The RILIM value is calculated by the following equation.
RILIM = 446 x ILIM x [0.099 x (5 V - VDD) + 1]
When selecting a value for RILIM be sure not to exceed the
absolute maximum voltage value for the ILIM pin. Note that
because the low-side MOSFET with low RDS(on) is used for
current sensing, the PCB layout, solder connections, and
PCB connection to the LX node must be done carefully to
obtain good results. RILIM should be connected directly to
LXS (pin 28).
Soft-Start of PWM Regulator
SiC402A/B has a programmable soft-start time that is
controlled by an external capacitor at the SS pin. After the
controller meets both UVLO and EN/PSV thresholds, the
controller has an internal current source of 3 µA flowing
through the SS pin to charge the capacitor. During the start
up process (figure 31), 50 % of the voltage at the SS pin is
used as the reference for the FB comparator. The PWM
comparator issues an on-time pulse when the voltage at the
FB pin is less than 40 % of the SS pin. As a result, the output
voltage follows the SS voltage. The output voltage reaches
and maintains regulation when the soft start voltage is
1.5 V. The time between the first LX pulse and VOUT
reaching regulation is the soft-start time (tSS). The
calculation for the soft-start time is shown by the following
equation.
The voltage at the SS pin continues to ramp up and
eventually equals 64 % of VDD. After the soft start completes,
the FB pin voltage is compared to an internal reference of
0.6 V. The delay time between the VOUT regulation point and
PGOOD going high is shown by the following equation.
Pre-Bias Startup
The SiC402A/B can start up normally even when there is an
existing output voltage present. The soft start time is still the
same as normal start up (when the output voltage starts from
zero). The output voltage starts to ramp up when 40 % of the
voltage at SS pin meets the existing FB voltage level.
Pre-bias startup is achieved by turning off the lower gate
when the inductor current falls below zero. This method
prevents the output voltage from discharging.
Figure 30 - Valley Current Limit
IPEAK
ILOAD
ILIM
Inductor Current
Figure 31 - Soft-Start Timing Diagram
tSS = CSS x1.5 V
3 μA
tPGOOD-DELAY
= C
SS
x (0.64 x V
DD
- 1.5 V)
3 μA
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Document Number: 63729
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Power Good Output
The PGOOD (power good) output is an open-drain output
which requires a pull-up resistor. When the voltage at the FB
pin is 10 % below the nominal voltage, PGOOD is pulled low.
It is held low until the output voltage returns above - 8 % of
nominal.
PGOOD will transition low if the VFB pin exceeds + 20 % of
nominal, which is also the over-voltage shutdown threshold.
PGOOD also pulls low if the EN/PSV pin is low when VDD is
present.
Output Over-Voltage Protection
Over-voltage protection becomes active as soon as the
device is enabled. The threshold is set at 600 mV + 20 %
(720 mV). When VFB exceeds the OVP threshold, DL latches
high and the low-side MOSFET is turned on. DL remains
high and the controller remains off, until the EN/PSV input is
toggled or VDD is cycled. There is a 5 µs delay built into the
OVP detector to prevent false transitions. PGOOD is also low
after an OVP event.
Output Under-Voltage Protection
When VFB falls 25 % below its nominal voltage (falls to
450 mV) for eight consecutive clock cycles, the switcher is
shut off and the DH and DL drives are pulled low to tri-state
the MOSFETs. The controller stays off until EN/PSV is
toggled or VDD is cycled.
VDD UVLO, and POR
UVLO (Under-Voltage Lock-Out) circuitry inhibits switching
and tri-states the DH/DL drivers until VDD rises above 3 V. An
internal POR (Power-On Reset) occurs when VDD exceeds
3 V, which resets the fault latch and a soft-start counter cycle
begins which prepares for soft-start. The SiC402A/B then
begins a soft-start cycle. The PWM will shut off if VDD falls
below 2.4 V.
LDO Regulator
SiC402A/B has an option to bias the switcher by using an
internal LDO from VIN. The LDO output is connected to VDD
internally. The output of the LDO is programmable by using
external resistors from the VDD pin to AGND (see figure 32).
The feedback pin (FBL) for the LDO is regulated to 750 mV.
The LDO output voltage is set by the following equation.
A minimum capacitance of 1 µF referenced to AGND is
normally required at the output of the LDO for stability.
Note that if the LDO voltage is set lower than 4.5 V, the
minimum output capacitance for the LDO is 10 µF.
LDO ENL Functions
The ENL input is used to enable/disable the internal LDO.
When ENL is a logic low, the LDO is off. When ENL is above
the VIN UVLO threshold, the LDO is enabled and the
switcher is also enabled if the EN/PSV and VDD are above
their threshold. The table below summarizes the function of
ENL and EN/PSV pins.
The ENL pin also acts as the switcher under-voltage lockout
for the VIN supply. When SiC402A/B is self-biased from the
LDO and runs from the VIN power source only, the VIN UVLO
feature can be used to prevent false UV faults for the PWM
output by programming with a resistor divider at the VIN, ENL
and AGND pins. When SiC402A/B has an external bias
voltage at VDD and the ENL pin is used to program the
VIN UVLO feature, the voltage at FBL needs to be higher
than 750 mV to force the LDO off.
Timing is important when driving ENL with logic and not
implementing VIN UVLO. The ENL pin must transition from
high to low within 2 switching cycles to avoid the PWM output
turning off. If ENL goes below the VIN UVLO threshold and
stays above 1 V, then the switcher will turn off but the LDO
will remain on.
LDO Start-Up
Before start-up, the LDO checks the status of the following
signals to ensure proper operation can be maintained.
1. ENL pin
2. VIN input voltage
When the ENL pin is high and VIN is above the UVLO point,
the LDO will begin start-up. During the initial phase, when the
VDD voltage (which is the LDO output voltage) is less than
0.75 V, the LDO initiates a current-limited start-up (typically
65 mA) to charge the output capacitors while protecting from
a short circuit event. When VDD is greater than 0.75 V but still
less than 90 % of its final value (as sensed at the FBL pin),
the LDO current limit is increased to ~ 115 mA. When VDD
has reached 90 % of the final value (as sensed at the FBL
pin), the LDO current limit is increased to ~ 200 mA and the
LDO output is quickly driven to the nominal value by the
internal LDO regulator. It is recommended that during LDO
Figure 32 - LDO Output Voltage Selection
VDD
RLDO1
to FBL pin
RLDO2
VLDO = 750 mV x 1 + RLDO1
RLDO2
EN/PSV ENL LDO Switcher
Disabled Low, < 0.4 V Off Off
Enabled Low, < 0.4 V Off On
Disabled 1 V < High < 2.6 V On Off
Enabled 1 V < High < 2.6 V On Off
Disabled High, > 2.6 V On Off
Enabled High, > 2.6 V On On
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Document Number: 63729
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start-up to hold the PWM switching off until the LDO has
reached 90 % of the final value. This prevents overloading
the current-limited LDO output during the LDO start-up.
Due to the initial current limitations on the LDO during power
up (figure 33), any external load attached to the VDD pin must
be limited to less than the start up current before the LDO
has reached 90 % of its final regulation value.
LDO Switch-Over Operation
The SiC402A/B includes a switch-over function for the LDO.
The switch-over function is designed to increase efficiency
by using the more efficient DC/DC converter to power the
LDO output, avoiding the less efficient LDO regulator when
possible. The switch-over function connects the VDD pin
directly to the VOUT pin using an internal switch. When the
switch-over is complete the LDO is turned off, which results
in a power savings and maximizes efficiency. If the LDO
output is used to bias the SiC402A/B, then after switch-over
the device is self-powered from the switching regulator with
the LDO turned off.
The switch-over starts 32 switching cycles after PGOOD
output goes high. The voltages at the VDD and VOUT pins are
then compared; if the two voltages are within ± 300 mV of
each other, the VDD pin connects to the VOUT pin using an
internal switch, and the LDO is turned off. To avoid unwanted
switch-over, the minimum difference between the voltages
for VOUT and VDD should be ± 500 mV.
It is not recommended to use the switch-over feature for an
output voltage less than VDD UVLO threshold since the
SiC402A/B is not operational below that threshold.
Switch-over MOSFET Parasitic Diodes
The switch-over MOSFET contains parasitic diodes that are
inherent to its construction, as shown in figure 34. If the
voltage at the VOUT pin is higher than VDD, then the
respective diode will turn on and the current will flow through
this diode. This has the potential of damaging the device.
Therefore, VOUT must be less than VDD to prevent damaging
the device.
Design Procedure
When designing a switch mode supply the input voltage
range, load current, switching frequency, and inductor ripple
current must be specified.
The maximum input voltage (VIN MAX.) is the highest
specified input voltage. The minimum input voltage (VIN MIN.)
is determined by the lowest input voltage after evaluating the
voltage drops due to connectors, fuses, switches, and PCB
traces.
The following parameters define the design.
• Nominal output voltage (VOUT)
• Static or DC output tolerance
• Transient response
• Maximum load current (IOUT).
There are two values of load current to evaluate - continuous
load current and peak load current. Continuous load current
relates to thermal stresses which drive the selection of the
inductor and input capacitors. Peak load current determines
instantaneous component stresses and filtering
requirements such as inductor saturation, output capacitors,
and design of the current limit circuit.
The following values are used in this design.
VIN = 12 V ± 10 %
VOUT = 1.5 V ± 4 %
fSW = 300 kHz
Load = 10 A maximum
Frequency Selection
Selection of the switching frequency requires making a
trade-off between the size and cost of the external filter
components (inductor and output capacitor) and the power
conversion efficiency.
The desired switching frequency is 300 kHz which results
from using components selected for optimum size and cost.
A resistor (RtON) is used to program the on-time (indirectly
setting the frequency) using the following equation.
To select RtON, use the maximum value for VIN, and for tON
use the value associated with maximum VIN.
Figure 33 - LDO Start-Up
Figure 34 - Switch-over MOSFET Parasitic Diodes
VOUT
Parastic diode
Switchover
MOSFET
Switchover
control
VDD
LDO
R
ton
= k
25 pF x f
sw
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Substituting for RtON results in the following solution.
RtON = 133.3 k, use RtON = 130 k
Inductor Selection
In order to determine the inductance, the ripple current must
first be defined. Low inductor values result in smaller size but
create higher ripple current which can reduce efficiency.
Higher inductor values will reduce the ripple current/voltage
and for a given DC resistance are more efficient. However,
larger inductance translates directly into larger packages and
higher cost. Cost, size, output ripple, and efficiency are all
used in the selection process.
The ripple current will also set the boundary for PSAVE
operation. The switching will typically enter PSAVE mode
when the load current decreases to 1/2 of the ripple current.
For example, if ripple current is 4 A then PSAVE operation will
typically start for loads less than 2 A. If ripple current is set at
40 % of maximum load current, then PSAVE will start for loads
less than 20 % of maximum current.
The inductor value is typically selected to provide a ripple
current that is between 25 % to 50 % of the maximum load
current. This provides an optimal trade-off between cost,
efficiency, and transient performance.
During the on-time, voltage across the inductor is
(VIN - VOUT). The equation for determining inductance is
shown next.
Example
In this example, the inductor ripple current is set equal to
45 % of the maximum load current. Therefore ripple current
will be 45 % x 10 A or 4.5 A. To find the minimum inductance
needed, use the VIN and tON values that correspond to
VINMAX.
A slightly larger value of 1 µH is selected. This will decrease
the maximum IRIPPLE to 4.43 A.
Note that the inductor must be rated for the maximum DC
load current plus 1/2 of the ripple current.
The ripple current under minimum VIN conditions is also
checked using the following equations.
Capacitor Selection
The output capacitors are chosen based upon required ESR
and capacitance. The maximum ESR requirement is
controlled by the output ripple requirement and the DC
tolerance. The output voltage has a DC value that is equal to
the valley of the output ripple plus 1/2 of the peak-to-peak
ripple. A change in the output ripple voltage will lead to a
change in DC voltage at the output.
The design goal for output voltage ripple is 3 % of 1.5 V or
45 mV. The maximum ESR value allowed is shown by the
following equations.
The output capacitance is usually chosen to meet transient
requirements. A worst-case load release, from maximum
load to no load at the exact moment when inductor current is
at the peak, determines the required capacitance. If the load
release is instantaneous (load changes from maximum to
zero in < 1 µs), the output capacitor must absorb all the
inductor's stored energy. This will cause a peak voltage on
the capacitor according to the following equation.
Assuming a peak voltage VPEAK of 1.65 V (150 mV rise upon
load release), and a 10 A load release, the required
capacitance is shown by the next equation.
During the load release time, the voltage cross the inductor
is approximately - VOUT. This causes a down-slope or falling
dI/dt in the inductor. If the load dI/dt is not much faster than
the dI/dt of the inductor, then the inductor current will tend to
track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor; therefore a smaller capacitance can be used.
The following can be used to calculate the needed
capacitance for a given dILOAD/dt.
Peak inductor current is shown by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 10 + 1/2 x 4.43 = 12.215 A
Imax. = maximum load release = 10 A
tON =VOUT
VINMAX. x fSW
L = (VIN - VOUT) x tON
IRIPPLE
L = (13.2 - 1.5) x 379 ns
4.5 A = 0.99 µH
TON_VINMIN =25 pF x RTON x VOUT
VINMIN
IRIPPLE =(VIN - VOUT) x tON
L
IRIPPLE_VINMIN =(10.8 - 1.5) x 451 ns
1 µH
= 451 ns
= 4.19 A
ESRMAX =VRIPPLE
IRIPPLEMAX
ESRMAX = 10.2 mΩ
=45 mV
4.43 A
C
OUT_MIN
=
L (I
OUT
+ x I
RIPPLEMAX
)
2
(V
PEAK
)
2
- (V
OUT
)
2
1
2
C
OUT_MIN
=
1 µH (10 + x 4.43)
2
(1.65)
2
- (1.5)
2
C
OUT_MIN
= 316 µF
1
2
Rate of change of Load Current = dILOAD
dt
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18
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
Example
This would cause the output current to move from 10 A to 0 A
in 4 µs, giving the minimum output capacitance requirement
shown in the following equation.
Note that COUT is much smaller in this example, 169 µF
compared to 316 µF based on a worst-case load release. To
meet the two design criteria of minimum 316 µF and maximum
10.2 m ESR, select one capacitor of 330 µF and 9 m ESR.
Stability Considerations
Unstable operation is possible with adaptive on-time
controllers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the FB
input or because the FB ripple voltage is too low. This causes
the FB comparator to trigger prematurely after the 250 ns
minimum off-time has expired. In extreme cases the noise can
cause three or more successive on-times. Double-pulsing will
result in higher ripple voltage at the output, but in most
applications it will not affect operation. This form of instability
can usually be avoided by providing the FB pin with a smooth,
clean ripple signal that is at least 10 mVp-p, which may dictate
the need to increase the ESR of the output capacitors. It is also
imperative to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a small
(~ 10 pF) capacitor across the upper feedback resistor, as
shown in figure 35. This capacitor should be left unpopulated
until it can be confirmed that double-pulsing exists. Adding the
CTOP capacitor will couple more ripple into FB to help eliminate
the problem. An optional connection on the PCB should be
available for this capacitor.
ESR loop instability is caused by insufficient ESR. The details
of this stability issue are discussed in the ESR Requirements
section. The best method for checking stability is to apply a
zero-to-full load transient and observe the output voltage ripple
envelope for overshoot and ringing. Ringing for more than one
cycle after the initial step is an indication that the ESR should
be increased.
ESR Requirements
A minimum ESR is required for two reasons. One reason is to
generate enough output ripple voltage to provide 10 mVp-p at
the FB pin (after the resistor divider) to avoid double-pulsing.
The second reason is to prevent instability due to insufficient
ESR. The on-time control regulates the valley of the output
ripple voltage. This ripple voltage is the sum of the two
voltages. One is the ripple generated by the ESR, the other is
the ripple due to capacitive charging and discharging during
the switching cycle. For most applications the minimum ESR
ripple voltage is dominated by the output capacitors, typically
SP or POSCAP devices. For stability the ESR zero of the
output capacitor should be lower than approximately one-third
the switching frequency. The formula for minimum ESR is
shown by the following equation.
Using Ceramic Output Capacitors
When the system is using high ESR value capacitors, the
feedback voltage ripple lags the phase node voltage by 90° .
Therefore, the converter is easily stabilized. When the system
is using ceramic output capacitors, the ESR value is normally
too small to meet the above ESR criteria. As a result, the
feedback voltage ripple is 180° from the phase node and
behaves in an unstable manner. In this application it is
necessary to add a small virtual ESR network that is composed
of two capacitors and one resistor, as shown in figure 36.
COUT = ILPK x
L x - x dt
2 (VPK - VOUT)
ILPK
VOUT
IMAX
dlLOAD
dlLOAD
dt =2.5 A
1 µs
COUT
= 12.215
x
1 µH x - x 1 µs
2 (1.65 - 1.5)
12.215
1.5
10
2.5
C
OUT
= 169 µF
Figure 35 - Capacitor Coupling to FB Pin
VOUT R1
R2
To FB pin
CTOP
ESR
MIN
=3
2 x π x C
OUT
x f
SW
Vishay Siliconix
SiC402A, SiC402BCD
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
www.vishay.com
19
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across CL and output ripple voltage.
They are defined in the following equations.
Figure 37 shows the magnitude of the ripple contribution due
to CL at the FB pin.
It is shown by the following equation.
Figure 38 shows the magnitude of the ripple contribution due
to the output voltage ripple at the FB pin.
It is shown by the following equation.
The purpose of this network is to couple the inductor current
ripple information into the feedback voltage such that the
feedback voltage has 90° phase lag to the switching node
similar to the case of using standard high ESR capacitors.
This is illustrated in figure 39.
The magnitude of the feedback ripple voltage, which is
dominated by the contribution from CL, is controlled by the
value of R1, R2 and CC. If the corner frequency of (R1//R2) x
CC is too high, the ripple magnitude at the FB pin will be
smaller, which can lead to double-pulsing. Conversely, if the
corner frequency of (R1//R2) x CC is too low, the ripple
magnitude at FB pin will be higher. Since the SiC402A/B
regulates to the valley of the ripple voltage at the FB pin, a
high ripple magnitude is undesirable as it significantly
impacts the output voltage regulation. As a result, it is
desirable to select a corner frequency for (R1//R2) x CC to
achieve enough, but not excessive, ripple magnitude and
phase margin. The component values for R1, R2, and CC
should be calculated using the following procedure.
Select CL (typical 10 nF) and RL to match with L and DCR
time constant using the following equation.
Figure 36 - Virtual ESR Ramp Circuit
Figure 37 - FB Voltage by CL Voltage
IL x DCR (s x L/DCR + 1)
S x RLCL + 1
V
CL =
ΔIL
8C x fSW
ΔVOUT =
(R
1
//R
2
) x S x C
C
(R
1
//R
2
) x S x C
C
+ 1
VFB
CL
= V
CL
x
Figure 38 - FB Voltage by Output Voltage
Figure 39 - FB Voltage in Phasor Diagram
VFBΔVOUT = ΔVOUT x R2
R1// + R2
1
S x CC
DCR x C
L
R
L
=L
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Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
Select CC by using the following equation.
The resistor values (R1 and R2) in the voltage divider circuit set
the VOUT for the switcher. The typical value for CC is from
10 pF to 1 nF.
Dropout Performance
The output voltage adjustment range for continuous
conduction operation is limited by the fixed 250 ns (typical)
minimum off-time of the one-shot. When working with low input
voltages, the duty-factor limit must be calculated using worst-
case values for on- and off-times.
The duty-factor limitation is shown by the next equation.
The inductor resistance and MOSFET on-state voltage
drops must be included when performing worst-case dropout
duty-factor calculations.
System DC Accuracy (VOUT Controller)
Three factors affect VOUT accuracy: the trip point of the FB
error comparator, the ripple voltage variation with line and
load, and the external resistor tolerance. The error comparator
offset is trimmed so that under static conditions it trips when
the feedback pin is 600 mV, 1 %.
The on-time pulse from the SiC402A/B in the design example
is calculated to give a pseudo-fixed frequency of 300 kHz.
Some frequency variation with line and load is expected. This
variation changes the output ripple voltage. Because adaptive
on-time converters regulate to the valley of the output ripple, ½
of the output ripple appears as a DC regulation error. For
example, if the output ripple is 50 mV with VIN = 6 V, then the
measured DC output will be 25 mV above the comparator trip
point. If the ripple increases to 80 mV with VIN = 25 V, then the
measured DC output will be 40 mV above the comparator trip.
The best way to minimize this effect is to minimize the output
ripple.
The use of 1 % feedback resistors may result in up to 1 % error.
If tighter DC accuracy is required, 0.1 % resistors should be
used.
The output inductor value may change with current. This will
change the output ripple and therefore will have a minor effect
on the DC output voltage. The output ESR also affects the
output ripple and thus has a minor effect on the DC output
voltage.
Switching Frequency Variation
The switching frequency varies with load current as a result of
the power losses in the MOSFETs and DCR of the inductor.
For a conventional PWM constant-frequency converter, as
load increases the duty cycle also increases slightly to
compensate for IR and switching losses in the MOSFETs and
inductor. An adaptive on-time converter must also compensate
for the same losses by increasing the effective duty cycle
(more time is spent drawing energy from VIN as losses
increase). The on-time is essentially constant for a given
VOUT/VIN combination, to offset the losses the off-time will
tend to reduce slightly as load increases. The net effect is that
switching frequency increases slightly with increasing load.
CC ≈ R1//R2
13
2 x π x fsw
x
DUTY =TON(MIN)
TON(MIN) x TOFF(MAX)
Vishay Siliconix
SiC402A, SiC402BCD
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
www.vishay.com
21
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
SIC402B EVALUATION BOARD SCHEMATIC
Figure 40 - Evaluation Board Schematic
TON
lxbst
SOFT
LX
Vo
BST
PGD
ILIM
FBL
EN_PSV
VDD
VOUT
FB
VIN
VDD
P8
VIN
P8
VIN
1
+
C17
330uF
+
C17
330uF
+
C10
10uF
+
C10
10uF
R15
10K
R15
10K
R8 4.64KR8 4.64K
B4 VO_GNDB4 VO_GND
1
P1
VDD
P1
VDD
1
R39 0RR39 0R
+
C18
330uF
+
C18
330uF
C30
68pF
C30
68pF
+
C22
10uF
+
C22
10uF
C26
1uF
C26
1uF
R23 6.81KR23 6.81K
P10
VOUT
P10
VOUT
1
C6
1uF
C6
1uF
+
C16
330uF
+
C16
330uF
P11
VO_GND
P11
VO_GND
1
+
C20
10uF
+
C20
10uF
R10
10k
R10
10k
C29
3.3nF
C29
3.3nF
U1
SiC401/2/3
U1
SiC401/2/3
FB 1
FBL
5
VDD
3
AGND
30 VOUT 2
VIN
6
SOFT
7
BST 8
VIN
9
VIN
10
VIN
11
NC 14
LX 23
NC 12
PGND
22 PGND
21
LX 25
LX 24
PGND
20 PGND
19 PGND
18 PGND
17 PGND
16 PGND
15 ENL 32
TON 31
AGND
35
EN/PSV 29
LXBST 13
ILIM 27
PGD 26
LXS 28
LX 33
VIN
34
AGND
4
P7
PGOOD
P7
PGOOD
1
B2
VIN_GND
B2
VIN_GND
1
P9
VIN_GND
P9
VIN_GND
1
R7 0R
R7 0R
C27
1uF
C27
1uF
R30
130K
R30
130K
R14
0
R14
0
R13 100R13 100
L1 1uHL1 1uH
+
C12
150uF
+
C12
150uF
B3 VoB3 Vo
1
C15
33uF
C15
33uF
R52
0
R52
0
P2
EN_PSV
P2
EN_PSV
1
C25
68pF
C25
68pF
B1
VIN
B1
VIN
1
www.vishay.com
22
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
BILL OF MATERIALS
Item Qty. Reference
Designator PCB Footprint Material Value Voltage Description Vendor P/N
1 1 C12 Radial 150 µF 35 V Cap, Radial 150 µF 35 V EU-FM1V151
2 3 C10, C20, C22 SM1210 X5R 10 µF 25 V Cap10 µF 25 V 1210 TMK325BJ106MM
3 3 C26, C27, C6 SM0805 X7R 1 µF 35 V CAP CER 1 µF 35 V X7R
0805 GMK212B7105KG-T
4 2 C30, C25 SM0402 X7R 68 pF 50 V CAP, 68 pF, 50 V, 0402 VJ0402Y680KXACW1BC
5 1 C15 SM0805 X7R 33 µF 10 V 33 µF 10 V 0805 LMK212BJ336MG-T
6 3 C16, C17, C18 Case D X7R 33 µF 6.3 V 33 µF 6.3 V solid tantalum
surface mount 293D337XD6R3D2
7 1 C29 SM0603 X7R 3.3 nF 50 V Cap, 3.3 nF 50 V VJ0603Y332KXACW1BC
8 4 R52, R7, R14, R39 SM0603 0 50 V RES 0 1% Generic
9 1 R30 SM0603 130 k50 V RES 130 k 1% Generic
10 1 R15 SM0603 10 k50 V RES 10 k 1% Generic
11 1 R13 SM0603 100 50 V RES 100 1% Generic
12 1 R8 SM0603 4.64 k50 V RES 4.64 k 1% Generic
13 1 R23 SM0603 6.81 k50 V RES 6.81 k 1% Generic
14 1 R10 SM0603 10 k50 V RES 10 k 1% Generic
15 1 U1 PowerPAK
MLP55-32L
SiC402B 10 A microBUCK®
SiC402A/B
Integarted Buck Regulator
with Programmable LDO
SiC402BCD
16 4 B1, B2, B3, B4 Connector
17 1 L1 IHLP4040 1 µH 1 µH IHLP4040DZER1R0M01
Vishay Siliconix
SiC402A, SiC402BCD
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
www.vishay.com
23
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
PCB LAYOUT OF THE EVALUATION BOARD
Figure 41 - Top Layer
Figure 43 - Middle Layer 2
Figure 45 - Top Component
Figure 42 - Middle Layer 1
Figure 44 - Bottom Layer
Figure 46 - Bottom Component
www.vishay.com
24
Document Number: 63729
S12-2109-Rev. B, 03-Sep-12
Vishay Siliconix
SiC402A, SiC402BCD
This document is subject to change without notice.
THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
For technical questions, contact: powerictechsupport@vishay.com
PACKAGE DIMENSIONS AND MARKING INFO
Note:
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y1 4.5M - 1994.
3. N is the number of terminals
Nd is the number of terminals in X-direction and
Ne is the number of terminals in Y-direction.
4. Dimensions applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5.
The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?63729.
Dime
nsion
s
Millimeters Inches
Note
Min. Nom. Max. Min. Nom. Max.
A 0.70 0.75 0.80 0.027 0.029 0.031
A1 0.00 - 0.05 0.00 - 0.002 8
A2 0.20 ref. 0.008 ref.
b 0.20 0.25 0.30 0.078 0.098 0.110 4
D 5.00 BSC 0.196 BSC
e 0.50 BSC 0.019 BSC
E 5.00 BSC 0.196 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N32 323
Nd 8 8 3
Ne 8 8 3
Dimen
sions
Millimeters Inches
Min. Nom. Max. Min. Nom. Max.
D2-1 3.43 3.48 3.53 0.135 0.137 0.139
D2-2 1.00 1.05 1.10 0.039 0.041 0.043
D2-3 1.00 1.05 1.10 0.039 0.041 0.043
D2-4 1.92 1.97 2.02 0.075 0.077 0.079
D2-5 0.36 0.014
E2-1 3.43 3.48 3.53 0.135 0.137 0.139
E2-2 1.61 1.66 1.71 0.063 0.065 0.067
E2-3 1.43 1.48 1.53 0.056 0.058 0.060
E2-4 0.45 0.018
Document Number: 64714 www.vishay.com
Revision: 29-Dec-08 1
Package Information
Vishay Siliconix
PowerPAK® MLP55-32L CASE OUTLINE
Notes
1. Use millimeters as the primary measurement.
2. Dimensioning and tolerances conform to ASME Y14.5M. - 1994.
3. N is the number of terminals.
Nd is the number of terminals in X-direction and Ne is the number of terminals in Y-direction.
4. Dimension b applies to plated terminal and is measured between 0.20 mm and 0.25 mm from terminal tip.
5. The pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of package body.
6. Exact shape and size of this feature is optional.
7. Package warpage max. 0.08 mm.
8. Applied only for terminals.
by marking
E
Pin 1 dot
Top View
D
(5 mm x 5 mm)
32L T/SLP
E2 - 2
(Nd-1) Xe
Ref.
Bottom View
Side View
D2 - 1
R0.200
Pin #1 identification
b
e
D2 - 4 D2 - 3
E2 - 3
D4
9
24
25 32
A
0.10 CB
2x
0.08C
C
A
A2
A1
B
(Nd-1) Xe
Ref.
L
0.36
0.360
56
0.10 CAB
4
D2 - 2
E2 - 1
0.10 CA
2x
8
17
16
0.45
1
MILLIMETERS INCHES
DIM MIN. NOM. MAX. MIN. NOM. MAX.
A 0.80 0.85 0.90 0.031 0.033 0.035
A1(8) 0.00 - 0.05 0.000 - 0.002
A2 0.20 REF. 0.008 REF.
b(4) 0.20 0.25 0.30 0.078 0.098 0.011
D 5.00 BSC 0.196 BSC
e 0.50 BSC 0.019 BSC
E 5.00 BSC 0.196 BSC
L 0.35 0.40 0.45 0.013 0.015 0.017
N(3) 32 32
Nd(3) 88
Ne(3) 88
D2 - 1 3.43 3.48 3.53 0.135 0.137 0.139
D2 - 2 1.00 1.05 1.10 0.039 0.041 0.043
D2 - 3 1.00 1.05 1.10 0.039 0.041 0.043
D2 - 4 1.92 1.97 2.02 0.075 0.077 0.079
E2 - 1 3.43 3.48 3.53 0.135 0.137 0.139
E2 - 2 1.61 1.66 1.71 0.063 0.065 0.067
E2 - 3 1.43 1.48 1.53 0.056 0.058 0.060
ECN: T-08957-Rev. A, 29-Dec-08
DWG: 5983
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Revision: 12-Mar-12 1Document Number: 91000
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