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Old Company Name in Catalogs and Other Documents
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April 1st, 2010
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Rev.2.41 Jan 10, 2006 Page 1 of 96
REJ03B0001-0241
M16C/62P Group (M16C/62P, M16C/62P T)
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0001-0241
Rev.2.41
Jan 10, 2006
1. Overview
The M16C/62P Group (M16C/62P, M16C/62PT) of single-chip micro computers are built u sing the high performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin, 100-pin and 128-pin
plastic molded QFP. These single-chip microcomputers operate using sophisticat ed instructions featuring a high level
of instruction efficiency. With 1M bytes of address space, they are capable of executing instructions at high speed. In
addition, this microcomputer contains a multiplier and DMAC which combined with fast instruction processing
capability, makes it su itable for control o f various OA , commu nication, and in dustrial equipm ent which requi res high-
speed arithmetic/logic operations.
1.1 Applications
Audio, cameras, television , home appliance, office/communications/portable/industrial equipment, automobile,
etc.
Specifications written in this manual are believed to be accurate,
but are not guaranteed to be entirely free of error. Specifications in
this manual may be changed for functional or performance
improvements. Pl ease make sure your manual is the latest edition.
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 2 of 96
REJ03B0001-0241
1.2 Performance Outline
Table 1.1 to 1.3 list Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version).
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 Product Code for the program and erase endurance, and operating ambient temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Table 1.1 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(128-pin version)
Item Performance
M16C/62P
CPU Number of Basic Instructions 91 instructions
Minimum Instruction Execution
Time 41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V)
Operating Mode Single-chip, memory expansion and microprocessor mode
Address Space 1 Mbyte (Available to 4 Mbytes by memory space expansion
function)
Memory Capacity See Table 1.4 to 1.5 Product List
Peripheral
Function Port Input/Output : 113 pins, Input : 1 pin
Multifunction Timer Timer A : 16 bits x 5 channels,
Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface 3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT-CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt Internal: 29 sources, External: 8 sources, Software: 4 sources,
Priority level : 7 leve l s
Clock Generation Circuit 4 circuits
Main clock generation circuit (*),
Subclock generation circuit (*),
On-chip oscillator, PLL synthesizer
(*)Equipped with a built-in feedback resistor.
Oscillation Stop Detection
Function Stop detection of main clock oscillation, re-oscillation detection
function
Voltage Detection Circuit Available (option (4))
Electric
Characteristics Supply Voltage VCC1=3.0 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to VCC1 (f(BCLK=10MHz)
Power Consumption 14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10MHz)
1.8µA (VCC1=VCC2=3V, f(XCIN)=32kHz, wait mode)
0.7µA (VCC1=VCC2=3V, stop mode)
Flash memory
version Program/Erase Supply Voltage 3.3±0.3 V or 5.0±0.5 V
Program and Erase Endurance 100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature -20 to 85°C,
-40 to 85°C (3)
Package 128-pin plastic mold LQFP
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 3 of 96
REJ03B0001-0241
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the progra m and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. Use the M16C/62PT on VCC1=VCC2
5. All options are on request basis.
Table 1.2 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(100-pin version)
Item Performance
M16C/62P M16C/62PT(4)
CPU
Number of Basic Instructions
91 instructions
Minimum Instruction
Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
Operating Mode Single-chip, me mory expansion
and microprocessor mode Single-chip
Address Space 1 Mbyte (Available to 4 Mbytes by
memory space expansion function) 1 Mbyte
Memory Capacity See Tabl e 1. 4 t o 1.7 Produ c t Li st
Peripheral
Function Port Input/Output : 87 pins, Input : 1 pin
Multifunction Timer Timer A : 16 bits x 5 channels, Timer B : 16 bits x 6 channels,
Three phase motor control circuit
Serial Interface 3 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
2 channels
Clock synchronous
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT -CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt
Internal: 29 sources, External : 8 sources, Software: 4 sources, Prio rity level: 7 levels
Clock Generation Cir cui t 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscill a to r, PLL synthesiz e r
(*)Equipped with a built-in fe edback resistor.
Oscillation Stop
Detection Function Stop detection of main clock oscillation, re-oscillation detection function
Voltage Detection Circuit Available (option (5))Absent
Electric
Characteristics
Supply Voltage VCC1=3.0 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, VCC2=2.7V to
VCC1 (f(BCLK=10MHz)
VCC1=VCC2=4.0 to 5.5V
(f(BCLK=24MHz)
Power Consumption
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
8 mA (VCC1=VCC2=3V, f(BCLK)=10 MHz)
1.8
µ
A (VCC1=VCC2=3V, f(XCIN)=32kHz,
wait mode)
0.7
µ
A (VCC1=VCC2=3V, stop mode )
14 mA (VCC1=VCC2=5V, f(BCLK)=24MHz)
2.0
µ
A (VCC1=VCC2=5V, f(XCIN)=32kHz,
wait mode)
0.8
µ
A (VCC1=VCC2=5V, stop mode)
Flash memory
version
Program/Erase Supply Voltage
3.3±0.3 V or 5.0±0.5 V 5.0±0.5 V
Program and Erase
Endurance 100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature -20 to 85°C,
-40 to 85°C (3) T version : -40 to 85°C
V version : -40 to 125°C
Package 100-pin plastic mold QFP, LQFP
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 4 of 96
REJ03B0001-0241
NOTES:
1. I2C bus is a registered trademark of Koninklijke Philips Electronics N. V.
2. IEBus is a registered trademark of NEC Electronics Corporation.
3. See Table 1.8 and 1.9 Product Code for the progra m and erase endurance, and operating ambient
temperature.
In addition 1,000 times/10,000 times are under development as of Jul., 2005. Please inquire about a release
schedule.
4. All options are on request basis.
Table 1.3 Performance Outline of M16C/62P Group (M16C/62P, M16C/62PT)(80-pin version)
Item Performance
M16C/62P M16C/62PT(4)
CPU
Number of Basic Instructions
91 instructions
Minimum Instruction
Execution Time
41.7ns(f(BCLK)=24MHz, VCC1=3.3 to 5.5V)
100ns(f(BCLK)=10MHz, VCC1=2.7 to 5.5V) 41.7ns(f(BCLK)=24MHz, VCC1=4.0 to 5.5V)
Operating Mode Single-chip mode
Address Space 1 Mbyte
Memory Capacity See Tabl e 1. 4 t o 1.7 Produ c t Li st
Peripheral
Function Port Input/Output : 70 pins, Input : 1 pin
Multifunction Timer Timer A : 16 bits x 5 channels (Timer A1 and A2 are internal timer),
Timer B : 16 bits x 6 channels (Timer B1 is internal timer)
Serial Interface 2 channels
Clock synchronous, UART, I2C bus(1), IEBus(2)
1 channel
Clock synchronous, I2C bus(1), IEBus(2)
2 channels
Clock synchronous (1 channel is only transmission)
A/D Converter 10-bit A/D converter: 1 circuit, 26 channels
D/A Converter 8 bits x 2 channels
DMAC 2 channels
CRC Calculation Circuit CCITT -CRC
Watchdog Timer 15 bits x 1 channel (with prescaler)
Interrupt
Internal: 29 sources, External : 5 sources, Software: 4 sources, Prio rity level: 7 levels
Clock Generation Cir cui t 4 circuits
Main clock generation circuit (*), Subclock generation circuit (*),
On-chip oscill a to r, PLL synthesiz e r
(*)Equipped with a built-in fe edback resistor.
Oscillation Stop
Detection Function Stop detection of main clock oscillation, re-oscillation detection function
Voltage Detection Circuit Available (option (4))Absent
Electric
Characteristics
Supply Voltage
VCC1=3.0 to 5.5 V, (f(BCLK=24MHz)
VCC1=2.7 to 5.5 V, (f(BCLK=10MHz) VCC1=4.0 to 5.5V, (f(BCLK=24MHz)
Power Consumption
14 mA (VCC1=5V, f(BCLK)=24MHz)
8 mA (VCC1=3V, f(BCLK)=10MHz)
1.8
µ
A (VCC1=3V, f(XCIN)=32kHz,
wait mode)
0.7µA (VCC1=3V, stop mode)
14 mA (VCC1=5V, f(BCLK)=24MHz)
2.0
µ
A (VCC1=5V, f(XCIN)=32kHz,
wait mode)
0.8µA (VCC1=5V, stop mode)
Flash memory
version
Program/Erase Supply Voltage
3.3 ± 0.3V or 5.0 ± 0.5V 5.0 ± 0.5V
Program and Erase
Endurance 100 times (all area)
or 1,000 times (user ROM area without block A and block 1)
/ 10,000 times (block A, block 1) (3)
Operating Ambient Temperature -20 to 85°C,
-40 to 85°C (3) T version : -40 to 85°C
V version : -40 to 125°C
Package 80-pin plastic mold QFP
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 5 of 96
REJ03B0001-0241
1.3 Block Diagram
Figure 1.1 is a M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin version Block Diagram,
Figure 1.2 is a M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Bloc k Diagram.
Figure 1.1 M16C/62P Group (M16C/62P, M16C/62PT) 128-pin and 100-pin versi on Block Diagram
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
Watchdog timer
(15 bits)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
Memory
ROM (1)
RAM (2)
A/D converter
(10 bits X 8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O
(8 bits X 3 channels)
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL freque ncy synthesizer
On-chip oscillator
M16C/60 series16-bit CPU core
Port P0
8
Port P1
8
Port P2
8 8 8 8
Port P6
8
8
R0LR0H
R1H R1L
R2
R3
A0
A1
FB
SB
ISP
USP
INTB
CRC arithmetic circuit (CCITT )
(Polynom ia l : X16+X12+X5+1)
Multiplier
7 8 8
Port P10
Port P9
Port P8_5Port P8
Port P7
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. Ports P11 to P14 exist only in 128-pin version.
4. Use M16C/62PT on VCC1= VCC2.
Port P5
Port P4Port P3
Clock synchronous serial I/O
(8 bits X 2 channels)
PC
FLG
Timer (16-bi t)
Three-phase mo tor
control circui t
8 8 82
Port P11 Port P12Port P14 Port P13
(3)
<VCC2 ports>(4) <VCC1 ports>(4)
<VCC1 ports>(4)
<VCC2 ports>(4)<VCC1 ports>(4)
(3) (3) (3)
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 6 of 96
REJ03B0001-0241
Figure 1.2 M16C/62P Group (M16C/62P, M16C/62PT) 80-pin version Block Diagram
Timer (16 -bit)
Output (timer A): 5
Input (timer B): 6
Internal peripheral functions
Watchdog timer
(15 bit s)
DMAC
(2 channels)
D/A converter
(8 bits X 2 channels)
A/D converter
(10 bits X 8 channels
Expandable up to 26 channels)
UART or
clock synchronous serial I/O (2 channels)
UART (1 channel)
System clock
generation circuit
XIN-XOUT
XCIN-XCOUT
PLL frequency synthesizer
On-chip oscillator
M16C/60 series16-bit CPU core
Port P0
8
Port P2
8
Port P3
8
Port P4
4
Port P5
8
Port P6
8
CRC arithmetic circuit (C CITT )
(Polynom ial : X16+X12+X5+1)
Memory
4 7 7 8
Port P10
Port P9Port P8
Port P7 Port P8_5
ROM (1)
RAM (2)
NOTES :
1. ROM size depends on microcomputer type.
2. RAM size depends on microcomputer type.
3. To use a UART2, set the CRD bit in the U2C0 register to “1” (CTS/RTS function disabled).
4. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version.
Set the direction bits in these ports to “1” (output mode), and set the output data to0” (“L”) using the program.
Clock synchronous ser ial I/O
(8 bits X 2 channels)
R0LR0H
R1H R1L
R2
R3
SB
FLG
USP
ISP
INTB
PC
Multiplier
A0
A1
FB
(4)
(4)
(3)
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 7 of 96
REJ03B0001-0241
1.4 Product List
Table 1.4 to 1.7 list the pro duct list, Figure 1.3 sho ws the Type No., Memory Size, and Package, Table 1.8 lists the
Product Code of Fl ash Memory versi on and ROMl ess vers io n for M16C/62P, and Ta ble 1.9 lists t he Product Code
of Flash Memory version for M16C/62PT. Figure 1.4 shows the Marking Diagram of Flash Memory version and
ROM-less version for M16C/62P (Top View), and Figure 1.5 shows the Marking Diagram of Flash Memory
version for M16C/62PT (Top View) at the time of ROM order.
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
Table 1.4 Product List (1) (M16C/62P) As of Dec. 2005
Type No. ROM Capacity RAM Capacity Package Type (1) Remarks
M30622M6P-XXXFP 48 Kbytes 4 Kbytes PRQP0100JB-A Mask ROM version
M30622M6P-XXXGP PLQP0100KB-A
M30622M8P-XXXFP 64 Kbytes 4 Kbytes PRQP0100JB-A
M30622M8P-XXXGP PLQP0100KB-A
M30623M8P-XXXGP PRQP0080JA-A
M30622MAP-XXXFP 96 Kbytes 5 Kbytes PRQP0100JB-A
M30622MAP-XXXGP PLQP0100KB-A
M30623MAP-XXXGP PRQP0080JA-A
M30620MCP-XXXFP 128 Kbytes 10 Kbytes PRQP0100JB-A
M30620MCP-XXXGP PLQP0100KB-A
M30621MCP-XXXGP PRQP0080JA-A
M30622MEP-XXXFP 192 Kbytes 12 Kbytes PRQP0100JB-A
M30622MEP-XXXGP PLQP0100KB-A
M30623MEP-XXXGP PLQP0128KB-A
M30622MGP-XXXFP 256 Kbytes 12 Kbytes PRQP0100JB-A
M30622MGP-XXXGP PLQP0100KB-A
M30623MGP-XXXGP PLQP0128KB-A
M30624MGP-XXXFP 20 Kbytes PRQP0100JB-A
M30624MGP-XXXGP PLQP0100KB-A
M30625MGP-XXXGP PLQP0128KB-A
M30622MWP-XXXFP 320 Kbytes 16 Kbytes PRQP0100JB-A
M30622MWP-XXXGP PLQP0100KB-A
M30623MWP-XXXGP PLQP0128KB-A
M30624MWP-XXXFP 24 Kbytes PRQP0100JB-A
M30624MWP-XXXGP PLQP0100KB-A
M30625MWP-XXXGP PLQP0128KB-A
M30626MWP-XXXFP 31 Kbytes PRQP0100JB-A
M30626MWP-XXXGP PLQP0100KB-A
M30627MWP-XXXGP PLQP0128KB-A
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 8 of 96
REJ03B0001-0241
(D): Under development
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
3. Please use M3062LFGPFP an d M3062LFGPGP for your new system instead of M3062 4FGPFP
and M30624FGPGP. The M16C/62P Group (M16C/62P, M16C/62PT) hardware manual is still good
for M30624FGPFP and M30624FGPGP.
Table 1.5 Product List (2) (M16C/62P) As of Dec. 2005
Type No. ROM Capacity RAM
Capacity Package Type (1) Remarks
M30622MHP-XXXFP 384 Kbytes 16 Kbytes PRQP0100JB-A Mask ROM version
M30622MHP-XXXGP PLQP0100KB-A
M30623MHP-XXXGP PLQP0128KB-A
M30624MHP-XXXFP 24 Kbytes PRQP0100JB-A
M30624MHP-XXXGP PLQP0100KB-A
M30625MHP-XXXGP PLQP0128KB-A
M30626MHP-XXXFP 31 Kbytes PRQP0100JB-A
M30626MHP-XXXGP PLQP0100KB-A
M30627MHP-XXXGP PLQP0128KB-A
M30626MJP-XXXFP (D) 512 Kbytes 31 Kbytes PRQP0100JB-A
M30626MJP-XXXGP (D) PLQP0100KB-A
M30627MJP-XXXGP (D) PLQP0128KB-A
M30622F8PF P 64K+4 Kbytes 4 Kbytes PRQP0100JB-A Flash memor y
version (2)
M30622F8PGP PLQP0100KB-A
M30623F8PGP PRQP0080JA-A
M30620FCPFP 128K+4 Kbytes 10 Kbytes PRQP0100JB-A
M30620FCPGP PLQP0100KB-A
M30621FCPGP PRQP0080JA-A
M3062LFGPFP(3) (D) 256K+4 Kbytes 20 Kbytes PRQP0100JB-A
M3062LFGPGP(3) (D) PLQP0100KB-A
M30625FGPGP PLQP0128KB-A
M30626FHPFP 384K+4 Kbytes 31 Kbytes PRQP0100JB-A
M30626FHPGP PLQP0100KB-A
M30627FHPGP PLQP0128KB-A
M30626FJPFP 512K+4 Kbytes 31 Kbytes PRQP0100JB-A
M30626FJPGP PLQP0100KB-A
M30627FJPGP PLQP0128KB-A
M30622SPFP 4 Kbytes PRQP 01 00 JB- A ROM-less version
M30622SPGP PLQP0100KB-A
M30620SPFP 10 Kbytes PRQP0100JB-A
M30620SPGP PLQP0100KB-A
M30624SPFP (D) 20 Kbytes PRQP0100JB-A
M30624SPGP (D) PLQP0100KB-A
M30626SPFP (D) 31 Kbytes PRQP0100JB-A
M30626SPGP (D) PLQP0100KB-A
M30624FGPFP 256K+4 Kbytes 20 Kbytes PRQP0100JB-A Flash memory version
M30624FGPGP PLQP0100KB-A
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 9 of 96
REJ03B0001-0241
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Table 1.6 Product List (3) (T version (M16C/62PT)) As of Dec. 2005
Type No. ROM Capacity RAM
Capacity Packag e T ype (1) Remarks
M3062CM6T-XXXFP (D) 48 Kbytes 4 Kbytes PRQP0100JB-A Mask ROM
version T Version
(High reliability
85°C version)
M3062CM6T-XXXGP (D) PLQP0100KB-A
M3062EM6T-XXXGP (P) PRQP0080JA-A
M3062CM8T-XXXFP (D) 64 Kbytes 4 Kbytes PRQP0100JB-A
M3062CM8T-XXXGP (D) PLQP0100KB-A
M3062EM8T-XXXGP (P) PRQP0080JA-A
M3062CMAT-XXXFP (D) 96 Kbytes 5 Kbytes PRQP0100JB-A
M3062CMAT-XXXGP (D) PLQP0100KB-A
M3062EMAT-XXXGP (P) PRQP0080JA-A
M3062AMCT-XXXFP (D) 128 Kbytes 10 Kbytes PRQP0100JB-A
M3062AMCT-XXXGP (D) PLQP0100KB-A
M3062BMCT-XXXGP (P) PRQP0080JA-A
M3062CF8TFP (D) 64 K+4 Kbytes 4 Kbytes PRQP0100JB-A Flash
memory
version (2)
M3062CF8TGP PLQP0100KB-A
M3062AFCTFP (D) 128K+4 Kbytes 10 Kbytes PRQP0 100JB-A
M3062AFCTGP (D) PLQP0100KB-A
M3062BFCTGP (P) PRQP0080JA-A
M3062JFHTFP (D) 384K+4 Kbytes 31 Kbytes PRQP0 100JB-A
M3062JFHTGP (D) PLQP0100KB-A
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 10 of 96
REJ03B0001-0241
(D): Under development
(P): Under planning
NOTES:
1. The old package type numbers of each package type are as follows.
PLQP0128KB-A : 128P6Q-A,
PRQP0100JB-A : 100P6S-A,
PLQP0100KB-A : 100P6Q-A,
PRQP0080JA-A : 80P6S-A
2. In the flash memory version, there is 4K bytes area (block A).
Table 1.7 Product List (4) (V version (M 16C/62PT)) As of Dec. 2005
Type No. ROM Capacity RAM
Capacity Package Type(1) Remarks
M3062CM6V-XXXFP (P) 48 Kbytes 4 Kbytes PRQP0100JB-A Mask ROM
version V Version
(High reliability
125°C version)
M3062CM6V-XXXGP (P) PLQP0100KB-A
M3062EM6V-XXXGP (P) PRQP0080JA-A
M3062CM8V-XXXFP (P) 64 Kbytes 4 Kbytes PRQP0100JB-A
M3062CM8V-XXXGP (P) PLQP0100KB-A
M3062EM8V-XXXGP (P) PRQP0080JA-A
M3062CMAV-XXXFP (P) 96 Kbytes 5 Kbytes PRQP0100JB-A
M3062CMAV-XXXGP (P) PLQP0100KB-A
M3062EMAV-XXXGP (P) PRQP0080JA-A
M3062AMCV-XXXFP (D) 128 Kbytes 10 Kbytes PRQP0100JB-A
M3062AMCV-XXXGP (D) PLQP0100KB-A
M3062BMCV-XXXGP (P) PRQP0080JA-A
M3062AFCVFP (D) 128K+4 Kbytes 10 Kbytes PRQP0100JB- A Flash
memory
version (2)
M3062AFCVGP (D) PLQP0100KB-A
M3062BFCVGP (P) PRQP0080JA-A
M3062JFHVFP (P) 384K+4 Kbytes 31 Kbytes PRQP0 100JB-A
M3062JFHVGP (P) PLQP0100KB-A
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 11 of 96
REJ03B0001-0241
Figure 1.3 Type No., Memory Size, and Package
Package type:
FP : Package PRQP0100JB-A (100P6S-A)
GP : Package PRQP0080JA-A (80P6S-A),
PLQP0100KB-A (100P6Q-A),
PLQP0128KB-A (128P6Q-A),
ROM No.
Omitted for flash memory version and
ROMless version
Memory type:
M: Mask ROM version
F: Flash memory version
S: ROM-less version
Type No. M 3 0 6 2 6 M H P - X X X F P
M16C/62(P) Group
M16C Family
Shows RAM capacity, pin count, etc
Numeric, Alphabet (L) : M16C/62P
Alphabet (L is excluded.) : M16C/62PT
ROM capacity:
6: 48 Kbytes
8: 64 Kbytes
A: 96 Kbytes
C: 128 Kbytes
E: 192 Kbytes
G: 256 Kbytes
W: 320 Kbytes
H: 384 Kbytes
J: 512 Kbytes
Classification
P : M16C/62P
T : T version (M16C/62PT)
V : V version (M16C/62PT)
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 12 of 96
REJ03B0001-0241
Figure 1.4 Marking Diagram of Flash Memory version and ROM-less version for M16C/62P (Top View)
Table 1.8 Product Code of Flash Memory version and ROMless version for M16C/62P
Product
Code Package
Internal ROM
(User ROM Area Without Block A,
Block 1)
Internal ROM
(Block A, Block 1) Operating
Ambient
Temperature
Program
and Erase
Endurance
Temperature
Range
Program
and Erase
Endurance
Temperature
Range
Flash memory
Version D3 Lead-
included 100 0°C to 60°C 100 0°C to 60°C-40°C to 85°C
D5 -20°C to 85°C
D7 1,000 10,000 -40°C to 85°C-40°C to 85°C
D9 -20°C to 85°C-20°C to 85°C
U3 Lead-free 100 100 0°C to 60°C-40°C to 85°C
U5 -20°C to 85°C
U7 1,000 10,000 -40°C to 85°C-40°C to 85°C
U9 -20°C to 85°C-20°C to 85°C
ROM-less
version D3 Lead-
included −− -40°C to 85°C
D5 -20°C to 85°C
U3 Lead-free −− -40°C to 85°C
U5 -20°C to 85°C
M1 6 C
M30626FHPFP
BD5
XXXXXXX
Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Chip version and product code
B : Shows chip ver sion.
Henceforth, whenever it changes a version, it continues with B, C, and D.
D5 : Shows Product code. (See table 1.8 Product Code)
Date code seven digits
The product without marking of chip version of the flash memory version and the ROMless version
corresponds to the chip version “A”.
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 13 of 96
REJ03B0001-0241
Figure 1.5 Marking Diagram of Flash Memory version for M16C/62PT (Top View)
Table 1.9 Product Code of Flash Memory version for M16C/62PT
Product
Code Package
Internal ROM
(User ROM Area
Without Block A, Block 1)
Internal ROM
(Block A, Block 1) Operating
Ambient
Temperature
Program
and Erase
Endurance
Temperature
Range
Program
and Erase
Endurance
Temperature
Range
Flash
memory
Version
T
Version
B Lead-
included 100 0°C to 60°C1000°C to 60°C-40°C to 85°C
V
Version
-40°C to 125°C
T
Version
B7 1,000 10,000 -40°C to 85°C-40°C to 85°C
V
Version
-40°C to 125°C-40°C to 125°C
T
Version
U Lead-free 100 100 0°C to 60°C-40°C to 85°C
V
Version
-40°C to 125°C
T
Version
U7 1,000 10,000 -40°C to 85°C-40°C to 85°C
V
Version
-40°C to 125°C-40°C to 125°C
M1 6 C
M3062 J FHT FP
YYY XXXXXXX Type No. (See Figure 1.3 Type No., Memory Size, and Package)
Date code seven digits
NOTES:
1. : Blank
Product code. (See table 1.9 Product Code)
” : Product code “B”
P B F ” : Product code “U
B 7 : Product code “B”
U 7 ” : Product code “U7”
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 14 of 96
REJ03B0001-0241
1.5 Pin Configuration
Figures 1.6 to 1.9 show the Pin Configuration (Top View).
Figure 1.6 Pin Configuration (Top View)
1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930
737475767778798081828384858687888990919293949596979899
100
101102
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128 39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
104
105
106
107
108
31 32 33 34 35 36 37
66676869707172
38
65
64
103
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P1_0/D8
P1_1/D9
P1_2/D10
AVSS
VCC1
XIN
XOUT
VSS
RESET
CNVSS
P8_7/XCIN
P8_6/XCOUT
BYTE
P7_4/TA2OUT/W
P7_6/TA3OUT
P5_6/ALE
P7_7/TA3IN
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
P5_7/RDY/CLKOUT
P4_7/CS3
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P10_0/AN0
P10_1/AN1
P10_2/AN2
P10_3/AN3
P9_3/DA0/TB3IN
P9_4/DA1/TB4IN
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_1/TB1IN/SIN3
P9_2/TB2IN/SOUT3
P8_0/TA4OUT/U
P6_0/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P8_2/INT0
P8_3/INT1
P8_5/NMI
P4_5/CS1
P4_6/CS2
P4_4/CS0
P5_0/WRL/WR
P5_1/WRH/BHE
P9_0/TB0IN/CLK3
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/TA0OUT(1)
P8_4/INT2/ZP
P8_1/TA4IN/U
P7_3/CTS2/RTS2/TA1IN/V
P7_5/TA2IN/W
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
VREF
AVCC
P9_7/ADTRG/SIN4
P14_1
P14_0
P13_7
P13_6
P13_5
P13_4
P1_3/D11
P1_4/D12
P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
P3_0/A8(/-/D7)
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
VCC2
VSS
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P12_4
P12_3
P11_3
P11_2
P11_1
P11_0
VCC1
VSS
P13_0
P13_1
P13_2
P13_3
P12_5
P12_6
P12_7
P11_4
P11_5
P11_6
P11_7
P12_2
P12_1
P12_0
<VCC2> (2)
<VCC1> (2)
M16C/62P Group (M16C/62P)
Package : PLQP0128KB-A (128P6Q-A)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
PIN CONFIGURATION (top view)
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 15 of 96
REJ03B0001-0241
Table 1.10 Pin Characteristics for 128-Pin Package (1)
Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin
1VREF
2AVCC
3 P9_7 SIN4 ADTRG
4 P9_6 SOUT4 ANEX1
5 P9_5 CLK4 ANEX0
6P9_4 TB4IN DA1
7P9_3 TB3IN DA0
8 P9_2 TB2IN SOUT3
9 P9_1 TB1IN SIN3
10 P9_0 TB0IN CLK3
11 P14_1
12 P14_0
13 BYTE
14 CNVSS
15 XCIN P8_7
16 XCOUT P8_6
17 RESET
18 XOUT
19 VSS
20 XIN
21 VCC1
22 P8_5 NMI
23 P8_4 INT2 ZP
24 P8_3 INT1
25 P8_2 INT0
26 P8_1 TA4IN/U
27 P8_0 TA4OUT/U
28 P7_7 TA3IN
29 P7_6 TA3OUT
30 P7_5 TA2IN/W
31 P7_4 TA2OUT/W
32 P7_3 TA1IN/V CTS2/RTS2
33 P7_2 TA1OUT/V CLK2
34 P7_1 TA0IN/TB5IN RXD2/SCL2
35 P7_0 TA0OUT TXD2/SDA2
36 P6_7 TXD1/SDA1
37 VCC1
38 P6_6 RXD1/SCL1
39 VSS
40 P6_5 CLK1
41 P6_4 CTS1/RTS1/CTS0/CLKS1
42 P6_3 TXD0/SDA0
43 P6_2 RXD0/SCL0
44 P6_1 CLK0
45 P6_0 CTS0/RTS0
46 P13_7
47 P13_6
48 P13_5
49 P13_4
50 P5_7 RDY/CLKOUT
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 16 of 96
REJ03B0001-0241
Table 1.11 Pin Character istics for 128-Pin Package (2 )
Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin
51 P5_6 ALE
52 P5_5 HOLD
53 P5_4 HLDA
54 P13_3
55 P13_2
56 P13_1
57 P13_0
58 P5_3 BCLK
59 P5_2 RD
60 P5_1 WRH/BHE
61 P5_0 WRL/WR
62 P12_7
63 P12_6
64 P12_5
65 P4_7 CS3
66 P4_6 CS2
67 P4_5 CS1
68 P4_4 CS0
69 P4_3 A19
70 P4_2 A18
71 P4_1 A17
72 P4_0 A16
73 P3_7 A15
74 P3_6 A14
75 P3_5 A13
76 P3_4 A12
77 P3_3 A11
78 P3_2 A10
79 P3_1 A9
80 P12_4
81 P12_3
82 P12_2
83 P12_1
84 P12_0
85 VCC2
86 P3_0 A8(/-/D7)
87 VSS
88 P2_7 AN2_7 A7(/D7/D6)
89 P2_6 AN2_6 A6(/D6/D5)
90 P2_5 AN2_5 A5(/D5/D4)
91 P2_4 AN2_4 A4(/D4/D3)
92 P2_3 AN2_3 A3(/D3/D2)
93 P2_2 AN2_2 A2(/D2/D1)
94 P2_1 AN2_1 A1(/D1/D0)
95 P2_0 AN2_0 A0(/D0/-)
96 P1_7 INT5 D15
97 P1_6 INT4 D14
98 P1_5 INT3 D13
99 P1_4 D12
100 P1_3 D11
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 17 of 96
REJ03B0001-0241
Table 1.12 Pin Characteristics for 128-Pin Package (3)
Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin
101 P1_2 D10
102 P1_1 D9
103 P1_0 D8
104 P0_7 AN0_7 D7
105 P0_6 AN0_6 D6
106 P0_5 AN0_5 D5
107 P0_4 AN0_4 D4
108 P0_3 AN0_3 D3
109 P0_2 AN0_2 D2
110 P0_1 AN0_1 D1
111 P0_0 AN0_0 D0
112 P11_7
113 P11_6
114 P11_5
115 P11_4
116 P11_3
117 P11_2
118 P11_1
119 P11_0
120 P10_7 KI3 AN7
121 P10_6 KI2 AN6
122 P10_5 KI1 AN5
123 P10_4 KI0 AN4
124 P10_3 AN3
125 P10_2 AN2
126 P10_1 AN1
127 AVSS
128 P10_0 AN0
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 18 of 96
REJ03B0001-0241
Figure 1.7 Pin Configuration (Top View)
1 2 3 4 5 6 7 8 9101112131415161718192021222324252627282930
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
515253545556575859606162636465666768697071727374757677787980
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P1_0/D8
P1_1/D9
P1_2/D10
P1_3/D11
P1_4/D12
VREF
AVSS
VCC1
XIN
XOUT
VSS
RESET
CNVSS
P8_7/XCIN
P8_6/XCOUT
BYTE P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
P3_0/A8(/-/D7)
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P7_4/TA2OUT/W
P7_6/TA3OUT
P5_6/ALE
P7_7/TA3IN
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
VCC2
VSS
P5_7/RDY/CLKOUT
P4_5/CS1
P4_6/CS2
P4_7/CS3
AVCC
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P10_0/AN0
P10_1/AN1
P10_2/AN2
P10_3/AN3
P9_3/DA0/TB3IN
P9_4/DA1/TB4IN
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_1/TB1IN/SIN3
P9_2/TB2IN/SOUT3
P8_0/TA4OUT/U
P6_0/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P7_2/CLK2/TA1OUT/V
P8_2/INT0
P7_1/RXD2/SCL2/TA0IN/TB5IN(1)
P8_3/INT1
P8_5/NMI
P9_7/ADTRG/SIN4
P4_4/CS0
P5_0/WRL/WR
P5_1/WRH/BHE
P9_0/TB0IN/CLK3
P7_0/TXD2/SDA2/TA0OUT(1)
P8_4/INT2/ZP
P8_1/TA4IN/U
P7_3/CTS2/RTS2/TA1IN/V
P7_5/TA2IN/W
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
<VCC2> (2)
<VCC1> (2)
M16C/62P Group
(M16C/62P, M16C/62PT)
Package : PRQP0100JB-A (100P6S-A)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
PIN CONFIGURATION (top view)
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 19 of 96
REJ03B0001-0241
Figure 1.8 Pin Configuration (Top View)
12345678910111213141516171819202122232425
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
515253545556
57585960616263646566676869707172737475
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
P0_0/AN0_0/D0
P0_1/AN0_1/D1
P0_2/AN0_2/D2
P0_3/AN0_3/D3
P0_4/AN0_4/D4
P0_5/AN0_5/D5
P0_6/AN0_6/D6
P0_7/AN0_7/D7
P1_0/D8
P1_1/D9
P1_2/D10
P1_3/D11
P1_4/D12
VREF
AVSS
VCC1
XIN
XOUT
VSS
RESET
CNVSS
P8_7/XCIN
P8_6/XCOUT
BYTE P2_0/AN2_0/A0(/D0/-)
P2_1/AN2_1/A1(/D1/D0)
P2_2/AN2_2/A2(/D2/D1)
P2_3/AN2_3/A3(/D3/D2)
P2_4/AN2_4/A4(/D4/D3)
P2_5/AN2_5/A5(/D5/D4)
P2_6/AN2_6/A6(/D6/D5)
P2_7/AN2_7/A7(/D7/D6)
P3_0/A8(/-/D7)
P3_1/A9
P3_2/A10
P3_3/A11
P3_4/A12
P3_5/A13
P3_6/A14
P3_7/A15
P4_0/A16
P4_1/A17
P4_2/A18
P4_3/A19
P7_4/TA2OUT/W
P7_6/TA3OUT
P5_6/ALE
P7_7/TA3IN
P5_5/HOLD
P5_4/HLDA
P5_3/BCLK
P5_2/RD
VCC2
VSS
P5_7/RDY/CLKOUT
P4_5/CS1
P4_6/CS2
P4_7/CS3
AVCC
P6_3/TXD0/SDA0
P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P6_1/CLK0
P6_2/RXD0/SCL0
P10_0/AN0
P10_1/AN1
P10_2/AN2
P10_3/AN3
P9_3/DA0/TB3IN
P9_4/DA1/TB4IN
P9_5/ANEX0/CLK4
P9_6/ANEX1/SOUT4
P9_1/TB1IN/SIN3
P9_2/TB2IN/SOUT3
P8_0/TA4OUT/U
P6_0/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P8_2/INT0
P8_3/INT1
P8_5/NMI
P9_7/ADTRG/SIN4
P4_4/CS0
P5_0/WRL/WR
P5_1/WRH/BHE
P9_0/TB0IN/CLK3
P8_4/INT2/ZP
P7_2/CLK2/TA1OUT/V
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/TA0OUT (1)
P7_5/TA2IN/W
P7_3/CTS2/RTS2/TA1IN/V
P1_5/D13/INT3
P1_6/D14/INT4
P1_7/D15/INT5
P10_7/AN7/KI3
P10_6/AN6/KI2
P10_5/AN5/KI1
P10_4/AN4/KI0
P8_1/TA4IN/U
<VCC2> (2)
<VCC1> (2)
Package : PLQP0100KB-A (100P6Q-A)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
2. Use the M16C/62PT on VCC1=VCC2.
PIN CONFIGURATION (top view)
M16C/62P Group
(M16C/62P, M16C/62PT)
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 20 of 96
REJ03B0001-0241
Table 1.13 Pin Characteristics for 100-Pin Package (1)
Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin
FP GP
1 99 P9_6 SOUT4 ANEX1
2 100 P9_5 CLK4 ANEX0
31 P9_4 TB4IN DA1
4 2 P9_3 TB3IN DA0
5 3 P9_2 TB2IN SOUT3
6 4 P9_1 TB1IN SIN3
7 5 P9_0 TB0IN CLK3
86BYTE
9 7 CNVSS
10 8 XCIN P8_7
11 9 XCOUT P8_6
12 10 RESET
13 11 XOUT
14 12 VSS
15 13 XIN
16 14 VCC1
17 15 P8_5 NMI
18 16 P8_4 INT2 ZP
19 17 P8_3 INT1
20 18 P8_2 INT0
21 19 P8_1 TA4IN/U
22 20 P8_0 TA4OUT/U
23 21 P7_7 TA3IN
24 22 P7_6 TA3OUT
25 23 P7_5 TA2IN/W
26 24 P7_4 TA2OUT/W
27 25 P7_3 TA1IN/V CTS2/RTS2
28 26 P7_2 TA1OUT/V CLK2
29 27 P7_1 TA0IN/TB5IN RXD2/SCL2
30 28 P7_0 TA0OUT TXD2/SDA2
31 29 P6_7 TXD1/SDA1
32 30 P6_6 RXD1/SCL1
33 31 P6_5 CLK1
34 32 P6_4 CTS1/RTS1/CTS0/CLKS1
35 33 P6_3 TXD0/SDA0
36 34 P6_2 RXD0/SCL0
37 35 P6_1 CLK0
38 36 P6_0 CTS0/RTS0
39 37 P5_7 RDY/CLKOUT
40 38 P5_6 ALE
41 39 P5_5 HOLD
42 40 P5_4 HLAD
43 41 P5_3 BCLK
44 42 P5_2 RD
45 43 P5_1 WRH/BHE
46 44 P5_0 WRL/WR
47 45 P4_7 CS3
48 46 P4_6 CS2
49 47 P4_5 CS1
50 48 P4_4 CS0
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 21 of 96
REJ03B0001-0241
Table 1.14 Pin Characteristics for 100-Pin Package (2)
Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin
FP GP
51 49 P4_3 A19
52 50 P4_2 A18
53 51 P4_1 A17
54 52 P4_0 A16
55 53 P3_7 A15
56 54 P3_6 A14
57 55 P3_5 A13
58 56 P3_4 A12
59 57 P3_3 A11
60 58 P3_2 A10
61 59 P3_1 A9
62 60 VCC2
63 61 P3_0 A8(/-/D7)
64 62 VSS
65 63 P2_7 AN2_7 A7(/D7/D6)
66 64 P2_6 AN2_6 A6(/D6/D5)
67 65 P2_5 AN2_5 A5(/D5/D4)
68 66 P2_4 AN2_4 A4(/D4/D3)
69 67 P2_3 AN2_3 A3(/D3/D2)
70 68 P2_2 AN2_2 A2(/D2/D1)
71 69 P2_1 AN2_1 A1(/D1/D0)
72 70 P2_0 AN2_0 A0(/D0/-)
73 71 P1_7 INT5 D15
74 72 P1_6 INT4 D14
75 73 P1_5 INT3 D13
76 74 P1_4 D12
77 75 P1_3 D11
78 76 P1_2 D10
79 77 P1_1 D9
80 78 P1_0 D8
81 79 P0_7 AN0_7 D7
82 80 P0_6 AN0_6 D6
83 81 P0_5 AN0_5 D5
84 82 P0_4 AN0_4 D4
85 83 P0_3 AN0_3 D3
86 84 P0_2 AN0_2 D2
87 85 P0_1 AN0_1 D1
88 86 P0_0 AN0_0 D0
89 87 P10_7 KI3 AN7
90 88 P10_6 KI2 AN6
91 89 P10_5 KI1 AN5
92 90 P10_4 KI0 AN4
93 91 P10_3 AN3
94 92 P10_2 AN2
95 93 P10_1 AN1
96 94 AVSS
97 95 P10_0 AN0
98 96 VREF
99 97 AVCC
100 98 P9_7 SIN4 ADTRG
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 22 of 96
REJ03B0001-0241
Figure 1.9 Pin Configuration (Top View)
44454647484950515253545557585960
61
62
63
64
65
66
67
68
69
70
71
72
73
74
56
P4_2
P3_0
P3_1
P3_2
P3_3
P3_4
P3_5
P3_6
P3_7
P4_0
P4_1
P0_0/AN0_0
P0_1/AN0_1
P0_2/AN0_2
P0_3/AN0_3
P0_4/AN0_4
P0_5/AN0_5
P0_6/AN0_6
P0_7/AN0_7
P10_1/AN1
P10_2/AN2
P10_3/AN3
P10_4/AN4/KI0
P10_5/AN5/KI1
P10_6/AN6/KI2
P10_7/AN7/KI3
P2_0/AN2_0
P2_1/AN2_1
P2_2/AN2_2
P2_4/AN2_4
P2_5/AN2_5
P2_6/AN2_6
P2_7/AN2_7
P2_3/AN2_3
M16C/62P Group
(M16C/62P, M16C/62PT)
Package : PRQP0080JA-A (80P6S-A)
NOTES:
1. P7_0 and P7_1 are N channel open-drain output pins.
PIN CONFIGURATION (top view)
1 2 3 4 5 6 7 8 9 1011121314151617
75
76
77
78
79
80
VCC1
XIN
XOUT
VSS
RESET
CNVSS(BYTE)
P8_7/XCIN
P8_6/XCOUT
P9_3/DA0/TB3IN
P9_4/DA1/TB4IN
P9_5/ANEX0/CLK4
P8_2/INT0
P8_3/INT1
P8_1/TA4IN
P8_4/INT2/ZP
P8_0/TA4OUT
P8_5/NMI
VREF
AVSS
AVCC
P10_0/AN0
P9_6/ANEX1/SOUT4
P9_0/TB0IN/CLK3
P9_7/ADTRG/SIN4
P9_2/TB2IN/SOUT3
18 19 20
21
22
23
24
25
26 P6_5/CLK1
P6_6/RXD1/SCL1
P6_7/TXD1/SDA1
P7_1/RXD2/SCL2/TA0IN/TB5IN (1)
P7_0/TXD2/SDA2/TA0OUT (1)
P7_6/TA3OUT
P7_7/TA3IN
27
28
29
30
31
32
33
34
35
36
37
38
39
40
414243
P4_3
P5_6
P5_5
P5_4
P5_3
P5_2
P5_7/CLKOUT
P6_3/TXD0/SDA0
P6_1/CLK0
P6_2/RXD0/SCL0
P6_0/CTS0/RTS0
P6_4/CTS1/RTS1/CTS0/CLKS1
P5_0
P5_1
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 23 of 96
REJ03B0001-0241
Table 1.15 Pin Characteristics for 80-Pin Package (1)
Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin
1 P9_5 CLK4 ANEX0
2P9_4 TB4IN DA1
3P9_3 TB3IN DA0
4 P9_2 TB2IN SOUT3
5 P9_0 TB0IN CLK3
6CNVSS
(BYTE)
7XCIN P8_7
8XCOUTP8_6
9RESET
10 XOUT
11 VSS
12 XIN
13 VCC1
14 P8_5 NMI
15 P8_4 INT2 ZP
16 P8_3 INT1
17 P8_2 INT0
18 P8_1 TA4IN
19 P8_0 TA4OUT
20 P7_7 TA3IN
21 P7_6 TA3OUT
22 P7_1 TA0IN/TB5IN RXD2/SCL2
23 P7_0 TA0OUT TXD2/SDA2
24 P6_7 TXD1/SDA1
25 P6_6 RXD1/SCL1
26 P6_5 CLK1
27 P6_4 CTS1/RTS1/CTS0/CLKS1
28 P6_3 TXD0/SDA0
29 P6_2 RXD0/SCL0
30 P6_1 CLK0
31 P6_0 CTS0/RTS0
32 P5_7 CLKOUT
33 P5_6
34 P5_5
35 P5_4
36 P5_3
37 P5_2
38 P5_1
39 P5_0
40 P4_3
41 P4_2
42 P4_1
43 P4_0
44 P3_7
45 P3_6
46 P3_5
47 P3_4
48 P3_3
49 P3_2
50 P3_1
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 24 of 96
REJ03B0001-0241
Table 1.16 Pin Characteristics for 80-Pin Package (2)
Pin No. Control Pin Port Interrupt Pin Timer Pin UART Pin Analog Pin Bus Control Pin
51 P3_0
52 P2_7 AN2_7
53 P2_6 AN2_6
54 P2_5 AN2_5
55 P2_4 AN2_4
56 P2_3 AN2_3
57 P2_2 AN2_2
58 P2_1 AN2_1
59 P2_0 AN2_0
60 P0_7 AN0_7
61 P0_6 AN0_6
62 P0_5 AN0_5
63 P0_4 AN0_4
64 P0_3 AN0_3
65 P0_2 AN0_2
66 P0_1 AN0_1
67 P0_0 AN0_0
68 P10_7 KI3 AN7
69 P10_6 KI2 AN6
70 P10_5 KI1 AN5
71 P10_4 KI0 AN4
72 P10_3 AN3
73 P10_2 AN2
74 P10_1 AN1
75 AVSS
76 P10_0 AN0
77 VREF
78 AVCC
79 P9_7 SIN4 ADTRG
80 P9_6 SOUT4 ANEX1
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 25 of 96
REJ03B0001-0241
1.6 Pin Description
I : Input O : Output I/O : Input and output
Power Supply : Power supplies which relate to the external bus pins are separated as VCC2, thus they can be
interfaced using the different voltage as VCC1.
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 and VCC2 pins. Also the apply condition is that VCC1 = VCC2.
3. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
4. Bus control pins in M16C/62PT cannot be used.
Table 1.17 Pin Description (100-pin and 128-pin Version) (1)
Signal Name Pin Name I/O
Type Power
Supply(3) Description
Power supply
input
VCC1,VCC2
VSS IApply 2.7 to 5.5 V to the VCC1 and VCC2 pins and 0 V to the VSS
pin. The VCC apply condition is that VCC1 VCC2. (1, 2)
Analog power
supply input AVCC
AVSS I VCC1 Applies the power supply for the A/D converter. Connect the AVCC
pin to VCC1. Connect the AVSS pin to VSS.
Reset input RESET IVCC1
The microcomputer is in a reset state when applying “L” to the this pin.
CNVSS CNVSS I VCC1 Switches processor mode. Connect this pin to VSS to when after
a reset to start up in single-chip mode. Connect this pin to VCC1 to
start up in microprocessor mode.
External data
bus width
select input
BYTE I VCC1 Switches the data bus in external memory space. The data bus is
16 bits long when the this pin is held "L" and 8 bits long when the
this pin is held "H". Set it to either one. Connect this pin to VSS
when an single-chip mode.
Bus control
pins (4) D0 to D7 I/O VCC2 Inputs and outputs data (D0 to D7) when these pins are set as the
separate bus.
D8 to D15 I/O VCC2 Inputs and outputs data (D8 to D15) when external 16-bit data bus
is set as the separate bus.
A0 to A19 O VCC2 Output address bits (A0 to A19).
A0/D0 to
A7/D7 I/O VCC2
Input and output data (D0 to D7) and output address bits (A0 to A7) by
timesharing when external 8-bit data bus are set as the multiplexed bus.
A1/D0 to
A8/D7 I/O VCC2 Input and output data (D0 to D7) and output address bits (A1 to A8)
by timesharing when external 16-bit data bus are set as the
multiplexed bus.
CS0 to CS3 O VCC2 Output CS0 to CS3 signals. CS0 to CS3 are chip-select signals to
specify an external space.
WRL/WR
WRH/BHE
RD
O VCC2 Output WRL, WRH, (WR, BHE), RD signals. WRL and WRH or
BHE and WR can be switched by program.
WRL, WRH and RD are selected
The WRL signal becomes "L" by writing data to an even address in
an external memory space.
The WRH signal becomes "L" by writing data to an odd address in
an external memory space.
The RD pin signal becomes "L" by reading data in an externa l
memory space.
WR, BHE and RD are selected
The WR signal becomes "L" by writing d ata in an external memory space.
The RD signal becomes "L" by reading data in an external memory space.
The BHE signal becomes "L" by accessing an odd address.
Select WR, BHE and RD for an external 8-bit data bus.
ALE O VCC2 ALE is a signal to latch the address.
HOLD I VCC2 While the HOLD pin is held "L", the microcomputer is placed in a
hold state.
HLDA O VCC2 In a hold state, HLDA outputs a "L" signal.
RDY I VCC2 While applying a "L" signal to the RDY pin, the microcomputer is
placed in a wait state.
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 26 of 96
REJ03B0001-0241
I : Input O : Output I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. This pin function in M16C/62PT cannot be used.
3. Ask the oscillator maker the oscillation characteristic.
Table 1.18 Pin Description (100-pin and 128-pin Version) (2)
Signal Name Pin Name I/O
Type Power
Supply(1) Description
Main clock
input XIN I VCC1 I/O pins for the main clock generation ci rcuit. Connect a ceramic
resonator or crystal oscillator be tween XIN and XOUT (3). To use
the external clock, input the clock from XIN and leave XOUT open.
Main clock
output XOUT O VCC1
Sub clock input XCIN I VCC1 I/O pins for a sub clock oscillation circuit. Connect a crystal
oscillator between XCIN and XCOUT (3). To use the external clock,
input the clock from XCIN and leave XCOUT open.
Sub clock
output XCOUT O VCC1
BCLK output (2) BCLK O VCC2 Outputs the BCLK signal.
Clock output CLKOUT O VCC2 The clock of the same cycle as fC, f8, or f32 is outputted.
INT interrupt
input INT0 to INT2 IVCC1 Input pins for the INT interrupt.
NT3 to INT5 IVCC2
NMI interrupt
input NMI IVCC1 Input pin for the NMI interrupt. Pin states can be read by the P8_5
bit in the P8 register.
Key input
interrupt input KI0 to KI3 I VCC1 Input pins for the key input interrupt.
Timer A TA0OUT to
TA4OUT I/O VCC1 These are timer A0 to timer A4 I/O pins. (however, output of
TA0OUT for the N-channel open drain output.)
TA0IN to
TA4IN I VCC1 These are timer A0 to timer A4 input pins.
ZP I VCC1 Input pin for the Z-phase.
Timer B TB0IN to
TB5IN I VCC1 These are timer B0 to timer B5 input pins.
Three-phase
motor control
output
U, U, V, V,
W, W O VCC1 These are Three-phase motor control output pins.
Serial interface CTS0 to
CTS2 I VCC1 Th ese are send control input pins.
RTS0 to
RTS2 O VCC1 These are recei ve control output pins.
CLK0 to
CLK4 I/O VCC1 These are transfer clock I/O pins.
RXD0 to
RXD2 I VCC1 Th ese are serial data input pins.
SIN3, SIN4 I VCC1 These are serial data input pins.
TXD0 to
TXD2 O VCC1 These are serial data output pins. (however, output of TXD2 for the
N-channel open drain output.)
SOUT3,
SOUT4 O VCC1 These are serial data output pins.
CLKS1 O VCC1 This is output pin for transfer clock output from multiple pins
function.
I2C mode SDA0 to
SDA2 I/O VCC1 These are serial data I/O pins. (however, output of SDA2 for the N-
channel open drain output.)
SCL0 to
SCL2 I/O VCC1 These are transfer clock I/O pins. (however, output of SCL2 for the
N-channel open drain output.)
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 27 of 96
REJ03B0001-0241
I : Input O : Output I/O : Input and output
NOTES:
1. When use VCC1 > VCC2, contacts due to some points or restrictions to be checked.
2. Ports P11 to P14 in M16C/62P (100-pin version) and M16C/62PT (100-pin version) cannot be used.
Table 1.19 Pin Description (100-pin and 128-pin Version) (3)
Signal Name Pin Name I/O
Type Power
Supply(1) Description
Reference
voltage input VREF I VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
A/D converter AN0 to AN7,
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
I VCC1 Analog input pins for the A/D converter.
ADTRG I VCC1 This is an A/D trigger input pin.
ANEX0 I/O VCC1 This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
ANEX1 I VCC1 This is the extended analog input pin for the A/D converter.
D/A converter DA0, DA1 O VCC1 This is the output pin for the D/A converter.
I/O port P0_0 to P0_7,
P1_0 to P1_7,
P2_0 to P2_7,
P3_0 to P3_7,
P4_0 to P4_7,
P5_0 to P5_7,
P12_0 to
P12_7 (2),
P13_0 to
P13_7 (2)
I/O VCC2 8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
P6_0 to P6_7,
P7_0 to P7_7,
P9_0 to P9_7,
P10_0 to
P10_7,
P11_0 to
P11_7 (2)
I/O VCC1 8-bit I/O ports having equivalent functions to P0.
(however , output of P7_0 and P7_1 for the N-channel open drain
output.)
P8_0 to P8_4,
P8_6, P8_7,
P14_0,
P14_1(2)
I/O VCC1 I/O ports having equivalent functions to P0.
Input port P8_5 I VCC1 Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 28 of 96
REJ03B0001-0241
I : Input O : Output I/O : Input and output
NOTES:
1. In this manual, hereafter, VCC refers to VCC1 unless otherwise noted.
2. In M16C/62PT, apply 4.0 to 5.5 V to the VCC1 pin.
3. Ask the oscillator maker the oscillation characteristic.
Table 1.20 Pin Description (80-pin Version) (1) (1)
Signal Name Pin Name I/O
Type Power
Supply Description
Power supply
input
VCC1, VSS
IApply 2.7 to 5.5 V to the VCC1 pin and 0 V to the VSS pin. (1, 2)
Analog power
supply input AVCC
AVSS I VC C1 Applies the power supply for the A/D converter. Connect the
AVCC pin to VCC1. Connect the AVSS pin to VSS.
Reset input RESET IVCC1
The microcomputer is in a reset state when applying “L” to the this pin.
CNVSS CNVSS
(BYTE) IVCC1
Switches processor mode. Connect this pin to VSS
to when after a
reset to start up in single-chip mode. Connect this pin to VCC1
to
start up in microprocessor mode. As for the BYTE pin of the 80-pin
versions, pull-up processing is performed within the microcomputer.
Main clock
input XIN I VCC1 I/O pins for the main clock generation circuit. Connect a ceramic
resonator or crystal oscillator between XIN and XOUT (3). To use
the external clock, input the clock from XIN and leave XOUT
open.
Main clock
output XOUT O VCC1
Sub clock input XCIN I VCC1 I/O pins for a sub clock oscill ation circuit. Connect a crystal
oscillator between XCIN and XCOUT (3). To use the external
clock, input the clock from XCIN and leave XCOUT open.
Sub clock
output XCOUT O VCC1
Clock output CLKOUT O VCC2 The clock of the same cycle as fC, f8, or f32 is outputted.
INT interrupt
input INT0 to IN T2 IVCC1 Input pins for the INT interrupt.
NMI interrupt
input NMI IVCC1 Input pin for the NMI interrupt.
Key input
interrupt input KI0 to KI3 I VCC1 Input pins for the key input interrupt.
Timer A TA0OUT,
TA3OUT,
TA4OUT
I/O VCC1 These are Timer A0,Timer A3 and Timer A4 I/O pins. (however,
output of TA0OUT for the N-channel open drain output.)
TA0IN, TA3IN,
TA4IN I VCC1 These are Timer A0, Timer A3 and Timer A4 inpu t pins.
ZP I VCC1 Input pin for the Z-phase.
Timer B TB0IN, TB2IN
to TB5IN I VCC1 These are Timer B0, Timer B2 to Timer B5 input pins.
Serial interface CTS0 to CTS1 I VCC1 These are send control input pins.
RTS0 to RTS1 O VCC1 These are receive control outp ut pins.
CLK0, CLK1,
CLK3, CLK4 I/O VCC1 The se are transfer clock I/O pins.
RXD0 to RXD2 I VCC1 These are serial data input pins.
SIN4 I VCC1 This is serial data input pin.
TXD0 to TXD2 O VCC1 These are serial data output pins. (however, output of TXD2 for
the N-channel open drain output.)
SOUT3,
SOUT4 O VCC1 The se are serial data output pins.
CLKS1 O VCC1 This is outp ut pin for transfer clock output from multiple pins
function.
I2C mode SDA0 to SDA2 I/O VCC1 These are serial data I/O pins. (however, output of SDA2 for the
N-channel open drain output.)
SCL0 to SCL2 I/O VCC1 These are transfer clock I/O pins. (however, output of SCL2 for
the N-channel open drain output.)
M16C/62P Group (M16C/62P, M16C/62PT) 1. Overview
Rev.2.41 Jan 10, 2006 Page 29 of 96
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I : Input O : Output I/O : Input and output
NOTES:
1. There is no external connections for port P1, P4_4 to P4_7, P7_2 to P7_5 and P9_1 in 80-pin version. Set the
direction bits in these ports to “1” (output mode), and set the output data to “0” (“L”) using the program.
Table 1.21 Pin Description (80-pin Version) (2)
Signal Name Pin Name I/O
Type Power
Supply(1) Description
Reference
voltage input VREF I VCC1 Applies the reference voltage for the A/D converter and D/A
converter.
A/D converter AN0 to AN7,
AN0_0 to
AN0_7,
AN2_0 to
AN2_7
I VCC1 Analog input pins for the A/D converter.
ADTRG I VCC1 This is an A/D trigger input pin.
ANEX0 I/O VCC1 This is the extended analog input pin for the A/D converter, and is
the output in external op-amp connection mode.
ANEX1 I VCC1 This is the extended analog input pin for the A/D converter.
D/A converter DA0, DA1 O VCC1 This is the output pin for the D/A converter.
I/O port (1) P0_0 to P0_7,
P2_0 to P2_7,
P3_0 to P3_7,
P5_0 to P5_7,
P6_0 to P6_7,
P10_0 to
P10_7
I/O VCC1 8-bit I/O ports in CMOS, having a direction register to select an
input or output.
Each pin is set as an input port or output port. An input port can
be set for a pull-up or for no pull-up in 4-bit unit by program.
P8_0 to P8_4,
P8_6, P8_7,
P9_0,
P9_2 to P9_7
I/O VCC1 I/O ports having equivalent functions to P0.
P4_0 to P4_3,
P7_0, P7_1,
P7_6, P7_7
I/O VCC1 I/O ports having equivalent functions to P0.
(however, output of P7_0 and P7_1 for the N-channel open drain
output.)
Input port P8_5 I VCC1 Input pin for the NMI interrupt.
Pin states can be read by the P8_5 bit in the P8 register.
M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU)
Rev.2.41 Jan 10, 2006 Page 30 of 96
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2. Central Processing Unit (CPU)
Figure 2.1 shows the CPU registers. The CPU has 13 registe rs. Of these, R0, R1, R2, R3, A0, A1 and FB comprise a
register bank. There are two register banks.
Figure 2.1 Central Processing Unit Register
2.1 Data Registers (R0, R1, R2 and R3)
The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to R3 are
the same as R0.
The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.
R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit data
register (R2R0). R3R1 is the same as R2R0.
Data Registers (1)
Address Registers (1)
Frame Base Registers (1)
Program Counter
Interrupt Table Register
User Stack Pointer
Interrupt Stack Pointer
Static Base Register
Flag Register
NOTES:
1. These registers comprise a register bank. There are two register banks.
R0H
b15 b8b7 b0
R3
INTBH
USP
ISP
SB
CDZSBOIU
IPL
R0L
R1H R1L
R2
b31
R3
R2
A1
A0
FB
b19
INTBL
b15 b0
PC
b19 b0
b15 b0
FLG
b15 b0
b15 b0
b7b8
Reserved Area
Carry Flag
Debug Flag
Zero Flag
Sign Flag
Register Bank Select Fla g
Overflow Flag
Interrupt Enable Flag
Stack Pointer Select Flag
Reserved Area
Processor Interrupt Prior ity Level
M16C/62P Group (M16C/62P, M16C/62PT) 2. Central Processing Unit (CPU)
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REJ03B0001-0241
2.2 Address Registers (A0 and A1)
The register A0 consists of 16 bits, and is used for address register indirect addressing and address register relative
addressing. They also are used for transfers and logic/logic operations. A1 is the same as A0.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
2.3 Frame Base Register (FB)
FB is configured with 16 bits, and is used for FB rel a tiv e addressing.
2.4 Interrupt Table Register (INTB)
INTB is configured with 20 bits, indicating the start address of an interrupt vector table.
2.5 Program Counter (PC)
PC is configured with 20 bits, indicating the address of an instruction to be executed.
2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)
Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.
Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.
2.7 Static Base Register (SB)
SB is configured with 16 bits, and is used for SB rel a tiv e addressing.
2.8 Flag Register (FLG)
FLG consists of 11 bits, indicating the CPU status.
2.8.1 Carry Flag (C Flag)
This flag retains a carry, borrow, or shift-out bit that has occu rred in the arithmetic/logic unit.
2.8.2 Debug Flag (D Flag)
The D flag is used exclusively for debugging purpose. During norm al use, it must be set to “0”.
2.8.3 Zero Flag (Z Flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, it is “0”.
2.8.4 Sign Flag (S Flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, it is “0”.
2.8.5 Register Bank Select Flag (B Flag)
Register bank 0 is selected when this flag is “0” ; register bank 1 is selected when this flag is “1”.
2.8.6 Overflow Flag (O Flag)
This flag is set to “1” when the operation resulted in an overflow; otherwise, it is “0”.
2.8.7 Interrupt Enable Flag (I Flag)
This flag enables a maskable interrupt.
Maskable interrupts are disabled when the I flag is “0”, and are enabled when the I flag is “1”. The I flag
is cleared to “0” when the interrupt request is accepted.
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REJ03B0001-0241
2.8.8 Stack Pointer Select Flag (U F lag)
ISP is selected when the U flag is “0”; USP is selected when the U flag is “1”.
The U flag is cleared to “0” when a hardware interrupt request is accepted or an INT instruction for software
interrupt Nos. 0 to 31 is executed.
2.8.9 Processor Interrupt Priority Level (IPL)
IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0
to level 7.
If a requested interrupt has priority greater than IPL, the interrupt is enabled.
2.8.10 Reserved Area
When write to this bit, write “0”. When read, its content is indeterminate.
M16C/62P Group (M16C/62P, M16C/62PT) 3. Memory
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REJ03B0001-0241
3. Memory
Figure 3.1 is a Memory Map of the M16C/62P group. The address space extends the 1M bytes from address 00000h to
FFFFFh.
The internal ROM is allocated in a lower address direction beginning with address FFFFFh. For example, a 64-Kbyte
internal ROM is allocated to the addresses from F0000h to FFFFFh.
As for the flash memory version, 4-Kbyte space (block A) exists in 0 F000h to 0FFFFh. 4-Kbyte space is mainly for
storing data. In addition to storing data, 4-Kbyte space also can store programs.
The fixed interrupt vector table is allocated to the addresses from FFFDCh to FFFFFh. Therefore, store the start
address of each interrupt routine here.
The internal RAM is allocated in an upper address direction beginning with address 00400h. For example, a 10-Kbyte
internal RAM is allocated to the addresses from 00400h to 02BFFh. In addition to storing data, the internal RAM also
stores the stack used when calling subroutines and when interrupts are generated.
The SRF is allocated to the addresses from 00000h to 003FFh. Peripheral function control registers are located here.
Of the SFR, any area which has no functions allocated is reserved for future use and cannot be used by users.
The special page vector table is allocated to the addresses from FFE00h to FFFDBh. This vector is used by the JMPS
or JSRS instructi on. For details, refer to the M16C/60 and M16C/20 Series Software Manual.
In memory expansion an d microp rocessor modes, some areas are reserved for future use and cannot b e used by u sers.
Use M16C/62P (80-pin version) and M16C/62PT in single-chip mode. The memory expansion and micro processor
modes cannot be used
.
Figure 3.1 Memory Map
00000h
XXXXXh
External area
Internal ROM
(program area) (5)
SFR
Internal RAM
Reserved area (1)
Reserved area (2)
FFFDCh
NOTES:
1. During memory expansion and microprocessor modes, can be used.
2. In memory expansion mode, can be used.
3. As for the flash memory version, 4-Kbyte space (block A) exists.
4. Shown here is a memory map for the case where the PM10 bit in the PM1 register is “1”
and the PM13 bit in the PM1 register is “1”.
5. When using the masked ROM version, write nothing to internal ROM area.
Undefined instruction
Overflow
BRK instruction
Address match
Single step
Watchdog timer
Reset
Special page
vector table
DBC
NMI
4 Kbytes 013FFh
02BFFh
017FFh
Address XXXXXh
033FFh
10 Kbytes
5 Kbytes
12 Kbytes
Size Address YYYYYhSize
F0000h
E8000h
F4000h
96 Kbytes
48 Kbytes
64 Kbytes Reserved area
External area
00400h
10000h
27000h
28000h
80000h
YYYYYh
FFFFFh
E0000h
256 Kbytes
128 Kbytes
192 Kbytes D0000h
320 Kbytes
C0000h
384 Kbytes
B0000h
A0000h
512 Kbytes 80000h
063FFh
053FFh
07FFFh
24 Kbytes
20 Kbytes
31 Kbytes
Internal RAM Internal ROM (3)
043FFh16 Kbytes
FFE00h
FFFFFh
Internal ROM
(data area) (3)
0FFFFh
0F000h
M16C/62P Group (M16C/62P, M16C/62PT) 4. S pecial Function Register (SFR)
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4. Special Function Register (SFR)
SFR(Special Function Register) is the control register of peripheral functions. Tables 4.1 to 4.6 list the SFR
information.
NOTES:
1. T he blank areas are reserved and cannot be accessed by users.
2. The PM00 and PM01 bits do not change at software reset, watchdog timer reset and oscillation stop detection reset.
3. The CM20, CM21, and CM27 bits do not change at oscillation stop detection reset.
4. The WDC5 bit is “0” (cold start) immediately after power-on. I t can only be set to “1” in a program.
5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.
6. This register in M16C/62PT cannot be used.
X : Nothing is mapped to this bit
Table 4.1 SFR Information (1) (1)
Address Register Symbol After Reset
0000h
0001h
0002h
0003h
0004h Processor Mode Register 0 (2) PM0 00000000b ( CNVSS pin is “L”)
00000011b(CNVSS pin is “H”)
0005h Processor Mode Register 1 PM1 00001000b
0006h System Clock Control Register 0 CM0 01001000b
0007h System Clock Control Register 1 CM1 00100000b
0008h Chip Select Control Register (6) CSR 00000001b
0009h Address Match Interrupt Enable Register AIER XXXXXX00b
000Ah Protect Register PRCR XX000000b
000Bh Data Bank Register (6) DBR 00h
000Ch Oscillation Stop Detection Register (3) CM2 0X000000b
000Dh
000Eh Watchdog Timer Start Register WDTS XXh
000Fh Watchdog Timer Control Register WDC 00XXXXXXb (4)
0010h Address Match Interrupt Register 0 RMAD0 00h
0011h 00h
0012h X0h
0013h
0014h Address Match Interrupt Register 1 RMAD1 00h
0015h 00h
0016h X0h
0017h
0018h
0019h Voltage Detection Register 1 (5, 6) VCR1 00001000b
001Ah Voltage Detection Register 2 (5, 6) VCR2 00h
001Bh Chip Select Expansion Control Register (6) CSE 00h
001Ch PLL Control Register 0 PLC0 0001X010b
001Dh
001Eh Processor Mode Register 2 PM2 XXX00000b
001Fh Low Voltage Detection Interrupt Register (6) D4INT 00h
0020h DMA0 Source Pointer SAR0 XXh
0021h XXh
0022h XXh
0023h
0024h DMA0 Destination Pointer DAR0 XXh
0025h XXh
0026h XXh
0027h
0028h DMA0 Transfer Counter TCR0 XXh
0029h XXh
002Ah
002Bh
002Ch DMA0 Control Register DM0CON 00000X00b
002Dh
002Eh
002Fh
0030h DMA1 Source Pointer SAR1 XXh
0031h XXh
0032h XXh
0033h
0034h DMA1 Destination Pointer DAR1 XXh
0035h XXh
0036h XXh
0037h
0038h DMA1 Transfer Counter TCR1 XXh
0039h XXh
003Ah
003Bh
003Ch DMA1 Control Register DM1CON 00000X00b
003Dh
003Eh
003Fh
M16C/62P Group (M16C/62P, M16C/62PT) 4. S pecial Function Register (SFR)
Rev.2.41 Jan 10, 2006 Page 35 of 96
REJ03B0001-0241
NOTES:
1. The blank areas are reserved and cannot be accessed by users.
X : Nothing is mapped to this bit
Table 4.2 SFR Information (2) (1)
Address Register Symbol After Reset
0040h
0041h
0042h
0043h
0044h INT3 Interrupt Control Register INT3IC XX00X000b
0045h Timer B5 Interrupt Control Register TB5IC XXXXX000b
0046h Timer B4 Interrupt Cont rol Register, UART1 BUS Collision De tection Interrupt Control Register TB4IC, U1BCNIC XXXXX000b
0047h Timer B3 Interrupt Cont rol Register, UART0 BUS Collision De tection Interrupt Control Register TB3IC, U0BCNIC XXXXX000b
0048h SI/O4 Interrupt Control Register, INT5 Interrupt Control Register S4IC, INT5IC XX00X000b
0049h SI/O3 Interrupt Control Register, INT4 Interrupt Control Register S3IC, INT4IC XX00X000b
004Ah UART2 Bus Collision Detection Interrupt Contr ol Register BCNIC XXXXX000b
004Bh DMA0 Interrupt Control Register DM0IC XXXXX000b
004Ch DMA1 Interrupt Control Register DM1IC XXXXX000b
004Dh Key Input Interrupt Control Register KUPIC XXXXX000b
004Eh A/D Conversion In terrupt Control Register ADIC XXXXX000b
004Fh UART2 Transmit Interrupt Control Register S2TIC XXXXX000b
0050h UART2 Receive Interrupt Control Register S2RIC XXXXX000b
0051h UART0 Transmit Interrupt Control Register S0TIC XX XXX000b
0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b
0053h UART1 Transmit Interrupt Control Register S1TIC XX XXX000b
0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b
0055h Timer A0 Interrupt Control Register TA0IC XXXXX000b
0056h Timer A1 Interrupt Control Register TA1IC XXXXX000b
0057h Timer A2 Interrupt Control Register TA2IC XXXXX000b
0058h Timer A3 Interrupt Control Register TA3IC XXXXX000b
0059h Timer A4 Interrupt Control Register TA4IC XXXXX000b
005Ah Timer B0 Interrupt Control Register TB0IC XXXXX000b
005Bh Timer B1 Interrupt Control Register TB1IC XXXXX000b
005Ch Timer B2 Inte rrupt Control Register TB2IC XXXXX000b
005Dh INT0 Interrupt Control Register INT0IC XX00X000b
005Eh INT1 Interrupt Control Register INT1IC XX00X000b
005Fh INT2 Interrupt Control Register INT2IC XX00X000b
0060h
0061h
0062h
0063h
0064h
0065h
0066h
0067h
0068h
0069h
006Ah
006Bh
006Ch
006Dh
006Eh
006Fh
0070h
0071h
0072h
0073h
0074h
0075h
0076h
0077h
0078h
0079h
007Ah
007Bh
007Ch
007Dh
007Eh
007Fh