IRSM836-025MA
1 www.irf.com © 2013 International Rectifier February 3, 2013
2A, 500V
Integrated Power Module for
Small Appliance Motor Drive Applications
Description
IRSM836-025MA is a 2A, 500V Integrated Power Module (IPM) designed for advanced appliance motor
drive applications such as energy efficient fans and pumps. IR's technology offers an extremely compact, high
perform ance AC motor-driver in an isolated package. This advance d IPM offers a combination of IR's low RDS(on)
Trench MOSFET technology and the industry benchmark 3-phase high voltage, rugged driver in a small PQFN
package. At only 12x12mm and featuring integrated bootstrap functionality, the compact footprint of this surface-
mount package makes it suitable for applications that are space-constrained. Integrated over-current protection,
fault reporting and under-voltage lockout functions deliver a high level of protection and fail-safe operation.
IRSM836-025MA funct ions with out a heat sink.
Features
• Integrated gate drivers and bootstrap functionality
• Open-source for leg-shunt current sensing
• Protection shutdown pin
• Low RDS(on) Trench FREDFET
• Under-voltage lockout for all channels
• Matched propagation delay for all channels
• Optimized dV/dt for loss and EMI trade offs
• 3.3V Schmitt-triggered active high input logic
• Cross-conduction prevention logic
• Motor power range up to ~90W, without heat sink
• Isolation 1500VRMS min
Base Part Number Package Type Standard Pack Orderable Part Number
Form Quantity
IRSM836-025MA 36L
PQFN 12 x 12 mm Tape and Reel 2000 IRSM836-025MATR
Tray 800 IRSM836-025MA
All part numbers are PbF
IRSM836-025MA
IRSM836-025MA
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Intern al Elect r i cal Schemati c
IRSM836-025MA
600V
3-Phase
Driver
HVIC
VCC
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
FAULT
ITRIP
EN
VB1 VB2VB3
V+
VSS
U, VS1
V, VS2
W, VS3
RCIN
VRU
COM
VRV VRW
Absol ute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the module may occur. These are not tested at
manufacturing. All voltage parameters are absolute voltages referenced to VSS unless otherwise stated in the table.
Symbol Description Min Max Unit
BVDSS MOSFET Blocking Voltage --- 500 V
IO @ T=25°C DC Output Current per MOSFET --- 2 A
IOP Pulsed Output Current (Note 1) --- 11
Pd @ TC=25°C Maximum Power Dissipation per MOSFET --- 25 W
VISO Isolation Voltage (1min) (Note 2) --- 1500 VRMS
TJ Operating Junction Temperature -40 150 °C
TL Lead Temperature (Soldering, 30 seconds) --- 260 °C
TS Storage Temperature -40 150 °C
VS1,2,3 High Side Floating Supply Offset Voltage VB1,2,3 - 20 VB1,2,3 +0.3 V
VB1,2,3 High Side Floating Supply Voltage -0.3 500 V
VCC Low Side and Logic Supply voltage -0.3 20 V
VIN Input Voltage of LIN, HIN, ITRIP, EN, RCIN, FLT VSS -0.3 VCC+0.3 V
Note 1: Pulse Width = 100µs, TC =25°C, Duty=1%.
Note 2: Characterized, not tested at manufacturing
IRSM836-025MA
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Recommended Operating Conditions
Symbol Description Min Max Unit
V+ Positive DC Bus Input Voltage --- 400 V
VS1,2,3 High Side Floating Supply Offset Voltage (Note 3) 400 V
VB1,2,3 High Side Floating Supply Voltage VS+12 VS+20 V
VCC Low Side and Logic Supply Voltage 13.5 16.5 V
VIN Input Voltage of LIN, HIN, ITRIP, EN, FLT 0 5 V
Fp PWM Carrier Frequency --- 20 kHz
The Input/Output logic diagram is shown in Figure 1. For proper operation the module should be used within the
recommended conditions. All voltages are absolute referenced to COM. The VS offset is tested with all supplies biased at 15V
differential.
Note 3: Logic operational for Vs from COM-5V to COM+250V. Logic state held for Vs from COM-5V to COM-VBS.
Static Electrical Characteristics
(VCC-COM) = (VB-VS) = 15 V. TA = 25oC unless otherwise specified. The VIN and IIN parameters are referenced to VSS and are
applicable to all six channels. T he VCCUV parameters are referenced to VSS. The VBSUV parameters are referenced to VS.
Symbol Description Min Typ Max Units Conditions
BVDSS Drain-to-Source Breakdown Voltage 500 --- --- V TJ=25°C, ILK=250µA
ILKH Leakage Current of High Side FET’s in
Parallel 10 µA TJ=25°C, VDS=500V
ILKL Leakage Current of Low Side FET’s in
Parallel Plus Gate Drive IC 15 µA TJ=25°C, VDS=500V
RDS(ON) Drain to Source ON Resistance --- 3.2 4 Ω TJ=25°C, VCC=15V, Id = 0.5A
VIN,th+ Positive Going Input Threshold 2.5 --- --- V
VIN,th- Negative Going Input Threshold --- --- 0.8 V
VCCUV+,
VBSUV+ VCC and VBS Supply Under-Voltage,
Positive Going Threshold 8 8.9 9.8 V
VCCUV-,
VBSUV- VCC and VBS supply Under-Voltage,
Negative Going Threshold 7.4 8.2 9 V
VCCUVH,
VBSUVH VCC and VBS Supply Under-Voltage
Lock-Out Hysteresis --- 0.7 --- V
IQBS Quiescent VBS Supply Current VIN=0V --- --- 125 µA
IQCC Quiescent VCC Supply Current VIN=0V --- --- 3.35 mA
IQCC, ON Quiescent VCC Supply Current VIN=4V --- --- 10 mA
IIN+ Input Bias Current VIN=4V --- 100 160 µA
IIN- Input Bias Current VIN=0V --- -- 1 µA
ITRIP+ ITRIP Bias Current VITRIP=4V --- 5 40 µA
ITRIP- ITRIP Bias Current VITRIP=0V --- -- 1 µA
VIT, TH+ ITRIP Threshold Voltage 0.37 0.46 0.55 V
VIT, TH- ITRIP Threshold Voltage --- 0.4 --- V
IRSM836-025MA
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VIT, HYS ITRIP Input Hysteresis --- 0.06 --- V
RBR Internal Bootstrap Equivalent Resistor
Value --- 200 --- Ω TJ=25°C
VRCIN,TH RCIN Positive Going Threshold --- 8 --- V
RON,FAULT FAULT Open-Drain Resistance --- 50 100 Ω
Note 4: Characterized, not tested at manufacturing
Dynamic Electrical Characteristics
(VCC-COM) = (VB-VS) = 15 V. TA = 25
o
C unless otherwise specified.
Symbol Description Min Typ Max Units Conditions
TON Input to Output Propagation Turn-On
Delay Time --- 1 1.5 µs ID=1mA, V+=50V
See Fig.2
TOFF Input to Output Propagation Turn-Off
Delay Time --- 1 1.5 µs
TFIL,IN Input Filt er Time (HIN, LIN) 200 330 --- ns VIN=0 & VIN=4V
TFIL,EN Input Filter Time (EN) 100 200 --- ns VIN=0 & VIN=4V
TBLT-ITRIP ITRIP Blanking Time 100 330 ns VIN=0 & VIN=4V, VI/Trip=5V
TFAULT Itrip to Fault --- 590 950 ns VIN=0 & VIN=4V
TEN EN Falling to Switch Turn-Off 750 950 ns VIN=0 & VIN=4V
TITRIP ITRIP to Switch Turn-Off Propagation Delay --- 950 1200 ns ID=1A, V+=50V, See Figure 3
MOSFET Avalanche Characteristics
Symbol Description Min Typ Max Units Conditions
EAS Single Pulse Avalanche Energy --- 62 --- mJ
T
J
=25°C, L=18mH, VDD=75V,
IAS=2.6A, SO-8 package
Thermal and Mechanical Characteristics
Symbol Description Min Typ Max Units Conditions
Rth(J-CT) Total Thermal Resistance Junct ion t o
Case Top --- 28.2 --- °C/W One device
Rth(J-CB) Total Thermal Resistance Junction to
Case Bottom --- 2.5 --- °C/W One device
IRSM836-025MA
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Qualification Information†
Qualification Level Industrial††
(per JEDEC JESD 47E)
Moisture Sensitivity Level MSL3†††
(per IPC/JEDEC J-STD-020C)
ESD
Machine Model Class B
(per JEDEC standard JESD22-A115)
Human Body Model Clas s 2
(per standard ESDA/JEDEC JS-001-2012)
RoHS Compliant Yes
†
Qualification standards can be found at International Rectifier’s web site http://www.irf.com/
††
Higher qualification ratings may be available should the user have such requirements. Please contact
your International Rectifier sales representative for further information.
†††
Higher MSL ratings may be available for the specific package types listed here. Please contact your
International Rectifier sales representative for further information.
IRSM836-025MA
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Input/Output Pin Equivalent Circ uit Diagrams
ESD
Diode
ESD
Diode
V
B
HO
V
S
ESD
Diode
ESD
Diode
LO
COM
600 V
20 V
Clamp
25 V
Clamp
V
CC
ESD
Diode
ESD
Diode
V
CC
RCIN or
FAULT
V
SS
ESD
Diode
ESD
Diode
V
CC
HIN
,
LIN
,
or EN
V
SS
33k
20
V
Clamp
ESD
Diode
ESD
Diode
V
CC
ITRIP
V
SS
1M
IRSM836-025MA
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Input-Output Logic Level Tabl e
Gate
Driver
IC
V+
U, V, W
Lo
Ho
Hin1,2,3
Lin1,2,3
EN Itrip Hin1,2,3 Lin1,2,3 U,V,W
1 0 1 0 V+
1 0 0 1 0
1 0 0 0 off
1 1 X X off
0 X X X off
Figure 1: Input/Output Logic Diagram
ITRIP
U,V,W
LIN1,2,3
HIN1,2,3
IRSM836-025MA
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Figure 2a: Input to Output propagation turn-on
delay time.
Figure 2b: Input to Output propagation turn-off
delay time.
Figure 2c: Diode Reverse Recovery.
Figure 2: Switching Parameter Definitions
50%
H
IN
/L
IN
V
DS
I
D
H
IN
/L
IN
T
OFF
t
f
10% I
D
50%
V
CE
V
DS
I
D
H
IN
/L
IN
T
ON
t
r
50%
H
IN
/L
IN
90% I
D
10% I
D
50%
V
DS
90% I
D
V
DS
I
F
H
IN
/L
IN
t
rr
I
rr
IRSM836-025MA
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Module Pin-Out Descripti on
Pin
Name
Description
1 HIN3 Logic Input for High Side Gate Driver - Phase 3
2 LIN1 Logic Input for Low Side Gate Driver - Phase 1
3 LIN2 Logic Input for Low Side Gate Driver - Phase 2
4 LIN3 Logic Input for Low Side Gate Driver - Phase 3
5 /FLT Fault Output Pin
6 Itrip Over-Current Protection Pin
7 EN Enable Pin
8 RCin Reset Programming Pin
9, 39 VSS, COM Ground for Gate Drive IC and Low Side Gate Drive Return
10, 11, 30,
37
U, VS1 Output 1, High Side Floating Supply Offset Voltage
12, 13 VR1 Phase 1 Low Side FET Source
14, 15 VR2 Phase 2 Low Side FET Source
16, 17, 38 V, VS2 Output 2, High Side Floating Supply Offset Voltage
18, 19 W , VS3 Output 3, High Side Floating Supply Offset Voltage
20, 21 VR3 Phase 3 Low Side FET Source
22-29 V+ DC Bus Voltage Positive
31 VB1 High Side Floating Supply Voltage 1
32 VB2 High Side Floating Supply Voltage 2
33 VB3 High Side Floating Supply Voltage 3
34 VCC 15V Supply
35 HIN1 Logic Input for High Side Gate Driver - Phase 1
36 HIN2 Logic Input for High Side Gate Driver - Phase 2b
36
35
34
33
32
31
30
29
28
21 20
17
16
11
1987
6543
Top View
2
27
10
19
18
37 38
39
12
13
14
15
23 22
25 24
26
Note
Pins 37 and 38 are not required to
be connected electrically on the
PCB
All pins with the same name are
internally connected. For example,
pins 10, 11, 30 and 37 are
internally connected.
IRSM836-025MA
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Fault Reporting and Progra m m able Fault Clear Timer
The IRSM836-025MA provides an integrated fault reporting output and an adjustable fault clear timer.
There ar e two s ituatio ns that would cause t he IRSM836-025MA to repor t a f ault via th e FAULT pin. T he firs t is an
under-voltage c onditio n of VCC and the sec ond is when th e ITRIP pi n recogn izes a fault. O nce the f ault co ndition
occurs , the F AULT pin is i n ter nal ly pulled to VSS an d t h e f ault clear t imer is ac tivated. The fault outp ut s tays in the
low state until the fault condition has been removed and the fault clear timer expires; once the fault clear timer
expires, the voltage on the FAULT pin will return to VCC.
The length of the fault clear time period (tFLTCLR) is determ ined by exponential charging character istics of
the capacitor where the time constant is set by RRCIN and CRCIN. In Figure 4 where we see that a fault condition
has occurred (UVLO or ITRIP), RCIN and FAULT are pulled to VSS, and once the fault has been removed, the
fault cle ar t imer begins. Fi gur e 5 shows tha t R RCIN is connec te d b et we en the VCC and the RCIN pin , while C RCIN is
placed between the RCIN and VSS pins.
Figure 4: RCIN and FAULT pin waveforms
Figure 5: Programming the fault clear timer
The design guidelines for this network are shown in Table 1.
CRCIN ≤1 nF
Ceramic
RRCIN 0.5 MΩ to 2 MΩ
>> RON,RCIN
Table 1: Design gui del ine s
The length of the fault clear time period can be determined by using the formula below.
( )
−−=
CC
THRCIN
RCINRCINFLTCLR V
V
CRt ,
1ln
V
CC
V
RCIN
Time
V
RCIN,TH
t
FLTCLR
V
SS
V
FAULT
Time
V
SS
ITRIP
High
Impedance State
V
cc
HIN
(
x
3
)
RCIN
EN
ITRIP
V
SS
FAULT
VRx
LIN
(
x
3
)
V
B
(
x
3
)
V
S
(
x
3
)
IRSM836-025MA
I
-
R
RCIN
C
RCIN
IRSM836-025MA
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Typical Application Connection IRSM836-025MA
IRSM836-025MA
HVIC
VCC
HIN1
HIN2
HIN3
LIN1
LIN2
LIN3
FAULT
ITRIP
EN
VB1
VB2
VB3
U, VS1
V, VS2
W, VS3
RCIN
Power
Supply
PWMWH
PWMVH
PWMUH
PWMVL
PWMWL
GATEKILL
AIN1
IFB+
IFB-
IFBO
VSS
VDD
VDDCAP
XTAL0
XTAL1
AIN2
SPD-REF
VSS COM
VBUS
IRMCK171
PWMUL
4.87k
2M
2M
1nF
0.5
6.04k
6.04k
7.68k
1. Electrolytic bus capacitors should be mounted as close to the module bus terminals as possible to reduce
ringing and EMI problems. Additional high frequency ceramic capacitor mounted close to the module pins
will further improve perform anc e.
2. In order to provide good decoupling between VCC-VSS and VB1,2,3-VS1,2,3 terminals, the capacitors
shown connected between these terminals should be located very close to the module pins. Additional
high frequency capacitors, typically 0.1µF, are recommended.
3. Value of the boot-strap capacitors depends upon the switching frequency. Their selection should be made
based on application note AN-1044.
4. P WM generator must be disabled within Fault duration to guarantee shutdown of the system. Over-
current condition must be cleared before resuming operation.
IRSM836-025MA
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Current Capabil i ty in a Typical Application
Figure 6 sho ws the c urrent capabilit y for this module at specified condit ions. The current capability of the
module is affected by application conditions including the PCB layout, ambient temperature, maximum PCB
temperature, modulation scheme, PCB copper thickness and so on. The curves below were obtained from
measurements carried out on the IRMCS1471_R4 reference design board which includes the IRSM836-025MA
and IR’s IRMCK171 digital control IC.
Figure 6: Maximum Sinusoidal Phase Current vs. PWM Switch ing Frequ ency
Sinusoidal Modulation, V+=320V, PF=0.98
0
50
100
150
200
250
300
6 8 10 12 14 16 18 20
RMS Current (mA)
Carrier Frequency (kHz)
320V, ∆Tca = 40
1oz, 3P 2oz, 3P
1oz, 2P 2oz, 2P
0
50
100
150
200
250
300
350
400
450
6 8 10 12 14 16 18 20
RMS Current (mA)
Carrier Frequency (kHz)
320V, ∆Tca = 70
1oz, 3P 2oz, 3P
1oz, 2P 2oz, 2P
IRSM836-025MA
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PCB Example
Figure 7 below shows an example layout for the application PCB. The effective area of the V+ top-layer
copper plane is ~3cm² in this example. For an FR4 PCB with 1oz copper, Rth(J-A) is about 40°C/W. A lower Rth(J-A)
can be achieved using thicker copper and/or additional layers.
Figure 7: PCB layout example and corresponding thermal image (6kHz, 2P, 2oz, ∆Tca=70°C, V+ = 320V, Iu = 419mArms, Po
= 92W)
At the module’s typical operating conditions, dV/dt of the phase node voltage is influenced by the load
capacitance which includes parasitic capacitance of the PCB, MOSFET output capacitance and motor winding
capacitance. To turn off the MOSFET, the load capacitance needs to be charged by the phase current. For the
IRMCS11 71 referenc e design, t urn-off dV/dt ranges fr om 2 to 5 V/ns depe nding on th e phase cur rent m agnitude.
Turn-on dV/dt is influenced by PCB parasitic capacitance and motor winding capacitance and typically ranges
from 4 to 6 V/ns. T he MOSFET turn-on loss combined with the complim entary body diode reverse recover y loss
comprises the majority of the total switching losses. Two-phase modulation can be used to reduce switching
losses and run the module at higher phase currents.
Module
IRSM836-025MA
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Revision History
January 30, 2013
Formatting corrections; added notes about what pins are internally connected; updated ordering
table stating all parts are PbF.
Data and Specifications are subject to change without notice
IR WORLD HEADQUARTER S : 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
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