74LVC1G74DC,125 - NXP Semiconductors

1. General description

The 74LVC1G74 is a single positive edge trigge red D-type flip-f lop with individual data ( D)

inputs, clock (CP) inputs, set (SD) and reset (RD) inputs, and complementary Q and Q

outputs.

This device is fully specified for partial power-down applications using IOFF. The IOFF

circuitry disables the output, preventing damaging backflow current through the device

when it is powered down.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition for predictable operation.

Schmitt trigger action at all input s makes the circuit hi ghly tolerant of slower input rise and

fall times.

2. Features and benefits

Wide supply voltage range from 1.65 V to 5.5 V

5 V tolerant inputs for interfacing with 5 V logic

High noise immunity

Complies with JEDEC standard:

JESD8-7 (1.65 V to 1.95 V)

JESD8-5 (2.3 V to 2.7 V)

JESD8-B/JESD36 (2.7 V to 3.6 V)

ESD protection:

HBM JESD22-A114F exceeds 2000 V

MM JESD22-A115-A exceeds 200 V

24 mA output drive (VCC =3.0V)

CMOS low power consumption

Latch-up performance exceeds 250 mA

Direct interface with TTL levels

Inputs accept voltages up to 5 V

Multiple package options

Specified from 40 Cto+85C and 40 Cto+125C

74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Rev. 11 — 4 June 2012 Product data sheet

Product data sheet Rev. 11 — 4 June 2012 2 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

3. Ordering information

4. Marking

[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.

Table 1. Ordering information

Type number Package

Tem perature range Name Description Version

74LVC1G74DP 40 Cto+125C TSSOP8 plastic thin shrink small outline package; 8 leads; body

widt h 3 mm; lea d leng th 0.5 mm SOT505-2

74LVC1G74DC 40 Cto+125C VSSOP8 plastic very thin shrink small outline package; 8 leads;

body width 2.3 mm SOT765-1

74LVC1G74GT 40 Cto+125C XSON8 plastic extremely thin small outline package; no leads; 8

terminals; body 1  1.95  0.5 mm SOT833-1

74LVC1G74GF 40 C to +125 C XSON8 extremely thin small outline package; no leads;

8 terminals; bod y 1.35 10.5 mm SOT1089

74LVC1G74GD 40 Cto+125C XSON8U plastic extremely thin small outline package; no leads;

8 terminals; UT LP based; body 3  2  0.5 mm SOT996-2

74LVC1G74GM 40 Cto+125C XQFN8 plastic, extremely thin quad flat package; no leads;

8 terminals; bod y 1.6  1.6  0.5 mm SOT902-2

74LVC1G74GN 40 C to +125 C XSON8 extremely thin small outline package; no leads;

8 terminals; bod y 1.2 1.0 0.35 mm SOT1116

74LVC1G74GS 40 C to +125 C XSON8 extremely thin small outline package; no leads;

8 terminals; bod y 1.35 1.0 0.35 mm SOT1203

Table 2. Marking codes

Type number Marking code[1]

74LVC1G74DP V74

74LVC1G74DC V74

74LVC1G74GT V74

74LVC1G74GF Y4

74LVC1G74GD V74

74LVC1G74GM V74

74LVC1G74GN Y4

74LVC1G74GS Y4

Product data sheet Rev. 11 — 4 June 2012 3 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

5. Functional diagram

Fig 1. Logic symbol Fig 2. IEC logic symbol

001aah757

SD QQ

001aah758

Fig 3. Logic diagra m

mna421

Product data sheet Rev. 11 — 4 June 2012 4 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

6. Pinning information

6.1 Pinning

Fig 4. Pin configuration SOT505-2 and SOT765-1 Fig 5. Pin configuration SOT833-1, SOT 1089,

SOT1116 and SOT1203

74LVC1G74

CP VCC

DSD

QRD

GND Q

001aab659

74LVC1G74

GND

001aab658

Transparent top view

Fig 6. Pin configu ration SOT996-2 Fig 7. Pin configuration SOT902 -2

001aah948

74LVC1G74

Transparent top view

GND

VCC

001aaf641

DRD

GND

Transparent top view

terminal 1

index area

74LVC1G74

Product data sheet Rev. 11 — 4 June 2012 5 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

6.2 Pin description

7. Functional description

[1] H = HIGH voltage level;

L = LOW voltage level;

X = don’t care.

[1] H = HIGH voltage level;

L = LOW voltage level;

= LOW-to-HIGH CP transition;

Qn+1 = state after the next LOW-to-HIGH CP transition.

Table 3. Pin description

Symbol Pin Description

SOT505-2, SOT765-1, SOT833-1, SOT1089,

SOT996-2, SOT1116 and SOT1203 SOT902-2

CP 1 7 clock input (LOW-to-HIGH, edge-triggered)

D 2 6 data input

Q3 5 complement output

GND 4 4 ground (0 V)

Q 5 3 true output

RD 6 2 asynchronous reset-direct input (active LOW)

SD 7 1 asynchronous set-direct input (active LOW)

VCC 8 8 supply voltage

Table 4. Function table for asynchro nous operation[1]

Input Output

SD RD CP D Q Q

LHXXHL

HLXXLH

LLXXHH

Table 5. Function table for synchronous operation[1]

Input Output

SD RD CP D Qn+1 Qn+1

HHLLH

HHHHL

Product data sheet Rev. 11 — 4 June 2012 6 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

8. Limiting values

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.

[3] For TSSOP8 packages: above 55 C the value of Ptot derates linearly with 2.5 mW/K.

For VSSOP8 packages: above 110 C the value of Ptot derates linearly with 8.0 mW/K.

For XSON8, XSON8U and XQFN8 packages: above 118 C the value of Ptot derates linearly with 7.8 mW/K.

9. Recommended operating conditions

Table 6. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 0.5 +6.5 V

IIK input clamping current VI<0V 50 - mA

VIinput voltage [1] 0.5 +6.5 V

IOK output clamping current VO>V

CC or VO<0V - 50 mA

VOoutput voltage Active mode [1] 0.5 VCC +0.5 V

Power-down mode [1][2] 0.5 +6.5 V

IOoutput curren t VO=0 VtoV

CC -50 mA

ICC supply current - 100 mA

IGND ground current 100 - mA

Ptot total power dissipation Tamb = 40 C to +125 C[3] - 300 mW

Tstg storage temperature 65 +150 C

Table 7. Operating conditions

Symbol Parameter Conditions Min Max Unit

VCC supply voltage 1.65 5.5 V

VIinput voltage 0 5.5 V

VOoutput voltage Active mode 0 VCC V

Power-down mode; VCC =0V 0 5.5 V

Tamb ambient temperature 40 +125 C

t/V input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V

VCC = 2.7 V to 5.5 V - 10 ns/V

Product data sheet Rev. 11 — 4 June 2012 7 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

10. Static characteristics

Table 8. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ[1] Max Unit

Tamb = 40 C to +85 C

VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC -- V

VCC = 2.3 V to 2.7 V 1.7 - - V

VCC = 2.7 V to 3.6 V 2.0 - - V

VCC = 4.5 V to 5.5 V 0.7  VCC -- V

VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCC V

VCC = 2.3 V to 2.7 V - - 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 V

VCC = 4.5 V to 5.5 V - - 0.3  VCC V

VOH HIGH-level output voltage VI = VIH or VIL

IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V

IO = 4 mA; VCC = 1.65 V 1.2 1.54 - V

IO = 8 mA; VCC = 2.3 V 1.9 2.15 - V

IO = 12 mA; VCC = 2.7 V 2.2 2.50 - V

IO = 24 mA; VCC = 3.0 V 2.3 2.62 - V

IO = 32 mA; VCC = 4.5 V 3.8 4.11 - V

VOL LOW-level output voltage VI = VIH or VIL

IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 V

IO = 4 mA; VCC = 1.65 V - 0.07 0.45 V

IO = 8 mA; VCC = 2.3 V - 0.12 0.30 V

IO = 12 mA; VCC = 2.7 V - 0.17 0.40 V

IO = 24 mA; VCC = 3.0 V - 0.33 0.55 V

IO = 32 mA; VCC = 4.5 V - 0.39 0.55 V

IIinput leakage current VI= 5.5 V or GND;

VCC =0Vto5.5V -0.1 5A

IOFF power-off leakage current VI or VO = 5.5 V ; VCC = 0 V - 0.1 10 A

ICC supply current VI= 5.5 V or GND;

VCC =1.65Vto5.5V; I

O=0A -0.110A

ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0 A;

VCC =2.3V to5.5 V -5500A

CIinput capacitance - 4.0 - pF

Product data sheet Rev. 11 — 4 June 2012 8 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

[1] All typical values are measured at Tamb = 25 C.

Tamb = 40 C to +125 C

VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65  VCC -- V

VCC = 2.3 V to 2.7 V 1.7 - - V

VCC = 2.7 V to 3.6 V 2.0 - - V

VCC = 4.5 V to 5.5 V 0.7  VCC -- V

VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35  VCC V

VCC = 2.3 V to 2.7 V - - 0.7 V

VCC = 2.7 V to 3.6 V - - 0.8 V

VCC = 4.5 V to 5.5 V - - 0.3  VCC V

VOH HIGH-level output voltage VI = VIH or VIL

IO = 100 A; VCC = 1.65 V to 5.5 V VCC  0.1 - - V

IO = 4 mA; VCC = 1.65 V 0.95 - - V

IO = 8 mA; VCC = 2.3 V 1.7 - - V

IO = 12 mA; VCC = 2.7 V 1.9 - - V

IO = 24 mA; VCC = 3.0 V 2.0 - - V

IO = 32 mA; VCC = 4.5 V 3.4 - - V

VOL LOW-level output voltage VI = VIH or VIL

IO = 100 A; VCC = 1.65 V to 5.5 V - - 0.10 V

IO = 4 mA; VCC = 1.65 V - - 0.70 V

IO = 8 mA; VCC = 2.3 V - - 0.45 V

IO = 12 mA; VCC = 2.7 V - - 0.60 V

IO = 24 mA; VCC = 3.0 V - - 0.80 V

IO = 32 mA; VCC = 4.5 V - - 0.80 V

IIinput leakage current VI= 5.5 V or GND;

VCC =0Vto5.5V --20 A

IOFF power-off leakage current VI or VO = 5.5 V ; VCC = 0 V - - 20 A

ICC supply current VI= 5.5 V or GND;

VCC =1.65Vto5.5V; I

O=0A --40A

ICC additional supply current per pin; VI = VCC  0.6 V; IO = 0 A;

VCC =2.3V to5.5 V --5000A

Table 8. Static characteristics …continued

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Typ[1] Max Unit

Product data sheet Rev. 11 — 4 June 2012 9 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

11. Dynamic characteristics

Table 9. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

tpd propagation delay CP to Q, Q; see Figure 8 [2]

VCC = 1.65 V to 1.95 V 1.5 6.0 13.4 1.5 13.4 ns

VCC = 2.3 V to 2.7 V 1.0 3.5 7.1 1.0 7.1 ns

VCC = 2.7 V 1.0 3.5 7.1 1.0 7.1 ns

VCC = 3.0 V to 3.6 V 1.0 3.5 5.9 1.0 5.9 ns

VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns

SD to Q, Q; see Figure 9 [2]

VCC = 1.65 V to 1.95 V 1.5 6.0 12.9 1.5 12.9 ns

VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns

VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns

VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns

VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns

RD to Q, Q; see Figure 9 [2]

VCC = 1.65 V to 1.95 V 1.5 5.0 12.9 1.5 12.9 ns

VCC = 2.3 V to 2.7 V 1.0 3.5 7.0 1.0 7.0 ns

VCC = 2.7 V 1.0 3.5 7.0 1.0 7.0 ns

VCC = 3.0 V to 3.6 V 1.0 3.0 5.9 1.0 5.9 ns

VCC = 4.5 V to 5.5 V 1.0 2.5 4.1 1.0 4.1 ns

tWpulse width CP HIGH or LOW;

see Figure 8

VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns

VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns

VCC = 2.7 V 2.7 - - 2.7 - ns

VCC = 3.0 V to 3.6 V 2.7 1.3 - 2.7 - ns

VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns

SD and RDLOW;

see Figure 9

VCC = 1.65 V to 1.95 V 6.2 - - 6.2 - ns

VCC = 2.3 V to 2.7 V 2.7 - - 2.7 - ns

VCC = 2.7 V 2.7 - - 2.7 - ns

VCC = 3.0 V to 3.6 V 2.7 1.6 - 2.7 - ns

VCC = 4.5 V to 5.5 V 2.0 - - 2.0 - ns

Product data sheet Rev. 11 — 4 June 2012 10 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

[1] Typical values are measured at Tamb =25C and VCC = 1.8 V, 2.5 V, 2.7 V, 3.3 V and 5.0 V respectively.

[2] tpd is the same as tPLH and tPHL.

[3] CPD is used to determine the dynamic power dissipation (PDin W).

PD=C

PD VCC2fiN+(CLVCC2fo) where:

fi= input frequency in MHz;

fo= output frequency in MHz;

CL= output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

(CLVCC2fo) = sum of outputs.

trec recovery time SD or RD; see Figure 9

VCC = 1.65 V to 1.95 V 1.9 - - 1.9 - ns

VCC = 2.3 V to 2.7 V 1.4 - - 1.4 - ns

VCC = 2.7 V 1.3 - - 1.3 - ns

VCC = 3.0 V to 3.6 V +1.2 3.0 - +1.2 - ns

VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns

tsu set-up time D to CP; see Figure 8

VCC = 1.65 V to 1.95 V 2.9 - - 2.9 - ns

VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - ns

VCC = 2.7 V 1.7 - - 1.7 - ns

VCC = 3.0 V to 3.6 V 1.3 0.5 - 1.3 - ns

VCC = 4.5 V to 5.5 V 1.1 - - 1.1 - ns

thhold time D to CP; see Figure 8

VCC = 1.65 V to 1.95 V 1.5 - - 1.5 - ns

VCC = 2.3 V to 2.7 V 1.0 - - 1.0 - ns

VCC = 2.7 V 1.0 - - 1.0 - ns

VCC = 3.0 V to 3.6 V 1.0 0.6 - 1.0 - ns

VCC = 4.5 V to 5.5 V 1.0 - - 1.0 - ns

fmax maximum

frequency CP; see Figure 8

VCC = 1.65 V to 1.95 V 80 - - 80 - MHz

VCC = 2.3 V to 2.7 V 175 - - 175 - MHz

VCC = 2.7 V 175 - - 175 - MHz

VCC = 3.0 V to 3.6 V 175 280 - 175 - MHz

VCC = 4.5 V to 5.5 V 200 - - 200 - MHz

CPD power dissipation

capacitance VI = GND to VCC;

VCC =3.3V [3] -15- - -pF

Table 9. Dynamic characteristics …continued

Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.

Symbol Parameter Conditions 40 C to +85 C40 C to +125 CUnit

Min Typ[1] Max Min Max

Product data sheet Rev. 11 — 4 June 2012 11 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

12. Waveforms

Measurement points are given in Table 10.

The shaded areas indicate when the input is permitted to change for predictable output performance.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 8. The clock input (CP) to output (Q, Q) propagation delays, the clock pulse width, the D to CP set-up, the

CP to D hold times and the maximum frequency

mnb141

tsu

tPHL

tPLH

tsu

1/fmax

GND

CP input

D input

VOH

VOL

Q output

VOH

VOL

Q output

Table 10. Measurement points

Supply voltage Input Output

VCC VMVM

1.65 V to 1.95 V 0.5 VCC 0.5 VCC

2.3 V to 2.7 V 0.5 VCC 0.5 VCC

2.7V 1.5V 1.5V

3.0V to 3.6V 1.5V 1.5V

4.5 V to 5.5 V 0.5 VCC 0.5 VCC

Product data sheet Rev. 11 — 4 June 2012 12 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Measurement points are given in Table 10.

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 9. The set ( S D) and reset (RD) input to output (Q, Q) propagation delays, the set and reset pulse widths and

the RD to CP recovery time

mnb142

rec

PHL

PLH

GND

SD input

GND

RD input

CP input

Q output

rec

Product data sheet Rev. 11 — 4 June 2012 13 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Test data is given in Table 11.

Definitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

VEXT = External voltage for measuring switching times.

Fig 10. Test circuit for measuring switching times

VEXT

VCC

VIVO

mna616

DUT

Table 11. Test data

Supply voltage Input Load VEXT

VCC VItr, tfCLRLtPLH, tPHL tPZH, tPHZ tPZL, tPLZ

1.65 V to 1.95 V VCC 2.0ns 30pF 1kopen GND 2VCC

2.3 V to 2.7 V VCC 2.0 ns 30 pF 500 open GND 2VCC

2.7 V 2.7 V 2.5 ns 50 pF 500 open GND 6 V

3.0 V to 3.6 V 2.7 V 2.5 ns 50 pF 500 open GND 6 V

4.5 V to 5.5 V VCC 2.5 ns 50 pF 500 open GND 2VCC

Product data sheet Rev. 11 — 4 June 2012 14 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

13. Package outline

Fig 11. Package outline SOT505-2 (TSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(1) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 0.95

0.75 0.38

0.22 0.18

0.08 3.1

2.9 3.1

2.9 0.65 4.1

3.9 0.70

0.35 8°

0°

0.13 0.10.20.5

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

0.47

0.33

SOT505-2 - - - 02-01-16

0.25

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2

1.1

pin 1 index

Product data sheet Rev. 11 — 4 June 2012 15 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Fig 12. Package outline SOT765-1 (VSSOP8)

UNIT A1

max. A2A3bpLHELpwyv

ceD(1) E(2) Z(1) θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.00 0.85

0.60 0.27

0.17 0.23

0.08 2.1

1.9 2.4

2.2 0.5 3.2

3.0 0.4

0.1 8°

0°

0.13 0.10.20.4

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

0.40

0.15

0.21

0.19

SOT765-1 MO-187 02-06-07

0.12

A2A1

(A3)

detail X

vMA

2.5 5 mm0

scale

VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1

pin 1 index

Product data sheet Rev. 11 — 4 June 2012 16 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Fig 13. Package outline SOT833-1 (XSON8)

terminal 1

index area

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT833-1 - - -

MO-252

- - -

SOT833-1

07-11-14

07-12-07

DIMENSIONS (mm are the original dimensions)

XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm

e1e1

0 1 2 mm

scale

Notes

1. Including plating thickness.

2. Can be visible in some manufacturing processes.

UNIT

mm 0.25

0.17 2.0

1.9 0.35

0.27

max b E

1.05

0.95

Dee

0.40

0.32

0.50.6

A(1)

max

0.5 0.04

8×

(2)

4×

(2)

Product data sheet Rev. 11 — 4 June 2012 17 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Fig 14. Package outline SOT1089 (XSON8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1089 MO-252

sot1089_po

10-04-09

10-04-12

Unit

mm max

nom

min

0.5 0.04 1.40

1.35

1.30

1.05

1.00

0.95 0.55 0.35 0.35

0.30

0.27

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1 x 0.5 mm SOT1089

A1bL

0.40

0.35

0.32

0.20

0.15

0.12

DEee

0 0.5 1 mm

scale

terminal 1

index area

detail X

terminal 1

index area

(4×)(2)

(8×)(2)

Product data sheet Rev. 11 — 4 June 2012 18 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Fig 15. Package outline SOT996-2 (XSON8U)

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

SOT996-2 - - -- - -

SOT996-2

07-12-18

07-12-21

UNIT A

max

mm 0.5 0.05

0.00 0.35

0.15 3.1

2.9 0.5 1.5 0.5

0.3 0.6

0.4 0.1 0.05

DIMENSIONS (mm are the original dimensions)

XSON8U: plastic extremely thin small outline package; no leads;

8 terminals; UTLP based; body 3 x 2 x 0.5 mm

0 1 2 mm

scale

b D

2.1

1.9

E e e1L L1

0.15

0.05

L2v w

0.05

y y1

0.1

eAC B

vMCw M

terminal 1

index area

B A

detail X

AA1

Product data sheet Rev. 11 — 4 June 2012 19 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Fig 16. Package outline SOT902-2 (XQFN8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT902-2 - - -

MO-255

- - -

sot902-2_po

10-11-02

11-03-31

Unit(1)

mm max

nom

min

0.5 0.05

0.00

1.65

1.60

1.55

1.65

1.60

1.55 0.55 0.5 0.15

0.10

0.05 0.1 0.05

Dimensions

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

XQFN8: plastic, extremely thin quad flat package; no leads;

8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2

A1b

0.25

0.20

0.15

DEee

0.35

0.30

0.25

L1vw

0.05

0 1 2 mm

scale

terminal 1

index area

terminal 1

index area

eAC B

vCw

metal area

not for soldering

detail X

Product data sheet Rev. 11 — 4 June 2012 20 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Fig 17. Package outline SOT1116 (XSON8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1116

sot1116_po

10-04-02

10-04-07

Unit

mm max

nom

min

0.35 0.04 1.25

1.20

1.15

1.05

1.00

0.95 0.55 0.3 0.40

0.35

0.32

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1

index area

(4×)(2)

(8×)(2) A1A

e1e1e1

4321

5678

Product data sheet Rev. 11 — 4 June 2012 21 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Fig 18. Package outline SOT1203 (XSON8)

References

Outline

version European

projection Issue date

IEC JEDEC JEITA

SOT1203

sot1203_po

10-04-02

10-04-06

Unit

mm max

nom

min

0.35 0.04 1.40

1.35

1.30

1.05

1.00

0.95 0.55 0.35 0.40

0.35

0.32

A(1)

Dimensions

Note

1. Including plating thickness.

2. Visible depending upon used manufacturing technology.

XSON8: extremely thin small outline package; no leads;

8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203

A1b

0.20

0.15

0.12

DEee

0.35

0.30

0.27

0 0.5 1 mm

scale

terminal 1

index area

(4×)(2)

(8×)(2)

e1e1e1

Product data sheet Rev. 11 — 4 June 2012 22 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

14. Abbreviations

15. Revision history

Table 12. Abbreviations

Acronym Description

CMOS Complementary Metal-Oxide Semiconductor

HBM Human Body Model

ESD ElectroStatic Discharge

MM Machine Model

DUT Device Under Test

TTL Transistor-Transistor Lo gic

Table 13. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC1G74 v.11 20120604 Product data sheet - 74LVC1G74 v.10

Modifications: •For type number 74LVC1G74GM the SOT code has changed to SOT902-2.

74LVC1G74 v.10 20111202 Product data sheet - 74LVC1G74 v.9

Modifications: •Legal pages updated.

74LVC1G74 v.9 20100805 Product data sheet - 74LVC1G74 v.8

74LVC1G74 v.8 20091203 Product data sheet - 74LVC1G74 v.7

74LVC1G74 v.7 20080626 Product data sheet - 74LVC1G74 v.6

74LVC1G74 v.6 20080219 Product data sheet - 74LVC1G74 v.5

74LVC1G74 v.5 20070809 Product data sheet - 74LVC1G74 v.4

74LVC1G74 v.4 20061207 Product data sheet - 74LVC1G74 v.3

74LVC1G74 v.3 20050201 Product specification - 74LVC1G74 v.2

74LVC1G74 v.2 20040909 Product specification - 74LVC1G74 v.1

74LVC1G74 v.1 20040202 Product specification - -

Product data sheet Rev. 11 — 4 June 2012 23 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

16. Legal information

16.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Definitions”.

[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

16.2 Definitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liab ility for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and tit le. A short data sh eet is intended

for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and

full information. For detailed and full information se e the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall pre vail.

Product specificatio n — The information and data provided in a Product

data sheet shall define the specification of the product as agreed be tween

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to off er functions and qualities beyond those described in the

Product data sheet.

16.3 Disclaimers

Limited warr a nty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information. NXP Se miconductors takes no

responsibility for the content in this document if provided by an inf ormation

source outside of NXP Semiconductors.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequ ential damages (including - wit hout limitatio n - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all informa tion supplied prior

to the publication hereof .

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-crit ical or

safety-critical systems or equipment, nor in app lications where failure or

malfunction of an NXP Semiconductors product can reasonably be expected

to result in perso nal injury, death or severe property or environmental

damage. NXP Semiconductors and its suppliers accept no liability for

inclusion and/or use of NXP Semiconducto rs products in such equipment or

applications and ther efore such inclu sion and/or use is at the cu stomer’s own

risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty tha t such application s will be suitable for the

specified use without further testing or modification.

Customers are responsible for the design and ope ration of their applications

and products using NXP Semiconductors product s, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suit able and fit for the custome r’s applications and

products planned, as well as fo r the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for th e customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings onl y and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanent ly and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individua l agreement. In case an individual

agreement is concluded only the ter ms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

No offer to sell or license — Nothing i n this document may be interpreted or

construed as an of fer t o sell product s that is open for accept ance or t he grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Document status[1][2] Product status[3] Definition

Objective [short] data sheet Development This document contains data from the objecti ve specification for product development.

Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.

Product [short] dat a sheet Production This document contains the product specification.

Product data sheet Rev. 11 — 4 June 2012 24 of 25

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product i s automotive qualified,

the product is not suitable for automo tive use. It i s neit her qualif ied nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automot ive specifications and standard s, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed produ ct claims result ing from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

16.4 Trademarks

Notice: All referenced b rands, produc t names, service names and trademarks

are the property of their respect i ve ow ners.

17. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

NXP Semiconductors 74LVC1G74

Single D-type flip-flop with set and reset; positive edge trigger

For more information, please visit: http://www.nxp.co m

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 June 2012

Document identifier: 74LVC1G74

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

18. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2

4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3

6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5

7 Functional description . . . . . . . . . . . . . . . . . . . 5

8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6

9 Recommended operating conditions. . . . . . . . 6

10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7

11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 9

12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14

14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 22

15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 22

16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 23

16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 23

16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 23

16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 24

17 Contact information. . . . . . . . . . . . . . . . . . . . . 24

18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25