PLL 6 Contents PLL2013X ............................................................................................................................ 6-1 PLL2013X General Description Features The PLL2013X is a Phase-Locked Loop (PLL) Frequency Synthesizer constructed in CMOS on single monolithic structure. The PLL macrofunctions provide frequency multiplication capabilities. The output clock frequency Fout is related to the reference input clock frequency Fin (XTALIN) by the following equation: * 0.25m CMOS device technology * 2.5V single power supply * Output frequency range: 20-170MHz * Jitter: 150 ps at 170MHz * Duty ratio: 45% to 55% (All tuned range) * Frequency changed by programmable dividers Fout = (m x Fin) / (p x 2s) * Provision for 14.318MHz crystal oscillator buffer (option) Where, Fout is the output clock frequency. Fin is the reference input clock frequency. m, p and s are the values for programmable dividers. PLL2013X consists of a Phase/Frequency Detector (PFD), a Charge Pump, an External Loop Filter, a Voltage Controlled Oscillator (VCO), a 6-bit Pre-divider, an 8-bit Main divider and a 2-bit Post Scaler as shown in Figure 6-1 * Lock detector (option) * Power down mode Block Diagram Figure 6-1 Fin Phase Locked Loop Block Diagram Pre-Divider P PFD Charge Pump Loop Filter (External) VCO Post Scaler S FOUT Main Divider M NOTE: X-tal oscillator and Lock detector are optional block. If customer concerns about this block - xtal buffer or lock detector, refer to next chapter. Samsung ASIC 6-1 STDM110 PLL2013X 20 MHz-170MHz FSPLL Pin Description NAME VDDD VSSD VDDA VSSA VBB I/O PAD vddd vssd vdda vssa vbba FIN FILTER I/O TYPE Digital Power Digital Ground Analog Power Analog Ground Analog sub bias /Digital sub bias Digital Input Analog Output FOUT PWRDN Digital Output Digital Input pot8_bb pic_bb P[5:0] M[7:0] S[1:0] Digital Input Digital Input Digital Input pic_bb pic_bb pic_bb Figure 6-2 pic_bb poa_bb PIN DESCRIPTION Digital power supply Digital ground Analog power supply Analog ground Analog / Digital sub bias Reference Frequency Input Pump out is connected to Filter. A capacitor is connected between the pin and analog ground. 20MHz~170MHz clock output FSPLL clock power down. - When PWRDN is High, PLL do not operate. - If PWRDN is not used, it should be tied to VSS. The values for 6bit programmable pre-divider. The values for 8bit programmable main divider. The values for 2bit programmable post scaler. Core Configuration FIN PWRDN M[7:0] P[5:0] S[1:0] STDM110 M[0] M[1] M[2] M[3] M[4] M[5] M[6] M[7] FOUT pll2013x P[0] P[1] P[2] P[3] P[4] P[5] FILTER S[0] S[1] 6-2 Samsung ASIC 20 MHz-170MHz FSPLL PLL2013X Absolute Maximum Ratings (Ta=25C) Characteristics Supply voltage Voltage on any digital pin Operating temperature Storage temperature Symbol VDDD, VDDA Value Unit 3.3 V Vin VSSD-0.25 to VDDD+0.25 V Topr Tstg 0 to 70 -45 to 125 C C Applicable Pin VDDD,VDDA,VSSD, VSSA,VBB P[5:0],M[7:0],S[1:0] PWRDN - NOTES: 1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Each condition value is applied with the other values kept within the following operating conditions and function operation under any of these conditions is not implied. 2. All voltages are measured with respect to VSS unless otherwise specified. 3. 100pF capacitor is discharged through a 1.5k resistor (human body model) Recommended Operating Conditions Characteristics Supply voltage Oscillator frequency External loop filter capacitance Operating temperature Symbol VDDD - VDDA Fosc LF Topr Min -0.1 Typ Max +0.1 14.318 820 0 70 Unit V MHz pF C NOTE: It is strongly recommended that all the supply pins (VDDA, VDDD) be powered from the same operating supply voltage to avoid power latch-up. Samsung ASIC 6-3 STDM110 PLL2013X 20 MHz-170MHz FSPLL DC Electrical Characteristics Characteristics Operating voltage Digital input voltage high Digital input voltage low Dynamic current Power down current Symbol VDDD/VDDA VIH VIL Idd Ipd Min 2.375 2.0 Typ 2.5 Max 2.625 0.8 3 50 Unit V V V mA A AC Electrical Characteristics Characteristics Crystal frequency Input Frequency Output clock frequency Input clock duty cycle Output clock duty cycle (at 170MHz) Input glitch pulse width Locking time Jitter, cycle to cycle Symbol FXTAL FIN FOUT TID Min 5 20 40 40 170 60 Unit MHz MHz Mhz % TOD 45 55 % TIGP TLT TJCC 1 150 +150 ns s ps -150 Typ 14.318 Max NOTE: It is strongly recommended that input signal is not generated glitch, but if customer cannot help generating glitch, customer must carefully considerate the specification. STDM110 6-4 Samsung ASIC 20 MHz-170MHz FSPLL PLL2013X Functional Description A PLL is the circuit synchronizing an output signal (generated by an VCO) with a reference or input signal in frequency as well as in phase. In this application, it includes the following basic blocks. -- The voltage-controlled oscillator to generate the output frequency -- The divider P divides the reference frequency by p -- The divider M divides the VCO output frequency by m -- The divider S divides the VCO output frequency by s -- The phase frequency detector detects the phase difference between the reference frequency and the output frequency (after division) and controls the charge pump voltage. -- The loop filter removes the high frequency components in charge pump voltage and gives smooth and clean control to VCO The m, p, s values can be programmed by 16bit digital data from the external source. So the PLL can be locked in the desired frequency. Fout = (m x Fin) / (p x s) where Fin = 14.318 MHz, m = M + 8, p = P + 2, s = 2S Table 6-1 Digital Data Format Main Divider M7, M6, M5, M4, M3, M2, M1, M0 Pre Divider P5, P4, P3, P2, P1, P0 Post Scaler S1, S0 NOTES: 1. S[1]-S[0]: Output frequency scaler 2. M[7]-M[0]: VCO frequency divider 3. P[5]-P[0]: Reference frequency input divider Samsung ASIC 6-5 STDM110 PLL2013X 20 MHz-170MHz FSPLL OUTPUT FREQUENCY EQUATION & TABLE ( M + 8) Frequency equation: FOUT = ----------------------------s- x FIN ( P + 2) x 2 Table 6-2 M7 0 P6 0 M6 1 P5 1 Example of Divider Ratio M5 M4 M3 M2 0 1 0 1 P4 P3 P2 P1 0 1 0 1 M1 0 P0 0 M0 1 P 42 M 85 p(P+2) 44 m(M+8) 93 S1 0 2S 1 S0 0 CORE EVALUATION GUIDE For the embedded PLL, we must consider the test circuits for the embedded PLL core in multiple applications. Hence the following requirements should be satisfied. -- -- The FILTER and FOUT pins must be bypassed for external test. For PLL test (below 2 examples), it is needed to control the dividers - M[7:0], P[5:0] and S[1:0] that generate multiple clocks. #1. Registers can be used for easy control of divider values. #2. N sample bits of 16-bit divider pins can be bypassed for test using MUX. Figure 6-3 PLL Functional Block Diagram 2.5V Digital Power 2.5V Analog Power GND External Clock Source GND FIN VDDD VSSD VDDA VSSA VBB PWRDN M[7:0] FOUT #1. 16-Bit Register Block pll2013x P[5:0] FILTER S[1:0] 820pF VSSA Test Pins of N Sample Bits #2. MUX Select Pin : 10F electronic capacitor, unless otherwise specified : 104 ceramic capacitor, unless otherwise specified Internal Divider Signal Line STDM110 6-6 Samsung ASIC 20 MHz-170MHz FSPLL Figure 6-4 PLL2013X The example of PLL block with dedicated 14.318 MHz XTAL-OSC FILTER up LDOUT FOUT LD down XTALIN XTAL OSC Fin XTALOUT PFD & CP Divider P LF VCO Scaler S Glue Logic PWRDN P[5:0] M[7:0] S[1:0] Divider M MUX *Divider Bus * Optional Test Pin XTAL Buffer Cell Figure 6-5 XTAL PAD Symbol E YN PADA PI PO PADB - A XTAL Buffer cell for PLL is supported MDL111 databook of SEC The XTAL must be located between PADA and PADB. Enable pin (E) must be HIGH in normal operation. PI pin must be connected to VDDD and the PO pin floated. Lock Detector Figure 6-6 Lock Detector Block Internal Up Signal LDOUT LS Internal Down Signal Lock State Detector LO The built-in lock detector circuit will only work, when it is used in conjunction with PFD block output up/down Samsung ASIC 6-7 STDM110 PLL2013X 20 MHz-170MHz FSPLL signal. (refer to Figure 6-6) We represent the output of lock detector in the timing diagram. (refer to Figure 6-7) Figure 6-7 Lock Detector Timing Diagram Up/Down LO LDOUT Unlock Lock PACKAGE CONFIGURATION 2.5V I/O Power C 36 35 34 33 32 31 30 29 28 27 26 25 VSSD SO S1 TST5 TST4 VDDO VSSO NC NC H VSSD H VDDD 8-bit Main Divider 2-bit Post Scaler L L VDDD 2.5V Digital Power C NC 24 L H 37 M0 L H 38 M1 L H 39 M2 L H 40 M3 L H 41 M4 L H 42 M5 L H 43 M6 L H 44 M7 FILTER 17 L H 45 P0 XTALOUT 16 L H 46 P1 XTALIN 15 L H 47 P2 VDDA 14 P3 VDDA 13 NC 21 VBB 20 VBB 19 C PWRDN 18 104 10F H L 820pF 25pF External Clock Source 25pF TST2 TST3 NC NC NC NC LDOUT VSSA VSSA C TST1 48 6-bit Pre Divider Input STDM110 pll2013x P5 H NC 22 P4 L FOUT 23 1 2 3 4 5 6 7 8 9 10 11 12 H H L C L C 2.5V Analog Power 6-8 2.5V Analog Power Samsung ASIC 20 MHz-170MHz FSPLL PLL2013X PACKAGE PIN DESCRIPTION NAME VDDD VSSD VBB PWRDN PIN No. 35,36 33,34 19,20 18 I/O TYPE DP DG AB/DB DI P[0]~P[5] VDDA VSSA XTALIN XTALOUT FOUT LDOUT FILTER 45~48,1,2 13,14 11,12 15 16 23 10 17 DI AP AG AI AO DO DO AO S[0]~S[1] M[0]~M[7] VDDO VSSO 32,31 37~44 28 27 DI DI PP PG PIN DESCRIPTION Digital power supply Digital ground Analog / digital sub bias FSPLL clock power down. - When PWRDN is High, PLL do not operate. - If PWRDN is not used, it should be tied to VSS. Pre-divider input Analog power supply Analog ground Crystal external clock input Xtal buffer output clock 20MHZ~170MHz clock output Lock detector output Pump out is connected to the Filter. A 900pF Capacitor is connected between the pin and analog pin Post scaler input 8-bit main divider input I/O pad power I/O pad power NOTES: 1. I/O TYPE PP and PG denote PAD power and PAD ground respectively. 2. XTALIN, XTALOUT, LDOUT is test pin for PLL in Samsung. Samsung ASIC 6-9 STDM110 PLL2013X 20 MHz-170MHz FSPLL PLL Components Figure 6-8 is the block diagram of the components of a PLL: the phase detector, charge pump, voltage controlled oscillator, and loop filter. In Samsung technology, the loop filter is implemented as external components close to the chip. Figure 6-8 PLL Functional Block Diagram XTALIN XTALOUT XTAL OSC DIVIDER P Fref PFD PUMP R,C2: Internal C1: External Fvco P[5:0] FILTER DIVIDER M M[7:0] Voltage Controlled Oscillator R DIVIDER S S[1:0] C1 FOUT C2 PWRDN Phase detector: The phase detector monitors the phase difference between the Fref and Fvco, and generates a control signal when it detects difference between the two. If the Fref frequency is higher then the Fvco frequency, its falling edge occurs before (lead) the falling edge of the Fvco output. When this occurs the phase detector signals the VCO to increase the frequency of the on-chip clock. If the falling edge of the Fref occurs after (lag) the falling edge of the Fvco output, the detector signals the VCO to decrease on-chip clock frequency. Figure 6-9 illustrates the lead and lag conditions. If the frequencies of the Fref and Fvco are the same, the detect or does not generate a control signal, so the frequencies remain the same. Figure 6-9 Lead and Lag Clocking Relationship Fref CLK Fvco CLK UP DOWN Charge Pump: The charge pump converts the phase detector control signal to a charge in voltage across the external filter that drives the VCO. As the Voltage Controlled Oscillator decreases, or increases, If the voltage remains constant, the frequency of the oscillator remains constant. STDM110 6-10 Samsung ASIC 20 MHz-170MHz FSPLL PLL2013X Loop Filter: The control signal that the phase detector generates for the charge pump may generate large excursions (ripples) each time the VCO output is compared to the system clock. To avoid overloading the VCO, a low pass filter samples and filters the high-frequency components out of the control signal. The filter is typically a single-pole RC filter consisting of a resistor and capacitor. Voltage Controlled Oscillator (VCO): The output voltage from the loop filter drives the VCO, causing its oscillation frequency to increase or decrease as a function of variations in voltage. When the VCO output matches the system clock in frequency and phase, the phase detector stops sending a control signal to the charge pump, which in turn stabilizes the input voltage to the loop filter. The VCO frequency then remains constant, and the PLL remains locked onto the system clock. Frequency Synthesis Frequency synthesis uses the system clock as a base frequency to generate higher/lower frequency clocks for internal logic. For high speed applications in high-end designs, transmission line effects cause problems because of parasitic and impedance mismatch among various on-board components. These problems can be eliminated by moving the high frequency to the chip level. On-chip clocks that are faster than the external system clock can be synthesized by inserting a divider in the feedback path. The divider is placed after voltage controlled oscillator, as illustrated in Figure 6-11. The signal is running at M times the system clock frequency, so the PLL matches the divider signal output to the system clock. This configuration reduces the problem of interfacing to the system clock on the board, and it reduces the noise generated by the system clock oscillator and driver for all the components in the system. Design Considerations The following design considerations apply: * Phase tolerance and jitter are independent of the PLL frequency. * Jitter is affected by the noise frequency in the power (VDDD/VSSD, VDDA/VSSA). It increases when the noise level increases. * A CMOS-level input reference clock is recommend for signal compatibility with the PLL circuit. Other levels such as TTL may degrade the tolerances. * The used of two, or more PLLs requires special design considerations. Please consult your application engineer for more information. * The following apply to the noise level, which can be minimized by using good analog power and ground isolation techniques in the system: - Use wide PCB traces for POWER (VDDD/VSSD, VDDA/VSSA, VBB) connections to the PLL core. - Separate the traces from the chip's VDDD/VSSD, VDDA/VSSA supplies. - Use proper VDDD/VSSD, VDDA/VSSA de-coupling. - Use good power and ground sources on the board. - Use power VBB for minimize substrate noise. * The PLL core should be placed as close as possible to the dedicated loop filter and analog power and ground pins. * It is inadvisable to locate noise-generating signals, such as data buses and high-current outputs, near the PLL I/O cells. * Other related I/O signals should be placed near the PLL I/O but do not have any pre-defined placement restriction. Samsung ASIC 6-11 STDM110 20 MHz-170MHz FSPLL PLL2013X PLL Specification We appreciate your interest in our products. If you have further questions, please specify in the attached form. Thank you very much. Parameter Min Typ Max Unit Remarks Supply voltage Output frequency range Input frequency range Cycle-to-cycle jitter Lock up time Dynamic current Standby current Output clock duty ratio Long term jitter Output slew rate * Do you need XTAL driver buffer in PLL core? If you need it, what is the crystal frequency range? If not, What is the input frequency range? * Do you need the lock detector? * Do you need the I/O cell of Samsung? * Do you need the external pin for PLL test? * What is the main frequency and frequency range? * How many FSPLLs do you use in your system? * What is output loading? * Could you internal/external pin configurations as required? * Specially requested function list: Samsung ASIC 6-12 STDM110