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Date Description Page 1.00 Dec 19, 2003 4524 Group User's Manual - 2.00 Aug 06, 2004 All pages 1-5 1-6 1-35 1-45 1-46 1-47 1-61 1-65 1-69 1-78 2-57 2-74 2-77 3-47 Summary First edition issued Words standardized: On-chip oscillator, A/D converter Power dissipation revised. ____________ Description of RESET pin revised. Fig.26 : Note 9 added. Some description revised. Fig.31: "DI" instruction added. Table 11:Revised. (5) LCD power supply circuit revised. Fig.51: State of quartz-crystal oscillator added. Fig.55: * Note 5 added, * "T5F" added to the transitions between from state E to states B, A, C and D * "Key-on wakeup""Wakeup" Note on Power source Voltage added. Table 2.5.1 : Notes 4 revised. Fig.2.7.4: State of quartz-crystal oscillator added. Fig.2.9.1: * Note 5 added, * "T5F" added to the transitions between from state E to states B, A, C and D * "Key-on wakeup""Wakeup" Note on Power source Voltage added. BEFORE USING THIS USER'S MANUAL This user's manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers. CHAPTER 3 APPENDIX This chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the list of registers. As for the Mask ROM confirmation form, the ROM programming confirmation form, and the Mark specification form which are to be submitted when ordering, refer to the "Renesas Technology Corp." Hompage (http:/ /www.renesas.com/en/rom). As for the Development tools and related documents, refer to the Product Info - 4524 Group (http:// www.renesas.com/eng/products/mpumcu/specific/lcd_mcu/expand/e4524.htm) of "Renesas Technology Corp." Homepage. Table of contents 4524 Group Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................... 2 FEATURES ......................................................................................................................................... 2 APPLICATION ................................................................................................................................... 2 PIN CONFIGURATION ..................................................................................................................... 3 BLOCK DIAGRAM ............................................................................................................................ 4 PERFORMANCE OVERVIEW .......................................................................................................... 5 PIN DESCRIPTION ........................................................................................................................... 6 MULTIFUNCTION ........................................................................................................................ 7 DEFINITION OF CLOCK AND CYCLE .................................................................................... 7 PORT FUNCTION ....................................................................................................................... 8 CONNECTIONS OF UNUSED PINS ........................................................................................ 9 PORT BLOCK DIAGRAMS ...................................................................................................... 10 FUNCTION BLOCK OPERATIONS .............................................................................................. 18 CPU ............................................................................................................................................. 18 PROGRAM MEMORY (ROM) .................................................................................................. 21 DATA MEMORY (RAM) ............................................................................................................ 22 INTERRUPT FUNCTION .......................................................................................................... 23 EXTERNAL INTERRUPTS ....................................................................................................... 27 TIMERS ...................................................................................................................................... 32 WATCHDOG TIMER ................................................................................................................. 45 A/D CONVERTER (COMPARATOR) ...................................................................................... 47 SERIAL I/O ................................................................................................................................. 53 LCD FUNCTION ........................................................................................................................ 57 RESET FUNCTION ................................................................................................................... 62 VOLTAGE DROP DETECTION CIRCUIT .............................................................................. 66 POWER DOWN FUNCTION .................................................................................................... 67 CLOCK CONTROL .................................................................................................................... 72 ROM ORDERING METHOD .......................................................................................................... 74 LIST OF PRECAUTIONS ............................................................................................................... 75 CONTROL REGISTERS ................................................................................................................. 79 INSTRUCTIONS ............................................................................................................................... 86 SYMBOL ..................................................................................................................................... 86 INDEX LIST OF INSTRUCTION FUNCTION ........................................................................ 87 MACHINE INSTRUCTIONS (INDEX BY ALPHABET) .......................................................... 92 MACHINE INSTRUCTIONS (INDEX BY TYPES) (CONTINUED) ..................................... 132 INSTRUCTION CODE TABLE ............................................................................................... 148 BUILT-IN PROM VERSION ......................................................................................................... 150 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z i Table of contents 4524 Group CHAPTER 2 APPLICATION 2.1 I/O pins ....................................................................................................................................... 2 2.1.1 I/O ports ............................................................................................................................. 2 2.1.2 Related registers ............................................................................................................... 5 2.1.3 Port application examples .............................................................................................. 13 2.1.4 Notes on use ................................................................................................................... 14 2.2 Interrupts .................................................................................................................................. 16 2.2.1 Interrupt functions ........................................................................................................... 16 2.2.2 Related registers ............................................................................................................. 19 2.2.3 Interrupt application examples ....................................................................................... 22 2.2.4 Notes on use ................................................................................................................... 32 2.3 Timers ....................................................................................................................................... 33 2.3.1 Timer functions ................................................................................................................ 33 2.3.2 Related registers ............................................................................................................. 34 2.3.3 Timer application examples ........................................................................................... 39 2.3.4 Notes on use ................................................................................................................... 49 2.4 A/D converter .......................................................................................................................... 50 2.4.1 Related registers ............................................................................................................. 51 2.4.2 A/D converter application examples ............................................................................. 52 2.4.3 Notes on use ................................................................................................................... 54 2.5 Serial I/O ................................................................................................................................... 56 2.5.1 Carrier functions .............................................................................................................. 56 2.5.2 Related registers ............................................................................................................. 57 2.5.3 Operation description ...................................................................................................... 59 2.5.4 Serial I/O application example ...................................................................................... 62 2.5.5 Notes on use ................................................................................................................... 65 2.6 LCD function ............................................................................................................................ 66 2.6.1 Operation description ...................................................................................................... 66 2.6.2 Related registers ............................................................................................................. 67 2.6.3 LCD application examples ............................................................................................. 69 2.6.4 Notes on use ................................................................................................................... 71 2.7 Reset .......................................................................................................................................... 72 2.7.1 Reset circuit ..................................................................................................................... 72 2.7.2 Internal state at reset ..................................................................................................... 73 2.7.3 Notes on use ................................................................................................................... 74 2.8 Voltage drop detection circuit ............................................................................................. 75 2.8.1 Note on use ..................................................................................................................... 76 2.9 Power down ............................................................................................................................. 77 2.9.1 Power down mode .......................................................................................................... 78 2.9.2 Related registers ............................................................................................................. 81 2.9.3 Power down function application example .................................................................. 85 2.9.4 Notes on use ................................................................................................................... 86 2.10 Oscillation circuit ................................................................................................................. 87 2.10.1 Oscillation circuit ........................................................................................................... 87 2.10.2 Oscillation operation ..................................................................................................... 89 2.10.3 Related register ............................................................................................................. 90 2.10.4 Notes on use ................................................................................................................. 90 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z ii Table of contents 4524 Group CHAPTER 3 APPENDIX 3.1 Electrical characteristics ........................................................................................................ 2 3.1.1 Absolute maximum ratings ............................................................................................... 2 3.1.2 Recommended operating conditions ............................................................................... 3 3.1.3 Electrical characteristics ................................................................................................... 5 3.1.4 A/D converter recommended operating conditions ....................................................... 7 3.1.5 Voltage drop detection circuit characteristics ................................................................ 8 3.1.6 Basic timing diagram ........................................................................................................ 8 3.2 Typical characteristics ............................................................................................................ 9 3.2.1 V DD-IDD characteristics ...................................................................................................... 9 3.2.2 Frequency characteristics ............................................................................................... 15 3.2.3 Port typical characteristics (V DD = 5.0 V) .................................................................... 18 3.2.4 Port typical characteristics (V DD = 3.0 V) .................................................................... 21 3.2.5 Input threshold characteristics ....................................................................................... 24 3.2.6 Pull-up resistor: VDD-RPU characteristics example .................................................... 27 3.2.7 Internal resistor for LCD power: Ta-RVLC ................................................................. 28 3.2.8 A/D converter typical characteristics ............................................................................ 29 3.2.9 Analog input current characteristics example ............................................................. 32 3.2.10 A/D converter operation current (V DD-I ADD) characteristics ...................................... 36 3.2.11 Voltage drop detection circuit characteristics ........................................................... 36 3.3 List of precautions ................................................................................................................. 38 3.3.1 Program counter .............................................................................................................. 38 3.3.2 Stack registers (SKs) ...................................................................................................... 38 3.3.3 Notes on I/O port ............................................................................................................ 38 3.3.4 Notes on interrupt ........................................................................................................... 41 3.3.5 Notes on timer ................................................................................................................. 42 3.3.6 Notes on A/D conversion ............................................................................................... 43 3.3.7 Notes on serial I/O ......................................................................................................... 44 3.3.8 Notes on LCD function ................................................................................................... 45 3.3.9 Notes on reset ................................................................................................................. 45 3.3.10 Notes on voltage drop detection circuit ..................................................................... 45 3.3.11 Notes on power down .................................................................................................. 46 3.3.12 Notes on oscillation circuit ........................................................................................... 47 3.3.13 Electric characteristic differences between Mask ROM and One Time PROM version MCU ... 47 3.3.14 Notes on Power Source Voltage ................................................................................ 47 3.4 Notes on noise ........................................................................................................................ 48 3.4.1 Shortest wiring length ..................................................................................................... 48 3.4.2 Connection of bypass capacitor across V SS line and V DD line .................................. 50 3.4.3 wiring to analog input pins ............................................................................................ 51 3.4.4 Oscillator concerns .......................................................................................................... 51 3.4.5 setup for I/O ports .......................................................................................................... 52 3.4.6 providing of watchdog timer function by software ...................................................... 52 3.5 Package outline ...................................................................................................................... 54 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z iii List of figures 4524 Group List of figures CHAPTER 1 HARDWARE Pin configuration (top view) (4524 Group) .................................................................................... 3 Block diagram (4524 Group) ........................................................................................................... 4 Port block diagram (1) .................................................................................................................... 10 Port block diagram (2) .................................................................................................................... 11 Port block diagram (3) .................................................................................................................... 12 Port block diagram (4) .................................................................................................................... 13 Port block diagram (5) .................................................................................................................... 14 Port block diagram (6) .................................................................................................................... 15 Port block diagram (7) .................................................................................................................... 16 Port block diagram (8) .................................................................................................................... 17 Fig. 1 AMC instruction execution example .................................................................................. 18 Fig. 2 RAR instruction execution example .................................................................................. 18 Fig. 3 Registers A, B and register E ........................................................................................... 18 Fig. 4 TABP p instruction execution example ............................................................................. 18 Fig. 5 Stack registers (SKs) structure .......................................................................................... 19 Fig. 6 Example of operation at subroutine call .......................................................................... 19 Fig. 7 Program counter (PC) structure ........................................................................................ 20 Fig. 8 Data pointer (DP) structure ................................................................................................ 20 Fig. 9 SD instruction execution example ..................................................................................... 20 Fig. 10 ROM map of M34524ED .................................................................................................. 21 Fig. 11 Page 1 (addresses 008016 to 00FF 16) structure ............................................................ 21 Fig. 12 RAM map ............................................................................................................................ 22 Fig. 13 Program example of interrupt processing ...................................................................... 24 Fig. 14 Internal state when interrupt occurs ............................................................................... 24 Fig. 15 Interrupt system diagram .................................................................................................. 24 Fig. 16 Interrupt sequence ............................................................................................................. 26 Fig. 17 External interrupt circuit structure ................................................................................... 27 Fig. 18 External 0 interrupt program example-1 ......................................................................... 30 Fig. 19 External 0 interrupt program example-2 ......................................................................... 30 Fig. 20 External 0 interrupt program example-3 ......................................................................... 30 Fig. 21 External 1 interrupt program example-1 ......................................................................... 31 Fig. 22 External 1 interrupt program example-2 ......................................................................... 31 Fig. 23 External 1 interrupt program example-3 ......................................................................... 31 Fig. 24 Auto-reload function .......................................................................................................... 32 Fig. 25 Timer structure (1) ............................................................................................................ 34 Fig. 26 Timer structure (2) ............................................................................................................ 35 Fig. 27 Timer 4 operation (reload register R4L: "03 16", R4H: "0216") ...................................... 42 Fig. 28 CNTR1 output auto-control function by timer 3 ............................................................ 43 Fig. 29 Timer 4 count start/stop timing ....................................................................................... 44 Fig. 30 Watchdog timer function ................................................................................................... 45 Fig. 31 Program example to start/stop watchdog timer ............................................................ 46 Fig. 32 Program example to enter the mode when using the watchdog timer ..................... 46 Fig. 33 A/D conversion circuit structure ...................................................................................... 47 Fig. 34 A/D conversion timing chart ............................................................................................. 50 Fig. 35 Setting registers ................................................................................................................. 50 Fig. 36 Comparator operation timing chart .................................................................................. 51 Fig. 37 Definition of A/D conversion accuracy ........................................................................... 52 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z iv List of figures 4524 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 69 70 71 72 73 74 75 76 77 Serial I/O structure ............................................................................................................ 53 Serial I/O register state when transfer ........................................................................... 54 Serial I/O connection example ......................................................................................... 55 Timing of serial I/O data transfer .................................................................................... 55 LCD clock control circuit structure .................................................................................. 57 LCD controller/driver ......................................................................................................... 58 LCD RAM map ................................................................................................................... 59 LCD controller/driver structure ......................................................................................... 60 LCD power source circuit example (1/3 bias condition selected) .............................. 61 Reset release timing ......................................................................................................... 62 RESET pin input waveform and reset operation .......................................................... 62 Structure of reset pin and its peripherals, and power-on reset operation ................ 63 Internal state at reset ....................................................................................................... 64 Internal state at reset ....................................................................................................... 65 Voltage drop detection reset circuit ................................................................................ 66 Voltage drop detection circuit operation waveform ....................................................... 66 VDD and VRST ............................................................................................................................................................................................................... 66 State transition ................................................................................................................... 69 Set source and clear source of the P flag .................................................................... 69 Start condition identified example using the SNZP instruction ................................... 69 Clock control circuit structure .......................................................................................... 72 Switch to ceramic oscillation/RC oscillation ................................................................... 73 Handling of X IN and X OUT when operating on-chip oscillator ....................................... 73 Ceramic resonator external circuit .................................................................................. 73 External RC oscillation circuit .......................................................................................... 73 External clock input circuit ............................................................................................... 74 External quartz-crystal circuit ........................................................................................... 74 External 0 interrupt program example-1 ......................................................................... 76 External 0 interrupt program example-2 ......................................................................... 76 External 0 interrupt program example-3 ......................................................................... 76 External 1 interrupt program example-2 ......................................................................... 77 External 1 interrupt program example-3 ......................................................................... 77 A/D converter program example-3 .................................................................................. 77 Analog input external circuit example-1 ......................................................................... 78 Analog input external circuit example-2 ......................................................................... 78 VDD and VRST ............................................................................................................................................................................................................... 78 Pin configuration of built-in PROM version ................................................................. 150 PROM memory map ........................................................................................................ 151 Flow of writing and test of the product shipped in blank .......................................... 151 CHAPTER 2 APPLICATION Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.1.1 2.1.2 2.2.1 2.2.2 2.2.3 2.2.4 2.2.5 2.2.6 2.2.7 2.2.8 2.2.9 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Key input by key scan .................................................................................................. 13 Key scan input timing ................................................................................................... 13 External 0 interrupt operation example ...................................................................... 23 External 0 interrupt setting example .......................................................................... 24 External 1 interrupt operation example ...................................................................... 25 External 1 interrupt setting example .......................................................................... 26 Timer 1 constant period interrupt setting example ................................................... 27 Timer 2 constant period interrupt setting example ................................................... 28 Timer 3 constant period interrupt setting example ................................................... 29 Timer 4 constant period interrupt setting example ................................................... 30 Timer 5 constant period interrupt setting example ................................................... 31 v List of figures 4524 Group Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 2.3.1 Peripheral circuit example ............................................................................................ 39 2.3.2 Timer 4 operation .......................................................................................................... 40 2.3.3 Watchdog timer function ............................................................................................... 41 2.3.4 Constant period measurement setting example ........................................................ 42 2.3.5 CNTR 0 output setting example .................................................................................... 43 2.3.6 CNTR 0 input setting example ...................................................................................... 44 2.3.7 Timer start by external input setting example .......................................................... 45 2.3.8 PWM output control setting example ......................................................................... 46 2.3.9 Constant period counter by timer 5 setting example ............................................... 47 2.3.10 Watchdog timer setting example ............................................................................... 48 2.4.1 A/D converter structure ................................................................................................ 50 2.4.2 A/D conversion mode setting example ....................................................................... 53 2.4.3 Analog input external circuit example-1 ..................................................................... 54 2.4.4 Analog input external circuit example-2 ..................................................................... 54 2.4.5 A/D converter operating mode program example ..................................................... 54 2.5.1 Serial I/O block diagram .............................................................................................. 56 2.5.2 Serial I/O connection example .................................................................................... 59 2.5.3 Serial I/O register state when transfer ....................................................................... 59 2.5.4 Serial I/O transfer timing .............................................................................................. 60 2.5.5 Setting example when a serial I/O of master side is not used ............................. 63 2.5.6 Setting example when a serial I/O interrupt of slave side is used ....................... 64 2.6.1 LCD clock control circuit structure .............................................................................. 66 2.6.2 LCD RAM map .............................................................................................................. 67 2.6.3 LCD display panel example ......................................................................................... 69 2.6.4 Segment assignment example ..................................................................................... 69 2.6.5 LCD RAM assignment example .................................................................................. 69 2.6.6 Initial setting example ................................................................................................... 70 2.7.1 Structure of reset pin and its peripherals,, and power-on reset operation ........... 72 2.7.2 Oscillation stabilizing time after system is released from reset ............................. 72 2.7.3 Internal state at reset ................................................................................................... 73 2.7.4 Internal state at reset ................................................................................................... 74 2.8.1 Voltage drop detection circuit ...................................................................................... 75 2.8.2 Voltage drop detection circuit operation waveform example .................................. 75 2.8.3 V DD and V RST ....................................................................................................................................................................................................... 76 2.9.1 State transition ............................................................................................................... 77 2.9.2 Start condition identified example ............................................................................... 80 2.9.3 Software setting example ............................................................................................. 85 2.10.1 Switch to ceramic oscillation/RC oscillation ............................................................ 87 2.10.2 Handling of X IN and X OUT when operating on-chip oscillator ................................. 87 2.10.3 Ceramic resonator external circuit ............................................................................ 88 2.10.4 External RC oscillation circuit ................................................................................... 88 2.10.5 External clock input circuit ......................................................................................... 88 2.10.6 External quartz-crystal circuit .................................................................................... 88 2.10.7 Structure of clock control circuit ............................................................................... 89 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z vi List of figures 4524 Group CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 3.2.1 A/D conversion characteristics data ........................................................................... 29 3.3.1 Analog input external circuit example-1 ..................................................................... 43 3.3.2 Analog input external circuit example-2 ..................................................................... 43 3.3.3 A/D converter operating mode program example ..................................................... 43 3.3.4 V DD and V RST ....................................................................................................................................................................................................... 45 3.4.1 Selection of packages .................................................................................................. 48 3.4.2 Wiring for the RESET input pin .................................................................................. 48 3.4.3 Wiring for clock I/O pins .............................................................................................. 49 3.4.4 Wiring for CNV SS pin ..................................................................................................... 49 3.4.5 Wiring for the V PP pin of the built-in PROM version ................................................ 50 3.4.6 Bypass capacitor across the V SS line and the V DD line ........................................... 50 3.4.7 Analog signal line and a resistor and a capacitor ................................................... 51 3.4.8 Wiring for a large current signal line ......................................................................... 51 3.4.9 Wiring to a signal line where potential levels change frequently .......................... 52 3.4.10 V SS pattern on the underside of an oscillator ......................................................... 52 3.4.11 Watchdog timer by software ...................................................................................... 53 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z vii List of tables 4524 Group List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Selection of system clock ..................................................................................................... 7 1 ROM size and pages ....................................................................................................... 21 2 RAM size ........................................................................................................................... 22 3 Interrupt sources ............................................................................................................... 23 4 Interrupt request flag, interrupt enable bit and skip instruction ................................. 23 5 Interrupt enable bit function ............................................................................................ 23 6 Interrupt control registers ................................................................................................ 25 7 External interrupt activated conditions ........................................................................... 27 8 External interrupt control register ................................................................................... 29 9 Function related timers .................................................................................................... 33 10 Timer related registers ................................................................................................... 36 11 A/D converter characteristics ........................................................................................ 47 12 A/D control registers ...................................................................................................... 48 13 Change of successive comparison register AD during A/D conversion ................. 49 14 Serial I/O pins ................................................................................................................. 53 15 Serial I/O control register .............................................................................................. 53 16 Processing sequence of data transfer from master to slave ................................... 56 17 Duty and maximum number of displayed pixels ........................................................ 57 18 LCD control registers ..................................................................................................... 59 19 Port state at reset .......................................................................................................... 63 20 Voltage drop detection circuit operation state ............................................................ 66 21 Functions and states retained at power down ........................................................... 67 22 Return source and return condition ............................................................................. 68 23 Key-on wakeup control register, pull-up control register and interrupt control register ...... 70 24 Clock control register MR ............................................................................................. 74 25 Product of built-in PROM version .............................................................................. 150 CHAPTER 2 APPLICATION Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.1.1 Timer control register W3 ........................................................................................... 5 2.1.2 Timer control register W4 ........................................................................................... 5 2.1.3 Timer control register W6 ........................................................................................... 6 2.1.4 Serial I/O control register J1 ...................................................................................... 6 2.1.5 A/D control register Q2 ............................................................................................... 7 2.1.6 A/D control register Q3 ............................................................................................... 7 2.1.7 Pull-up control register PU0 ....................................................................................... 8 2.1.8 Pull-up control register PU1 ....................................................................................... 8 2.1.9 Port output structure control register FR0 ................................................................ 9 2.1.10 Port output structure control register FR1 .............................................................. 9 2.1.11 Port output structure control register FR2 ............................................................ 10 2.1.12 Port output structure control register FR3 ............................................................ 10 2.1.13 Key-on wakeup control register K0 ....................................................................... 11 2.1.14 Key-on wakeup control register K1 ....................................................................... 11 2.1.15 Key-on wakeup control register K2 ....................................................................... 12 2.1.16 Connections of unused pins ................................................................................... 15 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z viii List of tables 4524 Group Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 2.2.1 Interrupt control register V1 ...................................................................................... 19 2.2.2 Interrupt control register V2 ...................................................................................... 20 2.2.3 Interrupt control register I1 ....................................................................................... 20 2.2.4 Interrupt control register I2 ....................................................................................... 21 2.2.5 Interrupt control register I3 ....................................................................................... 21 2.3.1 Interrupt control register V1 ...................................................................................... 34 2.3.2 Interrupt control register V2 ...................................................................................... 34 2.3.3 Interrupt control register I3 ....................................................................................... 35 2.3.4 Timer control register PA .......................................................................................... 35 2.3.5 Timer control register W1 ......................................................................................... 35 2.3.6 Timer control register W2 ......................................................................................... 36 2.3.7 Timer control register W3 ......................................................................................... 36 2.3.8 Timer control register W4 ......................................................................................... 37 2.3.9 Timer control register W5 ......................................................................................... 37 2.3.10 Timer control register W6 ....................................................................................... 38 2.4.1 Interrupt control register V2 ...................................................................................... 51 2.4.2 A/D control register Q1 ............................................................................................. 51 2.4.3 A/D control register Q2 ............................................................................................. 52 2.4.4 A/D control register Q3 ............................................................................................. 52 2.4.5 Recommended operating conditions (when using A/D converter) ...................... 55 2.5.1 Interrupt control register V2 ...................................................................................... 57 2.5.2 Interrupt control register I3 ....................................................................................... 57 2.5.3 Serial I/O mode register J1 ...................................................................................... 58 2.6.1 Duty and maximum number of displayed pixels .................................................... 66 2.6.2 LCD control register L1 ............................................................................................. 67 2.6.3 LCD control register L2 ............................................................................................. 68 2.6.4 Timer control register W6 ......................................................................................... 68 2.8.1 Voltage drop detection circuit operation state ....................................................... 75 2.9.1 Functions and states retained at power down mode ............................................ 79 2.9.2 Return source and return condition ......................................................................... 80 2.9.3 Start condition identification ...................................................................................... 80 2.9.4 Interrupt control register I1 ....................................................................................... 81 2.9.5 Interrupt control register I2 ....................................................................................... 81 2.9.6 Clock control register MR ......................................................................................... 82 2.9.7 Pull-up control register PU0 ..................................................................................... 82 2.9.8 Pull-up control register PU1 ..................................................................................... 83 2.9.9 Key-on wakeup control register K0 ......................................................................... 83 2.9.10 Key-on wakeup control register K1 ....................................................................... 84 2.9.11 Key-on wakeup control register K2 ....................................................................... 84 2.10.1 Clock control register MR ....................................................................................... 90 CHAPTER 3 APPENDIX Table Table Table Table Table Table Table Table Table Table 3.1.1 3.1.2 3.1.3 3.1.4 3.1.5 3.1.6 3.1.7 3.1.8 3.3.1 3.3.2 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Absolute maximum ratings .......................................................................................... 2 Recommended operating conditions 1 ...................................................................... 3 Recommended operating conditions 2 ...................................................................... 4 Electrical characteristics 1 .......................................................................................... 5 Electrical characteristics 2 .......................................................................................... 6 A/D converter recommended operating conditions .................................................. 7 A/D converter characteristics ...................................................................................... 7 Voltage drop detection circuit characteristics ........................................................... 8 Connections of unused pins ..................................................................................... 40 Recommended operating conditions (when using A/D converter) ...................... 44 ix CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS CONTROL REGISTERS INSTRUCTIONS BUILT-IN PROM VERSION HARDWARE DESCRIPTION/FEATURES/APPLICATION 4524 Group DESCRIPTION The 4524 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with main clock selection function, serial I/O, four 8-bit timers (each timer has one or two reload registers), 10-bit A/D converter, interrupts, and LCD control circuit. The various microcomputers in the 4524 Group include variations of the built-in memory size as shown in the table below. FEATURES Minimum instruction execution time .................................. 0.5 s (at 6 MHz oscillation frequency, in high-speed through-mode) Supply voltage Mask ROM version ...................................................... 2.0 to 5.5 V One Time PROM version ............................................. 2.5 to 5.5 V (It depends on oscillation frequency and operation mode) Timers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ...................................... 8-bit timer with a reload register Timer 3 ...................................... 8-bit timer with a reload register Timer 4 ................................. 8-bit timer with two reload registers Timer 5 .............................. 16-bit timer (fixed dividing frequency) Part number M34524M8-XXXFP M34524MC-XXXFP M34524EDFP (Note) ROM (PROM) size ( 10 bits) 8192 words 12288 words 16384 words Interrupt ........................................................................ 9 sources Key-on wakeup function pins ................................................... 10 LCD control circuit Segment output ........................................................................ 20 Common output .......................................................................... 4 Serial I/O ......................................................................... 8-bit 1 A/D converter .............. 10-bit successive approximation method Voltage drop detection circuit (Reset) ......................... Typ. 3.5 V Watchdog timer Clock generating circuit Main clock (ceramic resonator/RC oscillation/on-chip oscillator) Sub-clock (quartz-crystal oscillation) LED drive directly enabled (port D) APPLICATION Household appliance, consumer electronics, office automation equipment RAM size ( 4 bits) 512 words 512 words 512 words Package ROM type 64P6N-A 64P6N-A 64P6N-A Mask ROM Mask ROM One Time PROM Note: Shipped in blank. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-2 HARDWARE PIN CONFIGURATION 4524 Group D3 D2 P13 D0 D1 P12 P11 P03 P10 P02 P01 P00 COM3 COM2 COM1 COM0 PIN CONFIGURATION 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VLC3/SEG0 VLC2/SEG1 VLC1/SEG2 SEG3 SEG4 SEG5 SEG6 49 32 D4/SIN 50 31 51 30 52 29 D5/SOUT D6/SCK C N VS S VDCE SEG7 SEG8 SEG9 56 SEG10 SEG11 SEG12 59 22 60 21 61 20 SEG13 SEG14 SEG15 62 19 63 18 64 17 53 28 54 27 55 26 25 M34524Mx-XXXFP M34524EDFP 6 7 8 23 VDD VSS XOUT XIN RESET D7/CNTR0 C/CNTR1 D8/INT0 D9/INT1 9 10 11 12 13 14 15 16 P20/AIN0 5 24 P21/AIN1 4 P22/AIN2 SEG17 SEG18 SEG19 P43 P42 3 P32/AIN6 P31/AIN5 P30/AIN4 P23/AIN3 2 P33/AIN7 1 SEG16 58 P41 P40 57 XCIN XCOUT OUTLINE 64P6N-A Pin configuration (top view) (4524 Group) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-3 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Port P0 20 4 Common output Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU(4 bits) 4500 series CPU core Port P2 4 1 Port C 2 Port D 512 words 4 bits LCD display RAM including 20 words 4 bits RAM 8192, 12288, 16384 words 10 bits ROM Memory Voltage drop detection circuit Power-on reset circuit 4 Port P4 System clock generation circuit XIN -XOUT (Main clock) XCIN -XCOUT (Sub-clock) Port P3 4 8 4524 Group Segment output LCD drive control circuit (Max.20 segments 4 common) Serial I/O (8 bits 1) A/D converter (10 bits 8 ch) Watchdog timer (16 bits) Timer 1(8 bits) Timer 2(8 bits) Timer 3(8 bits) Timer 4(8 bits) Timer 5(16 bits) Timer 4 Port P1 Internal peripheral functions I/O port 4 HARDWARE BLOCK DIAGRAM Block diagram (4524 Group) 1-4 HARDWARE PERFORMANCE OVERVIEW 4524 Group PERFORMANCE OVERVIEW Parameter Number of basic instructions Minimum instruction execution time Memory sizes ROM M34524M8 M34524MC M34524ED RAM Input/Output D0-D7 I/O ports D 8 , D9 Output P00-P03 I/O P10-P13 I/O Timers P20-P23 P30-P33 P40-P43 C Timer 1 Timer 2 Timer 3 Timer 4 Timer 5 I/O I/O I/O Output A/D converter Serial I/O LCD control Selective bias value circuit Selective duty value Common output Segment output Internal resistor for power supply Interrupt Sources Nesting Subroutine nesting Device structure Package Operating temperature range Supply Mask ROM version voltage One Time PROM version Power Active mode dissipation Clock operating mode At RAM back-up Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Function 159 0.5 s (at 6 MHz oscillation frequency, in high-speed through mode) 8192 words 10 bits 12288 words 10 bits 16384 words 10 bits 512 words 4 bits (including LCD display RAM 20 words 4 bits) Eight independent I/O ports. Input is examined by skip decision. The output structure can be switched by software. Ports D4, D5, D6 and D7 are also used as SIN, SOUT, SCK and CNTR0 pin. Two independent output ports. Ports D8 and D9 are also used as INT0 and INT1, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched by software. 4-bit I/O port; Ports P20-P23 are also used as AIN0-AIN3, respectively. 4-bit I/O port; Ports P30-P33 are also used as AIN4-AIN7, respectively. 4-bit I/O port; The output structure can be switched by software. 1-bit output; Port C is also used as CNTR1 pin. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register and has an event counter. 8-bit programmable timer with two reload registers. 16-bit timer, fixed dividing frequency 10-bit 1, 8-bit comparator is equipped. 8-bit 1 1/2, 1/3 bias 2, 3, 4 duty 4 20 2r 3, 2r 2, r 3, r 2 (they can be switched by software.) 9 (two for external, five for timer, A/D, serial I/O) 1 level 8 levels CMOS silicon gate 64-pin plastic molded QFP (64P6N) -20 C to 85 C 2 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.) 2.5 to 5.5 V (It depends on the operation source clock, operation mode and oscillation frequency.) 2.8 mA (Ta=25C, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN) = 32 kHz, f(STCK) = f(XIN)) 20 A (Ta=25C, VDD = 5 V, f(XCIN) = 32 kHz) 0.1 A (Ta=25C, VDD = 5 V) 1-5 HARDWARE PIN DESCRIPTION 4524 Group PIN DESCRIPTION Pin VDD VSS CNVSS VDCE RESET Name Power supply Ground CNVSS Voltage drop detection circuit enable Reset input/output XIN Main clock input XOUT Main clock output XCIN XCOUT D0-D7 Sub-clock input Sub-clock output I/O port D Input is examined by skip decision. Input Output I/O D 8 , D9 Output port D Output P00-P03 I/O port P0 I/O P10-P13 I/O port P1 I/O P20-P23 I/O port P2 I/O P30-P33 I/O port P3 I/O P40-P43 I/O port P4 I/O Output port C Port C Common output COM0- COM3 SEG0-SEG19 Segment output VLC3-VLC1 LCD power supply Input/Output -- -- -- Input I/O Input Output Output Output Output - CNTR0, CNTR1 Timer input/output INT0, INT1 Interrupt input Input AIN0-AIN7 Analog input Input SCK SOUT SIN Serial I/O data I/O Serial I/O data output Serial I/O clock input Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z I/O I/O Output Input Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply "L" (0V) to CNVSS certainly. This pin is used to operate/stop the voltage drop detection circuit. When "H" level is input to this pin, the circuit starts operating. When "L" level is input to this pin, the circuit stops operating. An N-channel open-drain I/O pin for a system reset. When the watchdog timer, the built-in power-on reset, or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs "L" level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins X IN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. I/O pins of the sub-clock generating circuit. Connect a 32 kHz quartz-crystal oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Ports D4-D7 is also used as SIN, SOUT, SCK and CNTR0 pin. Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. Ports D8 and D9 are also used as INT0 pin and INT1 pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Port P2 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to "1". Ports P20-P23 are also used as AIN0-AIN3, respectively. Port P3 serves as a 4-bit I/O port. The output structure is N-channel open-drain. For input use, set the latch of the specified bit to "1". Ports P30-P33 are also used as AIN4-AIN7, respectively. Port P4 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. 1-bit output port. The output structure is CMOS. Port C is also used as CNTR1 pin. LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0- COM2 are used at 1/3 duty and pins COM0-COM3 are used at 1/4 duty. LCD segment output pins. SEG0-SEG2 pins are used as VLC3-VLC1 pins, respectively. LCD power supply pins. When the internal resistor is used, VDD pin is connected to VLC3 pin (if luminance adjustment is required, VDD pin is connected to VLC3 pin through a resistor). When the external power supply is used, apply the voltage 0 VLC1 VLC2 VLC3 VDD. VLC3-VLC1 pins are used as SEG0-SEG2 pins, respectively. CNTR0 pin has the function to input the clock for the timer 1 event counter, and to output the timer 1 or timer 2 underflow signal divided by 2. CNTR1 pin has the function to input the clock for the timer 3 event counter, and to output the PWM signal generated by timer 4.CNTR0 pin and CNTR1 pin are also used as Ports D7 and C, respectively. INT0 pin and INT1 pin accept external interrupts. They have the key-on wakeup function which can be switched by software. INT0 pin and INT1 pin are also used as Ports D8 and D9, respectively. A/D converter analog input pins. AIN0-AIN7 are also used as ports P20-P23 and P30- P33, respectively. Serial I/O data transfer synchronous clock I/O pin. SCK pin is also used as port D6. Serial I/O data output pin. SOUT pin is also used as port D5. Serial I/O data input pin. SIN pin is also used as port D4. 1-6 HARDWARE MULTIFUNCTION/DEFINITION OF CLOCK AND CYCLE 4524 Group MULTIFUNCTION Pin D4 D5 D6 D7 D8 D9 VLC3 VLC2 VLC1 Multifunction SIN SOUT SCK CNTR0 INT0 INT1 SEG0 SEG1 SEG2 Pin SIN SOUT SCK CNTR0 INT0 INT1 SEG0 SEG1 SEG2 Multifunction D4 D5 D6 D7 D8 D9 VLC3 VLC2 VLC1 Pin C P20 P21 P22 P23 P30 P31 P32 P33 Multifunction CNTR1 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Pin CNTR1 AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 AIN6 AIN7 Multifunction C P20 P21 P22 P23 P30 P31 P32 P33 Notes 1: Pins except above have just single function. 2: The output of D8 and D9 can be used even when INT0 and INT1 are selected. 3: The input of ports D4-D6 can be used even when SIN, SOUT and SCK are selected. 4: The input/output of D7 can be used even when CNTR0 (input) is selected. 5: The input of D7 can be used even when CNTR0 (output) is selected. 6: The port C "H" output function can be used even when CNTR1 (output) is selected. DEFINITION OF CLOCK AND CYCLE Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. * Clock (f(XIN)) by the external ceramic resonator * Clock (f(XIN)) by the external RC oscillation * Clock (f(XIN)) by the external input * Clock (f(RING)) of the on-chip oscillator which is the internal oscillator * Clock (f(XCIN)) by the external quartz-crystal oscillation Table Selection of system clock Register MR System clock MR3 MR2 MR1 MR0 0 0 0 0 f(STCK) = f(XIN) or f(RING) 1 f(STCK) = f(XCIN) 0 1 0 0 f(STCK) = f(XIN)/2 or f(RING)/2 1 f(STCK) = f(XCIN)/2 1 0 0 0 f(STCK) = f(XIN)/4 or f(RING)/4 1 f(STCK) = f(XCIN)/4 1 1 0 0 f(STCK) = f(XIN)/8 or f(RING)/8 1 f(STCK) = f(XCIN)/8 System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. Machine cycle The machine cycle is the standard cycle required to execute the instruction. Operation mode High-speed through mode Low-speed through mode High-speed frequency divided by 2 mode Low-speed frequency divided by 2 mode High-speed frequency divided by 4 mode Low-speed frequency divided by 4 mode High-speed frequency divided by 8 mode Low-speed frequency divided by 8 mode : 0 or 1 Note: The f(RING)/8 is selected after system is released from reset. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-7 HARDWARE PORT FUNCTION 4524 Group PORT FUNCTION Port Port D Pin D0-D3, D4/SIN, D5/SOUT, D6/SCK, D7/CNTR0 D8/INT0, D9/INT1 Port P0 P00-P03 Port P1 P10-P13 Port P2 P20/AIN0-P23/AIN3 Port P3 P30/AIN4-P33/AIN7 Port P4 P40-P43 Port C C/CNTR1 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Input Output I/O (8) Output structure N-channel open-drain/ CMOS I/O unit 1 Control instructions SD, RD SZD CLD Output (2) I/O (4) N-channel open-drain N-channel open-drain/ CMOS 4 OP0A IAP0 I/O (4) N-channel open-drain/ CMOS 4 OP1A IAP1 I/O (4) I/O (4) I/O (4) Output (1) N-channel open-drain 4 N-channel open-drain 4 N-channel open-drain/ CMOS CMOS 4 OP2A IAP2 OP3A IAP3 OP4A IAP4 RCP SCP 1 Control registers FR1, FR2 J1 W6 I1, I2 K2 FR0 PU0 K0 FR0 PU1 K1 Q2 Remark Output structure selection function (programmable) Key-on wakeup function (programmable) Built-in programmable pull-up functions and key-on wakeup functions (programmable) Built-in programmable pull-up functions and key-on wakeup functions (programmable) Q3 FR3 Output structure selection function (programmable) W4 1-8 HARDWARE CONNECTION OF UNUSED PINS 4524 Group CONNECTIONS OF UNUSED PINS XIN Connection Connect to VSS. XOUT Open. XCIN XCOUT D0-D3 Connect to VSS. Open. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Connect to VSS. Open. Open. Connect to Vss. Pin D4/SIN D5/SOUT D6/SCK D7/CNTR0 D8/INT0 D9/INT1 C/CNTR1 P00-P03 P10-P13 Open. Connect to Vss. P20/AIN0- P23/AIN3 P30/AIN4- Open. Connect to Vss. Open. P33/AIN7 P40-P43 Connect to Vss. Open. Connect to Vss. Open. Open. Open. Open. Open. COM0-COM3 VLC3/SEG0 VLC2/SEG1 VLC1/SEG2 SEG3-SEG19 Usage condition Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) Sub-clock input is selected for system clock (MR0=1). (Note 2) Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) RC oscillator is selected (CRCK instruction is executed) External clock input is selected for main clock (CMCK instruction is executed). (Note 3) Sub-clock input is selected for system clock (MR0=1). (Note 2) Sub-clock is not used. Sub-clock is not used. N-channel open-drain is selected for the output structure. (Note 4) SIN pin is not selected. N-channel open-drain is selected for the output structure. N-channel open-drain is selected for the output structure. SCK pin is not selected. N-channel open-drain is selected for the output structure. CNTR0 input is not selected for timer 1 count source. N-channel open-drain is selected for the output structure. "0" is set to output latch. "0" is set to output latch. CNTR1 input is not selected for timer 3 count source. The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) N-channel open-drain is selected for the output structure. (Note 5) SEG0 pin is selected. SEG1 pin is selected. SEG2 pin is selected. Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator) is selected for main clock. 2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting "1" to bit 1 (MR1) of clock control register MR, main clock is stopped. 3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input for the main clock. 4: Be sure to select the output structure of ports D0-D3 and P40-P43 and the pull-up function and key-on wakeup function of P00-P03 and P10-P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P00-P03 and P10-P13 with every two ports. If only one of the two pins is used, leave another one open. (Note when connecting to VSS and VDD) Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-9 HARDWARE PORT BLOCK DIAGRAM 4524 Group PORT BLOCK DIAGRAMS Clock (input) for timer 3 event count W 31 W 30 PWMOD SCP instruction S Q RCP instruction R (Note 1) C/CNTR1 (Note 2, Note 3) D Q R W32 Register Y Decoder W61 Skip decision (SZD instruction) FR 10 CLD instruction (Note 1) S SD instruction Decoder CLD instruction Skip decision (SZD instruction) FR11 (Note 1) S SD instruction Decoder CLD instruction Decoder CLD instruction RD instruction FR12 (Note 1) D2 (Note 2) R Q RD instruction SD instruction Skip decision (SZD instruction) S SD instruction Register Y D1 (Note 2) R Q RD instruction Register Y D0 (Note 2) R Q RD instruction Register Y Timer 3 underflow signal T Skip decision (SZD instruction) FR13 (Note 1) S D3 (Note 2) R Q This symbol represents a parasitic diode on the port. Notes 1: 2: Applied potential to these ports must be VDD or less. 3: When CNTR1 input is selected, output transistor is turned OFF. Port block diagram (1) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-10 HARDWARE PORT BLOCK DIAGRAM 4524 Group Register Y Skip decision (SZD instruction) Decoder F R 20 CLD instruction (Note 1) S Q SD instruction D4/SIN (Note 2) R RD instruction J11 Serial data input Skip decision (SZD instruction) Decoder Register Y CLD instruction FR21 D5/SOUT (Note 2) J10 R Q RD instruction Serial data output Register Y (Note 1) S SD instruction 0 1 Skip decision (SZD instruction) Decoder FR22 CLD instruction (Note 1) S Q D6/SCK (Note 2) SD instruction R RD instruction J11 J10 Synchronous clock (output) for serial data transfer J13 J1 2 Synchronous clock (input) for serial data transfer Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (2) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-11 HARDWARE PORT BLOCK DIAGRAM 4524 Group Register Y Skip decision (SZD instruction) Decoder CLD instruction F R 23 (Note 1) S SD instruction D7/CNTR0 (Note 2) W60 R Q RD instruction 0 1 Underflow signal divided by 2 of timer 1 or timer 2 W11 W10 Clock (input) for timer 1 event count Timer 1 count start synchronous circuit input Register Y Key-on wakeup (Note 3) External 0 interrupt External 0 interrupt circuit Decoder CLD instruction (Note 1) S SD instruction D8/INT0 (Note 2) R Q RD instruction Timer 3 count start synchronous circuit input Key-on wakeup (Note 3) External 1 interrupt circuit External 1 interrupt Register Y Decoder CLD instruction SD instruction RD instruction (Note 1) S R Q D9/INT1 (Note 2) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: As for details, refer to the description of external interrupt circuit. Port block diagram (3) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-12 HARDWARE PORT BLOCK DIAGRAM 4524 Group IAP0 instruction PU00 Pull-up transistor Register A A0 FR00 (Note 1) P00 (Note 2) D A0 OP0A instruction T Q K00 Key-on wakeup "L" level detection circuit IAP0 instruction PU01 Pull-up transistor Register A A1 FR00 (Note 1) P01 (Note 2) D A1 OP0A instruction T Q K01 Key-on wakeup Register A "L" level detection circuit IAP0 instruction PU02 Pull-up transistor A2 FR01 (Note 1) P02 (Note 2) D A2 OP0A instruction T Q K02 Key-on wakeup Register A "L" level detection circuit IAP0 instruction PU03 Pull-up transistor A3 FR01 A3 OP0A instruction (Note 1) P03 (Note 2) D T Q K03 Key-on wakeup "L" level detection circuit Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (4) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-13 HARDWARE PORT BLOCK DIAGRAM 4524 Group Pull-up transistor IAP1 instruction Register A A0 PU10 F R 02 (Note 1) P10 (Note 2) D A0 OP1A instuction T Q K10 "L" level detection circuit Key-on wakeup Pull-up transistor IAP1 instruction Register A PU11 A1 F R 02 (Note 1) P11 (Note 2) D A1 OP1A instuction T Q K11 "L" level detection circuit Key-on wakeup Pull-up transistor IAP1 instruction Register A PU12 A2 F R 03 (Note 1) P12 (Note 2) D A2 OP1A instuction T Q K12 Key-on wakeup "L" level detection circuit Pull-up transistor IAP1 instruction PU13 Register A A3 F R 03 (Note 1) A3 OP1A instuction P13 (Note 2) D T Q K13 Key-on wakeup "L" level detection circuit Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. Port block diagram (5) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-14 HARDWARE PORT BLOCK DIAGRAM 4524 Group Ai IAP2 instruction Register A (Note 3) Ai OP2A instruction Q2i (Note 3) (Note 1) (Note 3) Q2i D P20/AIN0-P23/AIN3 (Note 2) 0 T Q 1 Q1 Decoder Analog input Ai IAP3 instruction Register A (Note 3) Ai OP3A instruction Q3i (Note 1) (Note 3) Q3i D P30/AIN4-P33/AIN7 (Note 2) 0 T Q (Note 3) 1 Q1 Decoder Analog input IAP4 instruction Ai Register A (Note 3) (Note 3) FR3i Ai OP4A instruction (Note 1) D P40-P43 (Note 2) T Q Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3. Port block diagram (6) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-15 HARDWARE PORT BLOCK DIAGRAM 4524 Group LCD power supply Connecting to * when SEG is selected. LCD control signal (Note 1) VLC3/SEG0 (Notes 2 and 3) VDD L23 LCD power supply LCD power supply (VLC3/VDD) LCD power supply LCD control signal Connecting to * when SEG is selected. (Note 1) VLC2/SEG1 (Note 2) L22 LCD power supply LCD power supply (VLC2) LCD power supply LCD control signal L11 Connecting to * when SEG is selected. (Note 1) VLC1/SEG2 (Note 2) L21 LCD power supply LCD power supply (VLC1) L13 L20 Reset signal L12 EPOF+POF2 instruction (Continuous execution) Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential when VLC is selected must be as follows; * VDD VLC3 VLC2 VLC1 3: VLC3 = VDD when SEG is selected. Port block diagram (7) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-16 HARDWARE PORT BLOCK DIAGRAM 4524 Group LCD power supply LCD control signal Pch SEG3-SEG19 LCD control signal Nch LCD power supply LCD power supply LCD control signal Pch COM0-COM3 Pch LCD control signal LCD power supply LCD power supply LCD control signal Nch Nch LCD control signal Port block diagram (8) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-17 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group FUNCTION BLOCK OPERATIONS CPU (CY) (1) Arithmetic logic unit (ALU) (M(DP)) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation. ALU Addition (A) (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction. Fig. 1 AMC instruction execution example SC instruction RC instruction CY A3 A2 A1 A0 RAR instruction (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. A0 CY A3 A2 A1 Fig. 2 RAR instruction execution example Register B TAB instruction B3 B2 B1 B0 (4) Register D Register A A3 A2 A1 A0 TEAB instruction Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Register D is undefined after system is released from reset and returned from the RAM back-up. Accordingly, set the initial value. Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction A3 A2 A1 A0 B3 B2 B1 B0 Register B TBA instruction Register A Fig. 3 Registers A, B and register E TABP p instruction ROM Specifying address p6 p5 PCH p4 p3 p2 p1 p0 PCL DR2 DR1DR0 A3 A2 A1 A0 8 4 0 Low-order 4bits Register A (4) Middle-order 4 bits Register B (4) Immediate field value p The contents of The contents of register D register A Fig. 4 TABP p instruction execution example Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-18 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Program counter (PC) Executing BM instruction Executing RT instruction SK0 (SP) = 0 SK1 (SP) = 1 SK2 (SP) = 2 SK3 (SP) = 3 SK4 (SP) = 4 SK5 (SP) = 5 SK6 (SP) = 6 SK7 (SP) = 7 Stack pointer (SP) points "7" at reset or returning from RAM back-up mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed. Fig. 5 Stack registers (SKs) structure (SP) 0 (SK0) 000116 (PC) SUB1 Main program Subroutine Address SUB1 : 000016 NOP NOP * * * RT 000116 BM SUB1 000216 NOP (PC) (SK0) (SP) 7 Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction. Fig. 6 Example of operation at subroutine call Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-19 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM. Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 PCH Specifying page PCL Specifying address Fig. 7 Program counter (PC) structure Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Specifying RAM digit Register Y (4) Register X (4) Specifying RAM file Specifying RAM file group Register Z (2) Fig. 8 Data pointer (DP) structure Specifying bit position Set D3 0 0 0 D2 1 Register Y (4) D1 D0 1 Port D output latch Fig. 9 SD instruction execution example Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-20 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34524ED. Table 1 ROM size and pages Part number M34524M8 M34524MC M34524ED ROM (PROM) size ( 10 bits) 8192 words 12288 words 16384 words Pages 9 8 7 6 5 4 3 2 1 0 000016 007F16 008016 00FF16 010016 017F16 018016 Page 0 Interrupt address page Page 1 Subroutine special page Page 2 Page 3 64 (0 to 63) 96 (0 to 95) 128 (0 to 127) Note: Data in pages 64 to 127 can be referred with the TABP p instruction after the SBK instruction is executed. Data in pages 0 to 63 can be referred with the TABP p instruction after the RBK instruction is executed. A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction. 3FFF16 Page 127 Fig. 10 ROM map of M34524ED 008016 9 8 7 6 5 4 3 2 1 0 External 0 interrupt address 008216 External 1 interrupt address 008416 Timer 1 interrupt address 008616 Timer 2 interrupt address 008816 Timer 3 interrupt address 008A16 Timer 5 interrupt address 008C16 008E16 A/D interrupt address T imer 4, Serial I/O interrupt address 00FF16 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-21 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from RAM back-up). RAM includes the area for LCD. When writing "1" to a bit corresponding to displayed segment, the segment is turned on. Table 2 shows the RAM size. Figure 12 shows the RAM map. Table 2 RAM size Part number M34524M8 M34524MC M34524ED RAM size 512 words 4 bits (2048 bits) 512 words 4 bits (2048 bits) 512 words 4 bits (2048 bits) * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the RAM back-up, set these registers. Register Y RAM 512 words 4 bits (2048 bits) Register Z 1 0 Register X 0 1 2 3 ... 12 13 14 15 0 1 2 ... 11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 12 13 14 15 0 1 2 3 4 5 6 8 16 9 17 10 18 11 19 12 13 14 7 15 Note: The numbers in the shaded area indicate the corresponding segment output pin numbers. Fig. 12 RAM map Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-22 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * An interrupt activated condition is satisfied (request flag = "1") * Interrupt enable bit is enabled ("1") * Interrupt enable flag is enabled (INTE = "1") Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed. Table 3 Interrupt sources Priority Interrupt name level 1 External 0 interrupt 2 External 1 interrupt 3 Timer 1 interrupt Level change of INT0 pin Level change of INT1 pin Timer 1 underflow 4 Timer 2 interrupt Timer 2 underflow 5 Timer 3 interrupt Timer 3 underflow 6 Timer 5 interrupt Timer 5 underflow 7 A/D interrupt 8 Timer 4 interrupt or Serial I/O interrupt (Note) Completion of A/D conversion Timer 4 underflow or completion of serial I/O transmit/ receive (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * the next instruction is skipped with a skip instruction. Each interrupt request flag is set to "1" when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until it is cleared to "0" by the interrupt occurrence or the skip instruction. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set to "1" when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Activated condition Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1 Note: Timer 4 interrupt or serial I/O interrupt can be selected by the timer 4, serial I/O interrupt source selection bit (I30). Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 5 interrupt A/D interrupt Timer 4 interrupt Serial I/O interrupt Interrupt request flag EXF0 EXF1 T1F T2F T3F T5F ADF T4F SIOF Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT5 SNZAD SNZT4 SNZSI Table 5 Interrupt enable bit function Interrupt enable bit Occurrence of interrupt Enabled 1 Disabled 0 Interrupt nable bit V10 V11 V12 V13 V20 V21 V22 V23 V23 Skip instruction Invalid Valid 1-23 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). * Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0." * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) * Program counter (PC) ............................................................... Each interrupt address * Stack register (SK) The address of main routine to be .................................................................................................... executed when returning * Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) * Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 * Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs Activated condition INT0 pin interrupt waveform input INT1 pin interrupt waveform input Timer 1 underflow Main routine Timer 2 underflow Interrupt service routine Interrupt occurs * * * * EI R TI Interrupt is enabled Timer 3 underflow Timer 5 underflow A/D conversion completed Timer 4 underflow Request flag Enable bit (state retained) Enable flag Address 0 in page 1 EXF0 V10 EXF1 V11 T1F V12 T2F V13 T3F V20 Address 8 in page 1 T5F V21 Address A in page 1 ADF V 22 Address C in page 1 T4F V23 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address E in page 1 INTE 0 : Interrupt enabled state Serial I/O transmit/receive completed 1 SIOF I30 : Interrupt disabled state Fig. 13 Program example of interrupt processing Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Fig. 15 Interrupt system diagram 1-24 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (6) Interrupt control registers * Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. * Interrupt control register I3 The timer 4, serial I/O interrupt source selection bit is assigned to register I3. Set the contents of this register through register A with the TI3A instruction. The TAI3 instruction can be used to transfer the contents of register I3 to register A. * Interrupt control register V2 The timer 3, timer 5, A/D, Timer 4 and serial I/O interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 Timer 2 interrupt enable bit V12 Timer 1 interrupt enable bit V11 External 1 interrupt enable bit V10 External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 1 Interrupt control register V2 V23 Timer 4, serial I/O interrupt enable bit (Note 3) V22 A/D interrupt enable bit V21 Timer 5 interrupt enable bit V20 Timer 3 interrupt enable bit I30 Timer 4, serial I/O interrupt source selection bit R/W TAV1/TV1A Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) (Note 2) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) (Note 2) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) (Note 2) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) (Note 2) at reset : 00002 0 1 0 1 0 1 0 1 Interrupt control register I3 at power down : 00002 at power down : 00002 R/W TAV2/TV2A Interrupt disabled (SNZT4, SNZSI instruction is valid) Interrupt enabled (SNZT4, SNZSI instruction is invalid) (Note 2) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) (Note 2) Interrupt disabled (SNZT5 instruction is valid) Interrupt enabled (SNZT5 instruction is invalid) (Note 2) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) (Note 2) at reset : 02 0 1 at power down : state retained R/W TAI3/TI3A Timer 4 interrupt valid, serial I/O interrupt invalid Serial I/O interrupt valid, timer 4 interrupt invalid Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: These instructions are equivalent to the NOP instruction. 3: Select the timer 4 interrupt or serial I/O interrupt by the timer 4, serial I/O interrupt source selection bit (I30). (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V10-V1 3, V20-V23), and interrupt request flag are "1." The interrupt actually occurs 2 to 3 machine cycles after the machine cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles when the interrupt conditions are satisfied on execution of two-cycle instructions or three-cycle instructions. (Refer to Figure 16). Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-25 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Timer 1, Timer 2, Timer 3, Timer 4, Timer 5, A/D and Serial I/O interrupts External interrupt T1F,T2F,T3F,T4F T5F,ADF,SIOF EXF0,EXF1 INT0,INT1 Interrupt enable flag (INTE) System clock (STCK) T2 T3 T1 T2 T3 T2 T3 Interrupt enabled state T1 T2 T1 T2 The program starts from the interrupt address. Retaining level of system clock for 4 periods or more is necessary. Interrupt disabled state Flag cleared T3 2 to 3 machine cycles (Notes 1, 2) Interrupt activated condition is satisfied. T1 4524 Group Notes 1: The address to be executed when returning to the main routine is stacked to the last machine cycle. 2: The cycles are as follows according to the executed instruction at the time when each interrupt activated condition is satisfied. On execution of one-cycle instruction: Interrupt occurs after 2 machine cycles. On execution of two-cycle instruction: Interrupt occurs after 3 machine cycles. On execution of three-cycle instruction: Interrupt occurs after 3 machine cycles. EI instruction execution cycle T1 1 machine cycle When an interrupt request flag is set after its interrupt is enabled (Note 1) HARDWARE FUNCTION BLOCK OPERATIONS Fig. 16 Interrupt sequence 1-26 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group EXTERNAL INTERRUPTS The 4524 Group has the external 0 interrupt and external 1 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control registers I1 and I2. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin Valid waveform selection bit I11 I12 Activated condition D8/INT0 When the next waveform is input to D8/INT0 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms External 1 interrupt D9/INT1 I21 I22 When the next waveform is input to D9/INT1 pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms I12 Falling (Note 1) 0 One-sided edge detection circuit I11 0 D8/INT0 External 0 interrupt EXF0 1 Rising I13 Both edges detection circuit 1 Timer 1 count start synchronous circuit (Note 2) Level detection circuit K21 0 Key-on wakeup (Note 3) Edge detection circuit K20 1 Skip decision (SNZI0 instruction) I22 Falling (Note 1) 0 One-sided edge detection circuit I21 0 D9/INT1 External 1 interrupt EXF1 1 Rising I23 Both edges detection circuit 1 (Note 2) Level detection circuit K22 (Note 3) Edge detection circuit Timer 3 count start synchronous circuit K23 0 Key-on wakeup 1 Skip decision (SNZI1 instruction) Notes 1: This symbol represents a parasitic diode on the port. 2: I12 (I22) = 0: "L" level detected I12 (I22) = 1: "H" level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected Fig. 17 External interrupt circuit structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-27 HARDWARE 4524 Group FUNCTION BLOCK OPERATIONS (1) External 0 interrupt request flag (EXF0) (2) External 1 interrupt request flag (EXF1) External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to D8/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. External 1 interrupt request flag (EXF1) is set to "1" when a valid waveform is input to D9/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. * External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D8/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. * External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to D9/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. Set the bit 3 of register I1 to "1" for the INT0 pin to be in the input enabled state. Select the valid waveform with the bits 1 and 2 of register I1. Clear the EXF0 flag to "0" with the SNZ0 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." Set the bit 3 of register I2 to "1" for the INT1 pin to be in the input enabled state. Select the valid waveform with the bits 1 and 2 of register I2. Clear the EXF1 flag to "0" with the SNZ1 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. Set both the external 1 interrupt enable bit (V1 1) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the D8/INT0 pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs. The external 1 interrupt is now enabled. Now when a valid waveform is input to the D9/INT1 pin, the EXF1 flag is set to "1" and the external 1 interrupt occurs. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-28 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (3) External interrupt control registers * Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. * Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. Table 8 External interrupt control register Interrupt control register I1 I13 INT0 pin input control bit (Note 2) I12 Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) I11 I10 INT0 pin edge detection circuit control bit INT0 pin Timer 1 count start synchronous circuit selection bit at reset : 00002 0 1 0 1 0 1 0 1 Interrupt control register I2 I23 I22 I21 I20 INT1 pin input control bit (Note 2) Interrupt valid waveform for INT1 pin/ return level selection bit (Note 2) INT1 pin edge detection circuit control bit INT1 pin Timer 3 count start synchronous circuit selection bit 0 1 0 1 0 1 R/W TAI1/TI1A INT0 pin input disabled INT0 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected at reset : 00002 0 1 at power down : state retained at power down : state retained R/W TAI2/TI2A INT1 pin input disabled INT1 pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI1 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI1 instruction) One-sided edge detected Both edges detected Timer 3 count start synchronous circuit not selected Timer 3 count start synchronous circuit selected Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of these bits (I12 , I13, I22 and I23) are changed, the external interrupt request flag (EXF0, EXF1) may be set. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-29 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (4) Notes on External 0 interrupts Note on bit 2 of register I1 When the interrupt valid waveform of the D8/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 18) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 18). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18). * Depending on the input state of the D8/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 20) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 20). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20). *** *** Note [1] on bit 3 of register I1 When the input of the INT0 pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. LA 4 TV1A LA 8 TI1A NOP SNZ0 LA 4 TV1A LA 12 TI1A NOP SNZ0 *** NOP ; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... *** NOP ; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT0 pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ........................................................... : these bits are not used here. : these bits are not used here. Fig. 18 External 0 interrupt program example-1 Fig. 20 External 0 interrupt program example-3 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared, the power down function is selected and the input of INT0 pin is disabled, be careful about the following notes. *** * When the input of INT0 pin is disabled, invalidate the key-on wakeup function of INT0 pin (register K2 0 = "0") before system goes into the power down mode. (refer to Figure 19). ; (02) ; INT0 key-on wakeup invalid ........... ; RAM back-up *** LA 0 TK2A DI EPOF POF2 : these bits are not used here. Fig. 19 External 0 interrupt program example-2 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-30 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (5) Notes on External 1 interrupts Note on bit 2 of register I2 When the interrupt valid waveform of the D9/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the following notes. * Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 3 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 21) and then, change the bit 3 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 21). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 21). * Depending on the input state of the D9/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the bit 2 of register I2 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 1 of register V1 to "0" (refer to Figure 23) and then, change the bit 2 of register I2. In addition, execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction (refer to Figure 23). Also, set the NOP instruction for the case when a skip is performed with the SNZ1 instruction (refer to Figure 23). *** *** Note [1] on bit 3 of register I2 When the input of the INT1 pin is controlled with the bit 3 of register I2 in software, be careful about the following notes. LA 4 TV1A LA 8 TI2A NOP SNZ1 LA 4 TV1A LA 12 TI2A NOP SNZ1 *** NOP ; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Interrupt valid waveform is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ........................................................... *** NOP ; (02) ; The SNZ1 instruction is valid ........... ; (12) ; Control of INT1 pin input is changed ........................................................... ; The SNZ1 instruction is executed (EXF1 flag cleared) ........................................................... : these bits are not used here. : these bits are not used here. Fig. 21 External 1 interrupt program example-1 Fig. 23 External 1 interrupt program example-3 Note [2] on bit 3 of register I2 When the bit 3 of register I2 is cleared, the power down function is selected and the input of INT1 pin is disabled, be careful about the following notes. *** * When the input of INT1 pin is disabled, invalidate the key-on wakeup function of INT1 pin (register K2 2 = "0") before system goes into the power down mode. (refer to Figure 22). ; (02) ; INT1 key-on wakeup invalid ........... ; RAM back-up *** LA 0 TK2A DI EPOF POF2 : these bits are not used here. Fig. 22 External 1 interrupt program example-2 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-31 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group TIMERS The 4524 Group has the following timers. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function). * Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" after every n count of a count pulse. F F1 6 n : Counter initial value Count starts Reload Reload The contents of counter n 1st underflow 2nd underflow 0016 Time n+1 count n+1 count "1" Timer interrupt "0" request flag An interrupt occurs or a skip instruction is executed. Fig. 24 Auto-reload function The 4524 Group timer consists of the following circuits. * Prescaler : 8-bit programmable timer * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer * Timer 3 : 8-bit programmable timer * Timer 4 : 8-bit programmable timer * Timer 5 : 16-bit fixed dividing frequency timer * Timer LC : 4-bit programmable timer * Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, 3, 4 and 5 have the interrupt function, respectively) Prescaler and timers 1, 2, 3, 4, 5 and LC can be controlled with the timer control registers PA, W1 to W6. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-32 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group Table 9 Function related timers Prescaler 8-bit programmable * Instruction clock (INSTCK) Frequency dividing ratio 1 to 256 Timer 1 binary down counter 8-bit programmable * Instruction clock (INSTCK) 1 to 256 Circuit Structure binary down counter (link to INT0 input) Count source * Prescaler output (ORCLK) * Timer 5 underflow Use of output signal Control register PA * Timer 1, 2, 3, 4 and LC count sources * Timer 2 count source W1 * CNTR0 output W2 * Timer 1 interrupt (T5UDF) * CNTR0 input Timer 2 8-bit programmable binary down counter * System clock (STCK) 1 to 256 * Timer 3 count source * Prescaler output (ORCLK) * CNTR0 output * Timer 1 underflow (T1UDF) * Timer 2 interrupt W2 * PWM output (PWMOUT) Timer 3 8-bit programmable * PWM output (PWMOUT) binary down counter (link to INT1 input) * Prescaler output (ORCLK) 1 to 256 * CNTR1 output control * Timer 3 interrupt W3 1 to 256 * Timer 2, 3 count source W4 * Timer 2 underflow (T2UDF) * CNTR1 input Timer 4 Timer 5 8-bit programmable * XIN input binary down counter * Prescaler output (ORCLK) * CNTR1 output * Timer 4 interrupt (PWM output function) * XCIN input 16-bit fixed dividing 8192 * Timer 1, LC count source frequency 16384 * Timer 5 interrupt W5 32768 65536 Timer LC 4-bit programmable * Bit 4 of timer 5 Watchdog binary down counter 16-bit fixed dividing * Prescaler output (ORCLK) timer frequency Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z * Instruction clock (INSTCK) 1 to 16 * LCD clock 65534 * System reset (count twice) W6 * WDF flag decision 1-33 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group Division circuit On-chip oscillator Divided by 8 (CMCK) Multiplexer Ceramic resonance XI N Divided by4 MR0 0 RC oscillation Divided by 2 10 Internal clock generating circuit (divided by 3) 01 00 Instruction clock (INSTCK) PA0 (Note 4) 0 Quartz-crystal oscillation W60 0 System clock (STCK) 1 (CMCK/CRCK) (Note 1) (CRCK) XCIN MR3, MR2 11 Prescaler (8) ORCLK 1 Port D7 output D7/CNTR0 W23 0 1 /2 1 /2 1 I1 2 Falling 0 D8/INT0 Reload register RPS (8) T1UDF (TPSAB) 1 T2UDF I11 0 One-sided edge detection circuit (TABPS) (Note 2) 1 Rising 1 Both edges detection circuit (TPSAB) Register A (TABPS) I10 1 S Q I1 3 (TPSAB) Register B 0 R I10 W13 T1UDF W11, W10 00 INSTCK 01 ORCLK 10 T5UDF Timer 1 (8) (Note 4) W12 0 (TAB1) D7/CNTR0 W21, W20 00 01 ORCLK 10 T1UDF (TR1AB) (T1AB) (TAB1) Timer 2 (8) Timer 1 underflow signal (T1UDF) T2F Timer 2 interrupt Reload register R2 (8) 1 (T2AB) (TAB2) PWMOUT I2 2 Falling 0 I23 (T1AB) Register B Register A (Note 4) W22 0 11 D9/INT1 Timer 1 interrupt Reload register R1 (8) (T1AB) 1 11 STCK T1F 1 Rising (T2AB) (T2AB) (TAB2) Register B Register A One-sided edge detection circuit I2 1 (Note 3) 0 S Q I20 1 1 Both edges detection circuit Timer 2 underflow signal (T2UDF) 0 R I20 W33 T3UDF W31, W30 00 PWMOUT ORCLK T2UDF 01 10 11 Timer 3 (8) (Note 4) W32 0 T3F Timer 3 interrupt Reload register R3 (8) (T3AB) 1 (TAB3) C/CNTR1 T5UDF: Timer 5 underflow signal (from timer 5) PWMOUT: PWM output signal (from timer 4 output unit) Data is set automatically from each reload register when timer underflows (auto-reload function). (TR3AB) (T3AB) (T3AB) Register B Register A (TAB3) Timer 3 underflow signal (T3UDF) Notes 1: When CMCK instruction is executed, ceramic resonance is selected. When CRCK instruction is executed, RC oscillation is selected. When any instructions are not executed, on-chip oscillator clock (internal oscillation) is selected. 2: Timer 1 count start synchronous circuit is set by the valid edge of D8/INT0 pin selected by bits 1 (I11) and 2 (I12) of register I1. 3: Timer 3 count start synchronous circuit is set by the valid edge of D9/INT1 pin selected by bits 1 (I21) and 2 (I22) of register I2. 4: Count source is stopped by clearing to "0." Fig. 25 Timer structure (1) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-34 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group Register B Register A (T4HAB) Reload register R4H (8) (Note 5) W40 0 XIN ORCLK (Note 4) W41 0 Reload control circuit W 42 "H" interval expansion Timer 4 (8) 1 1 /2 1 1 T 0 (T4R4L) (T4AB) (T4AB) Register B PWMOD W43 Reload register R4L (8) (TAB4) Q R (TAB4) Register A T4F SIOF I30 0 1 Timer 4, Serial I/O interrupt (From Serial I/O) PWMOUT (To timer 2 and timer 3) Port C output PWMOD C/CNTR1 W31 W30 W32 (Note 4) W52 0 XCIN 1 Q D R T T3UDF W61 Timer 5 (16) (Note 6) 1 - - 4 - - - - - - - -13 14 15 16 W51, W50 11 10 01 T5F 00 W 62 0 Timer 5 interrupt Timer 5 underflow signal (T5UDF) (Note 4) W63 0 Timer LC (4) 1/2 LCD clock 1 ORCLK 1 Reload register RLC (4) (TLCA) (TLCA) Register A Watchdog timer (16) INSTCK 1 - - - - - - - - - - - - - - - - - - - 16 (Note 7) WRST instruction S Q WDF1 R Reset signal S Q (Note 9) WEF DWDT instruction R + WRST instruction(Note 8) D Q WDF2 T R Watchdog reset signal Reset signal INSTCK : Instruction clock (system clock divided by 3) ORCLK : Prescaler output (instruction clock divided by 1 to 256) Data is set automatically from each reload register when timer underflows (auto-reload function). Notes 4: Count source is stopped by clearing to "0." 5: XIN cannot be used as count source when bit 1 (MR1) of register MR is set to "1" and f(XIN) oscillation is stopped. 6: This timer is initialized (initial value = FFFF16) by stop of count source (W52 = "0"). 7: Flag WDF1 is cleared to "0" and the next instruction is skipped when the WRST instruction is executed while flag WDF1 = "1". The next instruction is not skipped even when the WRST instruction is executed while flag WDF1 = "0". 8: Flag WEF is cleared to "0" and watchdog timer reset does not occur when the DWDT instruction and WRST instruction are executed continuously. 9: The WEF flag is set to "1" at system reset or RAM back-up mode. Fig. 26 Timer structure (2) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-35 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group Table 10 Timer related registers Timer control register PA PA0 Prescaler control bit 0 1 Timer control register W1 W13 Timer 1 count auto-stop circuit selection bit (Note 2) W12 Timer 1 control bit W11 Timer 1 count source selection bits W10 CNTR0 output control bit W22 Timer 2 control bit W21 Timer 2 count source selection bits W20 Timer 3 count auto-stop circuit selection bit (Note 3) W32 Timer 3 control bit W31 W30 Timer 3 count source selection bits (Note 4) at power down : state retained R/W TAW1/TW1A 0 1 0 1 Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating W11 W10 Count source 0 Instruction clock (INSTCK) 0 0 Prescaler output (ORCLK) 1 1 Timer 5 underflow signal (T5UDF) 0 1 CNTR0 input 1 at reset : 00002 at power down : state retained R/W TAW2/TW2A 0 1 0 1 Timer 1 underflow signal divided by 2 output Timer 2 underflow signal divided by 2 output Stop (state retained) Operating W21 W20 Count source 0 System clock (STCK) 0 0 Prescaler output (ORCLK) 1 1 Timer 1 underflow signal (T1UDF) 0 1 PWM signal (PWMOUT) 1 Timer control register W3 W33 W TPAA Stop (state initialized) Operating at reset : 00002 Timer control register W2 W23 at power down : 02 at reset : 02 at reset : 00002 at power down : state retained R/W TAW3/TW3A 0 1 0 1 Timer 3 count auto-stop circuit not selected Timer 3 count auto-stop circuit selected Stop (state retained) Operating W31 W30 Count source 0 PWM signal (PWMOUT) 0 0 Prescaler output (ORCLK) 1 1 Timer 2 underflow signal (T2UDF) 0 1 CNTR1 input 1 Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10="1"). 3: This function is valid only when the timer 3 count start synchronous circuit is selected (I20="1"). 4: Port C output is invalid when CNTR1 input is selected for the timer 3 count source. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-36 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group Timer control register W4 W43 CNTR1 output control bit W42 PWM signal "H" interval expansion function control bit W41 Timer 4 control bit W40 Timer 4 count source selection bit 0 1 0 1 0 1 0 1 Timer control register W5 W53 Not used W52 Timer 5 control bit W51 Timer 5 count value selection bits W50 Timer LC control bit 0 1 0 1 W62 Timer LC count source selection bit W61 CNTR1 output auto-control circuit selection bit D7/CNTR0 pin function selection bit (Note 2) W60 at power down : state retained R/W TAW5/TW5A This bit has no function, but read/write is enabled. Stop (state initialized) Operating W51 W50 0 0 0 1 1 0 1 1 Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts at reset : 00002 0 1 0 1 0 1 0 1 R/W TAW4/TW4A CNTR1 output invalid CNTR1 output valid PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK) divided by 2 at reset : 00002 Timer control register W6 W63 at power down : 00002 at reset : 00002 at power down : state retained R/W TAW6/TW6A Stop (state retained) Operating Bit 4 (T54) of timer 5 Prescaler output (ORCLK) CNTR1 output auto-control circuit not selected CNTR1 output auto-control circuit selected D7(I/O)/CNTR0 input CNTR0 input/output/D7 (input) Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: CNTR0 input is valid only when CNTR0 input is selected for the timer 1 count source. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-37 HARDWARE 4524 Group FUNCTION BLOCK OPERATIONS (1) Timer control registers (2) Prescaler (interrupt function) * Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction. * Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. * Timer control register W2 Register W2 controls the selection of CNTR0 output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. * Timer control register W3 Register W3 controls the selection of timer 3 count auto-stop circuit, and the count operation and count source of timer 3. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. * Timer control register W4 Register W4 controls the CNTR1 output, the expansion of "H" interval of PWM output, and the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A. * Timer control register W5 Register W5 controls the count operation and count source of timer 5. Set the contents of this register through register A with the TW5A instruction. The TAW5 instruction can be used to transfer the contents of register W5 to register A. * Timer control register W6 Register W6 controls the operation and count source of timer LC, the selection of CNTR1 output auto-control circuit and the D7/ CNTR0 pin function. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to transfer the contents of register W6 to register A.. Prescaler is an 8-bit binary down counter with the prescaler reload register PRS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; set data in prescaler, and set the bit 0 of register PA to "1." When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes "0"), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, 3, 4 and LC count sources. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z (3) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; set data in timer 1 set count source by bits 0 and 1 of register W1, and set the bit 2 of register W1 to "1." When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to "1." Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to "1." Timer 1 underflow signal divided by 2 can be output from CNTR0 pin by clearing bit 3 of register W2 to "0" and setting bit 0 of register W6 to "1". 1-38 HARDWARE 4524 Group FUNCTION BLOCK OPERATIONS (4) Timer 2 (interrupt function) (6) Timer 4 (interrupt function) Timer 2 is an 8-bit binary down counter with the timer 2 reload register (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. Timer 2 starts counting after the following process; set data in timer 2, select the count source with the bits 0 and 1 of register W2, and set the bit 2 of register W2 to "1." Timer 4 is an 8-bit binary down counter with two timer 4 reload registers (R4L, R4H). Data can be set simultaneously in timer 4 and the reload register R4L with the T4AB instruction. Data can be set in the reload register R4H with the T4HAB instruction. The contents of reload register R4L set with the T4AB instruction can be set to timer 4 again with the T4R4L instruction. Data can be read from timer 4 with the TAB4 instruction. Stop counting and then execute the T4AB or TAB4 instruction to read or set timer 4 data. When executing the T4HAB instruction to set data to reload register R4H while timer 4 is operating, avoid a timing when timer 4 underflows. Timer 4 starts counting after the following process; set data in timer 4 set count source by bit 0 of register W4, and set the bit 1 of register W4 to "1." When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 interrupt request flag (T2F) is set to "1," new data is loaded from reload register R2, and count continues (auto-reload function). Timer 2 underflow signal divided by 2 can be output from CNTR0 pin by setting bit 3 of register W2 to "1" and setting bit 0 of register W6 to "1". (5) Timer 3 (interrupt function) Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction. Data can be read from timer 3 with the TAB3 instruction. Stop counting and then execute the T3AB or TAB3 instruction to read or set timer 3 data. When executing the TR3AB instruction to set data to reload register R3 while timer 3 is operating, avoid a timing when timer 3 underflows. Timer 3 starts counting after the following process; set data in timer 3 set count source by bits 0 and 1 of register W3, and set the bit 2 of register W3 to "1." When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes "0"), the timer 3 interrupt request flag (T3F) is set to "1," new data is loaded from reload register R3, and count continues (auto-reload function). INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 0 of register I2 to "1." Also, in this time, the auto-stop function by timer 3 underflow can be performed by setting the bit 3 of register W3 to "1." Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z When a value set in reload register R4L is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes "0"), the timer 4 interrupt request flag (T4F) is set to "1," new data is loaded from reload register R4L, and count continues (auto-reload function). When bit 3 of register W4 is set to "1", timer 4 reloads data from reload register R4L and R4H alternately each underflow. Timer 4 generates the PWM signal (PWMOUT) of the "L" interval set as reload register R4L, and the "H" interval set as reload register R4H. The PWM signal (PWMOUT) is output from CNTR1 pin. When bit 2 of register W4 is set to "1" at this time, the interval (PWM signal "H" interval) set to reload register R4H for the counter of timer 4 is extended for a half period of count source. In this case, when a value set in reload register R4H is n, timer 4 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set "1" or more to reload register R4H. When bit 1 of register W6 is set to "1", the PWM signal output to CNTR1 pin is switched to valid/invalid each timer 3 underflow. However, when timer 3 is stopped (bit 2 of register W3 is cleared to "0"), this function is canceled. Even when bit 1 of a register W4 is cleared to "0" in the "H" interval of PWM signal, timer 4 does not stop until it next timer 4 underflow. When clearing bit 1 of register W4 to "0" to stop timer 4, avoid a timing when timer 4 underflows. 1-39 HARDWARE 4524 Group (7) Timer 5 (interrupt function) Timer 5 is a 16-bit binary down counter. Timer 5 starts counting after the following process; set count value by bits 0 and 1 of register W5, and set the bit 2 of register W5 to "1." Count source for timer 5 is the sub-clock input (XCIN). Once count is started, when timer 5 underflows (the set count value is counted), the timer 5 interrupt request flag (T5F) is set to "1," and count continues. Bit 4 of timer 5 can be used as the timer LC count source for the LCD clock generating. When bit 2 of register W5 is cleared to "0", timer 5 is initialized to "FFFF16" and count is stopped. Timer 5 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When timer 5 underflow occurs at clock operating mode, system returns from the power down state. (8) Timer LC Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data. Timer LC starts counting after the following process; set data in timer LC, select the count source with the bit 2 of register W6, and set the bit 3 of register W6 to "1." FUNCTION BLOCK OPERATIONS (9) Timer input/output pin (D7/CNTR0 pin, C/CNTR1 pin) CNTR0 pin is used to input the timer 1 count source and output the timer 1 and timer 2 underflow signal divided by 2. CNTR1 pin is used to input the timer 3 count source and output the PWM signal generated by timer 4. When the PWM signal is output from C/CNTR1 pin, set "0" to the output latch of port C. The D7/CNTR0 pin function can be selected by bit 0 of register W6. The selection of CNTR1 output signal can be controlled by bit 3 of register W4. When the CNTR0 input is selected for timer 1 count source, timer 1 counts the rising waveform of CNTR0 input. When the CNTR1 input is selected for timer 3 count source, timer 3 counts the rising waveform of CNTR1 input. Also, when the CNTR1 input is selected, the output of port C is invalid (high-impedance state). (10) Timer interrupt request flags (T1F, T2F, T3F, T4F, T5F) Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, SNZT4, SNZT5). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction. When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes "0"), new data is loaded from reload register RLC, and count continues (auto-reload function). Timer LC underflow signal divided by 2 can be used for the LCD clock. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-40 HARDWARE 4524 Group (11) Count start synchronization circuit (timer 1, timer 3) Timer 1 and timer 3 have the count start synchronous circuit which synchronizes the input of INT0 pin and INT1 pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to "1" and the control by INT0 pin input can be performed. Timer 3 count start synchronous circuit function is selected by setting the bit 0 of register I2 to "1" and the control by INT1 pin input can be performed. When timer 1 or timer 3 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT0 pin or INT1 pin. The valid waveform of INT0 pin or INT1 pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 or I20 to "0" or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 or timer 3 underflow. (12) Count auto-stop circuit (timer 1, timer 3) Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to "1". It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected. Timer 3 has the count auto-stop circuit which is used to stop timer 3 automatically by the timer 3 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W3 to "1". It is cleared by the timer 3 underflow and the count source to timer 3 is stopped. This function is valid only when the timer 3 count start synchronous circuit is selected. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z FUNCTION BLOCK OPERATIONS (13) Precautions Note the following for the use of timers. * Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. * Timer count source Stop timer 1, 2, 3, 4 and LC counting to change its count source. * Reading the count value Stop timer 1, 2, 3 or 4 counting and then execute the data read instruction (TAB1, TAB2, TAB3, TAB4) to read its data. * Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the data write instruction (T1AB, T2AB, T3AB, T4AB, TLCA) to write its data. * Writing to reload register R1, R3, R4H When writing data to reload register R1, reload register R3 or reload regiser R4H while timer 1, timer 3 or timer 4 is operating, avoid a timing when timer 1, timer 3 or timer 4 underflows. * Timer 4 Avoid a timing when timer 4 underflows to stop timer 4. When "H" interval extension function of the PWM signal is set to be "valid", set "1" or more to reload register R4H. * Timer 5 Stop timer 5 counting to change its count source. * Timer input/output pin Set the port C output latch to "0" to output the PWM signal from C/CNTR pin. 1-41 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group CNTR1 output: invalid (W43 = "0") Timer 4 count source Timer 4 count value (Reload register) 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 (R4L) (R4L) (R4L) (R4L) (R4L) Timer 4 underflow signal PWM signal (output invalid) PWM signal "L" fixed Timer 4 start CNTR1 output: valid (W43 = "1") PWM signal "H" interval extension function: invalid (W42 = "0") Timer 4 count source Timer 4 count value (Reload register) 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) Timer 4 underflow signal 3 clock PWM signal 3 clock PWM period 7 clock PWM period 7 clock Timer 4 start CNTR1 output: valid (W43 = "1") PWM signal "H" interval extension function: valid (W42 = "1") (Note) Timer 4 count source Timer 4 count value (Reload register) 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 (R4L) (R4H) (R4L) (R4H) (R4L) (R4H) Timer 4 underflow signal 3.5 clock PWM signal Timer 4 start PWM period 7.5 clock 3.5 clock PWM period 7.5 clock Note: At PWM signal "H" interval extension function: valid, set "0116" or more to reload register R4H. Fig. 27 Timer 4 operation (reload register R4L: "0316", R4H: "0216") Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-42 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group CNTR1 output auto-control circuit by timer 3 is selected. CNTR1 output: valid (W43 = "1") CNTR1 output auto-control circuit selected (W61 = "1") PWM signal Timer 3 underflow signal Timer 3 start CNTR1 output CNTR1 output start CNTR1 output auto-control function PWM signal Timer 3 underflow signal Timer 3 start Timer 3 stop Register W61 CNTR1 output CNTR1 output start CNTR1 output stop When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is invalid, the CNTR1 output invalid state is retained. When the CNTR1 output auto-control function is set to be invalid while the CNTR1 output is valid, the CNTR1 output valid state is retained. When timer 3 is stopped, the CNTR1 output auto-control function becomes invalid. Note: When the PWM signal is output from C/CNTR1 pin, set the output latch of port C to "0". Fig. 28 CNTR1 output auto-control function by timer 3 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-43 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group Waveform extension function of CNTR1 output "H" interval: Invalid (W42 = "0"), CNTR1 output: valid (W43 = "1"), Count source: XIN input selected (W40 = "0"), Reload register R4L: "0316" Reload register R4H: "0216" Timer 4 count start timing Machine cycle Mi Mi+1 Mi+2 TW4A instruction execution cycle (W41) 1 System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 (R4L) (R4H) (R4L) Timer 4 underflow signal PWM signal Timer 4 count start timing Timer 4 count stop timing Machine cycle Mi Mi+1 Mi+2 TW4A instruction execution cycle (W41) 0 System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W41 Timer 4 count value (Reload register) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R4H) (R4L) 0216 (R4H) Timer 4 underflow signal PWM signal (Note 1) Timer 4 count stop timing Notes 1: In order to stop timer 4 at CNTR1 output valid (W43 = "1"), avoid a timing when timer 4 underflows. If these timings overlap, a hazard may occur in a CNTR1 output waveform. 2: At CNTR1 output valid, timer 4 stops after "H" interval of PWM signal set by reload register R4H is output. Fig. 29 Timer 4 count start/stop timing Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-44 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from "FFFF16" after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches "0000 16," the next count pulse is input), the WDF1 flag is set to "1." If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to "1," and the RESET pin outputs "L" level to reset the microcomputer. Execute the WRST instruction at each period of less than 65534 machine cycle by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to "1" after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to "0" and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is "1", the WDF1 flag is cleared to "0" and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is "0", the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid. FFFF 1 6 Value of 16-bit timer (WDT) 000016 WDF1 flag 65534 count (Note) WDF2 flag RESET pin output Reset released WRST instruction executed (skip executed) System reset After system is released from reset (= after program is started), timer WDT starts count down. When timer WDT underflow occurs, WDF1 flag is set to "1." When the WRST instruction is executed, WDF1 flag is cleared to "0," the next instruction is skipped. When timer WDT underflow occurs while WDF1 flag is "1," WDF2 flag is set to "1" and the watchdog reset signal is output. The output transistor of RESET pin is turned "ON" by the watchdog reset signal and system reset is executed. Note: The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock. Fig. 30 Watchdog timer function Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-45 HARDWARE FUNCTION BLOCK OPERATIONS ; WDF1 flag cleared *** WRST ; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared *** DI DWDT WRST *** Fig. 31 Program example to start/stop watchdog timer WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF Oscillation stop *** When the watchdog timer is used, clear the WDF1 flag at a cycle of less than 65534 machine cycles with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 31). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initialize the WDF1 flag with the WRST instruction just before the system enters the power down state (refer to Figure 32). The watchdog timer function is valid after system is returned from the power down. When not using the watchdog timer function, stop the watchdog timer function with the DWDT instruction and the WRST instruction continuously every system is returned from the power down. *** 4524 Group Fig. 32 Program example to enter the mode when using the watchdog timer Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-46 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group A/D CONVERTER (Comparator) Table 11 A/D converter characteristics Characteristics Parameter Successive comparison method Conversion format The 4524 Group has a built-in A/D conversion circuit that performs conversion by 10-bit successive comparison method. Table 11 shows the characteristics of this A/D converter. This A/D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset values. Resolution Relative accuracy 10 bits Linearity error: 2LSB Differential non-linearity error: 0.9LSB 31 s (High-speed through-mode at 6.0 MHz oscillation frequency) 8 Conversion speed Analog input pin Register B (4) Register A (4) 4 4 IAP2 (P20-P23) IAP3 (P30-P33) OP2A (P20-P23) OP3A (P30-P33) TAQ1 TQ1A Q13 Q12 Q11 Q10 4 TAQ2 TQ2A Q23 Q22 Q21 Q20 4 4 TAQ3 TQ3A Q33 Q32 Q31 Q30 4 4 2 8 TALA TABAD 8 TADAB Instruction clock 1/6 3 Q13 P20/AIN0 P21/AIN1 P22/AIN2 P23/AIN3 P30/AIN4 P31/AIN5 P32/AIN6 P33/AIN7 8-channel multi-plexed analog switch 0 A/D control circuit 1 ADF (1) A/D interrupt 1 Comparator Successive comparison register (AD) (10) 0 Q13 Q13 0 8 10 10 DAC operation signal 0 1 1 1 Q13 8 DA converter 8 8 VDD (Note 1) VSS Comparator register (8) (Note 2) Notes 1: This switch is turned ON only when A/D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q13=1). The value of the comparator register is retained even when the mode is switched to the A/D conversion mode (Q13=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. Fig. 33 A/D conversion circuit structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-47 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group Table 12 A/D control registers A/D control register Q1 Q13 A/D operation mode selection bit Q12 Q11 Analog input pin selection bits Q10 at reset : 00002 A/D conversion mode Comparator mode Q12 Q11 Q10 0 0 0 AIN0 0 0 1 AIN1 0 1 0 AIN2 0 1 1 AIN3 1 0 0 AIN4 1 0 1 AIN5 1 1 0 AIN6 1 1 1 AIN7 A/D control register Q2 Q23 P23/AIN3 pin function selection bit Q22 P22/AIN2 pin function selection bit Q21 P21/AIN1 pin function selection bit Q20 P20/AIN0 pin function selection bit at reset : 00002 0 1 0 1 0 1 0 1 A/D control register Q3 Q33 P33/AIN7 pin function selection bit Q32 P32/AIN6 pin function selection bit Q31 P31/AIN5 pin function selection bit Q30 P30/AIN4 pin function selection bit R/W TAQ1/TQ1A Analog input pins at power down : state retained R/W TAQ2/TQ2A at power down : state retained R/W TAQ3/TQ3A P23 AIN3 P22 AIN2 P21 AIN1 P20 AIN0 at reset : 00002 0 1 0 1 0 1 0 1 at power down : state retained P33 AIN7 P32 AIN6 P31 AIN5 P30 AIN4 Note: "R" represents read enabled, and "W" represents write enabled. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-48 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (1) A/D control register (4) A/D conversion completion flag (ADF) * A/D control register Q1 Register Q1 controls the selection of A/D operation mode and the selection of analog input pins. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. * A/D control register Q2 Register Q2 controls the selection of P20/AIN0-P23/AIN3. Set the contents of this register through register A with the TQ2A instruction. The TAQ2 instruction can be used to transfer the contents of register Q2 to register A. * A/D control register Q3 Register Q3 controls the selection of P30/AIN4-P33/AIN7. Set the contents of this register through register A with the TQ3A instruction. The TAQ3 instruction can be used to transfer the contents of register Q3 to register A. A/D conversion completion flag (ADF) is set to "1" when A/D conversion completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction. (2) Operating at A/D conversion mode The A/D conversion mode is set by setting the bit 3 of register Q1 to "0." (3) Successive comparison register AD Register AD stores the A/D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this register can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute these instructions during A/D conversion. When the contents of register AD is n, the logic value of the comparison voltage Vref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following formula: (5) A/D conversion start instruction (ADST) A/D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (6) Operation description A/D conversion is started with the A/D conversion start instruction (ADST). The internal operation during A/D conversion is as follows: When the A/D conversion starts, the register AD is cleared to "00016." Next, the topmost bit of the register AD is set to "1," and the comparison voltage V ref is compared with the analog input voltage VIN. When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to "1." When the comparison result is Vref > VIN, it is cleared to "0." The 4524 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A/D conversion stops after 62 machine cycles (31 s when f(X IN) = 6.0 MHz in high-speed through mode) from the start, and the conversion result is stored in the register AD. An A/D interrupt activated condition is satisfied and the ADF flag is set to "1" as soon as A/D conversion completes (Figure 34). Logic value of comparison voltage Vref Vref = V DD n 1024 n: The value of register AD (n = 0 to 1023) Table 13 Change of successive comparison register AD during A/D conversion At starting conversion ------------- 1st comparison 2nd comparison 3rd comparison After 10th comparison completes 1: 1st comparison result 3: 3rd comparison result 9: 9th comparison result Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z Comparison voltage (Vref) value Change of successive comparison register AD 1 1 1 0 1 2 0 0 ----- 0 0 0 ------------- 2 ------------- VDD ----- ------------- 0 0 0 2 ------------- 1 ----- ------------- 0 0 0 VDD ------------- 2 3 ----- ------------- 8 9 A VDD 4 VDD 2 A/D conversion result 1 VDD 2 VDD VDD 4 8 VDD 1024 2: 2nd comparison result 8: 8th comparison result A: 10th comparison result 1-49 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (7) A/D conversion timing chart Figure 34 shows the A/D conversion timing chart. ADST instruction 62 machine cycles A/D conversion completion flag (ADF) DAC operation signal Fig. 34 A/D conversion timing chart (8) How to use A/D conversion How to use A/D conversion is explained using as example in which the analog input from P30/AIN4 pin is A/D converted, and the highorder 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A/D interrupt is not used in this example. Select the AIN4 pin function with the bit 0 of the register Q3. Select the A IN4 pin function and A/D conversion mode with the register Q1 (refer to Figure 35). Execute the ADST instruction and start A/D conversion. Examine the state of ADF flag with the SNZAD instruction to determine the end of A/D conversion. Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z (Bit 3) (Bit 0) 1 A/D control register Q2 A IN4 pin function selected (Bit 3) 0 (Bit 0) 1 0 0 A/D control register Q1 A IN4 pin selected A/D conversion mode : Set an arbitrary value. Fig. 35 Setting registers 1-50 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (9) Operation at comparator mode The A/D converter is set to comparator mode by setting bit 3 of the register Q1 to "1." Below, the operation at comparator mode is described. (10) Comparator register In comparator mode, the built-in DA comparator is connected to the 8-bit comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruction. When changing from A/D conversion mode to comparator mode, the result of A/D conversion (register AD) is undefined. However, because the comparator register is separated from register AD, the value is retained even when changing from comparator mode to A/D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of comparison voltage Vref generated by the built-in DA converter can be determined from the following formula: Logic value of comparison voltage Vref Vref = VDD 256 n n: The value of register AD (n = 0 to 255) (12) Comparator operation start instruction (ADST instruction) In comparator mode, executing ADST starts the comparator operating. The comparator stops 8 machine cycles after it has started (4 s at f(XIN) = 6.0 MHz in high-speed through mode). When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1." (13) Notes for the use of A/D conversion * TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, simultaneously, the low-order 2 bits of register A is "0." * Operation mode of A/D converter Do not change the operating mode (both A/D conversion mode and comparator mode) of A/D converter with the bit 3 of register Q1 while the A/D converter is operating. Clear the bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to A/D conversion mode. The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to the register Q1, and execute the SNZAD instruction to clear the ADF flag. (11) Comparison result store flag (ADF) In comparator mode, the ADF flag, which shows completion of A/D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to "1." The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction. ADST instruction 8 machine cycles Comparison result store flag(ADF) DAC operation signal Comparator operation completed. (The value of ADF is determined) Fig. 36 Comparator operation timing chart Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-51 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (14) Definition of A/D converter accuracy Vn: Analog input voltage when the output data changes from "n" to "n+1" (n = 0 to 1022) The A/D conversion accuracy is defined below (refer to Figure 37). * 1LSB at relative accuracy * Relative accuracy Zero transition voltage (V0T) This means an analog input voltage when the actual A/D conversion output data changes from "0" to "1." Full-scale transition voltage (VFST) This means an analog input voltage when the actual A/D conversion output data changes from "1023" to "1022." Linearity error This means a deviation from the line between V0T and VFST of a converted value between V0T and VFST. Differential non-linearity error This means a deviation from the input potential difference required to change a converter value between V0T and VFST by 1 LSB at the relative accuracy. VFST-V0T (V) 1022 * 1LSB at absolute accuracy VDD 1024 (V) * Absolute accuracy This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics. Output data Full-scale transition voltage (VFST) 1023 1022 Differential non-linearity error = b-a [LSB] a Linearity error = c [LSB] a b a n+1 n Actual A/D conversion characteristics c a: 1LSB by relative accuracy b: Vn+1-Vn c: Difference between ideal Vn and actual Vn Ideal line of A/D conversion between V0-V1022 1 0 V0 V1 Zero transition voltage (V0T) Vn Vn+1 V1022 VDD Analog voltage Fig. 37 Definition of A/D conversion accuracy Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-52 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group SERIAL I/O Table 14 Serial I/O pins The 4524 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; * serial I/O register SI * serial I/O control register J1 * serial I/O transmit/receive completion flag (SIOF) * serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1. 1/8 1/4 1/2 INSTCK Pin D6/SCK D5/SOUT D4/SIN Pin function when selecting serial I/O Clock I/O (SCK) Serial data output (SOUT) Serial data input (SIN) Note: Even when the SCK, S OUT, SIN pin functions are used, the input of D6, D5, D4 are valid. J13J12 00 01 10 Synchronous circuit Serial I/O counter (3) SIOF Serial I/O interrupt 11 D6/SCK D5/SOUT D4/SIN SCK Q S SST instruction R Internal reset signal SOUT SIN MSB Serial I/O register (8) LSB TABSI TSIAB Register B (4) TABSI Register A (4) J11 J10 Fig. 38 Serial I/O structure Table 15 Serial I/O control register Serial I/O control register J1 J13 J12 J11 J10 at reset : 00002 at power down : state retained R/W TAJ1/TJ1A J13 J12 Synchronous clock 0 Instruction clock (INSTCK) divided by 8 0 Serial I/O synchronous clock selection bits 0 1 Instruction clock (INSTCK) divided by 4 0 Instruction clock (INSTCK) divided by 2 1 1 External clock (SCK input) 1 J11 J10 Port function 0 D6, D5, D4 selected/SCK, SOUT, SIN not selected 0 Serial I/O port function selection bits 1 SCK, SOUT, D4 selected/D6, D5, SIN not selected 0 0 SCK, D5, SIN selected/D6, SOUT, D4 not selected 1 1 SCK, SOUT, SIN selected/D6, D5, D4 not selected 1 Note: "R" represents read enabled, and "W" represents write enabled. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-53 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group At transmit (D7-D0: transfer data) At receive SIN pin Serial I/O register (SI) SOUT pin SOUT pin SIN pin D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 *D 7 D6 D5 D4 D3 D2 D1 * ** * * ** * Transfer data set Transfer start * *D 7 D6 D5 D4 D3 D2 * ** * * ** * Serial I/O register (SI) * ** * * ** * D0 ** * * ** * D1 D0 Transfer complete * * * ** * D7 D6 D5 D4 D3 D2 D1 D0 Fig. 39 Serial I/O register state when transfer (1) Serial I/O register SI (3) Serial I/O start instruction (SST) Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmitted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, do not select the SCK pin. When the SST instruction is executed, the SIOF flag is cleared to "0" and then serial I/O transmission/reception is started. (4) Serial I/O control register J1 Register J1 controls the synchronous clock, D6/SCK, D5/SOUT and D4/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A. (2) Serial I/O transmit/receive completion flag (SIOF) Serial I/O transmit/receive completion flag (SIOF) is set to "1" when serial data transmit or receive operation completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the interrupt or the skip instruction. The SIOF flag is cleared to "0" when the interrupt occurs or when the next instruction is skipped with the skip instruction. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-54 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (5) How to use serial I/O wiring between each pin with a resistor. Figure 40 shows the data transfer timing and Table 16 shows the data transfer sequence. Figure 40 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the Master (clock control) Slave (external clock) SRDY signal D3 (Bit 3) 0 0 1 (Bit 0) 1 D3 SCK SCK SOUT SIN SIN SOUT (Bit 0) (Bit 3) Serial I/O control register J1 Serial I/O port SCK,SOUT,SIN 1 1 1 Serial I/O control register J1 Serial I/O port SCK,SOUT,SIN 1 Instruction clock/8 selected as synchronous clock External clock selected as synchronous clock (Bit 0) (Bit 3) 0 (Bit 0) (Bit 3) Interrupt control register V2 0 Interrupt control register V2 Serial I/O interrupt enable bit Serial I/O interrupt enable bit (SNZSI instruction valid) (SNZSI instruction valid) : Set an arbitrary value. Fig. 40 Serial I/O connection example Master SOUT M7' SIN M0 S7 ' M1 S0 M2 S1 M3 S2 M4 S3 M5 S4 M6 S5 M7 S6 S7 SST instruction SCK Slave SST instruction SRDY signal SOUT SI N S0 S7 ' M7' S1 M0 S2 M1 S3 M2 S4 M3 S5 M4 S6 M5 S7 M6 M7 M0-M7: Contents of master serial I/O register S0-S7: Contents of slave serial I/O register Rising of SCK: Serial input Falling of SCK: Serial output Fig. 41 Timing of serial I/O data transfer Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-55 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group Table 16 Processing sequence of data transfer from master to slave Slave (reception) Master (transmission) [Initial setting] [Initial setting] * Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 40. * Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 40. TJ1A and TV2A instructions * Setting the port received the reception enable signal (SRDY) to the input mode. (Port D3 is used in this example) TJ1A and TV2A instructions * Setting the port transmitted the reception enable signal (SRDY) and outputting "H" level (reception impossible). SD instruction * [Transmission enable state] * Storing transmission data to serial I/O register SI. TSIAB instruction (Port D3 is used in this example) SD instruction *[Reception enable state] * The SIOF flag is cleared to "0." SST instruction * "L" level (reception possible) is output from port D3. RD instruction [Transmission] *Check port D3 is "L" level. [Reception] SZD instruction *Serial transfer starts. SST instruction *Check transmission completes. * Check reception completes. SNZSI instruction *Wait (timing when continuously transferring) SNZSI instruction * "H" level is output from port D3. SD instruction [Data processing] 1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally because serial transmit/receive is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to "1" when the clock is counted 8 times after executing the SST instruction. Be sure to set the initial level of the external clock to "H." Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-56 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group LCD FUNCTION (2) LCD clock control The 4524 Group has an LCD (Liquid Crystal Display) controller/ driver. When the proper voltage is applied to LCD power supply input pins (VLC1 -V LC3 ) and data are set in timer control register (W6), timer LC, LCD control registers (L1, L2), and LCD RAM, the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 20 segment signal output pins can be used to drive the LCD. By using these pins, up to 80 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. The LCD power input pins (VLC1-VLC3) are also used as pins SEG0-SEG2. When SEG0-SEG2. The internal power (VDD) is used for the LCD power. The LCD clock is determined by the timer LC count source selection bit (W6 2 ), timer LC control bit (W6 3 ), and timer LC. Accordingly, the LCD clock frequency (F) is obtained by the following formula. Numbers ( to ) shown below the formula correspond to numbers in Figure 42, respectively. (1) Duty and bias * When using the bit 4 of timer 5 as timer LC count source (W62="0") * When using the prescaler output (ORCLK) as timer LC count source (W62="1") F = ORCLK There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. * 1/2 duty, 1/2 bias * 1/3 duty, 1/3 bias * 1/4 duty, 1/3 bias 1 LC + 1 F = T54 1 2 [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Table 17 Duty and maximum number of displayed pixels Duty 1/2 1/3 1/4 1 LC + 1 1 2 F n Frame frequency = Maximum number of displayed pixels Used COM pins 40 segments COM0, COM1 (Note) 60 segments COM0-COM2 (Note) 80 segments COM0-COM3 n F Frame period = (Hz) (s) F: LCD clock frequency 1/n: Duty Note: Leave unused COM pins open. (Note) W63 W62 T54 0 ORCLK 1 0 Timer LC (4) 1 Reload register RLC (TLCA) 1/2 LCD clock (4) (TLCA) Register A Note: Count source is stopped by setting "0" to this bit. Fig. 42 LCD clock control circuit structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-57 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group VLC3/SEG0 VLC1/SEG2 VLC2/ SEG1 COM3 COM1 COM2 COM0 SEG3 to SEG19 r r SEG0 to SEG2 output r ......... r Multiplexer r r Control signal Bias control Common driver Segment driver Selector Decoder RAM ... Segment driver ... Selector ... RAM LCD clock (from timer block) 1/2,1/3,1/4 counter LCD ON/OFF control L13 L12 L11 L10 L23 L22 L21 L20 Register A Fig. 43 LCD controller/driver Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-58 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (3) LCD RAM (4) LCD drive waveform RAM contains areas corresponding to the liquid crystal display. When "1" is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed. When "1" is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lV LC3l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common output pin becomes VLC3 level. Z X 1 Bits Y 8 9 10 11 12 13 14 15 COM 3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM3 2 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM2 Note: The area marked " 12 1 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM1 13 0 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 COM0 3 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM3 2 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM2 1 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM1 0 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 COM0 3 SEG16 SEG17 SEG18 SEG19 14 2 1 SEG16 SEG16 SEG17 SEG17 SEG18 SEG18 SEG19 SEG19 0 SEG16 SEG17 SEG18 SEG19 COM3 COM2 COM1 COM0 " is not the LCD display RAM. Fig. 44 LCD RAM map Table 18 LCD control registers at reset : 00002 LCD control register L1 L13 Internal dividing resistor for LCD power supply selection bit (Note 2) L12 LCD control bit L11 LCD duty and bias selection bits L10 VLC3/SEG0 pin function switch bit (Note 3) L22 VLC2/SEG1 pin function switch bit (Note 4) L21 VLC1/SEG2 pin function switch bit (Note 4) L20 Internal dividing resistor for LCD power supply control bit Duty L11 L10 0 0 0 1 1 0 1 1 Bias Not available 1/2 1/3 1/4 at reset : 11112 0 1 0 1 0 1 0 1 R/W TAL1/TL1A 2r 3, 2r 2 r 3, r 2 Off On 0 1 0 1 LCD control register L2 L23 at power down : state retained 1/2 1/3 1/3 at power down : state retained W TL2A SEG0 VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: "r (resistor) multiplied by 3" is used at 1/3 bias, and "r multiplied by 2" is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG 2 pins are selected. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-59 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group 1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 14, 8) in RAM. 1 flame (2/F) M (1, 14, 8) COM0 0 (bit 0) COM1 1/F Voltage level VLC3 VLC1=VLC2 VSS COM1 1 X COM0 X (bit 3) VLC3 VLC1=VLC2 VSS SEG16 SEG16 COM1 SEG16 COM0 SEG16 ON OFF 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 14, 8) in RAM. 1 flame (3/F) M (1, 14, 8) COM0 1/F Voltage level 1 (bit 0) COM1 0 COM2 VLC3 VLC2 VLC1 VSS COM2 1 X (bit 3) COM1 SEG16 COM0 SEG16 COM2 SEG16 COM1 SEG16 COM0 SEG16 ON OFF ON VLC3 VLC2 VLC1 VSS 1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 14, 8) in RAM. 1 flame (4/F) M (1, 14, 8) COM0 COM1 COM2 COM3 1 /F Voltage level 0 (bit 0) 1 VLC3 VLC2 VLC1 VSS COM3 0 1 (bit 3) COM2 SEG16 COM1 COM0 F : LCD clock frequency SEG16 X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.) COM3 SEG16 ON COM2 SEG16 COM1 SEG16 OFF ON COM0 SEG16 VLC3 VLC2 VLC1 VSS OFF Fig. 45 LCD controller/driver structure Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 1-60 HARDWARE FUNCTION BLOCK OPERATIONS 4524 Group (5) LCD power supply circuit Select the LCD power circuit suitable for the LCD panel. The LCD control circuit structure is fixed by the following setting. Set the control of internal dividing resistor by bit 0 of register L2. Select the internal dividing resistor by bit 3 of register L1. Select the bias condition by bits 0 and 1 of register L1. * Internal dividing resistor The 4524 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is set to "0", the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to "0", the internal dividing resistor is turned off. The same six resistor (r) is prepared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows; * L13 = "0", 1/3 bias used: 2r 3 = 6r * L13 = "0", 1/2 bias used: 2r 2 = 4r * L13 = "1", 1/3 bias used: r 3 = 3r * L13 = "1", 1/2 bias used: r 2 = 2r * VLC3/SEG0 pin The selection of VLC3/SEG0 pin function is controlled with the bit 3 of register L2. When the VLC3 pin function is selected, apply voltage of V LC3 < VDD to the pin externally. When the SEG0 pin function is selected, VLC3 is connected to VDD internally. * VLC2/SEG1, VLC1/SEG2 pin The selection of VLC2/SEG1 pin function is controlled with the bit 2 of register L2. The selection of VLC1/SEG2 pin function is controlled with the bit 1 of register L2. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0 When ceramic resonator is used. When RC oscillation is used. When external clock is used. f(STCK) [MHz] f(STCK) [MHz] f(STCK) [MHz] 6 4.8 4.4 4.4 3.2 Recommended operating condition 2.2 2 (2.5) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 2.7 4 5.5 Recommended operating condition VDD [V] 2.7 Recommended operating condition 1.6 5.5 VDD [V] 2 (2.5) 2.7 4 5.5 VDD [V] 3-4 APPENDIX 3.1 Electrical characteristics 4524 Group 3.1.3 Electrical characteristics Table 3.1.4 Electrical characteristics 1 (Mask ROM version: Ta = -20 C to 85 C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol VOH Parameter "H" level output voltage Test conditions IOH = -10 mA IOH = -3 mA 4.1 VDD = 3 V IOH = -5 mA IOH = -1 mA 2.1 VDD = 5 V IOH = -20 mA 3 IOH = -6 mA IOH = -10 mA 4.1 2.1 IOH = -3 mA 2.4 VDD = 5 V P0, P1, P4, D0-D6, SCK, SOUT VOH "H" level output voltage D7, C, CNTR0, CNTR1 VDD = 3 V VOL "L" level output voltage "L" level output voltage "L" level output voltage V IOL = 6 mA 0.9 IOL = 2 mA 0.6 IOL = 15 mA 2 IOL = 5 mA 0.9 VDD = 3 V IOL = 9 mA IOL = 3 mA 1.4 0.9 VDD = 5 V IOL = 5 mA 2 IOL = 1 mA 0.6 IOL = 2 mA 0.9 VDD = 3 V "H" level input current 2.4 VDD = 3 V VDD = 5 V Unit V 2 0.9 P2, P3, RESET IIH Max. IOL = 12 mA IOL = 4 mA D0-D9, C, SCK, SOUT, CNTR0, CNTR1 VOL Typ. VDD = 5 V P0, P1, P4 VOL Limits Min. 3 V V V VI = VDD 1 A VI = 0 V P0, P1 No pull-up -1 A P0, P1, P2, P3, P4, D0-D7, VDCE, RESET, CNTR0, CNTR1, INT0, INT1 IIL "L" level input current P0, P1, P2, P3, P4, D0-D7, VDCE, SCK, SIN, CNTR0, CNTR1, INT0, INT1 Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-5 APPENDIX 3.1 Electrical characteristics 4524 Group Table 3.1.5 Electrical characteristics 2 (Mask ROM version: Ta = -20 C to 85 C, VDD = 2 to 5.5 V, unless otherwise noted) (One Time PROM version: Ta = -20 C to 85 C, VDD = 2.5 to 5.5 V, unless otherwise noted) Symbol IDD Parameter Test conditions VDD = 5 V Supply current at active mode (with a ceramic resonator) f(XIN) = 6 MHz f(XCIN) = 32 kHz Limits Min. f(STCK) = f(XIN)/8 Typ. 1.4 1.6 2 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 5.6 VDD = 5 V 1.1 2.2 f(XIN) = 4 MHz f(STCK) = f(XIN)/4 1.2 2.4 f(XCIN) = 32 kHz f(STCK) = f(XIN)/2 1.5 f(STCK) = f(XIN) 2 0.4 3 4 0.8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 0.5 1 0.6 1.2 f(STCK) = f(XIN) 0.8 1.6 110 120 f(STCK) = f(XIN)/8 at active mode (with a quartz-crystal VDD = 5 V f(STCK) = f(XIN)/8 55 f(XIN) = stop f(STCK) = f(XIN)/4 oscillator) f(XCIN) = 32 kHz f(STCK) = f(XIN)/2 60 65 70 140 VDD = 3 V f(STCK) = f(XIN) f(STCK) = f(XIN)/8 12 24 f(XIN) = stop f(STCK) = f(XIN)/4 13 26 f(XCIN) = 32 kHz f(STCK) = f(XIN)/2 14 f(STCK) = f(XIN) 28 30 VDD = 5 V 15 20 VDD = 3 V 5 at clock operation mode f(XCIN) = 32 kHz (POF instruction execution) at RAM back-up mode Ta = 25 C (POF2 instruction execution) VDD = 5 V 0.1 VI = 0 V P0, P1, RESET VT+ - VT- Hysteresis SCK, SIN, CNTR0, CNTR1, INT0, INT1 VT+ - VT- Hysteresis RESET VDD = 5 V 30 VDD = 3 V 50 60 120 VDD = 5 V 0.2 VDD = 3 V 0.2 VDD = 5 V 1 VDD = 3 V f(XIN) mA mA mA A 130 60 A A 15 1 A 10 VDD = 3 V Pull-up resistor value Unit 4 2.8 f(XCIN) = 32 kHz f(RING) 2.8 3.2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 VDD = 3 V f(XIN) = 4 MHz RPU Max. On-chip oscillator clock frequency VDD = 5 V Frequency error VDD = 3 V VDD = 5 V 10 %, Ta = 25 C 6 125 k 250 V V 0.4 1 0.5 2 1 3 MHz 1.8 17 % (with RC oscillation, RCOM RSEG error of external R, C not included ) VDD = 5 V 10 %, Ta = 25 C (Note) COM output impedance VDD = 5 V SEG output impedance VDD = 3 V VDD = 5 V 17 VDD = 3 V RVLC Internal resistor for LCD power supply 1.5 2 7.5 1.5 7.5 2 10 k 10 When dividing resistor 2r 3 selected 300 480 960 When dividing resistor 2r 2 selected 200 320 When dividing resistor r 3 selected 150 When dividing resistor r 2 selected 100 240 160 640 480 k k 320 Note: When RC oscillation is used, use the external 33 pF capacitor (C). Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-6 APPENDIX 3.1 Electrical characteristics 4524 Group 3.1.4 A/D converter recommended operating conditions Table 3.1.6 A/D converter recommended operating conditions (Comparator mode selected, Ta = -20 C to 85 C, unless otherwise noted) Symbol Parameter Supply voltage VDD Conditions Ta = 25 C Ta = -20 to 85 C VIA Analog input voltage f(XIN) Oscillation frequency VDD = 2.7 to 5.5 V Min. Limits Typ. Max. 2.7 5.5 3 5.5 0 VDD f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 0.8 0.4 f(STCK) = f(XIN)/2 0.2 f(STCK) = f(XIN) 0.1 Unit V V MHz Table 3.1.7 A/D converter characteristics (Ta = -20 C to 85 C, unless otherwise noted) Symbol Parameter Test conditions - - Resolution - Differential non-linearity error V0T Zero transition voltage VDD = 5.12 V VFST Full-scale transition voltage IADD A/D operating current VDD = 5 V (Note 1) VDD = 3 V A/D conversion time f(XIN) = 6 MHz Linearity error Min. Limits Typ. Ta = 25 C, VDD = 2.7 V to 5.5 V Unit Max. 10 2 bits LSB 0.9 LSB 20 12 5130 3075 0.9 0.3 248 124 62 31 8 20 15 32 16 8 4 mV Ta = -20 C to 85 C, VDD = 3 V to 5.5 V Ta = 25 C, VDD = 2.7 V to 5.5 V Ta = -20 C to 85 C, VDD = 3 V to 5.5 V TCONV 10 VDD = 3.072 V VDD = 5.12 V 0 0 5110 5120 VDD = 3.072 V 3063 3069 0.3 0.1 f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) - Comparator resolution - Comparator error (Note 2) VDD = 5.12 V - Comparator comparison time VDD = 3.072 V f(XIN) = 6 MHz 6 f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) mV mA s bits mV s Notes 1: When the A/D converter is used, IADD is added to IDD (supply current). 2: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison voltage Vref which is generated by the built-in DA converter can be obtained by the following formula. Logic value of comparison voltage Vref Vref = VDD 256 n n = Value of register AD (n = 0 to 255) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-7 APPENDIX 3.1 Electrical characteristics 4524 Group 3.1.5 Voltage drop detection circuit characteristics Table 3.1.8 Voltage drop detection circuit characteristics (Ta = -20 C to 85 C, unless otherwise noted) Symbol Test conditions Parameter Min. 3.3 2.7 VRST Detection voltage (Note 1) Ta = 25 C IRST Operation current at power down VDD = 5 V VDD = 3 V Detection time (Note 2) VDD (VRST-0.1 V) (Note 3) TRST Limits Typ. 3.5 50 30 0.2 Max. 3.7 4.2 100 60 1.2 Unit V A ms Notes 1: The detected voltage (VRST) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. 2: After the SVDE instruction is executed, the voltage drop detection circuit is valid at power down mode. 3: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST-0.1 V]. 3.1.6 Basic timing diagram Machine cycle Parameter Mi Mi+1 Pin (signal) name System clock STCK Port D output D0-D9 Port D input D0-D7 Ports P0, P1, P2, P3, P00-P03 P10-P13 P4 output P20-P23 P30-P33 P40-P43 Ports P0, P1, P2, P3, P00-P03 P10-P13 P4 input P20-P23 P30-P33 P40-P43 Interrupt input Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z INT0, INT1 3-8 APPENDIX 3.2 Typical characteristics 4524 Group 3.2 Typical characteristics The data described below are characteristic examples for the 4524 Group. Unless otherwise noted, the characteristics for Mask ROM version are shown here. The data shown here are just characteristics examples and are not guaranteed. For rated values, refer to "3.1 Electrical characteristics". Standard characteristics are different between Mask ROM version and One Time PROM version, due to the difference in the manufacturing processes. Even in the MCUs which have the same memory type, standard characteristics are different in each sample, too. 3.2.1 V DD-IDD characteristics (1) High-speed mode (ceramic resonance): V DD-IDD Measurement condition: f(X IN) = 6 MHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 C 4 3.5 High-speed through mode 3 I DD [mA] 2.5 High-speed frequency/2 mode 2 High-speed frequency/4 mode High-speed frequency/8 mode 1.5 1 0.5 0 2 2.5 3 3.5 VDD [V] 4 4.5 5 5.5 (2) High-speed mode (ceramic resonance): VDD-I DD Measurement condition: f(X IN) = 4 MHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 C 3 2.5 High-speed through mode I DD [mA] 2 High-speed frequency/2 mode 1.5 High-speed frequency/4 mode High-speed frequency/8 mode 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-9 APPENDIX 3.2 Typical characteristics 4524 Group (3) High-speed mode (ceramic resonance): VDD-I DD Measurement condition: f(X IN) = 2 MHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 C 2 1.8 High-speed through mode I DD [mA] 1.6 1.4 High-speed frequency/2 mode 1.2 High-speed frequency/4 mode High-speed frequency/8 mode 1 0.8 0.6 0.4 0.2 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] (4) High-speed mode (ceramic resonance): VDD-I DD Measurement condition: f(X IN) = 1 MHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 C 1.8 1.6 High-speed through mode 1.4 High-speed frequency/2 mode High-speed frequency/4 mode I DD [mA] 1.2 High-speed frequency/8 mode 1 0.8 0.6 0.4 0.2 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-10 APPENDIX 3.2 Typical characteristics 4524 Group (5) High-speed mode (ceramic resonance): V DD-IDD Measurement condition: f(X IN) = 400 kHz, f(XCIN) = stop, f(RING) = stop, Ta = 25 C 1.2 1.1 1 High-speed through mode 0.9 High-speed frequency/2 mode High-speed frequency/4 mode 0.8 I DD [mA] 0.7 High-speed frequency/8 mode 0.6 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD [V] (6) High-speed mode (on-chip oscillator): V DD-IDD Measurement condition: f(X IN) = stop f(X CIN) = stop, Ta = 25 C 1.2 1.1 1 0.9 High-speed through mode 0.8 I DD [mA] 0.7 0.6 High-speed frequency/2 mode 0.5 0.4 High-speed frequency/4 mode 0.3 High-speed frequency/8 mode 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-11 APPENDIX 3.2 Typical characteristics 4524 Group (7) High-speed mode (RC oscillation): R-I DD Measurement condition: f(X CIN) = stop, f(RING) = stop, V DD = 5.0 V, C = 33 pF, Ta = 25 C 2.6 2.4 2.2 2 1.8 I DD [mA] 1.6 1.4 1.2 1 0.8 High-speed High-speed High-speed High-speed 0.6 0.4 through mode frequency/2 mode frequency/4 mode frequency/8 mode 0.2 0 0 2 4 6 8 10 12 14 16 18 20 Resistor R [k] (8) High-speed mode (RC oscillation): R-I DD Measurement condition: f(X CIN) = stop, f(RING) = stop, V DD = 3.0 V, C = 33 pF, Ta = 25 C 1.3 1.2 1.1 1 0.9 I DD [mA] 0.8 0.7 0.6 0.5 0.4 0.3 High-speed through mode High-speed frequency/2 mode High-speed frequency/4 mode High-speed frequency/8 mode 0.2 0.1 0 0 2 4 6 8 10 12 14 16 18 20 Resistor R [k] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-12 APPENDIX 3.2 Typical characteristics 4524 Group (9) Low-speed mode (quartz-crystal oscillation): VDD-IDD Measurement condition: f(X IN) = stop, f(X CIN) = 32 kHz, f(RING) = stop, Ta = 25 C 50 45 40 Low-speed through mode I DD [A] 35 30 Low-speed frequency/2 mode 25 Low-speed frequency/4 mode Low-speed frequency/8 mode 20 15 10 5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] (10) Clock operating mode (POF instruction execution): V DD-I DD Measurement condition: f(X IN) = stop, f(X CIN) = 32 kHz, f(RING) = stop, Ta = 25 C 50 45 40 I DD [A] 35 30 25 20 15 10 5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-13 APPENDIX 3.2 Typical characteristics 4524 Group (11) RAM back-up mode (POF2 instruction execution): V DD-I DD Measurement condition: f(X IN) = stop, f(X CIN) = stop, f(RING) = stop, Ta = 25 C 100 90 80 70 60 I DD [nA] 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-14 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.2 Frequency characteristics (1) On-chip oscillator frequency characteristics: V DD-f(RING) 4 3.5 f(RING) [MHz] 3 Ta = -30 C 2.5 Ta = 25 C 2 Ta = 95 C 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] (2) On-chip oscillator frequency characteristics: Ta-f(RING) 3 2.5 f(RING) [MHz] 2 V DD = 5.0 V 1.5 1 V DD = 3.0 V 0.5 0 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Ta [C] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-15 APPENDIX 3.2 Typical characteristics 4524 Group (3) RC oscillation frequency characteristics: R-f(XIN) Measurement condition: V DD = 5.0 V, C = 33pF, Ta = 25 C 7 6 5 f(XIN) [MHz] 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Resistor R [k] (4) RC oscillation frequency characteristics (Ta-f(X IN)) Measurement condition: V DD = 5.0 V, C = 33pF 7 6 R = 3.3 k f(X IN)[MHz] 5 R = 4.7 k 4 R = 6.8 k 3 R = 9.1 k 2 R = 15 k R = 20 k 1 0 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Ta [C] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-16 APPENDIX 3.2 Typical characteristics 4524 Group (5) RC oscillation frequency characteristics: R-f(X IN) Measurement condition: V DD = 3.0 V, C = 33pF, Ta = 25 C 7 6 5 f(XIN) [MHz] 4 3 2 1 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Resistor R [k] (6) RC oscillation frequency characteristics (Ta-f(X IN)) Measurement condition: V DD = 3.0 V, C = 33pF 7 6 R = 3.3 k f(X IN)[MHz] 5 4 R = 4.7 k 3 R = 6.8 k R = 9.1 k 2 R = 15 k R = 20 k 1 0 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Ta [C] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-17 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.3 Port typical characteristics (V DD = 5.0 V) (1) Ports P0, P1, P4, D0-D 6: V OH-I OH Measurement condition: VDD = 5.0 V -100 -90 -80 -70 I OH [mA] -60 -50 Ta = -30 C Ta = 25 C Ta = 95 C -40 -30 -20 -10 0 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 VOH [V] (2) Ports D 7, C: V OH-I OH Measurement condition: VDD = 5.0 V -100 Ta = -30 C -90 Ta = 25 C -80 Ta = 95 C I OH [mA] -70 -60 -50 -40 -30 -20 -10 0 5 4.5 4 3.5 3 2.5 2 1.5 1 0.5 0 VOH [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-18 APPENDIX 3.2 Typical characteristics 4524 Group (3) Ports P0, P1, P4: V OL-I OL Measurement condition: V DD = 5.0 V Ta = -30 C 100 90 Ta = 25 C 80 Ta = 95 C I OL [mA] 70 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL [V] (4) Ports D 0-D 9, C: V OL-I OL Measurement condition: V DD = 5.0 V Ta = -30 C 100 90 Ta = 25 C 80 Ta = 95 C 70 I OL [mA] 60 50 40 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-19 APPENDIX 3.2 Typical characteristics 4524 Group (5) Ports P2, P3, RESET: VOL-I OL Measurement condition: VDD = 5.0 V 100 90 80 70 60 Ta = -30 C I OL [mA] 50 Ta = 25 C 40 Ta = 95 C 30 20 10 0 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VOL [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-20 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.4 Port typical characteristics (V DD = 3.0 V) (1) Ports P0, P1, P4, D 0-D 6: V OH-I OH Measurement condition: V DD = 3.0 V -50 -45 -40 -35 I OH [mA] -30 -25 -20 Ta = -30 C Ta = 25 C Ta = 95 C -15 -10 -5 0 3 2.5 2 1.5 1 0.5 0 VOH [V] (2) Ports D 7, C: V OH-I OH Measurement condition: V DD = 3.0 V -50 -45 -40 Ta = -30 C -35 I OH [mA] Ta = 25 C Ta = 95 C -30 -25 -20 -15 -10 -5 0 3 2.5 2 1.5 1 0.5 0 VOH [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-21 APPENDIX 3.2 Typical characteristics 4524 Group (3) Ports P0, P1, P4: VOL-IOL Measurement condition: VDD = 3.0 V 50 45 Ta = -30 C 40 Ta = 25 C 35 Ta = 95 C 30 I OL [mA] 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOL [V] (4) Ports D0 -D 9, C: V OL-I OL Measurement condition: VDD = 3.0 V 50 45 Ta = -30 C 40 Ta = 25 C I OL [mA] 35 Ta = 95 C 30 25 20 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOL [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-22 APPENDIX 3.2 Typical characteristics 4524 Group (5) Ports P2, P3, RESET: V OL-I OL Measurement condition: V DD = 3.0 V 50 45 40 35 30 I OL [mA] 25 Ta = -30 C Ta = 25 C 20 Ta = 95 C 15 10 5 0 0 0.5 1 1.5 2 2.5 3 VOL [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-23 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.5 Input threshold characteristics (1) Ports P0-P4, D 0-D 7 , VDCE: VDD-VIH, V DD-VIL Measurement condition: Ta = 25 C 5 4.5 4 3.5 VIH/V IL [V] 3 VIH VIL 2.5 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] (2) XIN: VDD-V IH, V DD-VIL Measurement condition: Ta = 25 C 5 4.5 4 3.5 VIH/V IL [V] 3 VIH VIL 2.5 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-24 APPENDIX 3.2 Typical characteristics 4524 Group (3) X CIN: VDD-V IH, V DD-VIL Measurement condition: Ta = 25 C 5 4.5 4 3.5 VIH/V IL [V] 3 VIH VIL 2.5 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD [V] (4) RESET: V DD-VIH, V DD-VIL Measurement condition: Ta = 25 C 5 4.5 4 VIH VIH/V IL [V] 3.5 3 VIL 2.5 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-25 APPENDIX 3.2 Typical characteristics 4524 Group (5) SCK , S IN, CNTR0, CNTR1, INT0, INT1: VDD-V IH, V DD-V IL Measurement condition: Ta = 25 C 5 4.5 4 3.5 VIH/V IL [V] 3 VIH VIL 2.5 2 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-26 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.6 Pull-up resistor: V DD-RPU characteristics example (1) Ports P0, P1, RESET: V DD-RPU Measurement condition: V I = 0 V 300 275 250 225 R PU (k) 200 175 150 125 100 75 Ta = 95 C 50 Ta = 25 C Ta = -30 C 25 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD (V) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-27 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.7 Internal resistor for LCD power: Ta-R VLC (1) V DD = 5.0 V: Ta-R VLC 600 550 2r 3 500 450 R VLC (k) 400 350 300 r 3 250 200 150 100 50 0 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Ta [C] (2) VDD = 3.0 V: Ta-R VLC 600 550 2r 3 500 450 400 R VLC (k) 350 300 r 3 250 200 150 100 50 0 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Ta [C] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-28 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.8 A/D converter typical characteristics 15 1LSB WIDTH +1LSB 0 ERROR 0 1LSB WIDTH [mV] ERROR [mV] -1LSB -15 0 1 1022 1023 Fig. 3.2.1 A/D conversion characteristics data Figure 3.2.1 shows the A/D accuracy measurement data. (1) Non-linearity error ......................... This means a deviation from the ideal characteristics between V0 to V1022 of actual A/D conversion characteristics. In Figure 3.2.1, it is (-)/1LSB. (2) Differential non-linearity error ..... This means a deviation from the ideal characteristics between the input voltages V 0 to V 1022 necessary to change the output data to "1." In Figure 3.2.1, this is /1LSB. (3) Zero transition error ..................... This means a deviation from the ideal characteristics between the input voltages 0 to VDD when the output data changes from "0" to "1." In Figure 3.2.1, this is the value of . (4) Full-scale transition error ............. This means a deviation from the ideal characteristics between the input voltages 0 to V DD when the output data changes from "1022" to "1023." In Figure 3.2.1, this is the value of . (5) Absolute accuracy ........................ This means a deviation from the ideal characteristics between 0 to VDD of actual A/D conversion characteristics. In Figure 3.2.1, this is the value of ERROR in each of , , and . For the A/D converter characteristics, refer to the section 3.1 Electrical characteristics. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-29 APPENDIX 3.2 Typical characteristics 4524 Group (1) V DD = 5.12 V Measurement condition: f(X IN) = 4 MHz (high-speed through mode), Ta = 25 C ERROR/1LSB WIDTH [mV] 15 Error 10 5 1LSB Width 0 -5 -10 -15 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 416 432 448 464 480 496 512 672 688 704 720 736 752 768 928 944 960 976 992 1008 1024 STEP No. ERROR/1LSB WIDTH [mV] 15 10 Error 5 1LSB Width 0 -5 -10 -15 256 272 288 304 320 336 352 368 384 400 STEP No. ERROR/1LSB WIDTH [mV] 15 10 Error 5 0 1LSB Width -5 -10 -15 512 528 544 560 576 592 608 624 640 656 STEP No. ERROR/1LSB WIDTH [mV] 15 10 Error 5 1LSB Width 0 -5 -10 -15 768 784 800 816 832 848 864 880 896 912 STEP No. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-30 APPENDIX 3.2 Typical characteristics 4524 Group (2) VDD = 3.072 V Measurement condition: f(X IN) = 2 MHz (high-speed through mode), Ta = 25 C ERROR/1LSB WIDTH [mV] 9 6 Error 3 0 1LSB Width -3 -6 -9 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 416 432 448 464 480 496 512 672 688 704 720 736 752 768 928 944 960 976 992 1008 1024 ERROR/1LSB WIDTH [mV] STEP No. 9 6 Error 3 0 1LSB Width -3 -6 -9 256 272 288 304 320 336 352 368 384 400 ERROR/1LSB WIDTH [mV] STEP No. 9 6 Error 3 0 1LSB Width -3 -6 -9 512 528 544 560 576 592 608 624 640 656 ERROR/1LSB WIDTH [mV] STEP No. 9 6 Error 3 0 1LSB Width -3 -6 -9 768 784 800 816 832 848 864 880 896 912 STEP No. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-31 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.9 Analog input current characteristics example (1) f(X IN) = 6 MHz, V DD = 5.0 V: V AIN-I AIN Measurement condition: High-speed through mode, Ta = 25 C 250 200 150 100 I AIN (nA) 50 0 -50 -100 -150 -200 -250 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 V AIN (V) (2) f(X IN ) = 4 MHz, V DD = 5.0 V: V AIN-IAIN Measurement condition: High-speed through mode, Ta = 25 C 150 120 90 60 I AIN (nA) 30 0 -30 -60 -90 -120 -150 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VAIN (V) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-32 APPENDIX 3.2 Typical characteristics 4524 Group (3) f(X IN ) = 2 MHz, V DD = 5.0 V: V AIN-IAIN Measurement condition: High-speed through mode, Ta = 25 C 100 80 60 40 I AIN (nA) 20 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VAIN (V) (4) f(X IN) = 1 MHz, V DD = 5.0 V: V AIN-I AIN Measurement condition: High-speed through mode, Ta = 25 C 50 40 30 20 I AIN (nA) 10 0 -10 -20 -30 -40 -50 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 VAIN (V) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-33 APPENDIX 3.2 Typical characteristics 4524 Group (5) f(X IN ) = 6 MHz, V DD = 3.0 V: V AIN-IAIN Measurement condition: High-speed through mode, Ta = 25 C 250 200 150 100 I AIN (nA) 50 0 -50 -100 -150 -200 -250 0 0.5 1 1.5 2 2.5 3 VAIN (V) (6) f(X IN) = 4 MHz, V DD = 3.0 V: V AIN-I AIN Measurement condition: High-speed through mode, Ta = 25 C 150 120 90 60 I AIN (nA) 30 0 -30 -60 -90 -120 -150 0 0.5 1 1.5 2 2.5 3 V AIN (V) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-34 APPENDIX 3.2 Typical characteristics 4524 Group (7) f(X IN ) = 2 MHz, V DD = 3.0 V: V AIN-IAIN Measurement condition: High-speed through mode, Ta = 25 C 100 80 60 40 I AIN (nA) 20 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 V AIN (V) (8) f(X IN) = 1 MHz, V DD = 3.0 V: V AIN-I AIN Measurement condition: High-speed through mode, Ta = 25 C 50 40 30 20 I AIN (nA) 10 0 -10 -20 -30 -40 -50 0 0.5 1 1.5 2 2.5 3 V AIN (V) Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-35 APPENDIX 3.2 Typical characteristics 4524 Group 3.2.10 A/D converter operation current (V DD-IA DD) characteristics Measurement condition: Ta = 25 C 200 180 160 IA DD [A] 140 120 100 80 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.5 VDD [V] 3.2.11 Voltage drop detection circuit characteristics (1) Detection voltage (Mask ROM version): Ta-VRST 5 4.5 V RST [V] 4 3.5 3 2.5 2 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Ta [C] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-36 APPENDIX 3.2 Typical characteristics 4524 Group (2) Detection voltage (One Time PROM version): Ta-V RST 5 4.5 V RST [V] 4 3.5 3 2.5 2 -20 -15 -10 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 Ta [C] (3) Operation current: V DD-I RST Measurement condition: Ta = 25 C 100 90 80 I RST [A] 70 60 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 V DD [V] Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-37 APPENDIX 4524 Group 3.3 List of precautions 3.3 List of precautions 3.3.1 Program counter Make sure that the PC H does not specify after the last page of the built-in ROM. 3.3.2 Stack registers (SKS ) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. 3.3.3 Notes on I/O port (1) Note when ports P0, P1, P4 and D0-D 7 are used as an input port In the following conditions, the pin state of port P0, P1, P4 or D0-D7 is transferred as input data to register A when the corresponding input instruction is executed. * Set bit i (i=0, 1, 2 or 3) of register FR0, FR1, FR2 or FR3 to "0" according to the port to be used. * Set the output latch of the specified port to "1" with the corresponding output instruction. If bit i of FR0, FR1, FR2 or FR3 is "0" and the output latch is set to "0," "0" is output to specified port. If bit i of FR0, FR1, FR2 or FR3 is "1", the output latch value is output to specified port. (2) Note when ports P2 and P3 are used as an input port In the following condition, the pin state of port P2 or P3 is transferred as input data to register A when the IAP2 or IAP3 instruction is executed. * Set the output latch of specified port P2i or P3i (i=0, 1, 2 or 3) to "1" with the OP2A or OP3A instruction. If the output latch is "0", "0" is output to specified port P2 or P3. (3) Noise and latch-up prevention Connect an approximate 0.1 F bypass capacitor directly to the VSS line and the V DD line with the thickest possible wire at the shortest distance, and equalize its wiring in width and length. The CNVSS pin is also used as the V PP pin (programming voltage = 12.5 V) at the One Time PROM version. Connect the CNVSS/VPP pin to V SS through an approximate 5 k resistor which is connected to the CNV SS/V PP pin at the shortest distance. (4) Multifunction * Be careful that the output of ports D8 and D9 can be used even when INT0 and INT1 pins are selected. * Be careful that the input of ports D4-D6 can be used even when SIN, SOUT and SCK pins are selected. * Be careful that the input/output of port D7 can be used even when input of CNTR0 pin is selected. * Be careful that the input of port D 7 can be used even when output of CNTR0 pin is selected. * Be careful that the "H" output of port C can be used even when output of CNTR1 pin is selected. (5) Connection of unused pins Table 3.3.1 shows the connections of unused pins. (6) SD, RD, SZD instructions When the SD and RD instructions are used, do not set "1010 2" or more to register Y. When the SZD instructions is used, do not set "1000 2" or more to register Y. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-38 APPENDIX 4524 Group 3.3 List of precautions (7) Port D 8/INT0 pin When the power down mode is used by clearing the bit 3 of register I1 to "0" and setting the input of INT0 pin to be disabled, be careful about the following note. * When the input of INT0 pin is disabled (register I1 3 = "0"), clear bit 0 of register K2 to "0" to invalidate the key-on wakeup before system goes into the power down mode. (8) Port D 9/INT1 pin When the power down mode is used by clearing the bit 3 of register I2 to "0" and setting the input of INT1 pin to be disabled, be careful about the following note. * When the input of INT1 pin is disabled (register I2 3 = "0"), clear bit 2 of register K2 to "0" to invalidate the key-on wakeup before system goes into the power down mode. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-39 APPENDIX 4524 Group 3.3 List of precautions Table 3.3.1 Connections of unused pins Connection Pin Usage condition Connect to V SS. Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) XIN Sub-clock input is selected for system clock (MR 0=1). (Note 2) Open. XOUT Internal oscillator is selected (CMCK and CRCK instructions are not executed.) (Note 1) RC oscillator is selected (CRCK instruction is executed) External clock input is selected for main clock (CMCK instruction is executed). (Note 3) Sub-clock input is selected for system clock (MR 0=1). (Note 2) Connect to V SS. Sub-clock is not used. XCIN Open. XCOUT Sub-clock is not used. Open. D0-D3 Connect to V SS. N-channel open-drain is selected for the output structure. (Note 4) Open. D4/S IN S IN pin is not selected. Connect to V SS. N-channel open-drain is selected for the output structure. Open. D5/S OUT Connect to V SS. N-channel open-drain is selected for the output structure. Open. D6/S CK S CK pin is not selected. Connect to V SS. N-channel open-drain is selected for the output structure. Open. D7/CNTR0 CNTR0 input is not selected for timer 1 count source. Connect to V SS. N-channel open-drain is selected for the output structure. Open. D8/INT0 "0" is set to output latch. Connect to V SS. Open. D9/INT1 "0" is set to output latch. Connect to V SS. Open. C/CNTR1 CNTR1 input is not selected for timer 3 count source. Open. P00-P03 The key-on wakeup function is not selected. (Note 4) Connect to Vss. N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) Open. P10-P13 The key-on wakeup function is not selected. (Note 4) Connect to Vss. N-channel open-drain is selected for the output structure. (Note 5) The pull-up function is not selected. (Note 4) The key-on wakeup function is not selected. (Note 4) Open. P20/A IN0- Connect to Vss. P23/AIN3 Open. P30/A IN4- Connect to Vss. P33/AIN7 Open. P40-P43 Connect to Vss. N-channel open-drain is selected for the output structure. (Note 4) COM0-COM3 Open. Open. VLC3/SEG0 SEG0 pin is selected. Open. VLC2/SEG1 SEG1 pin is selected. Open. VLC1/SEG2 SEG2 pin is selected. SEG3-SEG 19 Open. Notes 1: When the CMCK and CRCK instructions are not executed, the internal oscillation (on-chip oscillator) is selected for main clock. 2: When sub-clock (XCIN) input is selected (MR0 = 1) for the system clock by setting "1" to bit 1 (MR1) of clock control register MR, main clock is stopped. 3: Select the ceramic resonance by executing the CMCK instruction to use the external clock input for the main clock. 4: Be sure to select the output structure of ports D0-D3 and P40-P43 and the pull-up function and keyon wakeup function of P0 0-P0 3 and P1 0-P13 with every one port. Set the corresponding bits of registers for each port. 5: Be sure to select the output structure of ports P0 0-P03 and P10-P1 3 with every two ports. If only one of the two pins is used, leave another one open. (Note when connecting unused pins to V SS or V DD) Connect the unused pins to V SS or V DD using the thickest wire at the shortest distance against noise. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-40 APPENDIX 4524 Group 3.3 List of precautions 3.3.4 Notes on interrupt (1) Setting of INT0 interrupt valid waveform Set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction. Depending on the input state of D 8/INT0 pin, the external interrupt request flag (EXF0) may be set to "1" when the bit 2 of register I1 is changed. (2) Setting of INT0 pin input control Set a value to the bit 3 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction. Depending on the input state of D 8/INT0 pin, the external interrupt request flag (EXF0) may be set to "1" when the bit 3 of register I1 is changed. (3) Setting of INT1 interrupt valid waveform Set a value to the bit 2 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction. Depending on the input state of D 9/INT1 pin, the external interrupt request flag (EXF1) may be set to "1" when the bit 2 of register I2 is changed. (4) Setting of INT1 pin input control Set a value to the bit 3 of register I2, and execute the SNZ1 instruction to clear the EXF1 flag to "0" after executing at least one instruction. Depending on the input state of D 9/INT1 pin, the external interrupt request flag (EXF1) may be set to "1" when the bit 3 of register I2 is changed. (5) Multiple interrupts Multiple interrupts cannot be used in the 4524 Group. (6) Notes on interrupt processing When the interrupt occurs, at the same time, the interrupt enable flag INTE is cleared to "0" (interrupt disable state). In order to enable the interrupt at the same time when system returns from the interrupt, write EI and RTI instructions continuously. (7) D 8/INT0 pin When the external interrupt input pin INT0 is used, set the bit 3 of register I1 to "1". Even in this case, port D 8 output function is valid. Also, the EXF0 flag is set to "1" when bit 3 of register I1 is set to "1" by input of a valid waveform (valid waveform causing external 0 interrupt) even if it is used as an output port D 8. (8) D 9/INT1 pin When the external interrupt input pin INT1 is used, set the bit 3 of register I2 to "1". Even in this case, port D 9 output function is valid. Also, the EXF1 flag is set to "1" when bit 3 of register I2 is set to "1" by input of a valid waveform (valid waveform causing external 1 interrupt) even if it is used as an output port D 9. (9) POF instruction, POF2 instruction When the POF or POF2 instruction is executed continuously after the EPOF instruction, system enters the power down state. Note that system cannot enter the power down state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF or POF2 instruction continuously. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-41 APPENDIX 4524 Group 3.3 List of precautions 3.3.5 Notes on timer (1) Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. (2) Count source Stop timer 1, 2, 3, 4 or LC counting to change its count source. (3) Reading the count values Stop timer 1, 2, 3 or 4 counting and then execute the TAB1, TAB2, TAB3 or TAB4 instruction to read its data. (4) Writing to the timer Stop timer 1, 2, 3, 4 or LC counting and then execute the T1AB, T2AB, T3AB, T4AB or TLCA instruction to write its data. (5) Writing to reload register R1, reload register R3 and reload register R4H When writing data to reload register R1 while timer 1 is operating respectively, avoid a timing when timer 1 underflows. When writing data to reload register R3 while timer 3 is operating respectively, avoid a timing when timer 3 underflows. When writing data to reload register R4H while timer 4 is operating respectively, avoid a timing when timer 4 underflows. (6) Timer 4 * Avoid a timing when timer 4 underflows to stop timer 4. * When "H" interval extension function of the PWM signal is set to be "valid", set "0116" or more to reload register R4H. (7) Timer 5 Stop timer 5 counting to change its count source. (8) Timer input/output pin * Set the port C output latch to "0" to output the PWM signal from C/CNTR1 pin. (9) Watchdog timer * The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction, the WRST instruction continuously, and clear the WEF flag to "0". * The watchdog timer function is valid after system is returned from the power down state. When not using the watchdog timer function, stop the watchdog timer function and execute the DWDT instruction and the WRST instruction continuously every system is returned from the power down state. * When the watchdog timer function and power down function are used at the same time, initialize the flag WDF1 with the WRST instruction before system enters into the power down state. (10) Pulse width input to CNTR0 pin, CNTR1 pin Refer to section "3.1 Electrical characteristics" for rating value of pulse width input to CNTR0 pin, CNTR1 pin. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-42 APPENDIX 3.3 List of precautions 4524 Group 3.3.6 Notes on A/D conversion (1) Note when the A/D conversion starts again When the A/D conversion starts again with the ADST instruction during A/D conversion, the previous input data is invalidated and the A/D conversion starts again. (2) A/D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A/D accuracy may not be obtained. Therefore, reduce the impedance or, connect a capacitor (0.01 F to 1 F) to analog input pins. Figure 3.3.1 shows the analog input external circuit example-1. When the overvoltage applied to the A/D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 3.3.2. In addition, test the application products sufficiently. Sensor About 1k AIN Sensor AIN Apply the voltage withiin the specifications to an analog input pin. Fig. 3.3.2 Analog input external circuit example-2 Fig. 3.3.1 Analog input external circuit example-1 (3) Notes for the use of A/D conversion 2 Do not change the operating mode of the A/D converter by bit 3 of register Q1 during A/D conversion (A/D conversion mode and comparator mode). (4) Notes for the use of A/D conversion 3 When the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode with bit 3 of register Q1 in a program, be careful about the following notes. * Clear bit 2 of register V2 to "0" to change the operating mode of the A/D converter from the comparator mode to the A/D conversion mode (refer to Figure 3.3.3). * The A/D conversion completion flag (ADF) may be set when the operating mode of the A/D converter is changed from the comparator mode to the A/D conversion mode. Accordingly, set a value to bit 3 of register Q1, and execute the SNZAD instruction to clear the ADF flag to "0". * * * Clear bit 2 of register V2 to "0"....... Change of the operating mode of the A/D converter from the comparator mode to the A/D conversion mode Clear the ADF flag to "0" with the SNZAD instruction Execute the NOP instruction for the case when a skip is performed with the SNZAD instruction * * * Fig. 3.3.3 A/D converter operating mode program example Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-43 APPENDIX 3.3 List of precautions 4524 Group (5) A/D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains "0," not set to "1." In this case, the A/D interrupt does not occur even when the usage of the A/D interrupt is enabled. Accordingly, consider the time until the comparator operation is completed, and examine the state of ADF flag by software. The comparator operation is completed after 8 machine cycles. (6) Analog input pins When P20/AIN0-P23/AIN3, P3 0/AIN4-P33/AIN7 are set to pins for analog input, they cannot be used as I/O ports P2 and P3. (7) TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the highorder 2 bits of register A, and simultaneously, the low-order 2 bits of register A is "0." (8) Recommended operating conditions when using A/D converter The recommended operating conditions of supply voltage and system clock frequency when using A/ D converter are different from those when not using A/D converter. Table 3.3.2 shows the recommended operating conditions when using A/D converter. Table 3.3.2 Recommended operating conditions (when using A/D converter) Parameter Condition System clock frequency V DD = 4.0 to 5.5 V (through mode) (at ceramic resonance) V DD = 2.7 to 5.5 V (through mode) (Note 2) V DD = 2.7 to 5.5 V (Frequency/2 mode) V DD = 2.7 to 5.5 V (Frequency/4 mode) V DD = 2.7 to 5.5 V (Frequency/8 mode) Limits Unit Min. Typ. Max. 0.1 6.0 MHz 0.1 4.4 0.1 3.0 0.1 0.1 1.5 0.7 System clock frequency V DD = 2.7 to 5.5 V (through mode) 0.1 4.4 (at RC oscillation) V DD = 2.7 to 5.5 V (Frequency/2 mode) 0.1 (Note 2) V DD = 2.7 to 5.5 V (Frequency/4 mode) V DD = 2.7 to 5.5 V (Frequency/8 mode) 0.1 2.2 1.1 0.1 0.5 V DD = 4.0 to 5.5 V (through mode) 4.8 V DD = 2.7 to 5.5 V (through mode) 0.1 0.1 V DD = 2.7 to 5.5 V (Frequency/2 mode) 0.1 2.4 V DD = 2.7 to 5.5 V (Frequency/4 mode) 0.1 1.2 0.6 System clock frequency (ceramic resonance selected, at external clock input) MHz MHz 3.2 0.1 V DD = 2.7 to 5.5 V (Frequency/8 mode) Note: The frequency at RC oscillation is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits. 3.3.7 Notes on serial I/O (1) Note when an external clock is used as a synchronous clock: * An external clock is selected as the synchronous clock, the clock is not controlled internally. * Serial transmit/receive is continued as long as an external clock is input. If an external clock is input 9 times or more and serial transmit/receive is continued, the receive data is transferred directly as transmit data, so that be sure to control the clock externally. Note also that the SIOF flag is set to "1" when a clock is counted 8 times. * Be sure to set the initial input level on the external clock pin to "H" level. * Refer to section "3.1 Electrical characteristics" when using serial I/O with an external clock. Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-44 APPENDIX 3.3 List of precautions 4524 Group 3.3.8 Notes on LCD function (1) Timer LC count source Stop timer LC counting to change timer LC count source. (2) Writing to timer LC Stop timer LC counting and then execute the data write instruction (TLCA). (3) VLC3/SEG0 pin When the V LC3 pin function is selected, apply voltage of V LC3 < V DD to the pin externally. (4) V LC2/SEG1 pin, VLC1/SEG 2 pin * When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used; Apply voltage of 0 * Connect a resistor of 100 or more to an I/O port in series. * As for an input port, read data several times by a program for checking whether input levels are equal or not. * As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its output latch at fixed periods. * Rewrite data to pull-up control registers at fixed periods. 3.4.6 Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing. An example of VSS patterns on the underside of a printed circuit board AAAAAAA AAA AAAAAA AAA Oscillator wiring pattern example XIN XOUT VSS Separate the VSS line for oscillation from other VSS lines Fig. 3.4.10 V SS pattern on the underside of an oscillator Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-52 APPENDIX 3.4 Notes on noise 4524 Group * Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. * Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. * Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. * Decrements the SWDT contents by 1 at each interrupt processing. * Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). * Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less. N Main routine Interrupt processing routine (SWDT) N (SWDT) (SWDT)--1 EI Interrupt processing Main processing (SWDT) 0? (SWDT) =N? N Interrupt processing routine errors 0 >0 RTI Return Main routine errors Fig. 3.4.11 Watchdog timer by software Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z 3-53 APPENDIX 3.5 Package outline 4524 Group 3.5 Package outline 64P6N-A Plastic 64pin 1414mm body QFP EIAJ Package Code QFP64-P-1414-0.80 Weight(g) 1.11 Lead Material Alloy 42 MD e JEDEC Code - HD 64 b2 ME D 49 1 I2 48 Recommended Mount Pad HE E Symbol 33 16 A 32 L1 c A2 17 b y Rev.2.00 Aug, 06 2004 REJ09B0107-0200Z x M A1 F e L Detail F A A1 A2 b c D E e HD HE L L1 x y b2 I2 MD ME Dimension in Millimeters Min Nom Max - - 3.05 0.1 0.2 0 - - 2.8 0.3 0.35 0.45 0.13 0.15 0.2 13.8 14.0 14.2 13.8 14.0 14.2 0.8 - - 16.5 16.8 17.1 16.5 16.8 17.1 0.4 0.6 0.8 1.4 - - - - 0.2 0.1 - - 0 10 - 0.5 - - - - 1.3 14.6 - - - - 14.6 3-54 RENESAS 4-BIT CISC SINGLE-CHIP MICROCOMPUTER USER'S MANUAL 4524 Group Publication Data : Rev.1.00 Dec 19, 2003 Rev.2.00 Aug 06, 2004 Published by : Sales Strategic Planning Div. Renesas Technology Corp. (c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. 4524 Group User's Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0107-0200Z