(M) MOTOROLA MC14541B PROGRAMMABLE TIMER control logic. > Timing is initialized by. turning on power, whereupon the power. with the nth stage frequency being fog/2". e Available Outputs 28, 210 21 3 or 216 @ ncrements on Positive Edge Clock Transitions _ @ Built-in Low Power RC Oscillator (+ 2% accuracy over temperature range and + 20% sup: ply and + 3% over processing at < 10 kHz) @ Oscillator May Be Bypassed if External Clock Is Available (Ap- ply external clock to Pin 3) Reset Operation - e@ 2/S Select Provides Output Logic Lvel Flexibility @ Reset {auto or master) Disables Oscillator During Resetting to Provide No Active Power Dissipation Clock Rise and Fall Times @ Automatic Reset Initializes All Counters On Power Up @ Supply Voltage Range = 3.0 Vdc to 18 Vde with Aute Reset Disabled (Pin 5 = Vpp) 8.5 Vdc to 18 Vde with Auto = __ Reset Enabled (Pin 5 = Vgs) WT The MC145418 programmable timer consists of a 16-stage bihary counter, an integrated oscillator for use with an external capacitor and two resistors, an automatic power-on reset circuit, and | output on reset is enabled and initializes the counter, within the specified Vpp range, With the power already on, an external reset pulse can be applied. Upon retease of the initial reset command, the,oscillator will oscillate with a frequency determined by the external RC net- work. The 16-stage counter divides the oscillator frequency (fgsc} @ External Master Reset Totally Independent of Automatic @ Clock Conditioning Circuit Permits Operation with Very Slow . @ Operates as 2" Frequency Divider or Single Transition Timer ; L SUFFIX CERAMIC . CASE 620 P SUFFIX PLASTIC 6 CASE 648. D SUFFIX 6 SOIC CASE 7518 1 ORDERING INFORMATION MC14XXXBCP Plastic MC14XXXBCL Ceramic a MC14XXXBD = SOIC. a Ta = -55? to 125C for all packages. - MAXIMUM RATINGS (Voltages Referenced to Vgs) Symbol Parameter Value Unit Vpp__|DC Supply Voltage -05to + 18.0 v Vins Vout] Input or Output Voltage (DC or Transient) -0.5 to Vpp +0.5 Vv lin input Current (DC or Transient), per Pin +10 mA lout Output Cusrent (DC or Transient), per Pin +45 mA Pp Power Dissipation, per Packaget 500 mw Tstg [Storage Temperature -65 to +150 C Th Lead Temperature (8-Second Soldering) 260 C *Maximum Ratings are those values beyond which damage to the device may occur. +Temperature Derating: Plastic P and D/DW" Packages: - 7.0 mWPC From 65C To 125C Ceramic L" Packages: 12 mWPC From 100C Te 125C 6-377 ~ | PIN ASSIGNMENT _- 1 Rte Voo Fa vl 2C4Cte Bro. 3 Cars ak 4 CNC Nc fF 11 5 CAR Mode [ 10 6c mr a/G Sel P29 7 Co Vss afos NC = No Connection =MC14541B ELECTRICAL CHARACTERISTICS (Voltages Referenced to Vss) Characteristi Symbol | \DP ase ae favre Unit aracteristic ym Vde |" min | Max Min Typ # | Max | Min | Max Output Voltage O" Level 5.0 _ 0.05 -, 0 0.05 _ 0.05 Vin = Vpp or 0 . VOL 10 - 0.05 _ 0 0.05 _ 0.05 | Vde Be coreg 15 _ 0.05 _ 0 0.05 _ 0.05 4 Level 50 | 495 | -| 4.95 5.0 | 495 | Vin = 0 or Vpp . Vou 10 | 995 9.85 10 _ 9.95 | Vde 15 14.95 _ 14.95 15 _ 14,95 Input Voltage 0 Level (Vo = 4.5 or 0.5 Vde) Vv 5.0 _ 1.5 _ 2.25 15 _ 1.5 Vde (Vo = 9.0 or 1.0 Vdc) I 10 -|} 30 ~ 4.50 30 | 3.0 (Vo = 13.5 or 1.5 Vde) | 15 _ 4.0 8,75 4.0 _ 40 . "1" Level (Vo = 0.5 or 4.5 Vde) Vat 5.0 35 - 35 2.75 | 35 -1 Vde (Vo = 1.0 oF 9.0 Vdc) ~ iH} we | zo | -} 70 550 {| | 70 | | (Vo = 1.50r13.5 Vde) 15 11 _ 11 8.25 =] 1 _ Output Drive Current (VOH = 2.5 Vdc) Source IOH 5.0 -7,96 ad -6.42 | 12.83 _ - 4.49 mAdc (VOH = 9.5 Vdc) 10 -419 _ 3.38 ~6.75 _ - 2.37 _ (VOH = 13.5 Vde) 15 ~ 16.3 - -13.2 | -26.33 -| -9.24 _ (VOL = 0.4 Vdc} . Sink 5.0 1.93 - 1.56 3.12 _ 1.09 _ (VoL = 9.5 Vdc) a lo 10 4.96 - 4.0 8.0 - | 28 | mAdc (VOL = 1.5 Vde) _ 15 19.3 _ 15.6 31.2 10.9 _ Input Current lin 15 _ +01 - +0,00001| 40.1 _ +1.0 | pAdc Input Capacitance Cin _ _ _ ~ 5.0 7.5 _ _ pF (Vin = 9) ___. Quiescent Current eoGe ipp 5.0 _ 5.0 _ 0.005 5.0 _ 150 | wAde (Pin 5 is High) 10 _ 10 -_ 0.010 10 _ 300 Auto Reset Disabled 15 _- 20 _ 0,015 20 _ 600 Auto Reset Quiscent Current . _ IDoR 10 -| 250 _ 30 250 | 1500 | wAdc (Pin 5 is low) . 15 ~~ 500 _ 82 500 - 2000 Supply Current**t lb 5.0 Ip = (0.4 pAVKH2) f + IpD pAdc (Dynamic plus Quiescent) 10 Ip = (0.8 pA/KHz) f + Ipp 15 Ip = ( #Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC's potential performance. The formulas given are for the typical characteristics only at 25C, tWhen using the on chip oscillator the total supply current (in wAdc) becomes: it = Ip + 2 Cte Vpp f x 10 4 where Ip is in BA, Cig is in pF, Vpp in Volts DC, and f in kHz. (see Fig. 3) Dissipation during power-on with automatic reset enabled is typically 50 nA (@ Vop = 10 Vdc. , 6-378 1.2 A/KHZ) f + Ipp Vout) = Yop. This device contains protection circuitry to guard against damage due to high static voltages or electric flelds. However, precau- - tions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vip and Voy should be constrained to the range Vss * (Vin or Unused inputs must always be tied to an ap- propriate logic voltage level (e.g., either Vgg or Vpp). Unused outputs must be left open.SWITCHING CHARACTERISITCS* (Cy = 50 pF, Ta = 25C} MC14541B Characteristic Symbol Voo Min Typ # Max Unit Output Rise and Fall Time tTLH ns trLH: tTHE = (1.5 ns/pF) CL + 25 ns t ' 5.0 - 100 200 trey: THE = (0.75 ns/pF) CL + 12.5 ns THL 10 - 50 100 tTLH: tTHL = (0.55 ns/pF) CL + 9.5 ns 15 _ 40 80 Propagation Delay, Clock to 0 (28 Output} PLH . us 'PLH, tPHL = (1.7 ns/pF) Cy + 3415 ns tPHL 5.0 - 3.5 10.5 tly, tPHL = (0.66 ns/pF) Cy + 1217 ns 10 - 1.25 3.8 teyy. tpHeL = (0.5 ns/pF) C_ + 875 ns 15 - 0.9 29 Propagation Delay, Clock to Q (2'5 Output tPHL us PHL, tPLH = (1.7 ns/pF) C_ + 5915 ns tPLH 5.0 _ 6.0 18 tPHE, teLH = (0.66 ns/pF) Cy + 3467 ns 10 = 35 10 tPHL, tPLH = {0.5 ns/pF) Cy + 2475 ns 45 - 25 75 Clock Pulse Width tWHIcH 5.0 500 305 =~ ns 10 300 100 - 15 225 85 - Clock Pulse Frequency (50% Duty Cycte) fol 5.0 - 15 0.75 MHz 10 _ 40 2.0 18 ~ 6.0 3.0 MR Pulse Width tWHIR) 5.0 900 300 _ ns 10 300 100 - 15 225 85 - Master Reset Removal Time trem 5.0 420 210 _ ns 10 200 100 _ 15 200 100 _ *The formulas given are for the typical characteristics only at 25C, Data labelled Typ Is not to be used for design purposes but is intended as an indication of the IC's potential parformance. FIGURE 1 POWER DISSIPATION TEST CIRCUIT FIGURE 2 -- SWITCHING TIME TEST CIRCUIT AND WAVEFORM AND WAVE FORMS Vpo Yop 4 a p i Pul , : ulse alse R Generator Rs , Generator $s ej AR AR 4 0/8 Select O/6 Select @-4| Mode a ae Mode a r to A CL 4 A CL 8 T 158 T mr = MR = = - 22 TOO SS Epo = Vss (Ree and Cre outputs are jeft open) PHL 50% { Duty Cycle i 'THL 6-379Auto Resst MC14541B EXPANDED BLOCK DIAGRAM Al12 873 Ac 1 210 213 216 Cte 2 8-Stage Counter Reset Ag 3 5 6 10 98 Master Reset Mode are Selact Vop = Pin 14 Vgs = Pin 7 FREQUENCY SELECTION TABLE TRUTH TABLE Number of State . -- Counter Stages | Count . Pin o 1 A 8 = 2 Auto Reset, 5 | Auto Reset Oper. | Auto Reset 9 o 13 8192 ating Disabled Q 1 10 1024 Master Reset, 6 | Timer Operational | Master Reset On 1 9 8 256 ard, $ Output Initially Output Initially High 1 1 16 65536 Low After Reset After Reset Mode, 10 [Single Cycle Moda | Recycle Mode FIGURE 3 OSCILLATOR CIRCU!T USING RC CONFIGURATION To Clock _ Cirevit internal Rs Rte 6-380MC14541B FYPICAL RC OSCILLATOR CHARACTERISTICS FIGURE 4 RC OSCILLATOR STABILITY 8.0 E40 z z = = B = 0 a S 3 3 a 3-40 a g E 3 5 8.0 # . & oO -12 a Rte = S6 kfm Rg = 0,f = 10.15 kHz @ Vop = 10V, Ta = C = 1000 pF t-- = 120k0,f = 78 kH2 @ = 10V,Ta = 25C 100 1257 ~25 0 =55 25 50 78 Ta, AMBIENT TEMPERATURE (C} - 01 FIGURE 5 RC OSCILLATOR FREQUENCY AS A FUNCTION OF Ry AND Cyc - 100 = 1 50 asa 20 of Rye 10 (C = 1000 pF} (Rg = 2Ryc} 5.0 asa of C (Rio = 56 kn) (Rg = 120 kQ) 20 1.0 05 0.2 0k 40 100 Rrc, RESISTANCE {OHMS} 9,001 go C, CAPACITANCE (j:F} 0.0001 0.1 OPERATING CHARACTERISTICS With Auto Reset pin set to a 0" the counter circuit is initialized by turning on power. Or with power already on, the counter circuit is reset when the Master Reset pin is set to a 1". Both types of reset will result in synchronously resetting all counter stages independent of counter state. Auto Reset pin when set to a 1 provides a low power operation. The RC oscillator as shown in Figure 3 will oscillate with a frequency determined by the external RC net- work i.e., f= if (1 kHz <f< 100 kH BIL, NT Re 7) and =Rg 2 Ree where Rg = 10 kQ The time select inputs (A and B) provide a two-bit address to output any one of four counter stages (28, 210, 213 and 215). The 2" counts as shown in the Frequency Setection Table represents the Q output of the Nth stage of the counter, When A is 1", 276 js selected for both states of B. However, when B is 0, normal counting is interrupted and the 9th counter stage receives its clock directly from the oscillator (i.e., effectively outputing 28). The Q/G select output control pin provides for a choice of output level. When the counter is in a reset condition and Q/G select pin is set to a 0 the Q output isa 0, correspondingly when Q/@ select pin is set to a 1 the Q output is a 1. When the mode control pin is set to a "1", the selected count is continually transmitted to the output. But, with mode pin 'O and after a reset condition the RS flip-flop {see Expanded Block Diagram) resets, counting commences, and after 2"! counts the RS flip-flop sets which causes the output to change state. Hence, after another 2%-' counts the output will not change. Thus, a Master Reset pulse must be applied or a change in the mode pin level is required to reset the single cycle operation, DIGITAL TIMER APPLICATION SL tnput Output J Le = tt+tur MR When Master Reset (MR) receives a positive puise, the internal counters and latch are reset. The Q output goes high and remains high until the selected (via A and B) number of clock pulses are counted, the Q output then. goes low and remains low until another input pulse is received. This one shot is fully retriggerable and as accurate as the input frequency. An externa! clock can be used (pin 3 is the clock input, pins 1 and 2 ere outputs) if additional accuracy is needed. Notice that a setup time equal to the desired pulse width output is required immediately following initial power up, during which time Q output will be high. 6-381