FPGA Configuration Memory - Data Sheets - Atmel Corporation

Features

•Serial EEPROM Family for Configuring FLEX® Devices

•Simple Interface to SRAM FPGAs

•EE Programmable 2-Mbit Serial Memories Designed to Store Configuration Programs

for Field Programmable Gate Arrays (FPGAs)

•Cascadable Read Back to Support Additional Configurations or Future Higher-density

Arrays

•Low-power CMOS EEPROM Process

•Programmable Reset Polarity

•Available in the Space-efficient Surface-mount PLCC Package

•In-System Programmable via 2-wire Bus

•Emulation of Atmel’s AT24CXXX Serial EEPROMs

•Available in 3.3V ± 5% LV and 5V ± 5% C Versions

•System-friendly READY Pin

•Replacement for AT17C/LV002A

Description

The AT17C002A and AT17LV002A (high-density AT17A Series) FPGA Configuration

EEPROMs (configurators) provide an easy-to-use, cost-effective configuration mem-

ory for programming Altera FLEX devices. The AT17A Series is packaged in the

popular 20-lead PLCC and the 32-lead TQFP. The AT17A Series family uses a simple

serial-access procedure to configure one or more FPGA devices. The AT17A Series

organization supplies enough memory to configure one or multiple smaller FPGAs.

Using a feature of the AT17A Series, the user can select the polarity of the reset func-

tion by programming internal EEPROM bytes. The AT17A parts generate their own

internal clock and can be used as a system “master” for loading the FPGA devices.

The Atmel devices also support a system-friendly READY pin. The READY pin is used

to simplify system power-up considerations.

The AT17A Series Configurators can be programmed with industry-standard program-

mers or Atmel’s ATDH2200E Programming Kit.

FPGA

Configuration

EEPROM

Memory

2-megabit

Altera Pinout

AT17C002A

AT17LV002A

Rev. 2280B–08/01

2AT17C/LV002A

2280B–08/01

Block Diagram

EEPROM

CELL

MATRIX

ROW

DECODER

COLUMN

DECODER

nCSDCLK READY OE nCASC (A2) DATA

BIT

COUNTER

OSC

CONTROL

PROGRAMMING

DATA SHIFT

PROGRAMMING

MODE LOGIC

ROW

ADDRESS

COUNTER

POWER-ON

RESET

SER_EN

WP1

32-lead TQFP

DCLK

WP1

SER_EN

READY

nCS

GND

(A2) nCASC

DATA

VCC

Pin Configuration

20-lead PLCC

DCLK

WP1

SER_EN

READY

nCS

GND

(A2) nCASC

DATA

VCC

AT17C/LV002A

2280B–08/01

Device

Configuration

The control signals for the configuration EEPROM (nCS, OE and DCLK) interface directly with

the FPGA device control signals. All FPGA devices can control the entire configuration pro-

cess and retrieve data from the configuration EEPROM without requiring an external intelligent

controller.

The configuration EEPROM’s OE and nCS pins control the tri-state buffer on the DATA output

pin and enable the address counter and the oscillator. When OE is driven Low, the configura-

tion EEPROM resets its address counter and tri-states its DATA pin. The nCS pin also

controls the output of the AT17A Series Configurator. If nCS is held High after the OE reset

pulse, the counter is disabled and the DATA output pin is tri-stated. When nCS is driven Low,

the counter and the DATA output pin are enabled. When OE is driven Low again, the address

counter is reset and the DATA output pin is tri-stated, regardless of the state of the nCS.

When the Configurator has driven out all of its data and nCASC is driven Low, the device tri-

states the DATA pin to avoid contention with other Configurators. Upon power-up, the address

counter is automatically reset.

The READY pin is available as an open-collector indicator of the device’s reset status; it is

driven Low while the device is in its power-on reset cycle and released (tri-stated) when the

cycle is complete.

This document discusses the EPF10K device interface. For more details or information on

other Altera applications, please reference the “AT17A Series Conversions from Altera FPGA

Serial Configuration Memories” application note.

FPGA Device

Configuration

FPGA devices can be configured with an AT17A Series EEPROM (see Figure 1). The AT17A

Series device stores configuration data in its EEPROM array and clocks the data out serially

with its internal oscillator. The OE, nCS and DCLK pins supply the control signals for the

address counter and the output tri-state buffer. The AT17A Series device sends a serial bit-

stream of configuration data to its DATA pin, which is connected to the DATA0 input pin on the

FPGA device.

When the configuration data for an FPGA device exceeds the capacity of a single AT17A

Series device, multiple AT17A Series devices can be serially linked together (see Figure 2).

When multiple AT17A Series devices are required, the nCASC and nCS pins provide hand-

shaking between the cascaded EEPROMs.

The position of an AT17A Series device in a chain determines its operation. The first AT17A

Series device in a configurator chain is powered up or reset with nCS Low and is configured

for the FPGA device’s protocol. This AT17A Series device supplies all clock pulses to one or

more FPGA devices and to any downstream AT17A Series Configurator during configuration.

The first AT17A Series Configurator also provides the first stream of data to the FPGA devices

during multi-device configuration. Once the first AT17A Series device finishes sending config-

uration data, it drives its nCASC pin Low, which drives the nCS pin of the second AT17A

Series device Low. This activates the second AT17A Series device to send configuration data

to the FPGA device.

4AT17C/LV002A

2280B–08/01

Figure 1. Configuration with a Single AT17A Series Configurator(1)(2)(3)

Notes: 1. Use of the READY pin is optional.

2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before

configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)

3. Reset polarity of EEPROM must be set active Low (OE active High).

Figure 2. Configuration with Multiple AT17A Series Configurators(1)(2)(3)

Notes: 1. Use of the READY pin is optional.

2. Introducing an RC delay to the input of nCONFIG is recommended to ensure that VCC (5V/3.3V) is reached before

configuration begins. (nCONFIG can instead be connected to an active Low system reset signal.)

3. Reset polarity of EEPROM must be set active Low (OE active High).

MSEL1

nSTATUS

MSEL0

CONF_DONE

DATA0

DCLK

nCONFIG

EPF6K/EPF10K

AT17C512A/010A/020A/002A

AT17LV512A/010A/020A/002A

GND

nCS

DATA

DCLK

nCE

READY

VCC

SER_EN

VCC

0.1

1 k

MSEL1

nSTATUSMSEL0

CONF_DONE

DATA0

DCLK

nCONFIG

EPF10K

AT17C512A/010A/020A/002A

AT17LV512A/010A/020A/002A

DEVICE 1

GND

nCS nCASC

DATA

DCLK

AT17C512A/010A/020A/002A

AT17LV512A/010A/020A/002A

DEVICE 2

nCS

DATA

DCLK

READY

VCC

1 k

nCE

SER_EN

VCC

0.1

AT17C/LV002A

2280B–08/01

The READY pin is available as an open-collector indicator of the device’s reset status; it is

driven Low while the device is in its power-on reset cycle and released (tri-stated) when the

cycle is complete. It can be used to hold the FPGA device in reset while it is completing its

power-on reset but it cannot be used to effectively delay configuration (i.e., the output is

released well before the system VCC has stabilized).

The first AT17A Series device clocks all subsequent AT17A Series devices until configuration

is complete. Once all configuration data is transferred and nCS on the first AT17A Series

device is driven High by CONF_DONE on the FPGA devices, the first AT17A Series device

clocks 16 additional cycles to initialize the FPGA device before going into zero-power (idle)

state. If nCS on the first AT17A Series device is driven High before all configuration data is

transferred – or if the nCS is not driven High after all configuration data is transferred – nSTA-

TUS is driven Low, indicating a configuration error.

AT17A Series

Reset Polarity

The AT17A Series Configurator allows the user to program the polarity of the OE pin as either

RESET/OE or RESET/OE. For more details, please reference the “Programming Specification

for Atmel’s FPGA Configuration EEPROMs” application note.

Programming

Mode

The programming mode is entered by bringing SER_EN Low. In this mode the chip can be

programmed by the 2-wire serial interface. The programming is done at VCC supply only. Pro-

gramming supervoltages are generated inside the chip. See the “Programming Specification

for Atmel’s Configuration EEPROMs” application note for further information. The AT17 A-

series parts are read/write at 5V nominal. The AT17LV A-series parts are read/write at 3.3V

nominal.

Standby Mode The AT17A Series Configurator enters a low-power standby mode whenever nCS is asserted

High. In this mode, the configuration consumes less than 0.5 mA of current at 5V. The output

remains in a high-impedance state regardless of the state of the OE input.

6AT17C/LV002A

2280B–08/01

Pin Configurations

PLCC

TQFP

Pin Name I/O Description

2 31 DATA I/O Three-state data output for configuration. Open-collector bi-directional pin for programming.

4 2 DCLK I/O Clock output or clock input. Rising edges on DCLK increment the internal address counter

and present the next bit of data to the DATA pin. The counter is incremented only if the OE

input is held High, the nCS input is held Low, and all configuration data has not been

transferred to the target device (otherwise, as the master device, the DCLK pin drives Low).

5 4 WP1 I WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by

default due to internal pull-down resistor. This input pin is not used during FPGA loading

operations. See the “Programming Specification for Atmel’s Configuration EEPROMs”

application note for more details.

8 7 OE I Output enable (active High) and reset (active Low) when SER_EN is High. A Low logic level

resets the address counter. A High logic level (with nCS Low) enables DATA and permits the

address counter to count. In the mode, if this pin is Low (reset), the internal oscillator

becomes inactive and DCLK drives Low. The logic polarity of this input is programmable and

must be programmed active High (RESET active Low) by the user during programming for

Altera applications.

9 10 nCS I Chip select input (active Low). A Low input (with OE High) allows DCLK to increment the

address counter and enables DATA to drive out. If the AT17A Series is reset with nCS Low,

the device initializes as the first (and master) device in a daisy chain. If the AT17A Series is

reset with nCS High, the device initializes as a subsequent AT17A Series device in the chain.

10 12 GND Ground pin. A 0.2 µF decoupling capacitor should be placed between the VCC and GND

pins.

12 15 nCASC O Cascade select output (active Low). This output goes Low when the address counter has

reached its maximum value. In a daisy chain of AT17A Series devices, the nCASC pin of one

device is usually connected to the nCS input pin of the next device in the chain, which

permits DCLK from the master configurator to clock data from a subsequent AT17A Series

device in the chain.

A2 I Device selection input, A2. This is used to enable (or select) the device during programming,

(i.e., when SER_EN is Low; please refer to the “Programming Specification for Atmel’s

Configuration EEPROMs” application note for more details.)

15 20 READY O Open collector reset state indicator. Driven Low during power-up reset, released (tri-stated)

when power-up is complete. (Recommend a 4.7 kΩ pull-up on this pin if used.)

18 23 SER_EN I Serial enable must be held High during FPGA loading operations. Bringing SER_EN Low

enables the 2-wire serial programming mode.

20 27 VCC +3.3V/+5V power supply pin

AT17C/LV002A

2280B–08/01

Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C*NOTICE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent dam-

age to the device. These are stress ratings only,

and functional operation of the device at these or

any other conditions beyond those listed under

Operating Conditions is not implied. Exposure to

Absolute Maximum Ratings conditions for

extended periods of time may affect device

reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin

with Respect to Ground ..............................-0.1V to VCC +0.5V

Supply Voltage (VCC) .........................................-0.5V to +7.0V

Maximum Soldering Temp. (10 sec @ 1/16 in.)..............260°C

Operating Conditions

Symbol Description

AT17C002A AT17LV002A

UnitsMin Max Min Max

VCC

Commercial Supply voltage relative to GND

-0°C to +70°C

4.75 5.25 3.15 3.45 V

Industrial Supply voltage relative to GND

-40°C to +85°C

4.5 5.5 3.15 3.45 V

Military Supply voltage relative to GND

-55°C to +125°C4.5 5.5 3.15 3.45 V

8AT17C/LV002A

2280B–08/01

DC Characteristics

VCC = 5V ± 5% Commercial/5V ± 10% Industry/Military

Symbol Description Min Max Units

VIH High-level Input Voltage 2.0 VCC V

VIL Low-level Input Voltage 0.0 0.8 V

VOH High-level Output Voltage (IOH = -4 mA) Commercial 3.86 V

VOL Low-level Output Voltage (IOL = +4 mA) 0.32 V

VOH High-level Output Voltage (IOH = -4 mA) Industrial 3.76 V

VOL Low-level Output Voltage (IOL = +4 mA) 0.37 V

VOH High-level Output Voltage (IOH = -4 mA) Military 3.7 V

VOL Low-level Output Voltage (IOL = +4 mA) 0.4 V

ICCA Supply Current, Active Mode (at FMAX) 10 mA

ILInput or Output Leakage Current (VIN = VCC or GND) -10 10 µA

ICCS Supply Current, Standby Mode AT17C512A/010A Commercial 500 µA

Industrial/Military 500 µA

DC Characteristics

VCC = 3.3V ± 5%

Symbol Description Min Max Units

VIH High-level Input Voltage 2.0 VCC V

VIL Low-level Input Voltage 0.0 0.8 V

VOH High-level Output Voltage (IOH = -2.5 mA) Commercial 2.4 V

VOL Low-level Output Voltage (IOL = +3 mA) 0.4 V

VOH High-level Output Voltage (IOH = -2 mA) Industrial 2.4 V

VOL Low-level Output Voltage (IOL = +3 mA) 0.4 V

VOH High-level Output Voltage (IOH = -2 mA) Military 2.4 V

VOL Low-level Output Voltage (IOL = +2.5 mA) 0.4 V

ICCA Supply Current, Active Mode (at FMAX) 5 mA

ILInput or Output Leakage Current (VIN = VCC or GND) -10 10 µA

ICCS Supply Current, Standby Mode Commercial 100 µA

Industrial/Military 100 µA

AT17C/LV002A

2280B–08/01

AC Characteristics

AC Characteristics When Cascading

nCS

DCLK

DATA

TSCE

TLC THC

TOE

TCE

TCAC TOH

THOE

THCE

TSCE

TDF

TOH

nCS

DCLK

DATA

nCASL

TCDF

TOCK

LAST BIT

TOCE TOOE

TOCE

FIRST BIT

10 AT17C/LV002A

2280B–08/01

Notes: 1. Preliminary specifications for military operating range only.

2. AC test load = 50 pF.

3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.

Notes: 1. Preliminary specifications for military operating range only.

2. AC test load = 50 pF.

3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.

AC Characteristics for AT17C002A

VCC = 5V ± 5% Commercial/VCC = 5V ± 10% Industry/Military

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TOE(2) OE to Data Delay 30 35 ns

TCE(2) nCS to Data Delay 45 45 ns

TCAC(2) DCLK to Data Delay 50 55 ns

TOH Data Hold From nCS, OE or DCLK 0 0 ns

TDF(3) nCS or OE to Data Float Delay 50 50 ns

TLC DCLK Low Time Slave Mode 20 20 ns

THC DCLK High Time Slave Mode 20 20 ns

TSCE nCS Setup Time to DCLK (to guarantee proper counting) 20 25 ns

THCE nCS Hold Time from DCLK (to guarantee proper

counting)

00ns

TLOE OE Low Time (guarantees counter is reset) 20 20 ns

FMAX Maximum Input Clock Frequency Slave Mode 12 12.5 MHz

TLC DCLK Low Time Master Mode 30 250 30 250 ns

THC DCLK High Time Master Mode 30 250 30 250 ns

AC Characteristics for AT17C002A When Cascading

VCC = 5V ± 5% Commercial/VCC = 5V ± 10% Industry/Military

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TCDF (3) DCLK to Data Float Delay 50 50 ns

TOCK(2) DCLK to nCASC Delay 35 40 ns

TOCE(2) nCS to nCASC Delay 35 35 ns

TOOE(2) OE to nCASC Delay 30 30 ns

FMAX Maximum Input Clock Frequency 12.5 12.5 MHz

AT17C/LV002A

2280B–08/01

Notes: 1. Preliminary specifications for military operating range only.

2. AC test load = 50 pF.

3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.

Notes: 1. Preliminary specifications for military operating range only.

2. AC test load = 50 pF.

3. Float delays are measured with 5 pF AC loads. Transition is measured ± 200 mV from steady state active levels.

AC Characteristics for AT17LV002A

VCC = 3.3V ± 5% Commercial/VCC = 3.3V ± 5% Industry/Military

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TOE(2) OE to Data Delay 50 55 ns

TCE(2) nCS to Data Delay 55 60 ns

TCAC(2) DCLK to Data Delay 60 65 ns

TOH Data Hold From nCS, OE or DCLK 0.0 0 ns

TDF(3) nCS or OE to Data Float Delay 50 50 ns

TLC DCLK Low Time Slave Mode 25 25 ns

THC DCLK High Time Slave Mode 25 25 ns

TSCE nCS Setup Time to DCLK (to guarantee proper counting) 35 40 ns

THCE nCS Hold Time from DCLK (to guarantee proper

counting)

00ns

TLOE OE Low Time (guarantees counter is reset) 20 20 ns

FMAX Maximum Input Clock Frequency Slave Mode 15 10 MHz

TLC DCLK Low Time Master Mode 30 300 30 300 ns

THC DCLK High Time Master Mode 30 300 30 300 ns

AC Characteristics for AT17LV002A When Cascading

VCC = 3.3V ± 5% Commercial/VCC = 3.3V ± 5% Industry/Military

Symbol Description

Commercial Industrial/Military(1)

UnitsMin Max Min Max

TCDF(3) DCLK to Data Float Delay 50 50 ns

TOCK(2) DCLK to nCASC Delay 50 55 ns

TOCE(2) nCS to nCASC Delay 35 40 ns

TOOE(2) OE to nCASC Delay 35 35 ns

FMAX Maximum Input Clock Frequency Slave Mode 12.0 10 MHz

12 AT17C/LV002A

2280B–08/01

Note: 1. Use 2-Mbit density parts to replace Altera EPC2.

Note: 1. Use 2-Mbit density parts to replace Altera EPC2. Atmel AT127C/LV002A devices do not support JTAG programming; Atmel

AT17X002A devices use a 2-wire serial interface for in-system programming.

Ordering Information – 5V Devices

Memory

Size Ordering Code Package Operation Range

2-Mbit(1) AT17C002A-10JC 20J Commercial

(0°C to 70°C)

AT17C002A-10JI 20J Industrial

(-40°C to 85°C)

2-Mbit(1) AT17C002A-10QC 32A Commercial

(0°C to 70°C)

AT17C002A-10QI 32A Industrial

(-40°C to 85°C

Ordering Information – 3.3V Devices

Memory

Size Ordering Code Package Operation Range

2-Mbit(1) AT17LV002A-10JC 20J Commercial

(0°C to 70°C)

AT17LV002A-10JI 20J Industrial

(-40°C to 85°C)

2-Mbit(1) AT17LV002A-10QC 32A Commercial

(0°C to 70°C)

AT17LV002A-10Q1 32A Industrial

(-40°C to 85°C

Package Type

20J 20-lead, Plastic J-leaded Chip Carrier (PLCC)

32A 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

Packaging Information

13 AT17C/LV002A

2280B–08/01

9.00 (0.354) BSC

0.45 (0.018)

0.30 (0.012)

PIN 1 ID

0.80 (0.031) BSC

7.00 (0.276) BSC

0˚

7˚

0.20 (0.008)

0.10 (0.004)

0.75 (0.030)

0.45 (0.018)

1.20 (0.047) MAX

0.15 (0.006)

0.05 (0.002)

20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)

Dimensions in Inches and (Millimeters)

JEDEC STANDARD MS-018 AA

32A, 32-lead, Thin (1.0 mm) Plastic Gull Wing Quad

Flat Package (TQFP)

Dimensions in Millimeters and (Inches)

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