13
®
VSP3100
In this mode, three CDSs are used to process three inputs
simultaneously. Each channel consists of a 10-bit Offset
DAC (range from –400mV to +400mV). A 3-to-1 analog
MUX is inserted between the CDSs and a high-performance,
14-bit A/D converter. The outputs of the CDSs are then
multiplexed to the A/D converter for digitization. The ana-
log MUX is switched at the falling edge of CK2, and can be
programmed to cycle between the Red, Green, and Blue
channels. When D6 of the Configuration Register sets to
“0”, the MUX sequence is Red > Green > Blue. When D6
of the Configuration Register sets to “1”, the MUX sequence
is Blue > Green > Red.
MUX resets at the falling edge of CK1. In the case of a
Red > Green > Blue sequence, it resets to “R”, and in the
case of a Blue > Green > Red sequence, it resets to “B”.
The VSP3100 allows two types of output modes:
1) Normal (D7 of Configuration Register sets to “0”).
2) Demultiplexed (D7 of Configuration Register sets to “1”).
As specified in the “3-Channel CCD Mode” timing diagram,
the falling edge of CK2 must be in the LOW period of
ADCCK. If the falling edge of CK2 is in the HIGH period
of ADCCK (in the timing diagram, ADCCK for sampling
B-channel), the VSP3100 will not function properly.
3-CHANNEL CIS MODE
In this mode, the VSP3100 is operated as 3-channel sam-
plers and a digitizer. Unlike CCD modes, VSP3100 takes
only one sample on the falling edge of CK1 for each input.
Since only one sample is taken, CK2 is grounded in this
operation. The input signals are DC coupled in most cases.
Here, the VSP3100 inputs allow differential inputs. Using
the Red channel as an example, RINP is the CIS input signal,
and INN is the CIS common reference signal input. The
same applies to the Green channel (GINP and INN) and Blue
channel (BINP and INN).
In this mode, three CDSs become CISs (act like sample-and-
hold) to process three inputs simultaneously. Each channel
consists of a 10-bit Offset DAC (range from –400mV to
+400mV). A 3-to-1 analog MUX is inserted between the
CISs and a high-performance, 14-bit A/D converter. The
outputs of the CIS are then multiplexed to the A/D converter
for digitization. The analog MUX is switched at the falling
edge of CK2, and can be programmed cycling between the
Red, Green, and Blue channels. When D6 of the
Configuration Register sets to “0”, the MUX sequence is
Red > Green > Blue. When D6 of the Configuration Register
sets to “1”, the MUX sequence is Blue > Green > Red.
MUX resets at the falling edge of CK1. In the case of a
Red > Green > Blue sequence, it resets to “R”, and in the
case of a Blue > Green> Red sequence, it resets to “B”.
The VSP3100 allows two types of output modes:
1) Normal (D7 of Configuration Register sets to “0”).
2) Demultiplexed (D7 of Configuration Register sets to “1”).
As specified in the “3-Channel CIS Mode” timing diagram,
the falling edge of CK1 must be in the LOW period of
ADCCK. If the falling edge of CK1 is in the HIGH period
of ADCCK (in the timing diagram, ADCCK for sampling
B-channel), the VSP3100 will not function properly.
DIGITAL OUTPUT FORMAT
The Digital Output Format is shown in Table I. The VSP3100
can be operated in one of the following two digital output
modes:
(1) Normal output.
(2) Demultiplexed (B13-based Big Endian Format).
In Normal mode, the VSP3100 outputs the 14-bit data by B0
(pin 25) through B13 (pin 38) simultaneously.
In Demultiplexed mode, VSP3100 outputs the high byte
(upper 8 bits) by B6 (pin 31) through B13 (pin 38) at the
rising edge of ADCCK “HIGH”, then outputs the low byte
(lower 6 bits) by B8 (pin 33) through B13 (pin 38) at the
falling edge of ADCCK.
An 8-bit interface can be used between the VSP3100 and the
Digital Signal Processor, allowing for a low-cost system
solution.
BIT B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
High Byte B13 B12 B11 B10 B9 B8 B7 B6 Low Low Low Low Low Low
Low Byte B5 B4 B3 B2 B1 B0 Low Low Low Low Low Low Low Low
TABLE I. Digital Output Format.