M microIDTM 13.56 MHz RFID System Design Guide NEW CUSTOMER NOTIFICATION SYSTEM Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2001 Microchip Technology Inc. DS21299D DATA SHEET MARKINGS Microchip uses various data sheet markings to designate each document phase as it relates to the product development stage. The markings appear at the bottom of the data sheet, between the copyright and document and page numbers. The definitions for each marking are provided below for your use. Marking Description Advance Information The information is on products in the design phase. Your designs should not be finalized with this information as revised information will be published when the product becomes available. Preliminary This is preliminary information on new products in production but not yet fully characterized. The specifications in these data sheets are subject to change without notice. Before you finalize your design, please ensure that you have the most current revision of the data sheet by contacting your Microchip sales office. No Marking Information contained in the data sheet is on products in full production. "All rights reserved. Copyright (c) 2001, Microchip Technology Incorporated, USA. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip's products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights." Trademarks The Microchip name, logo, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, KEELOQ, SEEVAL, MPLAB and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Total Endurance, ICSP, In-Circuit Serial Programming, FilterLab, MXDEV, microID, FlexROM, fuzzyLAB, MPASM, MPLINK, MPLIB, PICDEM, ICEPIC, Migratable Memory, FanSense, ECONOMONITOR, Select Mode and microPort are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2001, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company's quality system processes and procedures are QS-9000 compliant for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001 certified. DS21299D - page ii 2001 Microchip Technology Inc. M Table of Contents PAGE PASSIVE RFID BASICS Introduction......................................................................................................................................... 1 Definitions.......................................................................................................................................... 1 System Handshake ........................................................................................................................... 4 Backscatter Modulation ..................................................................................................................... 4 Data Encoding................................................................................................................................... 4 Data Modulation for 125 kHz Devices (MCRF2XX) .......................................................................... 6 Anti-collision ...................................................................................................................................... 7 MCRF355/360 DATA SHEET Features ............................................................................................................................................ 9 Application ......................................................................................................................................... 9 Package Type ................................................................................................................................... 9 Description ........................................................................................................................................ 9 1.0 Electrical Characteristics .......................................................................................................... 11 2.0 Functional Description.............................................................................................................. 15 3.0 Resonant Circuit....................................................................................................................... 17 4.0 Device Programming................................................................................................................. 18 MCRF355/360 Guide Product Identification System....................................................................... 20 MICROCHIP DEVELOPMENT KIT SAMPLE FORMAT FOR THE MCRF355/360 DEVICES 21 FACTORY PROGRAMMING SUPPORT (SQTPSM) Introduction...................................................................................................................................... 23 File Specification ............................................................................................................................. 23 MCRF450/451/452/455 DATA SHEET Features .......................................................................................................................................... 25 Package Types................................................................................................................................ 25 Description ....................................................................................................................................... 25 Application........................................................................................................................................ 25 1.0 Electrical Characteristics ........................................................................................................... 27 2.0 Block Diagram ........................................................................................................................... 33 3.0 Detection and Encoding Section ............................................................................................... 35 4.0 Read/write Anti-collision Logic .................................................................................................. 36 5.0 Memory Section ........................................................................................................................ 51 6.0 Device Testing........................................................................................................................... 53 7.0 Examples................................................................................................................................... 54 8.0 Packaging Information............................................................................................................... 57 MCRF450/451/452/455 Product Identification System .................................................................... 62 CRC ALGORITHM FOR MCRF45X READ/WRITE DEVICE Introduction....................................................................................................................................... 63 Computation Algorithm..................................................................................................................... 64 Example with Source Code for CRC Calculation ............................................................................. 66 2001 Microchip Technology Inc. DS21299D-page iii Table of Contents M PAGE MCRF355/360 APPLICATION NOTE: MODE OF OPERATION AND EXTERNAL RESONANT CIRCUIT Introduction....................................................................................................................................... 69 Mode of Operation............................................................................................................................ 69 Anti-collision Features ...................................................................................................................... 71 External Circuit Configuration........................................................................................................... 72 Programming of Device.................................................................................................................... 74 ANTENNA CIRCUIT DESIGN FOR RFID APPLICATIONS Introduction....................................................................................................................................... 75 Review of a Basic Theory for RFID antenna Design........................................................................ 75 Induced Voltage in an Antenna Coil ................................................................................................. 77 Wire Types and Ohmic Losses ........................................................................................................ 80 Inductance of Various Antenna Coils ............................................................................................... 82 Configuration of Antenna Circuits..................................................................................................... 86 Consideration on Quality Factor Q and Bandwidth of Tuning Circuit ............................................... 88 Resonant Circuits ............................................................................................................................. 89 Tuning Method ................................................................................................................................. 92 Read Range of RFID Devices .......................................................................................................... 93 References ....................................................................................................................................... 94 MCRF355/360 READER REFERENCE DESIGN 1.0 2.0 3.0 4.0 5.0 6.0 Introduction................................................................................................................................ 95 Reader Circuits.......................................................................................................................... 95 Optimization for Long-Range Applications ................................................................................ 97 Reader Schematic..................................................................................................................... 99 Reader Bill of Materials ........................................................................................................... 100 Reader Source Code for the PICmicro(R) MCU ........................................................................ 102 13.56 MHZ READER REFERENCE DESIGN FOR THE MCRF450/451/452/455 READ/WRITE DEVICES 1.0 Introduction.............................................................................................................................. 117 2.0 Interrogator Circuits................................................................................................................. 119 INTERFACE CONTROL DOCUMENT FOR THE 13.56 MHZ MCRF450/451/452/455 ANTI-COLLISION INTERROGATOR Scope ............................................................................................................................................. 131 Referenced Documents.................................................................................................................. 131 External Interfaces ......................................................................................................................... 131 PICMICRO(R) MICROCONTROLLER FIRMWARE FLOW CHART OF MCRF45X DEMO READER 141 RECOMMENDED ASSEMBLY FLOWS 1.0 Wafer on Frame Assembly Flow ............................................................................................. 155 2.0 Wafer Assembly Flow.............................................................................................................. 156 WORLDWIDE SALES AND SERVICE DS21299D-page iv 160 2001 Microchip Technology Inc. M Author: AN680 Passive RFID Basics Youbok Lee and Pete Sorrells Microchip Technology Inc. INTRODUCTION Radio Frequency Identification (RFID) systems use radio frequency to identify, locate and track people, assets and animals. Passive RFID systems are composed of three components - a reader (interrogator), passive tag and host computer. The tag is composed of an antenna coil and a silicon chip that includes basic modulation circuitry and non-volatile memory. The tag is energized by a time-varying electromagnetic radio frequency (RF) wave that is transmitted by the reader. This RF signal is called a carrier signal. When the RF field passes through an antenna coil, there is an AC voltage generated across the coil. This voltage is rectified to result in a DC voltage for the device operation. The device becomes functional when the DC voltage reaches a certain level. The information stored in the device is transmitted back to the reader. This is often called backscattering. By detecting the backscattering signal, the information stored in the device can be fully identified. There are two classes of RFID device depending on type of memory cell : (a) read only device and (b) read and write device. The memory cell can be made of EEPROM or FRAM. EEPROM is based on CMOS silicon and FRAM is based on ferroelectric memory. Since CMOS process technology has been matured, the EEPROM can be produced relatively at lower cost than the FRAM device. However, FRAM based RFID device consumes less power which is desirable for low power device. Therefore, it is known as a good candidate for the future RFID device, if its manufacturing cost becomes compatible to that of the CMOS technology. Because of its simplicity for use, the passive RFID system has been used for many years in various RF remote sensing applications. Specifically in access control and animal tracking applications. In recent years, there have been dramatic increases in application demands. In most cases, each applications uses a unique packaging form factor, communication protocol, frequency, etc. Because the passive tag is remotely powered by reader's RF signal, it deals with very small power (~ w). Thus, the read range (communication distance between reader and tag) is typically limited within a proximity distance. The read range 2001 Microchip Technology Inc. varies with design parameters such as frequency, RF power level, reader's receiving sensitivity, size of antenna, data rate, communication protocol, current consumptions of the silicon device, etc. Low frequency bands (125 kHz - 400 kHz) were traditionally used in RFID applications. This was because of the availability of silicon devices. Typical carrier frequency (reader's transmitting frequency) in today's applications range from 125 kHz - 2.4 GHz. In recent years, the applications with high frequency (4 - 20 MHz) and microwave (2.45 GHz) bands have risen with the advent of new silicon devices. Each frequency band has advantages and disadvantages. The 4 - 20 MHz frequency bands offer the advantages of low (125 kHz) frequency and microwave (2.4 GHz) bands. Therefore, this frequency band becomes the most dominant frequency band in passive RFID applications. FIGURE 1: SIMPLE CONFIGURATION OF RFID SYSTEMS RF Energizing/Command Signal Reader (Interrogator) Backscattering Data Signal Passive RFID Tag RS-232 Host Computer DEFINITIONS READER, INTERROGATOR RFID reader is used to activate passive tag with RF energy and to extract information from the tag. For this function, the reader includes RF transmission, receiving and data decoding sections. In addition, the reader includes a serial communication (RS-232) capability to communicate with the host computer. Depend- DS00680C-page 1 AN680 ing on the complexity and purpose of applications, the reader's price range can vary from ten dollars to a few thousand dollar worth of components and packaging. The RF transmission section includes an RF carrier generator, antenna and a tuning circuit. The antenna and its tuning circuit must be properly designed and tuned for the best performance. See Application Note AN710 (DS00710) for the antenna circuit design. Data decoding for the received signal is accomplished using a microcontroller. The firmware algorithm in the microcontroller is written in such a way to transmit the RF signal, decode the incoming data and communicate with the host computer. Typicall, reader is a read only device, while the reader for read and write device is often called interrogator. Unlike the reader for read only device, the interrogator uses command pulses to communicate with tag for reading and writing data. TAG Tag consists of a silicon device and antenna circuit. The purpose of the antenna circuit is to induce an energizing signal and to send a modulated RF signal. The read range of tag largely depends upon the antenna circuit and size. The antenna circuit of tag is made of LC resonant circuit or E-field dipole antenna, depending on the carrier frequency. The LC resonant circuit is used for the frequency of less than 100 MHz. In this frequency band, the communication between the reader and tag takes place with magnetic coupling between the two antennas through the magnetic field. The antenna utilizing the inductive coupling is often called magnetic dipole antenna. The antenna circuit must be designed such a way to maximize the magnetic coupling between them. This can be achieved with the following parameters: a) b) c) LC circuit must be tuned to the carrier frequency of the reader Maximize Q of the tuned circuit Maximize antenna size within physical limit of application requirement. See Application Note AN710 for more details. When the frequency goes above 100 MHz, the requirement of LC values for its resonant frequency becomes too small to realize with discrete L and C components. As frequency increases, the wavelength is getting shorter. In this case, a true E-field antenna can be made of a simple conductor that has linear dimension less than or equivalent to half (1/2) the wavelength of the signal. The antenna that is made of a simple conductor is called electric dipole antenna. The electric dipole antenna utilizes surface current that is generated by an electric field (E-Field). The surface current on the conductor produces voltage at load. This voltage is used to DS00680C-page 2 energize the silicon device. Relatively simple antenna structure is formed for the higher frequency compared to the lower frequency. READ ONLY DEVICE, READ/WRITE DEVICE: For the read only device, the information that is in the memory can't be changed by RF command once it has been written. Read only devices are programmed as follows: (a) in the factory as a part of manufacturing process, (b) contactlessly programmed one time after the manufacturing (MCRF200 and MCRF250) or (c) can be programmed and also reprogrammed in contact mode (MCRF355 and MCRF360). A device with memory cells that can be reprogrammed by RF commands is called read/write device. The information in the memory can be reprogrammed by Interrogator command. Memory in today's RFID device is made of (a) CMOS or (b) FRAM array. The CMOS memory cell needs higher voltage for writing than reading. In the passive read/write device, the programming voltage is generated by multiplying the rectified voltage. The voltage multiplier circuit is often called a charge pumper. In addition to the programming voltage, the read/write device needs command decoder and other controller logics. As a result, the read/write device needs more circuit building blocks than that of the read only device. Therefore, the device size is larger and cost more than a read only device. The FRAM device needs the same voltage for reading and writing. However, its manufacturing cost is much higher than CMOS technology. Most of RFID device available today's market place are CMOS based device. READ/WRITE RANGE Read/write range is a communication distance between the reader (Interrogator) and tag. Specifically, the read range is a maximum distance to read data out from the tag and write range is a maximum distance to write data from interrogator to tag. The read/write range is related to: (1) Electromagnetic coupling of the reader (interrogator) and tag antennas, (2) RF Output power level of reader (interrogator), (3) Carrier frequency bands, (4) Power consumption of device, etc. The electromagnetic coupling of reader and tag antennas increases using similar size of antenna with higher Q in both sides. The read range is improved by increasing the carrier frequency. This is due to the gain in the radiation efficiency of the antenna as the frequency increases. However, the disadvantage of high frequency (900 MHz - 2.4 GHz) application are shallow skin depth and narrower antenna beam width. These cause less penetration and more directional problem, 2001 Microchip Technology Inc. AN680 CARRIER respectively. Low frequency application, on the other hand, has advantage in the penetration and directional, but a disadvantage in the antenna performance. The read range increases by reducing the current consumptions in the silicon device. This is because additional radiating power is available by reducing the power dissipation in the silicon device. Carrier is the transmitting radio frequency of reader (interrogator). This RF carrier provides energy to the tag device, and is used to detect modulation data from the tag using backscattering. In read/write device, the carrier is also used to deliver interrogator's command and data to the tag. MODULATION PROTOCOL Typical passive RFID carrier frequencies are: a) b) c) The passive RFID tag uses backscattering of the carrier frequency for sending data from the tag to reader. The amplitude of backscattering signal is modulated with modulation data of the tag device. The modulation data can be encoded in the form of ASK (NRZ or Manchester), FSK or PSK. Therefore, the modulation signal from the tag is Amplitude-Amplitude, AmplitudeFSK and Amplitude-PSK. See MicroID 125 kHz Design Guide for Amplitude, Amplitude-FSK and Amplitude-PSK reader. 125 kHz - 400 kHz 4 MHz - 24 MHz 900 MHz - 2.45 GHz. The frequency bands must be selected carefully for applications because each one has its own advantages and disadvantages. Table 1 shows the characteristic of each frequency bands. TABLE 1: Frequency Bands Antenna Components Read Range (typical) Low Frequency (125 - 400) kHz Coil (> 100 turns) and capacitor Proximity (8") Best Least Possible Proximity Medium Frequency Coil (< 10 turns) (4 MHz - 24 MHz) and capacitor Medium (15") Good Not much Possible Low cost and high volume Long ( > 1 m) Poor Very high Difficult Line of sight with long range High Frequency (>900 MHz) E-field dipole (a piece of conductor) 2001 Microchip Technology Inc. Usability in Penertration Orientation Applications metal or humid (skin depth) (Directionality) (typical) environment DS00680C-page 3 AN680 SYSTEM HANDSHAKE 9. Typical handshake of a tag and reader (interrogator) is as follows: BACKSCATTER MODULATION A. Read Only Tag 1. 2. 3. 4. The reader continuously transmits an RF signal and watches always for modulated backscattering signal. Once the tag has received sufficient energy to operate correctly, it begins clocking its data to a modulation transistor, which is connected across the antenna circuit. The tag's modulation transistor shorts the antenna circuit, sequentially corresponding to the data which is being clocked out of the memory array. Shorting and releasing the antenna circuit accordingly to the modulation data causes amplitude fluctuation of antenna voltage across the antenna circuit. The reader detects the amplitude variation of the tag and uses a peak-detector to extract the modulation data. See Figure 4-1 in MCRF45X data sheet for more details. This terminology refers to the communication method used by a passive RFID tag to send data to the reader using the same reader's carrier signal. The incoming RF carrier signal to the tag is transmitted back to the reader with tag's data. The RF voltage induced in the tag's antenna is amplitude-modulated by the modulation signal (data) of tag device. This amplitude-modulation can be achieved by using a modulation transistor across the LC resonant circuit or partially across the resonant circuit. The changes in the voltage amplitude of tag's antenna can affect on the voltage of the reader antenna. By monitoring the changes in the reader antenna voltage (due to the tag's modulation data), the data in the tag can be reconstructed. B. Read and Write Tag The RF voltage link between reader and tag antennas are often compared to a weakly coupled transformer coils; as the secondary winding (tag coil) is momentarily shunted, the primary winding (reader coil) experiences a momentary voltage drop. (Example: MCRF45X devices with FRR and Reader Talks First mode) DATA ENCODING 5. 1. 2. 3. 4. 5. 6. 7. 8. The interrogator sends a command to initiate communication with tags in the fields. This command signal is also used for energizing the passive device. Once the tag has received sufficient energy and command, it responses back with its ID for acknowledgment. The interrogator now knows which tag is in the field. The interrogator sends a command to the identified tag for what to do next: processing (read or write) or sleep. If the tag receive processing and reading commands, it transmits a specified block data and waits for the next command. If the tag receives processing and writing commands along with block data, it writes the block data into the specified memory block, and transmits the written block data for verification. After the processing, the interrogator sends an "end" command to send the tag into the sleep ("silent") mode. If the device receives "end" command after processing, it sends an acknowledgement (8-bit preamble) and stays in sleep mode. During the sleep mode, the device remains in non-modulating (detuned) condition as long as it remains in the power-up. This time the handshake is over. The interrogator is now looking for the next tag for processing, establishes an handshake and repeats the processing. DS00680C-page 4 Data encoding refers to processing or altering the data bitstream in-between the time it is retrieved from the RFID chip's data array and its transmission back to the reader. The various encoding algorithms affect error recovery, cost of implementation, bandwidth, synchronization capability and other aspects of the system design. Entire textbooks are written on the subject, but there are several popular methods used in RFID tagging today: 1. 2. NRZ (Non-Return to Zero) Direct. In this method no data encoding is done at all; the 1's and 0's are clocked from the data array directly to the output transistor. A low in the peak-detected modulation is a `0' and a high is a `1'. Differential Biphase. Several different forms of differential biphase are used, but in general the bitstream being clocked out of the data array is modified so that a transition always occurs on every clock edge, and 1's and 0's are distinguished by the transitions within the middle of the clock period. This method is used to embed clocking information to help synchronize the reader to the bitstream. Because it always has a transition at a clock edge, it inherently provides some error correction capability. Any clock edge that does not contain a transition in the data stream is in error and can be used to reconstruct the data. 2001 Microchip Technology Inc. AN680 3. Biphase_L (Manchester). This is a variation of biphase encoding in which there is not always a transition at the clock edge. The MCRF355/360 and MCRF45X devices use this encoding method. FIGURE 2: VARIOUS DATA CODING WAVEFORMS Data DESCRIPTION WAVEFORM SIGNAL 1 0 1 Bit Rate CLK 1 0 0 0 1 1 0 1 0 Digital Data Clock Signal NRZ_L (Direct) Non-Return to Zero - Level `1' is represented by logic high level. `0' is represented by logic low level. Biphase_L (Manchester) Biphase - Level (Split Phase) A level change occurs at middle of every bit clock period. `1' is represented by a high to low level change at midclock. `0' is represented by a low to high level change at midclock. Differential Biphase - Space A level change occurs at middle of every bit clock period. Differential Biphase_S `1' is represented by a change in level at start of clock. `0' is represented by no change in level at start of clock. Note: Manchester coding is used for the MCRF355/360 and MCRF45X 2001 Microchip Technology Inc. DS00680C-page 5 AN680 DATA MODULATION FOR 125 kHZ DEVICES (MCRF2XX) 0's and 1's in the bitstream, and the reader has Although all the data is transferred to the host by amplitude-modulating the carrier (backscatter modulation), the actual modulation of 1's and 0's is accomplished with three additional modulation methods: 1. 2. Direct. In direct modulation, the Amplitude Modulation of the backscatter approach is the only modulation used. A high in the envelope is a `1' and a low is a `0'. Direct modulation can provide a high data rate but low noise immunity. FSK (Frequency Shift Keying). This form of modulation uses two different frequencies for data transfer; the most common FSK mode is FC/8/10. In other words, a `0' is transmitted as an amplitude-modulated clock cycle with period corresponding to the carrier frequency divided by 8, and a `1' is transmitted as an amplitude-modulated clock cycle period corresponding to the carrier frequency divided by 10. The amplitude modulation of the carrier thus switches from FC/8 to FC/10 corresponding to FIGURE 3: PSK provides fairly good noise immunity, a moderately simple reader design, and a faster data rate than FSK. Typical applications utilize a backscatter clock of FC/2, as shown in Figure 4. FSK MODULATED SIGNAL, FC/8 = 0, FC/10 = 1 8 cycles = 0 DS00680C-page 6 3. only to count cycles between the peak-detected clock edges to decode the data. FSK allows for a simple reader design, provides very strong noise immunity, but suffers from a lower data rate than some other forms of data modulation. In Figure 3, FSK data modulation is used with NRZ encoding. PSK (Phase Shift Keying). This method of data modulation is similar to FSK, except only one frequency is used, and the shift between 1's and 0's is accomplished by shifting the phase of the backscatter clock by 180 degrees. Two common types of PSK are: * Change phase at any `0', or * Change phase at any data change (0 to 1 or 1 to 0). 8 cycles = 0 10 cycles = 1 10 cycles = 1 8 cycles = 0 2001 Microchip Technology Inc. AN680 FIGURE 4: PSK MODULATED SIGNAL Phase Shift Phase Shift Phase Shift Phase Shift ANTI-COLLISION In many existing applications, a single-read RFID tag is sufficient and even necessary: animal tagging and access control are examples. However, in a growing number of new applications, the simultaneous reading of several tags in the same RF field is absolutely critical: library books, airline baggage, garment and retail applications are a few. In order to read multiple tags simultaneously, the tag and reader must be designed to detect the condition that more than one tag is active. Otherwise, the tags will all backscatter the carrier at the same time and the amplitude-modulated waveforms shown in Figure 3 and Figure 4 would be garbled. This is referred to as a collision. No data would be transferred to the reader. The tag/reader interface is similar to a serial bus, even though the "bus" travels through the air. In a wired serial bus application, arbitration is necessary to prevent bus contention. The RFID interface also requires arbitration so that only one tag transmits data over the "bus" at one time. A number of different methods are in use and in development today for preventing collisions; most are patented or patent pending. Yet, all are related to making sure that only one tag "talks" (backscatters) at any one time. See the MCRF250 (DS21267), MCRF355/360 (DS21287) and MCRF45X (DS40232) data sheets for various anti-collision algorithms. 2001 Microchip Technology Inc. DS00680C-page 7 AN680 NOTES: DS00680C-page 8 2001 Microchip Technology Inc. M MCRF355/360 MCRF355/360 Data Sheet FEATURES DESCRIPTION * * * * * * The MCRF355 and MCRF360 are Microchip's 13.56 MHz microIDTM family of RFID tagging devices. They are uniquely designed read-only passive Radio Frequency Identification (RFID) devices with an advanced anti-collision feature. The device is powered remotely by rectifying RF magnetic fields that are transmitted from the reader. * * * * * * Carrier frequency: 13.56 MHz Data modulation frequency: 70 kHz Manchester coding protocol 154 bits of user-reprogrammable memory On-board 100 ms sleep timer Built-in anti-collision algorithm for reading up to 50 tags in the same RF field "Cloaking" feature minimizes the detuning effects of adjacent tags Internal 100 pF resonant capacitor (MCRF360) Read-only device in RF field Rewritable with contact programmer or factoryprogrammed options Very low power CMOS design Die, wafer, PDIP or SOIC package options APPLICATION RF Carrier L1 Reader MCRF355/360 Modulated L2 RF Data PACKAGE TYPE PDIP/SOIC VPRG 1 8 VDD CLK 2 7 NC Ant. A 3 6 Ant. B NC 4 5 VSS 2001 Microchip Technology Inc. The device has a total of six pads (see Figure 1-1). Three (ant. A, B, VSS) are used to connect the external resonant circuit elements. The additional three pads (VPRG, CLK, VDD) are used for programming and testing of the device. The device needs an external resonant circuit between antenna A, B, and VSS pads. The resonant frequency of the circuit is determined by the circuit elements between the antenna A and VSS pads. The resonant circuit must be tuned to the carrier frequency of the reader for maximum performance. The circuit element between the antenna B and VSS pads is used for data modulation. See Application Note AN707 (DS00707) for further operational details. The MCRF360 includes a 100 pF internal resonant capacitor (100 pF). By utilizing this internal resonant capacitor, the device needs external coils only for the resonant circuit. Examples of the resonant circuit configuration for both the MCRF355 and MCRF360 are shown in Section 3. When a tag (device with the external LC resonant circuit) is brought to the reader's RF field, it induces an RF voltage across the LC resonant circuit. The device rectifies the RF voltage and develops a DC voltage. The device becomes functional as soon as VDD reaches the operating voltage level. The device includes a modulation transistor that is located between antenna B and VSS pads. The transistor has high turn-off (a few M) and low turn-on (3 ) resistance. The turn-on resistance is called modulation resistance (RM). When the transistor turns off, the resonant circuit is tuned to the carrier frequency of the reader. This condition is called uncloaking. When the modulation transistor turns on, its low turn-on resistance shorts the external circuit element between the antenna B and VSS. As a result, the resonant circuit no longer resonates at the carrier frequency. This is called cloaking. DS21287D-page 9 MCRF355/360 The induced voltage amplitude (on the resonant circuit) changes with the modulation data: higher amplitude during uncloaking (tuned), and lower amplitude during cloaking (detuned). This is called "amplitude modulation" signal. The receiver channel in the reader detects this amplitude modulation signal and reconstructs the modulation data. The occurrence of the cloaking and uncloaking of the device is controlled by the modulation signal that turns the modulation transistor on and off, resulting in communication from the device to the reader. The data stream consists of 154 bits of Manchesterencoded data at a 70 KHz rate. The Manchester code waveform is shown in Figure 2-2. After completion of the data transmission, the device goes into sleep mode for about 100 ms. The device repeats the transmitting and sleep cycles as long as it is energized. During the sleep time the device remains in an uncloaked state. DS21287D-page 10 Sleep time is determined by a built-in low-current timer. There is a wide variation of the sleep time between each device. This wide variation of sleep time results in a randomness of the time slot. Each device wakes up and transmits its data in a different time slot with respect to each other. Based on this scenario, the reader is able to read many tags that are in the same RF field. The device has a total of 154 bits of reprogrammable memory. All bits are reprogrammable by a contact programmer. A contact programmer (part number PG103003) is available from Microchip Technology Inc. Factory programming prior to shipment, known as Serialized Quick Turn ProgrammingSM (SQTPSM), is also available. The device is available in die form or packaged in SOIC or PDIP. Note: Information provided herein is preliminary and subject to change without notice. 2001 Microchip Technology Inc. MCRF355/360 1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: ABSOLUTE MAXIMUM/MINIMUM RATINGS Parameters Coil Current Assembly temperature Storage temperature TABLE 1-2: Symbol Min. Max. Units IPP_AC TASM TSTORE Conditions -- 40 mA Peak-to-Peak coil current -- 300 C < 10 sec -65 150 C -- DC CHARACTERISTICS All parameters apply across the specified operating ranges, unless otherwise noted. Commercial (C): Parameters TAMB = -20oC to 70oC Symbol Min. Reading voltage VDDR 2.4 -- -- V Hysteresis voltage VHYST -- TBD -- TBD Operating current IDDR -- 7 10 A VDD = 2.4V during reading at 25C Testing voltage VDDT -- 4 -- V -- Programming voltage: High level input voltage Low level input voltage High voltage VIH VIL VHH 0.7 * VDDT -- -- -- -- 20 -- 0.3 * VDDT -- V V V External DC voltage for programming and testing Current leakage during sleep time IDD_OFF -- 10 -- nA (Note 1) Modulation resistance RM -- 3 4 DC resistance between Drain and Source gates of the modulation transistor (when it is turned on) RPDW 5 8 -- K CLK and VPRG internal pull-down resistor Pull-Down resistor Typ. Max. Units Conditions VDD voltage for reading -- Note 1: This parameter is not tested in production. 2001 Microchip Technology Inc. DS21287D-page 11 MCRF355/360 TABLE 1-3: AC CHARACTERISTICS All parameters apply across the specified operating ranges, unless otherwise Commercial (C): TAMB = -20oC to 70oC noted. Parameters Carrier frequency Modulation frequency Coil voltage during reading Symbol Min. FC Typ. Max. 13.56 Units Conditions MHz Reader's transmitting frequency FM 58 70 82 kHz Manchester coding VPP_AC 4 -- -- VPP Peak-to-Peak AC voltage across the coil during reading VCLMP_AC -- 32 -- VPP Peak -to-Peak coil clamp voltage 115 500 kHz 25C 50 100 150 ms Off time for anti-collision feature, at 25C CRES 85 100 115 pF Internal resonant capacitor between Antenna A and VSS, at 13.56 MHz FR 12.65 13.56 14.711 TWC -- 2 10 ms Time to program bit, at 25C Clock high time THIGH -- 4.4 -- s 25C Clock low time TLOW -- 4.4 -- s 25C Stop condition pulse width TPW:STO -- 1000 -- ns 25C Stop condition setup time TSU:STO -- 200 -- ns 25C Setup time for high voltage TSU:HH -- 800 -- ns 25C High voltage delay time TDL:HH -- 800 -- ns Delay time before the next clock, at 25C Data input setup time TSU:DAT -- 450 -- ns 25C Data input hold time THD:DAT -- 1.2 -- s 25C 200 -- ns 25C Coil clamp voltage Test mode clock frequency FCLK Sleep time TOFF Internal resonant capacitor (MCRF360) Resonant frequency (MCRF360) Write/Erase pulse width Output valid from clock TAA -- Data retention -- 200 DS21287D-page 12 -- MHz with L = 1.377 H Years For T < 120C 2001 Microchip Technology Inc. MCRF355/360 TABLE 1-4: PAD COORDINATES (MICRONS) Lower Lower Left X Left Y Pad Name Upper Right X Passivation Openings Upper Right Y Pad Width Pad Height Pad Pad Center X Center Y Ant. A -610.0 489.2 -521.0 578.2 89 89 -565.5 533.7 Ant. B -605.0 -579.8 -516.0 -490.8 89 89 -560.5 -535.3 VSS -605.0 -58.2 -516.0 30.8 89 89 -560.5 -13.7 VDD 463.4 -181.4 552.4 -92.4 89 89 507.9 -136.9 CLK 463.4 496.8 552.4 585.8 89 89 507.9 541.3 VPRG 463.4 157.6 552.4 246.6 89 89 507.9 202.1 Note 1: All coordinates are referenced from the center of the die. The minimum distance between pads (edge to edge) is 10 mil. 2: Die Size = 1.417 mm x 1.513 mm = 1417 m x 1513 m = 55.79 mil x 59.57 mil FIGURE 1-1: MCRF355/360 DIE LAYOUT Y (Notch edge of wafer) 1162.4 984.4 (-565.5, 533.7) 250.2 (507.9, 202.1) (0, 0) X 250 VDD 432.6 (507.9, -136.9) (-560.5, -535.3) Ant B VPRG 1513 VSS 1158 458.4 (-560.5, -13.7) CLK (507.9, 541.3) 767.2 Ant A 1157.4 1417 All units in the layout are P m. Die Size before Saw: 1.417 mm x 1.513 mm = 1417 P m x 1513 P m = 55.79 mil x 59.57 mil Bond Pad Size: 89 P m x 89 P m = 0.089 mm x 0.089 mm = 3.5 mil x 3.5 mil 2001 Microchip Technology Inc. DS21287D-page 13 MCRF355/360 TABLE 1-5: DIE MECHANICAL DIMENSIONS Specifications Min. Typ. Max. Unit Comments Bond pad opening -- -- 3.5 x 3.5 89 x 89 -- -- mil m (Note 1, Note 2) Die backgrind thickness -- -- 8 177.8 -- -- mil m Sawed 8" wafer on frame (option = WF) (Note 3) -- -- 11 279.4 -- -- mil m * Bumped, sawed 8" wafer on frame (option = WFB) * Unsawed wafer (option = W) * Unsawed 8" bumped wafer (option = WB), (Note 3) Die backgrind thickness tolerance -- -- -- -- 1 25.4 mil m (Note 4) Die passivation thickness (multilayer) -- 0.9050 -- m (Note 5) Die Size: Die size X*Y before saw (step size) Die size X*Y after saw -- -- 55.79 x 59.57 54.22 x 58 -- -- mil mil -- -- Note 1: The bond pad size is that of the passivation opening. The metal overlaps the bond pad passivation by at least 0.1 mil. 2: Metal Pad Composition is 98.5% Aluminum with 1% Si and 0.5% Cu. 3: As the die thickness decreases, susceptibility to cracking increases. It is recommended that the die be as thick as the application will allow. 4: This specification is not tested. For design guidance only. 5: The Die Passivation thickness can vary by device depending on the mask set used. 6: The conversion rate is 25.4 m/mil. Notice: Extreme care is urged in the handling and assembly of die products since they are susceptible to mechanical and electrostatic damage. TABLE 1-6: PAD FUNCTION TABLE Name Ant. A Connected to external resonant circuit, (Note) Ant. B Connected to external resonant circuit, (Note) Vss Connected to external resonant circuit. Device ground during test mode, (Note) VDD DC voltage supply for programming CLK Main clock pulse for device VPRG Input/Output for programming and read test Note: DS21287D-page 14 Function See Figure 3-1 for the connection with external resonant circuit. 2001 Microchip Technology Inc. MCRF355/360 2.0 FUNCTIONAL DESCRIPTION 2.1.3 The device contains three major sections: (1) Analog Front-End, (2) Controller Logic and (3) Memory. Figure 2-1 shows the block diagram of the device. 2.1 Analog Front-End Section This section includes power supply, power-on-reset, and data modulation circuits. 2.1.1 POWER SUPPLY The power supply circuit generates DC voltage (VDD) by rectifying induced RF coil voltage. The power supply circuit includes high-voltage clamping diodes to prevent excessive voltage development across the antenna coil. 2.1.2 POWER-ON-RESET (POR) This circuit generates a power-on-reset when the tag first enters the reader field. The reset releases when sufficient power has developed on the VDD regulator to allow for correct operation. DATA MODULATION The data modulation circuit consists of a modulation transistor and an external LC resonant circuit. The external circuit must be tuned to the carrier frequency of the reader (i.e., 13.56 MHz) for maximum performance. The modulation transistor is placed between antenna B and Vss pads and has small turn-on resistance (RM). This small turn-on resistance shorts the external circuit between the antenna B and Vss pads as it turns on. The transistor turns on during the "High" period of the modulation data and turns off during the "Low" period. When the transistor is turned off, the resonant circuit resonates at the carrier frequency. Therefore, the external circuit develops maximum voltage across it. This condition is called uncloaking (tuned). When the transistor is turned on, its low turn-on resistance shorts the external circuit, and therefore the circuit no longer resonates at the carrier frequency. The voltage across the external circuit is minimized. This condition is called cloaking (detuned). The device transmits data by cloaking and uncloaking based on the on/off condition of the modulation transistor. Therefore, with the 70 kHz - Manchester format, the data bit "0" will be sent by cloaking (detuned) and uncloaking (tuned) the device for 7 ms each. Similarly, the data bit "1" will be sent by uncloaking (tuned) and cloaking (tuned) the device for 7 ms each. See Figure 2-2 for the Manchester waveform. FIGURE 2-1: BLOCK DIAGRAM ANALOG FRONT-END SECTION Power Supply VDD Power on Reset POR CONTROLLER LOGIC SECTION Column and Row Decoders Clock Generator Modulation Logic Modulation Modulation Pulse MEMORY SECTION Address CLK Pulse Column Drivers (High Voltage Circuit) Data Sleep Timer (anti-collision) Wake-up Signal Read/Write Logic Set/Clear 154-Bit Memory Array Test Logic VPRG and CLK 2001 Microchip Technology Inc. DS21287D-page 15 MCRF355/360 2.2 2.2.3 Controller Logic Section 2.2.1 This circuit generates a sleep time (100 ms 50%) for the anti-collision feature. During this sleep time (TOFF), the modulation transistor remains in a turned-on condition (cloaked) which detunes the LC resonant circuit. CLOCK PULSE GENERATOR This circuit generates a clock pulse (CLK). The clock pulse is generated by an on-board time-base oscillator. The clock pulse is used for baud rate timing, data modulation rate, etc. 2.2.2 SLEEP TIMER 2.2.4 READ/WRITE LOGIC This logic controls the reading and programming of the memory array. MODULATION LOGIC This logic acts upon the serial data (154 bits) being read from the memory array. The data is then encoded into Manchester format. The encoded data is then fed to the modulation transistor in the Analog Front-End section. The Manchester code waveform is shown in Figure 2-2. FIGURE 2-2: CODE WAVEFORMS Data DESCRIPTION WAVEFORM SIGNAL 1 0 1 1 0 0 0 1 1 0 1 0 Digital Data Internal Clock Signal CLK BIPHASE-L (Manchester) NRZ-L (Reference only) Biphase - Level (Split Phase) A level change occurs at middle of every bit clock period. "1" is represented by a high to low level change at midclock. "0" is represented by a low to high level change at midclock. Non-Return to Zero - Level "1" is represented by logic high level. "0" is represented by logic low level. Note: The CLK and NRZ-L signals are shown for reference only. BIPHASE-L (Manchester) is the device output. DS21287D-page 16 2001 Microchip Technology Inc. MCRF355/360 3.0 RESONANT CIRCUIT capacitor that is connected across the two inductors form a parallel resonant circuit to pick up incoming RF signals and also to send modulated signals to the reader. The first coil (L1) is connected between antenna A and B pads. The second coil (L2) is connected between antenna B and VSS pads. The capacitor is connected between antenna A and VSS pads. The MCRF355 requires external coils and capacitor in order to resonate at the carrier frequency of the reader. About one-fourth (1/4) of the turns of the coil should be connected between antenna B and VSS; remaining turns should be connected between antenna A and B pads. The MCRF360 includes a 100 pF internal resonant capacitor. Therefore, the device needs only external coils for the resonant circuit. For example, the device needs 1.377 H of inductance for the carrier frequency = 13.56 MHz. Figure 3-1(b) shows the resonant circuit formed by two capacitors (C1 and C2) and one inductor. Figure 3-1(c) shows a configuration of an external circuit for the MCRF360. By utilizing the 100 pF internal resonant capacitor, only L1 and L2 are needed for the external circuit. Figures 3-1 (a) and (b) show possible configurations of the external circuits for the MCRF355. In Figure 3-1 (a), two external antenna coils (L1 and L2) in series and a FIGURE 3-1: CONFIGURATION OF EXTERNAL RESONANT CIRCUITS 1 f 0 = ---------------------2 CL T Ant. A RF Carrier Interrogator MCRF355 C L1 Ant. B L2 Modulated RF Data Where: LT = L1 + L2 + 2LM LM = Mutual inductance between L1 and L2 VSS L1 > L2 (a) Ant. A RF Carrier C1 Interrogator 1 f 0 = ------------------------------------------C1C2 2 L ---------------------- C1 + C2 MCRF355 L Ant. B C2 Modulated RF Data VSS C1 > C2 (b) 1 f 0 = ----------------------------------------------------------- 12 2 ( L T ) ( 100x10 ) Ant. A RF Carrier L1 100 pF Interrogator Ant. B Modulated RF Data L2 VSS MCRF360 Where: LT = L1 + L2 + 2LM LM = Mutual inductance between L1 and L2 L1 > L2 (c) 2001 Microchip Technology Inc. DS21287D-page 17 MCRF355/360 4.0 DEVICE PROGRAMMING 4.3 1. MCRF355/360 is a reprogrammable device in contact mode. The device has 154 bits of reprogrammable memory. It can be programmed in the following procedure. (A programmer, part number PG103003, is also available from Microchip.) 4.1 3. 4. Programming logic is enabled by applying power to the device and clocking the device via the CLK pad while loading the mode code via the VPRG pad (See Examples 4-1 through 4-4 for test definitions). Both the CLK and the VPRG pads have internal pull-down resistors. 4.2 Apply VDDT voltage to VDD. Leave VSS, CLK, and VPRG at ground. Load mode code into the VPRG pad. The VPRG is sampled at CLK low to high edge. The above mode function (3.2.2) will be executed when the last bit of code is entered. Power the device off (VDD = VSS) to exit programming mode. An alternative method to exit the programming mode is to bring CLK logic "High" before VPRG to VHH (high voltage). Any programming mode can be entered after exiting the current function. 2. Programming Logic 5. 6. Pin Configuration Pin Timing 4.4 Connect antenna A, B, and VSS pads to ground. 1. 2. 3. Programming Mode Erase EE Code: Program EE Code: Read EE Code: Note: 4.5 0111010100 0111010010 0111010110 `0' means logic "Low" (VIL) and `1' means logic "High" (VIH). Signal Timing Examples 4-1 through 4-4 show the timing sequence for programming and reading of the device. EXAMPLE 4-1: CLK Number PROGRAMMING MODE 1: ERASE EE 1 2 3 4 5 6 7 8 9 10 11 CLK VHH... VPRG VIL VIH... TWC Note: Erases entire array to a `1' state between CLK and Number 11 and 12. DS21287D-page 18 2001 Microchip Technology Inc. MCRF355/360 EXAMPLE 4-2: PROGRAMMING MODE 2: PROGRAM EE CLK Number 1 2 ... 5 6 7 8 9 10 11 ... 165 CLK Pulse high to program bit to "0" VHH... VIL VPRG Leave low to leave bit at "1" VIH... TWC TWC Program bit #0 ... Program bit #153 Note: Pulsing VPRG to VHH for the bit programming time while holding the CLK low programs the bit to a `0'. EXAMPLE 4-3: PROGRAMMING MODE 3: READ EE 1 CLK Number 2 5 6 7 8 9 10 11 12 165 CLK VPRG VIH... VIL Turn off programmer drive during CLK high MCRF355 can drive VPRG. EXAMPLE 4-4: bit #0 bit #1 ... bit #153 data data data TIMING DATA THIGH TLOW CLK TPW:STO THD:DAT VPRG VHH... VIH VIL TAA TSU:STO TSU:DAT TWC VHH VIH... TSU:HH TDL:HH VIL 2001 Microchip Technology Inc. DS21287D-page 19 MCRF355/360 MCRF355/360 GUIDE PRODUCT IDENTIFICATION SYSTEM To order or obtain information, (e.g., on pricing or delivery), please refer to the factory or the listed sales office. MCRF355 - /WF Package: Temperature Range: Part Number: WF WFB W WB S SB SN P = = = = = = = = Sawed wafer on frame (8 mil backgrind) Bumped, sawed wafer on frame (8 mil backgrind) Wafer (11 mil backgrind) Bumped wafer (11 mil backgrind) Dice in waffle pack Bumped die in waffle pack 150 mil SOIC PDIP = -20C to +70C MCRF355 = 13.56 MHz Anti-Collision device MCRF360 = 13.56 MHz Anti-Collision device with 100 pF of on-chip resonance capacitance Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS21287D-page 20 2001 Microchip Technology Inc. M TB031 Microchip Development Kit Sample Format for the MCRF355/360 Devices Header 13 Bytes of User Data 111111111 0 16-Bit Checksum Customer 0 Byte 13 0 Byte 12 0 ... 0 Byte 2 0 Byte 1 0 Checksum 0 Checksum 0 Number 9 bit header 8 bit customer number 104 bits (13 x 8) of user data 17 bits of zeros between each byte, header, and checksum 16 bits of checksum Total: 154 bits Notes: * Users can program all 154 bits of the MCRF355/360. The array can be programmed in any custom format and with any combination of bits. * The format presented here is used for Microchip microIDTM Development System (DV103003) and can be ordered as production material with a unique customer number. * See TB032 for information on ordering custom programmed production material. * The Microchip Development System (DV103003) uses nine 1's (111111111) as header. * The preprogrammed tag samples in the development kit have hex 11(= 0001 0001) as the customer number. * For the development system, users can program the customer number (1 byte) plus the 13 bytes of user data, or they can deselect the "Microchip Format" option in the MicroIDTM RFLAB and program all 154 bits in any format. * When users program the samples using the MicroIDTM RFLAB, the RFLAB calculates the checksum (2 bytes) automatically by adding up all 14 bytes (customer number + 13 bytes of user data), and put into the checksum field in the device memory. See Example 1 for details. * When the programmed tag is energized by the reader field, the tag outputs all 154 bits of data. * When the demo reader detects data from the tag, it reports the 14 bytes of the data (customer number plus 13 bytes of user data) to the host computer if the header and checksum are correct. The reader does not send the header and checksum to the host computer. * The "MicroIDTM RFLab" or a simple terminal program such as "terminal.exe" can be used to read the reader's output (28 hex digits) on the host computer. * When the demo reader is used in the terminal mode (terminal.exe), the tag's data appear after the first two dummy ASCII characters (GG). See Example 2 for details. EXAMPLE-2: CHECKSUM Checksum (XXXXXXXX XXXXXXXX) = Byte 1 + Byte 2 + ......+ Byte 13 + Customer Number (1 byte) EXAMPLE-3: READER'S OUTPUT IN TERMINAL MODE ("TERMINAL.EXE") The demo reader outputs GG+28 hex digits, i.e., GG 12345678901234567890ABCDEFGF. The first two ASCII characters (GG) are dummy characters. The tag's data are the next 28 hex digits (112 bits) after the first two ASCII characters (GG). 2001 Microchip Technology Inc. DS91031C-page 21 TB031 NOTES: DS91031C-page 22 2001 Microchip Technology Inc. M TB032 Factory Programming Support (SQTPSM) INTRODUCTION If code files are compressed, they should be self-extracting files. The MCRF355 and MCRF360 are 13.56 MHz RF tags which can be contact programmed. The contact programming of the device can be performed by the user or factory-programmed by Microchip Technology, Inc. upon customer request. All 154 bits of data may be programmed in any format or pattern defined by the customer. The code files are used in alphabetical order of their file names (including letters and numbers). Used (i.e., programmed) code files are discarded by Microchip after use. Each line of the code file must contain one ID code for one IC. For factory programming, ID codes and series numbers must be supplied by the customer or an algorithm may be specified by the customer. This technical brief describes only the case in which identification codes (ID) and series numbers are supplied. The customer may supply the ID codes and series numbers on floppy disk or via email. The codes must conform to the Serialized Quick Turn ProgrammingSM (SQTPSM) format below: The code is in hexadecimal format. The code line is exactly 154 bits (39 hex characters, where the last 2 bits of the last character are don't cares). Each line must end with a carriage return. Each hexadecimal ID code must be preceded by a decimal series number. Series number and ID code must be separated by a space. FILE SPECIFICATION The series number must be unique and ascending to avoid double programming. SQTP codes supplied to Microchip must comply with the following format: The series numbers of two consecutive files must also count up for proper linking. The ID code file is a plain ASCII text file from floppy disk or email (no headers). FIGURE 1: EXAMPLE OF TWO SEQUENTIAL CODE FILES Filename FILE0000.TXT 00001 A34953DBCA001F261234567890ABCDEF0123457 00002 C4F55308B492A7831234567890ABCDEF012345B 00003 38FAC359981200B71234567890ABCDEF012345F " " 12345 9278256DCAFE87561234567890ABCDEF987654B Last Code ID Code Series Number Carriage Return Filename Next Code FILE0001.TXT 12346 EA43786937DCFB871234567890ABCDEF987654B 12347 459724FCA487ED241234567890ABCDEF9876547 " " Code File " " Space Necessary 2001 Microchip Technology Inc. DS91032A-page 23 TB032 NOTES: DS91032A-page 24 2001 Microchip Technology Inc. M MCRF450/451/452/455 MCRF450/451/452/455 Data Sheet FEATURES * * * * * * * * * * * * * * * * * * * Contactless read and write 1024 bits (32 blocks) of total memory 928 bits of user programmable memory User controlled write-protection of each block Manchester coding protocol with CRC for reading 70 kHz data rate RF field gaps and 1-of-16 PPM with CRC for writing High speed deterministic anti-collision algorithm for reading and writing virtually any number of tags in the same RF field Three pads for external antenna circuit (MCRF450, 451, 455) Two pads for external antenna (MCRF452) Internal resonance capacitors (MCRF451, 452, 455) Factory programmed unique 32-bit tag ID Interrogator talks first (ITF) or tag talks first (TTF) operation Fast and normal modes for data transmission Anti-tearing feature for secure write transactions Full 32-bit EAS support Very low power CMOS design Die, wafer, bumped wafer, PDIP or SOIC package options Asynchronous operation for low power/extended read range PACKAGE TYPES PDIP/SOIC ANT. A 1 8 VDD NC 2 7 FCLK ANT. B 3 6 NC CLK 4 5 VSS DESCRIPTION The MCRF45X is a contactless read/write passive RFID device that is optimized for 13.56 MHz RF carrier signal. The device needs an external LC resonant circuit to communicate with interrogator wirelessly. The device is powered remotely by rectifying an RF signal that is transmitted from the interrogator, and transmits or updates its contents of memory based on commands from the interrogator. The device is engineered to be used effectively for item level tagging applications such as retail and inventory management, where a large volume of tags are read and written in the same interrogator field. APPLICATION Read/Write Command Interrogator (Reader/Writer) Ant. A L Data MCRF452 VSS The device contains 32 blocks of EEPROM memory. Each block consists of 32 bits. The first three blocks (B0 - B2: 96 bits) are allocated for device operation, the remaining 29 blocks (B3 - B29: 928 bits) are for user data. The 928 (B3 - B31) user bits are contactlessly writable block-wise by interrogator commands. All blocks except bits 30 and 31 in block 0 are write-protectable. 2001 Microchip Technology Inc. DS40232C-page 25 MCRF450/451/452/455 The device has two operational modes depending on the conditions of talk first (TF) and fast read (FR) bits. These modes are: "tag talks first" (TTF) and "interrogator talks first" (ITF) modes. The device operates in TTF mode if both TF and FR bits are set. In this mode, the device transmits its fast read response data (96 bits in default) as soon as it is energized, and waits for the next commands. The device operates in the "interrogator talks first" mode, if the TF bit is cleared. In this mode, the device requires an interrogator command before it sends any data. The device uses an internal oscillator for data timing of the read operation. The data rate for reading is 70 kHz and uses Manchester format. The communication between the interrogator and the device takes place asynchronously. The interrogator sends commands to the device by amplitude modulating its RF carrier signal. 1-of-16 Pulse Position Modulation (PPM) and specially timed gap pulses are used for the modulation of the carrier signal. The device includes a detection circuit to detect these interrogator commands. To enhance the detection accuracy in the device, the interrogator sends a time reference signal (time calibration pulse) to the device followed by the command and programming data. The time reference signal is used to calibrate timing of the internal decoder of the device. Depending on the metal mask options, the device includes internal resonant capacitor between antenna A and VSS pads: (a) no internal resonant capacitor for the MCRF450, (b) 100 pF for the MCRF451, (c) two 50 pF in series (25 pF in total) for the MCRF452 and (d) 50 pF for the MCRF455. The internal resonant capacitor for each metal mask option is shown in Figures 1-2 through 1-5. The MCRF450 needs an external LC resonant circuit that is connected between antenna A, antenna B, and VSS pads. See Figure 1-2 for the external circuit configuration. The MCRF452 needs a single external antenna coil only between antenna A and VSS pads as shown in Figure 1-4. This external circuit along with the internal resonant capacitor must be tuned to the carrier frequency of the interrogator for maximum performance. The device sends data to the interrogator by turning on/ off the internal modulation transistor. This internal modulation transistor is located between antenna B and VSS. The modulation transistor has very small turn-on resistance between Drain (antenna B) and Source (VSS) terminals during its turn-on time. When the modulation transistor turns-on, the resonant circuit component between antenna B and VSS, that is in parallel with the modulation transistor, is shorted due to the low turn-on resistance. This results in a change of the LC value of the circuit. As a result, the circuit no longer resonates at the carrier frequency of the interrogator. Therefore, the voltage across the circuit is minimized. This condition is called cloaking. When the modulation transistor turns-off, the circuit resonates at the carrier frequency of the interrogator, and develops maximum voltage. This condition is called uncloaking. Therefore, the data is sent to the interrogator by turning-on (cloaking) and off (uncloaking) the modulation transistor. Therefore, the voltage amplitude of the carrier signal across the LC resonant circuit changes depending on the amplitude of modulation data (cloaking for logic "High" level and uncloaking for logic "Low" level). This is called amplitude modulation signal. The receiver channel in the Interrogator detects this amplitude modulation signal and reconstructs the modulation data for decoding. The device includes a unique anti-collision algorithm to be read or written effectively in multiple tag environments. To minimize data collision, the algorithm utilizes time division multiplexing of the device response. Therefore, each device can communicate with the interrogator in a different time slot. The devices in the interrogator's RF field remain in a non-modulating condition if they are not in the given time slot. This enables the interrogator to communicate with the multiple devices one at a time without data collision. The details of the algorithm are described in Section 4.0. To enhance data integrity for writing, the device includes an anti-tearing feature. This anti-tearing feature provides verification of data integrity for incomplete write cycles due to failed communication from the interrogator to the device during the write sequences. When a tag (device with the external LC resonant circuit) is brought to the interrogator's RF field, it develops an RF voltage across the external circuit. The device rectifies the RF voltage and develops a DC voltage (VDD). The device becomes functional as soon as VDD reaches the operating voltage level. DS40232C-page 26 2001 Microchip Technology Inc. MCRF450/451/452/455 1.0 ELECTRICAL CHARACTERISTICS TABLE 1-1: ABSOLUTE RATINGS Parameters Symbol Min. Max. Units IPP_AC -- 40 mA Peak-to-Peak coil current Coil current into coil pad Conditions Maximum power dissipation PMPD -- 0.5 W -- Ambient temperature with power applied TAMB -40 125 C -- TASM -- 300 C < 10 Sec TSTORE -65 150 C -- Assembly temperature Storage temperature Note: Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-2: DC CHARACTERISTICS All parameters apply across the specified operating ranges, unless otherwise noted. Parameters Commercial (C): TAMB = -20oC to 70oC Symbol Min. Typ. Max. Units VDDR 2.8 -- -- V VDD voltage for reading at 25C Operating current in normal mode IOPER_N -- 20 -- A VDD = 2.8V during reading at 25C Operating current in fast mode IOPER_F -- 45 -- A VDD = 2.8V during reading at 25C Writing current IWRITE -- 130 -- A At 25C, VDD = 2.8V Writing voltage VWRITE 2.8 -- -- VDC RM -- 3 5 Reading voltage Modulation resistance 2001 Microchip Technology Inc. Conditions At 25 C DC turn-on resistance between Drain and Source terminals of the modulation transistor at VDD = 2.8V DS40232C-page 27 MCRF450/451/452/455 TABLE 1-3: AC CHARACTERISTICS All parameters apply across the specified oper- Commercial (C): TAMB = -20oC to 70oC ating ranges, unless otherwise noted. Parameters Symbol Min. Typ. Max. Units FC 2 13.56 35 MHz (Note 1) Coil voltage during reading VPP_AC 4 -- -- VPP Peak-to-Peak AC voltage across the coil during reading (Note 1) Internal Resonant Capacitor CRES_100 85 100 115 pF Between Ant. A and VSS pads at 13.56 MHz and at 25C, MCRF451 Internal Resonant Capacitor CRES_2_50A 42.5 50 57.5 pF Between Ant. A and B pads at 13.56 MHz and at 25C, MCRF452 Internal Resonant Capacitor CRES_2_50B 42.5 50 57.5 pF Between Ant. B and VSS pads at 13.56 MHz and at 25C, MCRF452 Carrier frequency Conditions Internal Resonant Capacitor CRES_50 42.5 50 57.5 pF Between Ant. A and VSS pads at 13.56 MHz and at 25C, MCRF455 Coil detuning voltage VDETUNE -- TBD -- VPP Coil voltage at which the limiting circuit becomes active Interrogator data (ITD) rate_normal FITD_NORM -- 1.4286 -- kHz -- Interrogator data (ITD) rate_fast FITD_FAST -- 25 -- kHz -- FDVD 58 70 82 kHz Modulation depth of 1-of-16 PPM MDEPTH_PPM -- -- 100 % -- Pulse width of 1-of-16 PPM for normal mode PWPPM_N -- 175 -- s See Figure 4-2 and Table 4-7 for details. Pulse width of 1-of-16 PPM for fast mode PWPPM_F -- 10 -- s See Figure 4-2 and Table 4-7 for details. Symbol width of 1-of-16 PPM for normal mode SWPPM_N -- 2.8 -- ms -- Symbol width of 1-of-16 PPM for fast mode SWPPM_F -- 160 -- s -- Gap pulse width of Fast Read command GPW_FR -- 175 -- s See Figure 4-3 and Table 4-7 for details. TWRITE -- 5 -- ms Write time for a 32-bit block. TDECODE -- TBD -- s Time delay between end of command symbol and start of the device response. 2.5 2.925 ms -- Device data rate EEPROM (Memory) Writing Time Command Decode Time Time slot TSLOT Both normal and fast modes TLW TBD 1 TBD ms -- Modulation depth of Fast Read command MDEPTH_FRR -- -- 100 % -- Command Duration of Fast Read command (FRR and FRB) T_CMD_FRR -- 1.575 -- ms 175 s/pulse position x 9 pulse positions = 1.575 ms Listening Window Note 1: Not tested in production. DS40232C-page 28 2001 Microchip Technology Inc. MCRF450/451/452/455 TABLE 1-3: AC CHARACTERISTICS All parameters apply across the specified oper- Commercial (C): TAMB = -20oC to 70oC ating ranges, unless otherwise noted. Parameters Symbol Min. Typ. Max. Units Conditions Input impedance A Zin_A -- TBD -- Input impedance between antenna pad A and VSS, at 13.56 MHz with modulation transistor off (no external coils) Input impedance B Zin_B -- TBD -- Input impedance between antenna pad B and VSS, at 13.56 MHz with modulation transistor off (no external coils) Data retention -- 200 -- -- Years Endurance -- 1 -- -- Million At 25C Cycles For T < 120C Note 1: Not tested in production TABLE 1-4: PAD COORDINATES (MICRONS) Passivation Openings Lower Left X Lower Left Y Upper Right X Upper Right Y Pad Width Pad Height -853.50 -953.90 -764.50 -864.90 89.00 89.00 -809.00 -909.40 Ant. Pad B 759.50 -955.50 848.50 -866.50 89.00 89.00 804.00 -911.00 VSS 769.10 939.70 858.10 1028.70 89.00 89.00 813.60 984.20 VDD -839.50 83.70 -750.50 172.70 89.00 89.00 -795.00 128.20 CLK 721.10 116.00 810.10 205.00 89.00 89.00 765.60 160.50 FCLK -821.50 872.50 -732.50 961.50 89.00 89.00 -777.00 917.00 Pad Name Ant. Pad A Pad Pad Center X Center Y Note 1: All coordinates are referenced from the center of the die. The minimum distance between pads (edge to edge) is 10 mil. 2: Unsawed die size = 74.96 mil x 89.15 mil. 2001 Microchip Technology Inc. DS40232C-page 29 MCRF450/451/452/455 TABLE 1-5: DIE MECHANICAL DIMENSIONS Specifications Min. Typ. Max. Unit Comments Bond pad opening -- -- 3.5 x 3.5 89 x 89 -- -- mil m Note 1, Note 2 Die backgrind thickness -- -- 8 177.8 -- -- mil m Sawed 8" wafer on frame (option = WF) (Note 3) -- -- 11 279.4 -- -- mil m * Bumped, sawed 8" wafer on frame (option = WFB) * Unsawed wafer (option = W) * Unsawed 8" bumped wafer (option = WB), (Note 3) Die backgrind thickness tolerance -- -- -- -- 1 25.4 mil m Note 4 Die passivation thickness (multilayer) -- 0.9050 -- m Note 5 Die Size: Die size X*Y before saw (step size) Die size X*Y after saw -- -- 74.96 x 89.15 73.39 x 87.58 -- -- mil mil -- -- Note 1: The bond pad size is that of the passivation opening. The metal overlaps the bond pad passivation by at least 0.1 mil. 2: Metal Pad Composition is 98.5% Aluminum with 1% Si and 0.5% Cu. 3: As the die thickness decreases, susceptibility to cracking increases. It is recommended that the die be as thick as the application will allow. 4: This specification is not tested. For design guidance only. 5: The Die Passivation thickness can vary by device depending on the mask set used. 6: The conversion rate is 25.4 m/mil. Notice: Extreme care is urged in the handling and assembly of die products since they are susceptible to mechanical and electrostatic damage. DS40232C-page 30 2001 Microchip Technology Inc. MCRF450/451/452/455 FIGURE 1-1: MCRF450/451/452/455 DIE LAYOUT Top View y (Notch edge of wafer) 1679.6 1501.6 NC V SS (813.6, 984.2) (-777, 917) 734.7 699.8 1915.4 NC 1984.2 (765.6, 160.5) (-795, 128.2) NC 1471.6 x (0, 0) 948.6 982.5 (-809, -909.4) Ant. A (804, -911) 1524 Ant. B 1702 Die Size before Saw: 1904.00 m x 2264.4 m = 1.904 mm x 2.2644 mm = 74.96 mil x 89.15 mil Bond Pad Size: 89 m x 89 m = 0.089 mm x 0.089 mm = 3.5 mil x 3.5 mil Note: Units in the coordinate are in m. See Table 1.5 for Die Mechanical Dimension. 2001 Microchip Technology Inc. DS40232C-page 31 MCRF450/451/452/455 FIGURE 1-4: TABLE 1-6: MCRF452 PAD FUNCTION TABLE Name Ant. A NC Function MCRF452 Ant. Pad A Connected to antenna coil L1 Int. Res. Cap. Ant. Pad B Connected to antenna coils L1 and L2 (450/451/455), NC for 452 L Int. Res. Cap. Connected to antenna coil L2 Device ground during test mode, (Note 1) VSS NC NC Ant. B NC VSS Not connected, (Note 2) Internal Resonant Capacitor between Ant. A and Ant. B pads (CRES_2_50A) = 50 pF Note 1: Substrate = VSS 2: Leave floating or connect to VSS Internal Resonant Capacitor between Ant. B and Vss pads (CRES_2_50B) = 50 pF NC: FIGURE 1-2: Not connected L: MCRF450 Note: External Antenna Coil Substrate = VSS Total Internal Resonant Capacitance = 25pF Ant. A C NC NC MCRF450 L1 FIGURE 1-5: MCRF455 Ant. A L2 Ant. B NC NC NC VSS MCRF455 L1: External Antenna Coil A L2: External Antenna Coil B C: NC: Note: L1 Int. Res. Cap. External Capacitor L2 Not connected Ant. B NC VSS Substrate = VSS Internal Resonant Capacitor (CRES_50) = 50 pF FIGURE 1-3: MCRF451 Ant. A NC NC L1: External Antenna Coil A L2: External Antenna Coil B NC: Note: Not connected Substrate = VSS MCRF451 L1 L2 Int. Res. Cap. Ant. B NC VSS Internal Resonant Capacitor (CRES_100) = 100 pF L1: L2: NC: Note: DS40232C-page 32 External Antenna Coil A External Antenna Coil B Not connected Substrate = VSS 2001 Microchip Technology Inc. MCRF450/451/452/455 2.0 BLOCK DIAGRAM The device contains four major sections. They are: Analog Front-End, Detection/Encoding, Read/Write Anti-collision, and Memory sections. Figure 2-1 shows the block diagram of the device. 2.1 Analog Front-End Section This section includes high and low voltage regulators, power-on-reset, 70 kHz clock generator, and modulation circuits. 2.1.1 HIGH AND LOW VOLTAGE REGULATOR The high voltage circuit generates the programming voltage for the memory section. The low voltage circuit generates DC voltage (VDD) to operate the device. 2.1.2 The device transmits data by cloaking and uncloaking based on the on/off condition of the modulation transistor. Therefore, with the 70 kHz - Manchester format, the data bit "0" will be sent by cloaking and uncloaking the device for 7 s each. Similarly, the data bit "1" will be sent by uncloaking and cloaking the device for 7 s each. See Figure 4-1 for the Manchester waveform. 2.1.5 DETUNING CIRCUIT The purpose of this circuit is to prevent excessive RF voltage across the resonant circuit. This circuit monitors VDD and detunes the resonant circuit if the RF coil voltage exceeds the threshold limit (VDETUNE) which is above the operating voltage of the device. POWER ON RESET (POR) This circuit generates a power-on-reset voltage. The reset releases when sufficient power has been developed by the voltage regulator to allow for correct operation. 2.1.3 CLOCK GENERATOR This circuit generates a clock (CLK). The main clock is generated by an on-board 70 kHz time base oscillator. This clock is used for all timing in the device except for the fast mode PPM decoding. 2.1.4 DATA MODULATION The data modulation circuit consists of a modulation transistor and an resonant LC resonant circuit. The resonant circuit must be tuned to the carrier frequency of the interrogator (i.e., 13.56 MHz) for maximum performance. The modulation transistor is placed between antenna B and Vss pads, and is designed to result in the turn-on resistance of less than four ohms (RM). This small turnon resistance shorts the resonant circuit component between the antenna B and VSS pads as it turns on. This results in a change of the resonant frequency of the resonant circuit. As a result, the resonant circuit becomes detuned to the carrier frequency of the interrogator. The voltage across the resonant circuit is minimized during this time. This condition is called "cloaking". The transistor, however releases the resonant circuit as it turns off. Therefore, the resonant circuit tunes to the carrier frequency of the interrogator again, and develops maximum voltage. This condition is called "uncloaking". 2001 Microchip Technology Inc. DS40232C-page 33 MCRF450/451/452/455 FIGURE 2-1: BLOCK DIAGRAM DETECTION/ENCODING SECTION ANALOG FRONT-END SECTION External Antenna Circuit High/Low Voltage Regulator MEMORY SECTION High Voltage (HV) From High Voltage Regulator Memory Array Demodulator (Detector) To Memory (High Voltage) VDD PPM Decoder Fast Mode Oscillator Detuning Circuit VDD Command Decoder Registers Power on Reset (POR) CRC/Parity Generator and Checker To Anti-collision Command Controller (VDD) Clock Generator Data Encoder Main Clock Modulation READ/WRITE ANTI-COLLISION SECTION VDD from POR Anti-Collision Command Controller Time Slot Counter FIGURE 2-2: Data CLK NRZ - L (Reference only) DS40232C-page 34 (TC, TSMAX, Tag ID) DATA WAVEFORM OF DEVICE DESCRIPTION WAVEFORM SIGNAL BIPHASE - L (Manchester) Time Slot Generator 1 0 1 1 0 0 0 1 1 0 1 0 Digital Data Internal Clock Signal Non-Return to Zero - Level "1" is represented by logic high level. "0" is represented by logic low level. Biphase - Level (Split Phase) A level change occurs at middle of every bit clock period. "1" is represented by a high to low level change at midclock. "0" is represented by a low to high level change at midclock. 2001 Microchip Technology Inc. MCRF450/451/452/455 3.0 DETECTION AND ENCODING SECTION 2. This section encodes data with the Manchester format and also detects commands from the interrogator. 3.1 Demodulator (Detector) This circuit demodulates the interrogator commands, and sends them to the Pulse Position Modulation (PPM) decoder. 3.2 Fast Mode Oscillator This oscillator generates a clock that is used for decoding fast mode commands. 3.3 PPM Signal Decoder This section decodes the PPM signals, and sends the results to both the command decoder and CRC/parity checker. 3.4 Command Decoder This section decodes the interrogator commands and sends the results to the anti-collision/command controller. 3.5 3. 3.6 Special Case 1: When reading block 0 or 2, a calculated CRC (CCRC) is sent. This is because both the TF and FR bits in the block 0 are nonwrite-protectable while the rest of the bits in the block are write-protectable. This means the stored CRC (SCRC) in the block no longer represents the CRC of the block data if only the TF or the FR bit is reprogrammed. This is also true for block 2 which is a write-protection block: The write-protected bit can not be reprogrammed once it has been written. Therefore, the stored CRC in these blocks (0 and 2) are not used. Instead, the device calculates the current CRC of the block and sends it to the interrogator. Special Case 2: For the Fast Read (FR) response (this is the device response to an FRR command), bits 0-15 (FRR_CRC) in block 0 are sent as the CRC of the fast read field (FRF: blocks 3-5). See Table 4-3 for device responses. Data Encoder This section multiplexes serial data, encodes it into Manchester format, and sends it to the modulation circuit. See Figure 2-2 for the Manchester waveform. CRC/Parity Generator and Checker This section generates CRC and parity bits for transmitting and receiving data. The device utilizes a 16-bit cyclic redundancy code (CRC) for error detection. Its polynomial and initial values are: CRC Polynomial: X16+X12+X5+X0 Initial Value: $FFFF This polynomial is also known as CRC CCITT (Consultative Committee for International Telegraph and Telephone). The interrogator also uses the same CRC for data processing. The device uses the CRC in the following ways: 1. Normal case: The interrogator will send a write command with CRC. When the device receives the command, it checks the CRC prior to any processing. If it is a correct CRC, the device programs the block data and also stores the CRC in the EEPROM. As soon as the data is written in the memory, both the programmed data and stored CRC (SCRC) are sent back to the interrogator as a verification. The device also sends both the programmed data and stored CRC (SCRC) when as a response to the read command. If the CRC is incorrect, the device ignores the incoming message (does not respond to the interrogator) and waits for the next command with a correct CRC. 2001 Microchip Technology Inc. DS40232C-page 35 MCRF450/451/452/455 4.0 READ/WRITE ANTI-COLLISION LOGIC 4. This section includes the anti-collision algorithm of the device, and consists of the anti-collision/command controller, the time slot counter, and the time slot generator. 4.1 Figure 4-1 shows the anti-collision algorithm flowchart, which consists of four control loops. They are: Detection, Processing, Sleeping, and Reactivation loops. All devices in the interrogator's RF field are controlled by five different commands and internal control flags. The interrogator commands are: 1. 2. 3. The matching code (MC1 and MC2) command consists of 12 bits (or 3 symbols). The first 8 bits (or the first two symbols) are selected from the 32bit Tag ID. The next 4 bits (or the 3rd symbol) determine the matching code type (3 bits) and a parity bit (see Section 4.2.3.6). The command lasts for about 11.2 ms including the time calibration pulses. Description of Algorithm The read and write anti-collision algorithm is based on time division multiplexing of tag responses. Each device is allowed to communicate with the interrogator in its time slot only. When not in its assigned time slot, the device remains in a non-modulating condition. This enables the interrogator to communicate with other devices in the same interrogator field with fewer chances of data collision. Fast Read Request (FRR): If the TF bit of the device is cleared, then it will respond to only this command from the interrogator. This command consists of five specially timed gap pulses. See Figs. 4-3 to 4-8. The position of the five gap pulses in the given time span (1.575 ms) determines the parameters of the command. The command has three parameters: TCMAX, TSMAX, and Data transmission speed. The details of these parameters will be discussed in the following sections. If the device receives the FRR command, it sends the fast read (FR) response (96 bits in default) and then listens for 1 ms (TLW) for a matching code from the interrogator. Fast Read Bypass (FRB): This command is used in the Reactivation loop. This command is only applicable to a device with the fast read bit (FR bit: bit 31 in block 0) cleared. The device responds with 64 bits of data which includes block 1 data (32-bit Tag ID), and then listens for 1 ms (TLW) for a matching code from the interrogator. The command structure is the same as the FRR command: Five specially timed gap pulses (1.575 ms). The command parameter (see Figure 4-8) determines the data rate (normal speed or fast speed) of subsequent interrogator commands. Matching Code 1 (MC1): This command consists of time calibration pulses (TCP) followed by 1-of-16 PPM signals. It is used when the device does not need any further processing. This MC1 command causes a device which is in the Detection loop to enter the Sleeping loop. DS40232C-page 36 Matching Code 2 (MC2): The command structure is the same as MC1: TCP followed by 1-of16 PPM signals. The command is used when the device needs further processing (read/ write). The device enters the Processing Loop if it receives this command in the Detection Loop. 5. End Process (EP): This command consists of the time reference pulses followed by 1-of-16 PPM signals. The EP command causes a device to exit the Processing loop and enter the Sleeping loop. 4.1.1 DETECTION LOOP The device can enter this loop in two ways if the fast read (FR: bit 31 of block 0) bit is set. The two ways depend on the condition of the talk-first (TF: bit 30 of block 0) bit. They are: (1) If the TF bit is cleared, the device enters this loop and waits for a fast read request (FRR) command. This is called "interrogator talks first" (ITF) mode. (2) If the TF bit is set, the device enters this loop by transmitting the fast read (FR) response without waiting for an FRR command. This case (2) is called "tag talks first" (TTF) mode. For case (1) above, the parameters of the FRR are: (a). Maximum number of time slots (TSMAX=1, 16, or 64), (b). Maximum transmission counter (TCMAX = 1, 2, or 4), and (c). Data transmission speed (normal or fast mode). The purpose of the TCMAX and TSMAX parameters is to acknowledge the device in the Detection loop as fast as possible. TSMAX represents the maximum number of time slots between the end of the FRR command and the beginning of the fast read (FR) response. One time slot (TSLOT) represents 2.5 ms. For example, TSMAX = 64 represents a maximum of 160 ms of time delay before sending the FR response. See Section 4.2.4 for the calculation of actual time delay. TCMAX represents the maximum number of fast read (FR) responses a device can send after an FRR command. For example, TCMAX = 4 means the device can send its FR response four times (after the FRR command) for acknowledgment (matching code). The TSMAX and TCMAX values are determined by the interrogator's decision on how many tags are in the field. The interrogator may assign TSMAX = 1 and TCMAX = 1 assuming there is only one tag in the field. The efficiency of the detection will increase in multiple 2001 Microchip Technology Inc. MCRF450/451/452/455 tag environments by assigning a higher number to both the TSMAX and TCMAX. If the device receives the FRR, it clears the Position 1 flag, waits for its time slot and replies with the fast read (FR) response and then listens for 1 ms. The FR response consists of a maximum of 160 manchester data bits (default: 96 bits, see Table 4-3 and Example 7-1) which includes the 32-bit Tag ID and the fast read field data (blocks 3-5). TABLE 4-1: CONDITIONS FOR TCMAX = ELAPSED FOR ITF MODE Rolling Modulo -8 TC TCMAX =1 TCMAX =2 TCMAX =4 To acknowledge the FR response, the interrogator can start to send a matching code (MC) during the device's 1 ms listening window (TLW). The MC is encoded with 1-of-16 PPM signal. See Figure 4-9 for the 1-of-16 PPM signal. The MC1 is given to the device if the device does not need any further processing. If the device receives the MC1, it enters the Sleeping loop and stays in the loop in a non-modulating condition. The MC2 command is given to the device if further processing (read/write) is required. If the device receives the MC2 command, it enters the Processing loop. 0 0 1 elapsed -- -- 0 1 0 elapsed elapsed -- 0 1 1 elapsed -- -- 1 0 0 elapsed elapsed elapsed 1 0 1 elapsed -- -- 1 1 0 elapsed elapsed -- 1 1 1 elapsed -- elapsed 0 0 0 elapsed elapsed -- If the device misses the MC within the listening window, it sends the FR response again after its time slot if two conditions are met: (1) Position 1 flag is cleared and (2) TCMAX has not elapsed. The device checks the condition (elapsed or not elapsed) of TCMAX using an internal transmission counter (TC). The transmission counter (TC) consists of 3 bits. If the Position 1 flag is cleared, the device increments the TC by 1 each time it does not receive a MC during its listening window. See the flow chart in Figure 4-1 for the conditional increment of the transmission counter. Table 4-1 shows an example of detecting the elapsed TCMAX using a rolling modulo-8 transmission counter. 4.1.2 For the TTF case, the device repeats its FR response according to the TCMAX and TSMAX parameters as specified in Table 5-5. Even though the device is operating in TTF mode, it will respond to its correct MC during its listening window. If TCMAX = 1, 2 or 4, it will also respond to FRR commands just as in the ITF case (see Section 4.1.1.1). 4.1.1.1 Matching Code Queuing Once the device receives the FRR command, it sends the FR response and waits for a matching code (MC) during its listening window. If the device does not receive its correct MC code before its TCMAX has elapsed (see Table 4-1), it goes back to the beginning of the Detection loop (position 1 in the loop), and waits for either a new FRR command or matching code (MC1 or MC2). This is called "matching code queuing". In this queuing, the device stays in the Detection loop waiting for an interrogator command (FRR or MC). This queuing takes place within the Detection loop and is controlled by the conditions of Set Position 1 Flag and TCMAX. This queuing allows the interrogator to communicate with a device outside its listening window. The result is enhanced and accelerated processing of individual devices in a multiple tag environment. 2001 Microchip Technology Inc. PROCESSING LOOP The reading and writing processes take place in this loop. Devices in this loop are waiting for commands for processing. In order to read from or write to the device, its "Processing Flag" (PF) must be set. Any device entering this loop with its PF cleared is called a followalong tag. This follow-along tag in the loop is not processed for reading or writing. If the device with PF set receives the End process (EP) command, it exits this loop and enters the Sleeping loop. However, the same EP command sends the follow-along tag back to the Detection loop. If the device receives the FRR or FRB command in this loop, it sees the command as invalid, resets itself, and goes back to the initial power up state. 4.1.3 SLEEPING LOOP This loop is used to keep all processed devices in a "silent" condition. The devices stay in this loop in a nonmodulating condition as long as they remain in the field. 4.1.4 REACTIVATION LOOP This loop is used to process a device with its fast read (FR) bit cleared. A device in this loop waits for the fast read bypass (FRB) command. If a device receives the FRB, it transmits the contents of block 1 (Tag ID) in its memory and waits for matching code 2 (MC2) in its listening window. If the device in this loop receives matching code 2 (MC2), it leaves this loop and enters the Processing loop. This reactivation loop has no anticollision capability; it is designed for reactivation of single devices. This loop can be effectively used in retail store applications to process returning items from customers. DS40232C-page 37 MCRF450/451/452/455 FIGURE 4-1: ANTI-COLLISION FLOW CHART No Power Up in Tuned State SleepID=TagID TC=0. Set Processing Flag Yes FR Bit Set ? Talk-First Bit Set? No No No PPM Symbol? FRR? No 1 Yes TC > 0? Yes Yes Yes Clear Position 1 Flag Set Position 1 Flag Listen for FRBypass Decode FRRequest No FRB Received? Wait 1.16/64 Yes Read Back Block 1 Send FRResponse No Yes Listening Window Expire? Listening Window Expire? REACTIVATION No No Receiving? No 3rd Symbol =MC2? DETECTION 3 PPM Symbols? Yes No Increment Transmission Counter Receiving? No No 3 PPM Symbols? Correct Matching Code? Yes Position 1 Flag Set? Yes No 3rd Symbol =MC2? Yes Yes Clear Processing Flag Correct Matching Code? Wait for Commands No Correct Matching Code? Yes PROCESSING Yes Decode Command at Correct Speed No No Processing Flag Set? Yes No 3rd Symbol =MC1? Execute Command Yes Yes Yes No TCMAX ELAPSED ? No Yes No Yes No Yes Set Processing Flag Valid Command? Yes Yes Read or Write Command? No No No End Command? Yes Processing Flag Set? Maintain Logic State Yes SLEEPING DS40232C-page 38 2001 Microchip Technology Inc. MCRF450/451/452/455 4.2 Anti-Collision Command Controller This section manages the anti-collision algorithm and establishes the communications between the interrogator and device. 4.2.1 STRUCTURE OF READ/ WRITE COMMAND SIGNALS The interrogator's read/write commands have the following structure: Read/Write command = Command + Address + Data + Parity (or CRC) The commands are summarized in the table below: TABLE 4-2: READ/WRITE COMMANDS FROM INTERROGATOR TO DEVICE Interrogator Command Command Code Address Data Unused 00X xxxxx -- -- -- Read 32-bit block 110 aaaaa -- Parity 3 symbols Unused 111 00xxx -- -- -- Unused 111 0100x -- -- -- End Process 111 01010 -- Parity 3 symbols Unused 111 01011 -- -- -- Unused 111 011xx -- -- -- Unused 111 1000x -- -- -- Set Talk First Bit 111 10010 -- Parity 3 symbols Set FR Bit 111 10011 -- Parity 3 symbols Clear Talk First Bit 111 10100 -- Parity 3 symbols Clear FR Bit 111 10101 -- Parity 3 symbols Unused 111 1011x -- -- -- Unused 111 11xxx -- -- -- Unused 100 xxxxx -- -- -- Write 32-bit block 101 aaaaa 32 bits CRC-16 14 symbols Unused 01x xxxxx -- -- -- Legend: Parity or CRC Symbol Length aaaaa = Block address x = don't care Command and address are sent MSN (most significant nibble) first Data and parity/CRC are sent LSN (least significant nibble) first. 2001 Microchip Technology Inc. DS40232C-page 39 MCRF450/451/452/455 4.2.2 STRUCTURE OF DEVICE RESPONSE When the device receives the interrogator command, it responds with 70 kHz - Manchester encoded data having the following structures: For blocks 0 and 2: Device Response = Preamble (8 bits) + Block Number (5 bits) + "000" + Block Data (32 bits) + Calculated CRC (CCRC: 16 bits) For all other blocks: Device Response = Preamble (8 bits) + Block Number (5 bits) + "000" + Block Data (32 bits) + Stored CRC (SCRC: 16 bits) TABLE 4-3: INTERROGATOR COMMANDS AND DEVICE RESPONSES Interrogator Command Delay Device Response Read 32-bit block for block 0 and block 2 TDECODE Preamble, block #, "000", block data, CCRC Read 32-bit block except for block 0 and block 2 TDECODE Preamble, block #,"000", block data, SCRC Write 32-bit block TWRITE For blocks 0 and 2: Preamble, block #, "000",block data, CCRC For all others: Preamble, block #, "000", block data, SCRC Set Fast Read (FR) bit TWRITE Preamble, 1 byte 0's, block 0 data, CCRC Clear Fast Read (FR) bit TWRITE Preamble, 1 byte 0's, block 0 data, CCRC Set Talk First (TF) bit TWRITE Preamble, 1 byte 0's, block 0 data, CCRC TWRITE Preamble, 1 byte 0's, block 0 data, CCRC Clear Talk First (TF) bit End Process (EP) TDECODE FRR f(TSMAX, TCMAX, 8-bit Tag ID) FRB TDECODE Preamble Preamble,TC, TP, "0", Tag ID, FRF, FRR_CRC (bits 0-15 in block 0) (maximum of 160 data bits) Preamble, address of block #1(00001),"000", Tag ID (32 bits), SCRC (64 data bits) References used in this table. Examples are given in Section 7.0. Preamble = 11111110 (8 bits)."0" is transmitted last. Block # = 5 bit addressed block, transmits LSB (least significant bit) first. Block data = 32-bit data of the addressed block, transmits LSB first. CCRC = Calculated CRC of the preceding block number and block data. Transmits LSB first. SCRC = Stored CRC. This SCRC is the CRC of the write command, address, and data from the interrogator, LSB first. The device stores the CRC of the command for each block. See Section 5.2 for details. TP = Tag parameters (4 bits: "0", DF0, DF1, parity). where DF0 and DF1 determine the FR field length (see Table 5-6). TC = Transmission counter (3 bits), transmits LSB first. Parity = Even parity bit of TC and TP. Tag ID = 32 bits of unique identification code of the device, transmits LSB first. This Tag ID is preprogrammed in the factory prior to shipping. 8-bit Tag ID = 8 bits of Tag ID selected from the 32 bits of the unique tag identification code. Transmits LSB first (see Section 4.2.3.6 for selecting the 8 bits from the Tag ID). FRF = Fast Read Field (blocks 3-5), transmits LSB first (see Section 5.0). f(TSMAX, TCMAX, 8-bit Tag ID = Delay is a function of the TSMAX, TCMAX and 8-bit Tag ID. TWRITE = Writing time for EEPROM (see Table 1-3). FRR_CRC = CRC of 32-bit Tag ID first followed by fast read field (FRF) data. TDECODE = Time requirement for command decoding (see Table 1-3). DS40232C-page 40 2001 Microchip Technology Inc. MCRF450/451/452/455 4.2.3 DETECTION OF INTERROGATOR COMMANDS The interrogator sends commands to the device by amplituding modulating the carrier signal (gap pulse). The interrogator uses two classes of encoding signals for modulation. They are (a) 1-of-16 PPM for data transmission, and (b) specially timed gap pulse sequence for the fast read commands (FRR and FRB). The fast read commands consist of five gap pulses within nine possible gap pulse positions (1.575 ms). The combination of the possible gap positions determines the command type and parameters of the fast read command. The interrogator also sends time calibration pulses (TCP) prior to the 1-of-16 PPM. The TCP is used to calibrate the time base of the decoder in the device. The specifics of the two encoding methods and the TCP are described in the following sections. 4.2.3.1 FAST READ COMMANDS The fast read commands are composed of five 175 swide gap pulses (see Figure 4-2) whose spacing within 1.575 ms determines the command type and its parameters. Table 4-4 shows the specification of the gap signal for the fast read commands. Two commands are used for the fast read. They are: (1) Fast Read Request (FRR) in the Detection loop, and (2) Fast Read Bypass (FRB) in the Reactivation loop. See Tables 4-5 and 46 for the FRR gap pulse positions and also Figures 4-3 to 4-8 for the gap modulation patterns. TABLE 4-4: The parameters of FRR are (1) number of time slots (TSMAX = 1,16,or 64), (2) max transmission counter (TCMAX), and (3) data transmission speed. The FRB has only a data transmission speed parameter (normal or fast speed mode). The device extracts these parameters based on the positions of the five gap pulses within the 1.575 ms time span as shown in Figures 4-3 to 4-8. TSMAX=1 is given if there is only one device in the field. This is called "conveyor mode" or "single tag environment". In this mode, the device responds with the FR response signal in every time slot until it receives a correct matching code, or until TCMAX is elapsed. 4.2.3.2 DATA TRANSMISSION SPEED The interrogator can send data with two different data rates: (1) Normal and (2) Fast speed modes. The normal speed uses 2.8 ms/symbol, and the fast speed uses 160 s/symbol. One symbol represents one 4-bit data packet (see Section 4.2.3.4 for 1-of-16 PPM). The data transmission speed is a parameter of the fast read commands (FRR and FRB). This parameter indicates the data speed of subsequent interrogator commands. The data rate of the device output (70 kHz) is not affected by this parameter. SPECIFICATION OF GAP SIGNAL FOR FAST READ COMMANDS (FRR AND FRB) Number of gaps for one command Total available number of gap positions within the command time span Command time span Gap pulse width 2001 Microchip Technology Inc. 5 9 1.575 ms 175 s DS40232C-page 41 MCRF450/451/452/455 TABLE 4-5: SPECIFICATION OF MODULATION SEQUENCE FOR FAST READ REQUEST (FRR) Maximum Time Slot (TSMAX) TCMAX Gap Pulse Position Data Transmission Mode 1 (1,2,3,4,6) Normal Speed (1,3,5,6,8) Fast Speed (1,2,3,4,5) Normal Speed (1,3,5,6,7) Fast Speed (1,2,3,5,6) Normal Speed (1,3,5,7,8) Fast Speed (1,2,4,6,8) Normal Speed (1,3,4,6,8) Fast Speed (1,2,4,6,7) Normal Speed (1,3,4,6,7) Fast Speed (1,2,4,5,6) Normal Speed (1,3,4,5,6) Fast Speed (1,2,4,5,7) Normal Speed (1,3,4,5,7) Fast Speed 2 1 4 1 2 16 4 64 1 TABLE 4-6: SPECIFICATION OF MODULATION SEQUENCE FOR FRB COMMAND Symbol Gap Pulse Position Data Transmission Mode FRB_N (1,2,3,5,7) Normal Speed FRB_F (1,3,5,7,9) Fast Speed DS40232C-page 42 2001 Microchip Technology Inc. MCRF450/451/452/455 FIGURE 4-2: PULSE WAVEFORM OF GAP AND 1-OF-16 PPM SIGNALS 100% 95% 50% 5% 0% td1 t t2 t1 t4 t3 t5 td2 t6 t7 t8 TABLE 4-7: WAVEFORM CHARACTERISTICS OF GAP AND 1-OF-16 PPM SIGNALS Signal Gap signal and 1-of-16 PPM for normal mode 1-of-16 PPM for fast mode Symbol Min. Typ. Max. Unit Conditions td1 -- 25 -- s -- td2 -- 25 -- s -- t1 0 12.5 -- s -- t2 0 12.5 -- s -- t3 -- 75 -- s -- t4 0 12.5 -- s -- t5 0 12.5 -- s -- t6 -- 100 -- s PWPPM_N t7 -- 125 -- s -- t8 -- 175 -- s -- td1 -- 1.25 -- s -- td2 -- 1.25 -- s -- t1 0 0.75 -- s -- t2 0 0.75 -- s -- t3 -- 4.5 -- s -- t4 0 0.75 -- s -- t5 0 0.75 -- s -- t6 -- 6 -- s PWPPM_F t7 -- 7.5 -- s -- t8 -- 10 -- s -- 2001 Microchip Technology Inc. DS40232C-page 43 MCRF450/451/452/455 The following figures show the various modulation patterns of the fast read commands (FRR and FRB). Each command consists of a combination of five gap pulses within nine possible gap positions. The pulse width of each gap is 175 s and the total time span of each command for the nine possible positions is 1.575 ms (175 s x 9 = 1.575 ms). FIGURE 4-3: In the figures, Pmn represents mth gap pulse at nth gap position in the given data packet (symbol). GAP MODULATION PATTERNS FOR FRR, NORMAL SPEED, TSMAX = 1 (s) 1 0.5 (A) TCMAX = 1 P11 P22 P33 P44 P56 0 600 400 200 800 1000 1600 1400 1200 (s) 1 (B) TCMAX = 2 0.5 P11 P22 P33 P44 P55 0 800 600 400 200 1000 1600 1400 1200 (s) 1 (C) TCMAX = 4 0.5 P11 P22 P33 P45 P56 800 1000 0 200 FIGURE 4-4: 400 600 1400 1200 1600 GAP MODULATION PATTERNS FOR FRR, FAST SPEED, TSMAX = 1 (s) 1 (A) TCMAX = 1 0.5 P11 P23 P35 P46 800 1000 P58 0 200 400 600 1400 1200 1600 (s) 1 (B) TCMAX = 2 0.5 P11 P23 P35 P46 800 1000 P57 0 200 400 600 1400 1200 1600 (s) 1 (C) TCMAX = 4 0.5 P11 P23 P35 P47 P58 0 200 DS40232C-page 44 400 600 800 1000 1200 1400 1600 2001 Microchip Technology Inc. MCRF450/451/452/455 FIGURE 4-5: GAP MODULATION PATTERNS FOR FRR, NORMAL SPEED, TSMAX = 16 (s) 1 (A) TCMAX = 1 0.5 P11 P22 P34 P46 P58 0 200 600 400 800 1000 1200 1600 1400 (s) 1 (B) TCMAX = 2 0.5 P11 P22 P34 P46 P57 0 200 600 400 800 1000 1200 1600 1400 (s) 1 (C) TCMAX = 4 0.5 P11 P22 P34 P45 P56 800 1000 0 200 FIGURE 4-6: 600 400 1200 1600 1400 GAP MODULATION PATTERNS FOR FRR, FAST SPEED, TSMAX = 16 (s) 1 (A) TCMAX = 1 0.5 P11 P23 P34 P46 P58 0 200 400 600 800 1000 1200 1600 1400 (s) 1 (B) TCMAX = 2 0.5 P11 P23 P34 P46 P57 0 200 400 600 800 1000 1200 1600 1400 (s) 1 (C) TCMAX = 4 0.5 P11 P23 P34 P45 P56 800 1000 0 200 FIGURE 4-7: 400 600 1200 1600 1400 GAP MODULATION PATTERNS FOR FRR, TSMAX = 64, TCMAX = 1 (s) 1 (A) NORMAL SPEED 0.5 P11 P22 P34 P45 P57 0 200 400 600 800 1000 1200 1400 1600 (s) 1 (B) FAST SPEED 0.5 P11 P23 P34 P45 P57 0 200 2001 Microchip Technology Inc. 400 600 800 1000 1200 1400 1600 DS40232C-page 45 MCRF450/451/452/455 FIGURE 4-8: GAP MODULATION PATTERNS FOR FRB (FAST REQUEST BYPASS) (s) 1 (A) NORMAL SPEED 0.5 P11 P23 P33 P45 P57 0 200 800 600 400 1000 1600 1400 1200 (s) 1 0.5 (B) FAST SPEED P11 P23 P35 P47 P59 0 200 4.2.3.3 800 600 400 1000 1600 1400 1200 USAGE OF TSMAX AND TCMAX The parameters of the TSMAX and TCMAX are determined by an expected number of tags in the Detection Loop. The following table shows the recommended FRR command repeat time for each of the 7 possible combinations of TSMAX and TCMAX. The command repeat time in Table 4-8 is calculated by: Command Repeat Time = TSMAX x TCMAX x 2.5ms x 1.17 where: 1.17 is related to the tolerance of the baud rate. TABLE 4-8: FRR COMMAND REPEAT TIME VS. (TSMAX, TCMAX) (TSMAX,TCMAX) (1,1) (1,2) (1,4) (16,1) (16,2) (16,4) (64,1) Command Repeat Time 2.925 ms 5.85 ms 11.7 ms 46.8 ms 93.6 ms 187.2 ms 187.2 ms 4.2.3.4 (TCP) composed of three pulses in positions zero, six and fourteen of a 1-of-16 PPM symbol as shown in Figure 4-10. 1-OF-16 PPM The interrogator uses 1-of-16 Pulse Position Modulation (PPM) for matching codes (MC1 and MC2), End Process (EP), and also commands in Table 4-2. 1-of16 PPM uses only one gap pulse in one of sixteen possible pulse positions for sending 4-bit symbols (24=16). This means one symbol (one data packet) represents 4 bits of binary data. One symbol lasts for 2.8 ms and 160 s for normal speed and fast speed mode, respectively. All communications begin with time calibration pulses TABLE 4-9: 1-OF-16 PPM PULSE SPECIFICATIONS Normal Mode Fast Mode Modulation depth 100% 100% Pulse width 175 s 10 s Gap width 100 s 6 s 16 16 Pulse positions per symbol Symbol width Calibration sequence DS40232C-page 46 2.8 ms 160 s Pulses in positions 0,6,14 Pulses in positions 0,6,14 2001 Microchip Technology Inc. MCRF450/451/452/455 FIGURE 4-9: Hex Value 0 1-OF-16 PPM REPRESENTATION FOR HEX VALUES FOR NORMAL SPEED MODE 175 350 525 700 875 1050 1225 1400 4 5 6 7 8 1575 1750 1925 2100 (s) 2450 2675 2800 2275 PWPPM_N "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" Gap Position Order 0 1 2 2001 Microchip Technology Inc. 3 9 10 11 12 13 14 15 DS40232C-page 47 MCRF450/451/452/455 4.2.3.5 CALIBRATION OF TIME REFERENCE FOR DECODING The device uses time calibration pulses (TCP) to match its internal decoder timing to the interrogator timing. The interrogator transmits the timing pulses at the start of all commands and at least every 17 symbols. The TCP uses a code violation of the 1-of-16 PPM signal consisting of three gap pulses within one symbol. The first gap pulse is located at position 0, the second gap pulse at position 6, and the third at position 14 of the symbol. The time period between the last two gap pulses is used to calibrate the device's timing for decoding. Figure 4-10 shows the calibration pulses for normal speed mode. The waveform of the gap pulses is the same as the 1-of-16 PPM signal as shown in Figure 4-2. For the fast speed mode, the gap positions are the same. PWPPM_F is the gap pulse width and SWPPM_F is the symbol width of the fast mode. FIGURE 4-10: CALIBRATION PULSES FOR NORMAL SPEED MODE (ms) PWPPM_N PWPPM_N PWPPM_N 1 Calibration Time Reference 0.5 0 0 500 Position 0 DS40232C-page 48 1000 1500 Position 6 2000 2500 3000 Position 14 2001 Microchip Technology Inc. MCRF450/451/452/455 4.2.3.6 CALCULATION OF MATCHING CODE When the interrogator receives the FR response from a device, it sends a matching code (MC) to select the device. The MC is sent during the device's listening window. There are two different types of matching codes. They are MC1 and MC2. Both MC1 and MC2 are used in the Detection loop and MC2 is used in the Reactivation loop as detailed in Figure 4-1. The MC1 command is used to send the device to the Sleeping loop, and MC2 is used to send the device to the Processing loop. The MC is an 8-bit "match" of tag ID followed by 4-bit matching code type and parity bit such that: Matching code (12 bits) = "match (8 bits of tag ID)" + matching code type (3 bits)+ parity (1 bit) The matching code type and parity bit is bit-wise structured as follows: * MC1: 010P * MC2: 100P where P represents the parity bit of all match bits (8 bits) plus the MC type (3 bits). The "match" part of the MC is eight bits of the 32-bit Tag ID. The interrogator selects the 8 bits from the 32-bit Tag ID by calculating the bit range of the Tag ID. Equation 4-1 shows the equation for selecting the bit range using the transmission counter (TC). Both the EQUATION 4-2: 32-bit Tag ID and TC are included in the FR response. An example for the calculation of the matching code is given in Section 7-2. EQUATION 4-1: BIT-WISE EQUATION FOR "MATCH" "Match" = Tag ID bit range a: b {4*TC} modulo 32: {4 (TC +1) + 3} modulo 32 where {} modulo 32 means the remainder of {} divided by 32. For example, {28} modulo 32 and {35} modulo 32 are 28 and 3, respectively. 4.2.4 TIME SLOT GENERATOR This block generates time slots for the device. The time slot represents the time delay between the end of the FRR command and the beginning of the FR response. The available time slots are 1, 16 or 64. One time slot represents 2.5 ms. The device calculates the actual time slot based on the TSMAX, TC and Tag ID. The maximum time slot (TSMAX) is assigned to the device by the FRR command (see Figs. 4-3 to 4-7), or set to 16 if the talk first (TF) bit is set. Four or six bits of the Tag ID are used at a time to calculate the time slot, with TC being the shift parameter to choose which portion of the 32-bit Tag ID is used as shown in Equation 4-2. EQUATION FOR TIME SLOT CALCULATION TSMAX Time Slot = Tag ID bit range a:b 64 {[4(TC+1)+1] modulo 32: [4 TC] modulo 32} XOR TC LSB 16 {[4(TC+1)-1] modulo 32: [4 TC] modulo 32} XOR TC LSB 1 0 Note: The exclusive-or (XOR) in the above equation in Equation 4-2. This is called "semi-inverting" that randomizes worst case tag IDs, e.g. a Tag ID of `77777777' or `00000000'. Table 4-10 shows examples of the calculation. 2001 Microchip Technology Inc. DS40232C-page 49 MCRF450/451/452/455 TABLE 4-10: EXAMPLE: TAG ID = H'825FE1A0' Relevant Tag ID TC Selected Tag ID before XOR with LSB of TC TSMAX=16 TSMAX=64 Calculated Time Slot (TS) (after XOR with LSB of TC) Hexadecimal Binary TSMAX=16 TSMAX=64 0 h'825FE1(A0)' b'1010 0000' h'0' h'20' h'0' d'0' h'20' d'32' 1 h'825FE(1A)0' b'0001 1010' h'A' h'1A' h'5' d'5' h'25' d'37' 2 h'825F(E1)A0' b'1110 0001' h'1' h'21' h'1' d'1' h'21' d'33' 3 h'825(FE)1A0' b'1111 1110' h'E' h'3E' h'1' d'1' h'01' d'1' 4 h'82(5F)E1A0' b'0101 1111' h'F' h'1F' h'F' d'15' h'1F' d'31' 5 h'8(25)FE1A0' b'0010 0101' h'5' h'25' h'A' d'10' h'1A' d'26' 6 h'(82)5FE1A0' b'1000 0010' h'2' h'02' h'2' d'2' h'02' d'2' 7 h'(08)25FE1A' b'0000 1000' h'8' h'08' h'7' d'7' h'37' d'55' In Table 4-10, h/x..x/ represents hexadecimal number, d/x..x/ represents decimal number, and b/x..x/ represents binary number. Table 4-10 shows the calculated time slot (TS) is 5 for TC = 1 and TSMAX = 16 with Tag ID = h/825FE1A0/. This means the device waits for 12.5 ms (5 x 2.5 ms = 12.5 ms) in a non-modulating condition between the end of FRR and the start of the FR response. 4.2.5 TIME SLOT COUNTER This section generates the sleep time (2.5 ms x TS) of the device. During the sleep time, the device remains in a non-modulating condition. Also the TS is 37 for TC = 1 and TSMAX = 64. This means the device waits for 92.5 ms (37 x 2.5 ms = 92.5 ms) between the end of FRR and the start of the FR response in a non-modulating condition. DS40232C-page 50 2001 Microchip Technology Inc. MCRF450/451/452/455 5.0 MEMORY SECTION 5.2 The memory section is organized into two groups: (1) Main Memory Section and (2) Stored CRC Memory Section. 5.1 Main Memory Section The main section is organized into 32 blocks as shown in Table 5-1. Each block has 32 bits. The first 3 blocks (0 - 2) are used for predefined parameters and device operation. The next three blocks (3 - 5) are used as the fast read fields. The blocks from 6 to 31 (26 blocks) are used for user data memory. The memory is read or written in 32-bit selectable units, with the exception of the fast read (FR) bit and the talk first (TF) bit, which are individually selectable. TABLE 5-1: This memory section is used to store the CRC of the main memory section, and organized into 32 blocks. Each block has 16 bits. Each block contains the CRC in the corresponding block of the main memory section. The stored CRC (SCRC) corresponds to the interrogator command (write 32-bit block) and data. MEMORY ORGANIZATION Main Memory Section (32 blocks x 32 bits) Stored CRC (SCRC) Section (32 blocks x 16 bits) M S B F R Stored CRC (SCRC) Memory Section Comments L1111119876543210 S543210 B TF SNR 3 Tag Parameters SNR 2 FR Response CRC SNR 1 Block 0 (Tag Parameters/FR) SNR 0 Block 1 (Tag ID = Serial Number) 33222222222211111111119876543210 1098765432109876543210 Fast Read Field Block 2 (Write-Protect 1st kb) (LS Block) Block 3 (FR Field Least Significant Block) Block 4 (FR Field) Fast Read Field (MS Block) Block 5 (FR Field Most Significant Block) Block 6 (User Data) Block 7 (User Data) Block 8 (User Data) Block 9 (User Data) Block 10 (User Data) Block 11 (User Data) . . . . . . . . . . . . . . . . . . . . . . . . Block 29 (User Data) Block 30 (User Data) Block 31 (User Data) 2001 Microchip Technology Inc. DS40232C-page 51 MCRF450/451/452/455 5.3 BIT LAYOUT 5.3.1 BLOCK 0 The bit layout in block 0 is given in the following table. FR and TF bits are not write-protectable. TABLE 5-2: BIT LAYOUT OF BLOCK 0 B0:31 B0:30 B0:29 B0:28 B0:27 B0:26 B0:25 TF TFT1 TFT0 DF1 DF0 MT1* B0:23 B0:22 B0:21 B0:20 B0:19 B0:18 B0:17 B0:16 TM2* TM1* TM0* B0:15 B0:14 B0:13 B0:12 B0:11 B0:10 B0:9 B0:8 FR B0:24 MT0* FRR CRC 15 FRR CRC 14 FRR CRC 13 FRR CRC 12 FRR CRC 11 FRR CRC 10 FRR CRC 9 FRR CRC 8 B0:7 B0:6 B0:5 B0:4 B0:3 B0:2 FRR CRC 7 FRR CRC 6 FRR CRC 5 FRR CRC 4 FRR CRC 3 FRR CRC 2 Note: DESCRIPTION OF BITS TABLE 5-3: FR BIT (B0:31) Answer to Fast Read Request signal 1 Yes (e.g. "Item" is unpaid in retail EAS applications) 0 No (e.g. "Item" has been purchased in retail EAS applications) Note: B0:0 * These are `hardwired' bits, not EEPROM bits. 5.3.1.1 FR B0:1 FRR CRC 1 FRR CRC 0 FR bit is not write-protectable. TABLE 5-4: TF BIT (B0:30) TF Talk first TABLE 5-6: DF BITS (B0:27 - B0:26) DF1 DF0 0 0 32 bits (Default) 0 1 48 bits 1 0 64 bits 1 1 96 bits TABLE 5-7: MT1 MT0 FR Data Field Length MT BITS (B0:25 - B0:24) Memory type 0 Wait for FRR command 0 0 Single level EEPROM (Default) 1 Send Fast Read Response without waiting for FRR command 0 1 Reserved for future uses (e.g.; multi level EEPROM) TF bit is not write-protectable. 1 0 Reserved for future uses (e.g.; FRAM) 1 1 Reserved for future uses Note: TABLE 5-5: TFT BITS (B0:29 - B0:28) Talk First TCMAX 1 TFT1 TFT0 0 0 1 0 1 2 1 0 4 1 1 Never Elapses (Default) 2 Note: The MT bits are "hardwired". Note 1: Only applicable in tag talks first (TTF) mode. If FRR, TCMAX in command applies. Maximum time slot (TSMAX) parameter is set to 64 for TTF mode. 2: The device continuously sends its FR response until it receives its correct matching code. On average, the device will send its FR response every 80 ms. DS40232C-page 52 2001 Microchip Technology Inc. MCRF450/451/452/455 TABLE 5-8: TM BITS (B0:23 - B0:21) TM2 TM1 TM0 Total memory size 0 0 0 512 bits 0 0 1 1 Kbit (Default) 0 1 0 TBD 0 1 1 TBD 1 0 0 TBD 1 0 1 TBD 1 1 0 TBD 1 1 1 TBD 6.0 The device will be shipped to customers with the Fast Read (FR) bit set, and with block 1 write-protected. The following bits are factory programmed prior to shipping: 1. 2. 3. Note: 4. DF0(B0:26) and DF1(B0:27) are set to "0". TFT0(B0:28) and TFT1(B0:29) bits are set to "1". All bits in the FR field (blocks 3-5) are programmed to "1"s. The FRR_CRC(B0:0 - B0:15) bits are also programmed according to the Tag ID and item (3) above. The TM bits are "hardwired". TABLE 5-9: B0: (20-16) AND B0: (15-0) B0:(20-16) Available for user B0:(15-0) CRC for the Fast Read Response 5.3.2 DEVICE TESTING BLOCK 1: UNIQUE 32-BIT TAG ID Block 1 contains 32 bits of unique Tag ID with stored CRC (SCRC). The ID is uniquely serialized. 5.3.3 BLOCK 2: WRITE-PROTECT FOR THE FIRST KBITS Each bit corresponds to a 32-bit block, i.e. bit 0 to block 0, bit 1 to block 1, etc. Write-protection is a one way process, i.e. once a block is write-protected, it cannot be modified. It should be noted that the write-protect block itself can be write-protected. TF and FR bits in block 0 are not write-protectable even if the write-protection bit in the block is set. TABLE 5-10: WRITE-PROTECT Block X Write Status Bit X of Write-Protect Block Block X writable 1 Block X write-protected 0 5.3.4 BLOCKS 3-5: FAST READ FIELDS These blocks contain data bits for the FR response. The state of the DF bits (see Table 5-6) in block 0 determines the actual number of bits to be sent. This block can be used as a customer ID or also as additional tag ID numbers. 2001 Microchip Technology Inc. DS40232C-page 53 MCRF450/451/452/455 7.0 EXAMPLES EXAMPLE 7-1: READ/WRITE PULSE SEQUENCE To write 1 block (32 bits) in normal mode with TS = 1: ~ 78.014 ms To read 1 block (32 bits) in normal mode with TS = 1: ~ 42.214 ms FRR or FRB Command: 5 gap pulses = 1.575 ms. Interrogator Command (FRR/FRB) t TDECODE (2.8 ms) For FR Response: (Preamble (8 bits) + Tc (3 bits) + Tp (4 bits) + "0" + 32 bits of Tag ID + FRF (32-96 bits) + bits 0-15 in Block #0 = 160 bits max = 2.286 ms) For FRB Response: (Preamble (8 bits) + "00001" + "000" + 32-bit Tag ID (block 1 data) + SCRC (16 bits) = 64 bits = 0.914 ms) Time Slot (TS) Listening window (TLW) for 1 ms Tag Response (FR response) t Matching Code during listening window: MC code = Calibration pulse (1 symbol) + Matched Tag ID (8 bits) + MC code type (3 bits) + 1 Parity bit = Cal. pulse (1 symbol) + 12 bits = 4 symbols = 11.2 ms Interrogator Command (MC and Read/Write) t For Reading: Cal. pulse (1 symbol) + Read Command (MSN first) + Address (MSN first + Parity) = Cal. pulse + 3 symbols = 11.2 ms Twrite for EEPROM (5 ms) For Writing: Cal. pulse (1 symbol) + Write Command (MSN first) + Address (MSN first) + data (LSN first) + Parity/CRC (LSN first) = Cal. pulse (1 symbol) + 14 symbols = 42 ms Tag Response (to Read/Write) t Device Outputs: After a completion of write cycle: Preamble (8 bits) + written block # (5 bits) + "000" + written block data (32 bits) + CCRC/SCRC (16 bits) = 64 bits = 0.914 ms After read command: Preamble (8 bits) + block # (5 bits) + "000" + block data (32 bits) + CCRC/SCRC (16 bits) = 64 bits = 0.914 ms Interrogator Command (End Process) t End Process Command: Cal. pulse + End Process Command (111) + Address (01010) + Parity (1) = Cal. Pulse + 3 symbols = 11.2 ms Tag Response to End Process t Device Response: 8-bit preamble (11111110) (0.114 ms) DS40232C-page 54 2001 Microchip Technology Inc. MCRF450/451/452/455 EXAMPLE 7-2: CALCULATION OF MATCHING CODE FOR TAG ID = 825FE1A0 (HEX, MSB FIRST) The "match" part of the matching code is calculated by the Bit-Wise Equation in Equation 4-1: "Match (8 bits)" = Tag ID bit range a:b = {4(TC)}modulo 32: {4(TC + 1) + 3}modulo 32 For TC = 2, the above equation gives a = 8, and b = 15. The "Match (8 bits)" is chosen from (8th 9th 10th 11th) and (12th 13th 14th 15th) bits of the Tag ID. Therefore, for the Tag ID = 825FE1A0 (hex) = b/1000 0010 0101 1111 1110 0001 1010 0000/, "Match (8 bits)" = b/1110 0001/ = 1E (hex). Using this "Match" part, a complete set of matching code is assembled as: 1E5 for MC1, and 1E9 for MC2 where: 5 in the MC1 was from b/0101/ (010 for MC1 and the last "1" is a parity bit), and 9 in the MC2 was from b/1001/ (100 for MC2 and the last "1" is a parity bit). Gap position in the 1-of-16 PPM signal for the calculated MC codes: The gap position numbers in the 1-of-16 PPM for the calculated MC codes are (see Figure 4-9 for 1-of-16 PPM): Positions 1, 14, and 5 for 1E5 for MC1 code Positions 1, 14, and 9 for 1E9 for MC2 code. The "Match" part of the matching code for various TCs are given in Table 7-1. TABLE 7-1: CALCULATED "MATCH" FOR TAG ID = 825FE1A0 (HEX) 2001 Microchip Technology Inc. TC "Match (8 bits) in hex" 0 0A 1 A1 2 1E 3 EF 4 F5 5 52 6 28 7 80 DS40232C-page 55 MCRF450/451/452/455 EXAMPLE 7-3: TO WRITE DATA INTO THE DEVICE The interrogator command structure for writing (see Section 4.2.1) is: Calibration pulse + Writing Command (MSN first) + Address (MSN first) + Data (LSN first) + Parity/CRC (LSN first) If the interrogator wants to write data "0123cdef (Hex, MSB to LSB)" to block 5, the following message will be sent: Calibration pulse + Write Command (MSN first) + Address (MSN first) + Data (LSN first) + Parity/CRC (LSN first) = 101 (write command) + 00101 (address) + f e d c 3 2 1 0 (data, hex) + CRC = Calibration pulse + a 5 f e d c 3 2 1 0 6 0 2 e (hex string) The hex string above is encoded with the 1-of-16 PPM signals. See Figure 4-10 for the 1-of-16 PPM representation of hex values. Referring to Figure 4-10, the gap positions in the 1-of-16 PPM for the above hex string are: Positions 10 (a), 5 (5), 15 (f), 14 (e), 13 (d), 12 (c), 3 (3), 2 (2), 1 (1), 0 (0), 6 (6), 0 (0), 2 (2), e (14). EXAMPLE 7-4: TO READ DATA FROM THE DEVICE To read the content of block 5 that has been programmed in the previous example, the interrogator sends the following command: Calibration pulse + Read Command (110) + Address (00101) + Parity (0) = Calibration pulse + C50 (hex) The gap positions in the 1-of-16 PPM signal for the above hex string are: 12 (C), 5 (5), 0 (0). Device Response: When the device receives the above interrogator command, the device outputs the following 70 kHz Manchester encoded data string (see Section 4.2.2 for the structure of device response): Preamble (8 bits) + Block number (5 bits, LSB first) + `000' + Block Data (32 bits, LSB first) + SCRC (16 bits) = 1-1-1-1-1-1-1-0 (f7) + 1-0-1-0-0-0-0-0 (5 0) + 1-1-1-1 0-1-1-1 1-0-1-1... 1-0-0-0 0-0-0-0 (f e d c 3 2 1 0) + 0-1-1-0 0-0-0-0 0-1-0-0 0-1-1-1 (602e). EXAMPLE 7-5: TO SEND THE "END PROCESS" COMMAND The interrogator command structure (see Section 4.2) for the End Process is: Calibration pulse + End Process Command (111) + Address (01010) + Parity (1) = Calibration pulse + EA1 (hex) The gap positions in the 1-of-16 PPM signal for the above hex string are: 14 (E), 10 (A), 1 (1). Device Response: The device outputs the 8-bit preamble ("11111110") when it receives the End Process command, and enters the Sleeping Loop. DS40232C-page 56 2001 Microchip Technology Inc. MCRF450/451/452/455 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead PDIP (300 mil) MCRF450 XXXXXNNN 0025 XXXXXXXX XXXXXNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Legend: Note: * XX...X Y YY WW NNN Example: Example: MCRF450 XXX0025 NNN Customer specific information* Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 2001 Microchip Technology Inc. DS40232C-page 57 MCRF450/451/452/455 8-Lead Plastic Dual In-line (P) - 300 mil (PDIP) E1 D 2 n 1 E A2 A L c A1 B1 p eB UNITS DIMENSION LIMITS Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic B MIN n p A A2 A1 E E1 D L c B1 B eB .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 10 5 10 5 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS40232C-page 58 2001 Microchip Technology Inc. MCRF450/451/452/455 8-Lead Plastic Small Outline (SN) - Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h 45 c A2 A UNITS DIMENSION LIMITS Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter Significant Characteristic L MIN n p A A2 A1 E E1 D h L c B .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 .10 .18 5.79 6.02 3.71 3.91 4.80 4.90 .25 .38 .48 .62 0 4 .20 .23 .33 .42 0 12 0 12 MIN MAX 1.75 1.55 .25 6.20 3.99 5.00 .51 .76 8 .25 .51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2001 Microchip Technology Inc. DS40232C-page 59 MCRF450/451/452/455 ON-LINE SUPPORT Systems Information and Upgrade Hot Line Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. Connecting to the Microchip Internet Web Site The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: * Latest Microchip Press Releases * Technical Support Section with Frequently Asked Questions * Design Tips * Device Errata * Job Postings * Microchip Consultant Program Member Listing * Links to other useful web sites related to Microchip Products * Conferences for products, Development Systems, technical information and more * Listing of seminars and events DS40232C-page 60 2001 Microchip Technology Inc. MCRF450/451/452/455 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y Device: MCRF450/451/452/455 N Literature Number: DS40232C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? 2001 Microchip Technology Inc. DS40232C-page 61 MCRF450/451/452/455 MCRF450/451/452/455 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. MCRF450/451/452/455 /X WF WFB W Package: WB S Device: = Sawed 8" wafer on frame (8 mil backgrind) = Bumped, sawed 8" wafer on frame (11 mil backgrind) = 8" wafer (11 mil backgrind) = Bumped 8" wafer (11 mil backgrind) = Dice in waffle pack (11 mil backgrind) SB = Bumped die in waffle pack (11 mil backgrind) SN = SOIC, 8-lead, 300 mil body P = PDIP, 8-lead, 150 mil body MCRF450/451/452/455 = 13.56 MHz Read/Write Anti-collision device Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. Your local Microchip sales office (see last page) 2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 3. The Microchip's Bulletin Board, via your local CompuServe number (CompuServe membership NOT required). Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. DS40232C-page 62 2001 Microchip Technology Inc. M AN752 CRC Algorithm for MCRF45X Read/Write Device Author: Youbok Lee, Ph.D. Microchip Technology Inc. INTRODUCTION The 13.56 MHz read/write devices (MCRF4XX) use a 16-bit Cyclic Redundancy Code (CRC) to ensure the integrity of data. Its polynomial and initial values are: CRC Polynomial: X0+X5+X12+X16 = 1000-01000000-1000-(1) = 8408 (hex) Initial Value: $FFFF This polynomial is also known as CRC CCITT-16. The interrogator applies the same polynomial to the incoming and transmitting data. FIGURE 1: P(x) = x1 x2 x3 CCITT-16 CRC ENCODER x4 x5 x6 XOR x7 x8 x9 x10 x11 x12 x13 x14 x15 x16 (x0) XOR Data XOR LSB Data in LSB first 2001 Microchip Technology Inc. DS00752A-page 63 AN752 COMPUTATION ALGORITHM Data: 8552F189 (hex): 0001-1010-1010-01001111-1000-1001 (binary, LSB first for each nibble). Figure 1 shows the CCITT-16 CRC encoder. Figure 2 is the computational flow chart for computer programming. The encoder consists of 16 shift registers and 3 exclusive-OR gates. The registers start with 1111-11111111-1111 (or FFFF in hex). The encoder performs XOR and shifts its content until the last bit is entered. The final register's content after the last data bit is the calculated CRC value of the data set. Table 1 shows each step of the calculation. The content of the register after the last bit is 07F1. This 07F1 is the calculated CRC of the data. When transmitting data, this calculated CRC is attached to the data. The interrogator sends the data and CRC with LSN (Least Significant Nibble) first. Therefore, the hex string to be sent will be: 981F25581F70 and for data = 8552F189. Example: The following procedure shows a workout example of the CRC calculation using the encoder. FIGURE 2: FLOW-CHART OF CRC COMPUTATION CRC Poly = 8408 (1000-0100-0000-1000) Input Data Initialize CRC = FFFF (1111-1111-1111-1111) Test Data bit = LSB of Data bits K = XOR CRC (LSB) with Test Data bit No ( K = 1) K=0 Yes Shift CRC to right by 1 and CRC = XOR CRC with CRC Poly Shift CRC to right by 1 No Shift Data bits to right by 1 Is Test Data bit the MSB of Data bits ? Yes Stop DS00752A-page 64 2001 Microchip Technology Inc. AN752 TABLE 1: Bit No. CRC WORKOUT EXAMPLE FOR DATA = 8552F189 (HEX) Input Data Register Contents X1 X2 X3 X4 X5 - X6 X7 X8 X9 Hex Value X10 X11 X12 - X13 X14 X15 X16 1 1 1 1 1 - 1 1 1 1 1 1 1 - 1 1 1 1 FFFF 1 0 1 1 1 1 1 - 0 1 1 1 1 1 1 - 0 1 1 1 FBF7 2 0 1 1 1 1 1 - 0 0 1 1 1 1 1 - 0 0 1 1 F9F3 3 0 1 1 1 1 1 - 0 0 0 1 1 1 1 - 0 0 0 1 F8F1 4 1 0 1 1 1 1 - 1 0 0 0 1 1 1 - 1 0 0 0 7C78 5 1 1 0 1 1 1 - 0 1 0 0 0 1 1 - 0 1 0 0 BA34 6 0 0 1 0 1 1 - 1 0 1 0 0 0 1 - 1 0 1 0 5D1A 7 1 1 0 1 0 1 - 0 1 0 1 0 0 0 - 0 1 0 1 AA85 8 0 1 1 0 1 0 - 0 0 1 0 1 0 0 - 1 0 1 0 D14A 9 1 1 1 1 0 1 - 1 0 0 1 0 1 0 - 1 1 0 1 ECAD 10 0 1 1 1 1 0 - 0 1 0 0 1 0 1 - 1 1 1 0 F25E 11 1 1 1 1 1 1 - 1 0 1 0 0 1 0 - 0 1 1 1 FD27 12 0 1 1 1 1 1 - 0 1 0 1 0 0 1 - 1 0 1 1 FA9B 13 0 1 1 1 1 1 - 0 0 1 0 1 0 0 - 0 1 0 1 F945 14 1 0 1 1 1 1 - 1 0 0 1 0 1 0 - 0 0 1 0 7CA2 15 1 0 0 1 1 1 - 1 1 0 0 1 0 1 - 0 0 0 1 3E51 16 0 1 0 0 1 1 - 0 1 1 0 0 1 0 - 0 0 0 0 9B20 Initial 17 1 1 1 0 0 1 - 0 0 1 1 0 0 1 - 1 0 0 0 C998 18 1 1 1 1 0 0 - 0 0 0 1 1 0 0 - 0 1 0 0 E0C4 19 1 1 1 1 1 0 - 1 0 0 0 1 1 0 - 1 0 1 0 F46A 20 1 1 1 1 1 1 - 1 1 0 0 0 1 1 - 1 1 0 1 FE3D 21 1 0 1 1 1 1 - 1 1 1 0 0 0 1 - 1 1 1 0 7F1E 22 0 0 0 1 1 1 - 1 1 1 1 0 0 0 - 1 1 1 1 3F8F 23 0 1 0 0 1 1 - 0 1 1 1 1 0 0 - 1 1 1 1 9BCF 24 0 1 1 0 0 1 - 0 0 1 1 1 1 0 - 1 1 1 1 C9EF 25 0 1 1 1 0 0 - 0 0 1 1 1 1 - 1 1 1 1 E0FF 26 0 1 1 1 1 0 - 1 0 0 0 0 1 1 1 - 0 1 1 1 F477 27 0 1 1 1 1 1 - 1 1 0 0 1 1 - 0 0 1 1 FE33 28 1 0 1 1 1 1 - 1 1 1 0 0 0 1 - 1 0 0 1 7F19 29 1 0 0 1 1 1 - 1 1 1 1 0 0 0 - 1 1 0 0 3F8C 30 0 0 0 0 1 1 - 1 1 1 1 1 0 0 - 0 1 1 0 1FC6 31 0 0 0 0 0 1 - 1 1 1 1 1 1 0 - 0 0 1 1 0FE3 32 1 0 0 0 0 0 - 1 1 1 1 1 1 1 - 0 0 0 1 07F1 (CRC Value) 2001 Microchip Technology Inc. 0 DS00752A-page 65 AN752 APPENDIX A: EXAMPLE WITH C-SOURCE CODE FOR CRC CALCULATION # include <stdio.h> # include <stdlib.h> # include "onescnt.h" # define NULL 0 # define true 1 # define false 0 void main (int argc, char *argv[ ]) { int i, j, k, message[40], num_bits, bitcount, bytecount, crc, next_bit, crc_temp, message_temp; int maskreg[8] = {1, 2, 4, 8, 16, 32, 64, 128}; int crc_nibble[4]; char ch FILE *fin; if (argc != 2) { printf ("proper usage is CCITT {indata file with data in hex}\n"); abort (); } if ( (fin =fopen(argv[1], "r")) ==NULL) {printf("Can't open %s\n", argv[1]; abort();} i = 0; while ( (ch=fgetc(fin)) !=EOF) { message_temp = 0; //retrieve the input data field and convert to an integer message field if ((ch >= `a') && (ch <= `f')) ch = ch - 0x20 if ((ch >= `A') && (ch <= `F')) ch = ch - 0x70 if ((ch >= `0') && (ch <= `?')) { message_temp = ch - `0'; message[i++] = message_temp; } } // At this point, message[ ] holds data with nibbles (4 bits on each array). This will be used for CRC calculation message[ i ] = -1; k = i // The above is used for array checking and k value is the total number of nibbles. printf ("Read in %d nibbles. \n", k); printf ("Original data in hex read in from data file: \n"); for (i = 0; i < k; i++) printf("%x ", message[ i ]); printf("\n\n"); // Now computing the CRC of data //----------- Initialization -----------------------------crc = 0xffff; //initial CRC value crc_poly = 0x8408; //1000-0100-0000-1000 //--------------------------------------------------------printf ("Initial CRC value in hex: %x ... \n", crc); num_bits = k*4; for ( i = 0; i < num_bits; i++) { bitcount = i % 4; bytecount = i/4; next_bit = (message[bytecount] & maskreg[bitcount]); //This will find the next data bit to apply next_bit = ((next_bit >> bitcount) & 1); //This will move the current data bit to LSB of next_bit // and make all bits except LSB bit to zero crc_temp = crc^next_bit; //xor the last nibble of crc (actually the last bit of CRC) with next_bit if (crc_temp & 1) { printf ("xor = 1\n"); crc = crc >> 1; //Shift the crc by 1 to right crc = crc^crc_poly ; //xor current crc with crc_poly DS00752A-page 66 2001 Microchip Technology Inc. AN752 crc = crc|0x8000; //this may not be necessary } // if it is zero, just shift crc by 1 if (!(crc_temp &1)) { printf ("xor = 0\n"); crc = crc >> 1; crc = crc & 0x7fff;// this may not be necessary } printf("Temp CRC after iteration %d: ", i); for (j = i; j<num_bits; j++) printf(" "); } printf("%d\n", crc); } crc_nibble [0] = crc & x000f; crc_nibble [1] = (crc & x000f >> 4; crc_nibble [2] = (crc & x000f >> 8; crc_nibble [3] = (crc & x000f >> 12; printf("Bit order for shifting in nibbles in LSB first. \n"); printf ("\n CRC at end: %x ", crc); printf ("Send %x %x %x %x \n", crc_nibble[0], crc_nibble[1],crc_nibble[2],crc_nibble[3],); printf("\n\n"); fclose(fin); } 2001 Microchip Technology Inc. DS00752A-page 67 AN752 NOTES: DS00752A-page 68 2001 Microchip Technology Inc. M AN707 MCRF 355/360 Application Note: Mode of Operation and External Resonant Circuit Author: Youbok Lee, Ph.D. Microchip Technology Inc. INTRODUCTION The MCRF355 passive RFID device is designed for low cost, multiple reading, and various high volume tagging applications using a frequency band of 13.56 MHz. The device has a total of 154 memory bits that can be reprogrammed by a contact programmer. The device operates with a 70 kHz data rate, and asynchronously with respect to the reader's carrier. The device turns on when the coil voltage reaches 4 VPP and outputs data with a Manchester format (see Figure 2-3 in the data sheet). With the given data rate (70 kHz), it takes about 2.2 ms to transmit all 154 bits of the data. After transmitting all data, the device goes into a sleep mode for 100 ms +/- 50%. The MCRF355 needs only an external parallel LC resonant circuit that consists of an antenna coil and a capacitor for operation. The external LC components must be connected between antenna A, B, and ground pads. The circuit formed between Antenna Pad A and the ground pad must be tuned to the operating frequency of the reader antenna. MODE OF OPERATION The device transmits data by tuning and detuning the resonant frequency of the external circuit. This process is accomplished by using an internal modulation gate FIGURE 3: (CMOS), that has a very low turn-on resistance (2 ~ 4 ohms) between Drain and Source. This gate turns on during a logic "High" period of the modulation signal and off otherwise. When the gate turns on, its low turnon resistance shorts the external circuit between Antenna Pad B and the ground pad. Therefore, the resonant frequency of the circuit changes. This is called detuned or cloaking. Since the detuned tag is out of the frequency band of the reader, the reader can't see it. The modulation gate turns off as the modulation signal goes to a logic "Low." This turn-off condition again tunes the resonant circuit to the frequency of the reader antenna. Therefore the reader sees the tag again. This is called tuned or uncloaking. The tag coil induces maximum voltage during "uncloaking (tuned)" and minimum voltage during cloaking (detuned). Therefore, the cloaking and uncloaking events develop an amplitude modulation signal in the tag coil. This amplitude modulated signal in the tag coil perturbs the voltage envelope in the reader coil. The reader coil has maximum voltage during cloaking (detuned) and minimum voltage during uncloaking (tuned). By detecting the voltage envelope, the data signal from the tag can be readily reconstructed. Once the device transmits all 154 bits of data, it goes into "sleep mode" for about 100 ms. The tag wakes up from sleep time (100 ms) and transmits the data package for 2.2 ms and goes into sleep mode again. The device repeats the transmitting and sleep cycles as long as it is energized. VOLTAGE ENVELOPE IN READER COIL When tag is in cloaking V t When tag is in uncloaking 2001 Microchip Technology Inc. DS00707B-page 69 AN707 FIGURE 4: (A) UNCLOAKING (TUNED) AND (B) CLOAKING (DETUNED) MODES AND THEIR RESONANT FREQUENCIES f 0 = 13.56 MHz SW = OFF MCRF355 L1 (a) C 2 f L2 SW OFF Coil voltage in tag SW = ON MCRF355 L1 f (b) C 2 f0 = ( 13.56 + f ) MHz L2 SW ON f0 = 13.56 MHz C1 L MCRF355 (c) 2 C2 SW = OFF f SW OFF Coil voltage in tag C1 MCRF355 SW = ON (d) L 2 C2 DS00707B-page 70 f f0 = ( 13.56 - f ) MHz SW ON 2001 Microchip Technology Inc. AN707 ANTI-COLLISION FEATURES called anti-collision. Theoretically, more than 50 tags can be read in the same RF field. However, it is affected by distance from the tag to the reader, angular orientation, movement of the tags, and spacial distribution of the tags. During sleep mode, the device remains in a cloaked state where the circuit is detuned. Therefore, the reader can't see the tag during sleep time. While one tag is in sleep mode, the reader can receive data from other tags. This enables the reader to receive clean data from many tags without any data collision. This ability to read multiple tags in the same RF field is FIGURE 5: EXAMPLE OF READING MULTIPLE TAGS Data Packet Data Packet Sleep Tag 1 t Tag 2 t Tag 3 t Tag N t t1 t2 t3 tN t Reading data from Tag N Reading data from Tag 3 Reading data from Tag 2 Reading data from Tag 1 2001 Microchip Technology Inc. DS00707B-page 71 AN707 EXTERNAL CIRCUIT CONFIGURATION Since the device transmits data by tuning and detuning the antenna circuit, caution must be given in the external circuit configuration. For a better modulation index, the differences between the tuned and detuned frequencies must be wide enough (about 3 ~ 6 MHz). Figure 6 shows various configurations of the external circuit. The choice of the configuration must be chosen depending on the form-factor of the tag. For example, (a) is a better choice for printed circuit tags while, (b) is a better candidate for coil-wound tags. Both (a) and (b) relate to the MCRF355. In configuration (a), the tuned resonance frequency is determined by a total capacitance and inductance from Antenna Pad A to VSS. During cloaking, the internal switch (modulation gate) shorts Antenna Pad B and VSS. Therefore, the inductance L2 is shorted out. As a result, the detuned frequency is determined by the total capacitance and inductance L1. When shorting the inductance between Antenna Pad B and VSS, the detuned (cloak) frequency is higher than the tuned (uncloak) frequency In configuration (b), the tuned frequency (uncloak) is determined by the inductance L and the total capacitance between Antenna Pad A and VSS. The circuit detunes (cloak) when C2 is shorted. This detuned frequency (cloak) is lower than the tuned (uncloak) frequency. The MCRF360 includes a 100 pF internal capacitor. This device needs only an external inductor for operation. The explanation on tuning and detuning is the same as for configuration (a). DS00707B-page 72 2001 Microchip Technology Inc. AN707 FIGURE 6: VARIOUS EXTERNAL CIRCUIT CONFIGURATIONS 1 f tuned = ---------------------2 L T C MCRF355 Ant. Pad A 1 f detuned = ---------------------2 L 1 C L1 L T = L 1 + L 2 + 2L m C L2 Ant. Pad B VSS where: Lm L1 > L2 K (a) Two inductors and one capacitor = mutual inductance = K L1 L2 = coupling coefficient of two inductors 0K1 MCRF355 Ant. Pad A C1 1 f tuned = ---------------------2 LC T f detuned L Ant. Pad B C2 VSS C1 > C2 1 = ---------------------2 LC 1 C1 C2 C T = -------------------C +C 1 2 (b) Two capacitors and one inductor MCRF360 Ant. Pad A L1 L2 C = 100 pF 1 f tuned = ---------------------2 L T C 1 f detuned = ---------------------2 L 1 C Ant. Pad B VSS L T = L 1 + L 2 + 2L m L1 > L2 (c) Two inductors with one internal capacitor 2001 Microchip Technology Inc. DS00707B-page 73 AN707 PROGRAMMING OF DEVICE All of the memory bits in the are reprogrammable by a contact programmer or by factory programming prior to shipment, known as Serialized Quick Turn ProgrammingSM (SQTPSM). For more information about contact programming, see the microIDTM 13.56 MHz System Design Guide (DS21299). For information about SQTP programming, please see TB032 (DS91032), of the design guide. DS00707B-page 74 2001 Microchip Technology Inc. M AN710 Antenna Circuit Design for RFID Applications Author: Youbok Lee, Ph.D. Microchip Technology Inc. REVIEW OF A BASIC THEORY FOR RFID ANTENNA DESIGN INTRODUCTION Current and Magnetic Fields Passive RFID tags utilize an induced antenna coil voltage for operation. This induced AC voltage is rectified to provide a voltage source for the device. As the DC voltage reaches a certain level, the device starts operating. By providing an energizing RF signal, a reader can communicate with a remotely located device that has no external power source such as a battery. Since the energizing and communication between the reader and tag is accomplished through antenna coils, it is important that the device must be equipped with a proper antenna circuit for successful RFID applications. Ampere's law states that current flowing in a conductor produces a magnetic field around the conductor. The magnetic field produced by a current element, as shown in Figure 7, on a round conductor (wire) with a finite length is given by: An RF signal can be radiated effectively if the linear dimension of the antenna is comparable with the wavelength of the operating frequency. However, the wavelength at 13.56 MHz is 22.12 meters. Therefore, it is difficult to form a true antenna for most RFID applications. Alternatively, a small loop antenna circuit that is resonating at the frequency is used. A current flowing into the coil radiates a near-field magnetic field that falls off with r-3. This type of antenna is called a magnetic dipole antenna. For 13.56 MHz passive tag applications, a few microhenries of inductance and a few hundred pF of resonant capacitor are typically used. The voltage transfer between the reader and tag coils is accomplished through inductive coupling between the two coils. As in a typical transformer, where a voltage in the primary coil transfers to the secondary coil, the voltage in the reader antenna coil is transferred to the tag antenna coil and vice versa. The efficiency of the voltage transfer can be increased significantly with high Q circuits. This section is written for RF coil designers and RFID system engineers. It reviews basic electromagnetic theories on antenna coils, a procedure for coil design, calculation and measurement of inductance, an antenna tuning method, and read range in RFID applications. EQUATION 1: o I B = --------- ( cos 2 - cos 1 ) 4r where: I = current r = distance from the center of wire 0 = permeability of free space and given as 4 x 10-7 (Henry/meter) In a special case with an infinitely long wire where: 1 = -180 2 = 0 Equation 1 can be rewritten as: EQUATION 2: o I B = --------2r 2 ( Weber m ) FIGURE 7: CALCULATION OF MAGNETIC FIELD B AT LOCATION P DUE TO CURRENT I ON A STRAIGHT CONDUCTING WIRE Z Wire 2 dL I R 1 0 2001 Microchip Technology Inc. 2 ( Weber m ) r P X B (into the page) DS00710B-page 75 AN710 The magnetic field produced by a circular loop antenna is given by: FIGURE 8: CALCULATION OF MAGNETIC FIELD B AT LOCATION P DUE TO CURRENT I ON THE LOOP EQUATION 3: 2 o INa Bz = -------------------------------2 2 32 2(a + r ) X 2 = o INa 1 ------------------ ----3 2 r 2 for r >>a coil 2 I a where y I = current r V = V o sin t a = radius of loop r = distance from the center of wire 0 = permeability of free space and given as 0 = 4 x 10-7 (Henry/meter) The above equation indicates that the magnetic field strength decays with 1/r3. A graphical demonstration is shown in Figure 9. It has maximum amplitude in the plane of the loop and directly proportional to both the current and the number of turns, N. R P BZ z FIGURE 9: DECAYING OF THE MAGNETIC FIELD B VS. DISTANCE r B r-3 Equation 3 is often used to calculate the ampere-turn requirement for read range. A few examples that calculate the ampere-turns and the field intensity necessary to power the tag will be given in the following sections. r DS00710B-page 76 2001 Microchip Technology Inc. AN710 INDUCED VOLTAGE IN AN ANTENNA COIL Faraday's law states that a time-varying magnetic field through a surface bounded by a closed path induces a voltage around the loop. Figure 10 shows a simple geometry of an RFID application. When the tag and reader antennas are in close proximity, the time-varying magnetic field B that is produced by a reader antenna coil induces a voltage (called electromotive force or simply EMF) in the closed tag antenna coil. The induced voltage in the coil causes a flow of current on the coil. This is called Faraday's law. The induced voltage on the tag antenna coil is equal to the time rate of change of the magnetic flux . EQUATION 4: d dt V = - N ------where: N = number of turns in the antenna coil = magnetic flux through each turn The negative sign shows that the induced voltage acts in such a way as to oppose the magnetic flux producing it. This is known as Lenz's Law and it emphasizes the fact that the direction of current flow in the circuit is such that the induced magnetic field produced by the induced current will oppose the original magnetic field. The magnetic flux in Equation 4 is the total magnetic field B that is passing through the entire surface of the antenna coil, and found by: EQUATION 5: = B* dS where: B = magnetic field given in Equation 2 S = surface area of the coil * = inner product (cosine angle between two vectors) of vectors B and surface area S Note: Both magnetic field B and surface S are vector quantities. The presentation of inner product of two vectors in Equation 5 suggests that the total magnetic flux that is passing through the antenna coil is affected by an orientation of the antenna coils. The inner product of two vectors becomes minimized when the cosine angle between the two are 90 degrees, or the two (B field and the surface of coil) are perpendicular to each other and maximized when the cosine angle is 0 degrees. The maximum magnetic flux that is passing through the tag coil is obtained when the two coils (reader coil and tag coil) are placed in parallel with respect to each other. This condition results in maximum induced voltage in the tag coil and also maximum read range. The inner product expression in Equation 5 also can be expressed in terms of a mutual coupling between the reader and tag coils. The mutual coupling between the two coils is maximized in the above condition. FIGURE 10: A BASIC CONFIGURATION OF READER AND TAG ANTENNAS IN RFID APPLICATIONS Tag Coil V = V0sin(t) Tag I = ,0sin(t) Reader Electronics 2001 Microchip Technology Inc. Tuning Circuit B = B0sin(t) Reader Coil DS00710B-page 77 AN710 Using Equations 3 and 5, Equation 4 can be rewritten as: From Equations 4 and 5, a generalized expression for induced voltage Vo in a tuned loop coil is given by: EQUATION 6: EQUATION 8: d 21 d V = - N 2 -------------- = - N 2 ----- B dS dt dt 2 o i1 N 1 a d = - N 2 ----- ------------------------------------* dS dt 2 2 32 2(a + r ) 2 2 o N 1 N2 a ( b ) ------------------------------------------2 2 32 2(a + r ) = - di 1 -------dt di 1 = - M -------dt V 0 = 2fNSQB o cos where: f = frequency of the arrival signal N = number of turns of coil in the loop S = area of the loop in square meters (m2) Q = quality factor of circuit Bo = strength of the arrival signal = angle of arrival of the signal In the above equation, the quality factor Q is a measure of the selectivity of the frequency of the interest. The Q will be defined in Equations 31 through 47. FIGURE 11: ORIENTATION DEPENDENCY OF THE TAG ANTENNA where: V = voltage in the tag coil B-field i1 = current on the reader coil a = radius of the reader coil b = radius of tag coil r = distance between the two coils a Tag M = mutual inductance between the tag and reader coils, and given by: EQUATION 7: 2 o N1 N 2 ( ab ) M = ---------------------------------------2 2 32 2(a + r ) The induced voltage developed across the loop antenna coil is a function of the angle of the arrival signal. The induced voltage is maximized when the antenna coil is placed in parallel with the incoming signal where = 0. The above equation is equivalent to a voltage transformation in typical transformer applications. The current flow in the primary coil produces a magnetic flux that causes a voltage induction at the secondary coil. As shown in Equation 6, the tag coil voltage is largely dependent on the mutual inductance between the two coils. The mutual inductance is a function of coil geometry and the spacing between them. The induced voltage in the tag coil decreases with r-3. Therefore, the read range also decreases in the same way. DS00710B-page 78 2001 Microchip Technology Inc. AN710 EXAMPLE 2: CALCULATION OF B-FIELD IN A TAG COIL The MCRF355 device turns on when the antenna coil develops 4 VPP across it. This voltage is rectified and the device starts to operate when it reaches 2.4 VDC. The B-field to induce a 4 VPP coil voltage with an ISO standard 7810 card size (85.6 x 54 x 0.76 mm) is calculated from the coil voltage equation using Equation 8. EXAMPLE 4: An optimum coil diameter that requires the minimum number of ampere-turns for a particular read range can be found from Equation 3 such as: EQUATION 11: 3 --2 2 2 (a + r ) NI = K -------------------------2 a EQUATION 9: V o = 2fNSQBo cos = 4 2B z K = --------o where: and 4 ( 2) B o = ---------------------------------- = 0.0449 2fNSQ cos ( wbm -2 ) where the following parameters are used in the above calculation: Tag coil size = Frequency = Q of tag antenna = coil 40 AC coil voltage to = turn on the tag 4 VPP EXAMPLE 3: 2 2 12 3 2 2 32 3 2(a + r ) ( 2a ) - 2a ( a + r ) d ( NI ) -------------- = K -------------------------------------------------------------------------------------------------------4 da a 2 2 2 2 12 ( a - 2r ) ( a + r ) = K ----------------------------------------------------------3 a 13.56 MHz 4 cos = By taking derivative with respect to the radius , (85.6 x 54) mm2 (ISO card size) = 0.0046224 m2 Number of turns = OPTIMUM COIL DIAMETER OF THE READER COIL The above equation becomes minimized when: 2 2 a - 2r = 0 1 (normal direction, = 0). NUMBER OF TURNS AND CURRENT (AMPERE-TURNS) Assuming that the reader should provide a read range of 15 inches (38.1 cm) for the tag given in the previous example, the current and number of turns of a reader antenna coil is calculated from Equation 3: EQUATION 10: 2 2 32 2B z ( a + r ) ( NI )rms = -------------------------------2 a The above result shows a relationship between the read range versus optimum coil diameter. The optimum coil diameter is found as: EQUATION 12: a= 2r where: a = radius of coil r = read range. The result indicates that the optimum loop radius, a, is 1.414 times the demanded read range r. -6 2 2 32 2 ( 0.0449 x 10 ) ( 0.1 + ( 0.38 ) ) = ------------------------------------------------------------------------------------7 2 ( 4 x 10 ) ( 0.1 ) = 0.43 ( ampere - turns ) The above result indicates that it needs a 430 mA for 1 turn coil, and 215 mA for 2-turn coil. 2001 Microchip Technology Inc. DS00710B-page 79 AN710 WIRE TYPES AND OHMIC LOSSES EQUATION 14: 1 = ----------------f Wire Size and DC Resistance The diameter of electrical wire is expressed as the American Wire Gauge (AWG) number. The gauge number is inversely proportional to diameter, and the diameter is roughly doubled every six wire gauges. The wire with a smaller diameter has a higher DC resistance. The DC resistance for a conductor with a uniform cross-sectional area is found by: f = frequency = permeability of material = conductivity of the material EXAMPLE 5: EQUATION 13: l R DC = -----S where: The skin depth for a copper wire at 13.56 MHz can be calculated as: () EQUATION 15: where: 1 = -----------------------------------------------------------------------7 -7 f ( 4 x 10 ) ( 5.8 x 10 ) l = total length of the wire = conductivity S = cross-sectional area Table 6 shows the diameter for bare enamel-coated wires, and DC resistance. and AC Resistance of Wire At DC, charge carriers are evenly distributed through the entire cross section of a wire. As the frequency increases, the reactance near the center of the wire increases. This results in higher impedance to the current density in the region. Therefore, the charge moves away from the center of the wire and towards the edge of the wire. As a result, the current density decreases in the center of the wire and increases near the edge of the wire. This is called a skin effect. The depth into the conductor at which the current density falls to 1/e, or 37% of its value along the surface, is known as the skin depth and is a function of the frequency and the permeability and conductivity of the medium. The skin depth is given by: DS00710B-page 80 0.0179 = ---------------f (m) = 0.187 ( mm ) The wire resistance increases with frequency, and the resistance due to the skin depth is called an AC resistance. An approximated formula for the AC resistance is given by: EQUATION 16: 1 a R ac ------------- = ( RDC ) -----2 2 ( ) where: a = coil radius 2001 Microchip Technology Inc. AN710 TABLE 6: AWG WIRE CHART Wire Size (AWG) Dia. in Mils (bare) Dia. in Mils (coated) Ohms/ 1000 ft. Cross Section (mils) 1 289.3 -- 0.126 83690 2 287.6 -- 0.156 66360 3 229.4 -- 0.197 52620 4 204.3 -- 0.249 41740 5 181.9 -- 0.313 33090 6 162.0 -- 0.395 26240 7 166.3 -- 0.498 20820 8 128.5 131.6 0.628 16510 9 114.4 116.3 0.793 13090 10 101.9 106.2 0.999 10380 11 90.7 93.5 1.26 8230 12 80.8 83.3 1.59 6530 13 72.0 74.1 2.00 5180 14 64.1 66.7 2.52 4110 15 57.1 59.5 3.18 3260 16 50.8 52.9 4.02 2580 17 45.3 47.2 5.05 2060 18 40.3 42.4 6.39 1620 19 35.9 37.9 8.05 1290 20 32.0 34.0 10.1 1020 21 28.5 30.2 12.8 812 22 25.3 28.0 16.2 640 23 22.6 24.2 20.3 511 24 20.1 21.6 25.7 404 25 17.9 19.3 32.4 320 Note: Wire Size (AWG) Dia. in Mils (bare) Dia. in Mils (coated) Ohms/ 1000 ft. Cross Section (mils) 26 15.9 17.2 41.0 253 27 14.2 15.4 51.4 202 28 12.6 13.8 65.3 159 29 11.3 12.3 81.2 123 30 10.0 11.0 106.0 100 31 8.9 9.9 131 79.2 32 8.0 8.8 162 64.0 33 7.1 7.9 206 50.4 34 6.3 7.0 261 39.7 35 5.6 6.3 331 31.4 36 5.0 5.7 415 25.0 37 4.5 5.1 512 20.2 38 4.0 4.5 648 16.0 39 3.5 4.0 847 12.2 40 3.1 3.5 1080 9.61 41 2.8 3.1 1320 7.84 42 2.5 2.8 1660 6.25 43 2.2 2.5 2140 4.84 44 2.0 2.3 2590 4.00 45 1.76 1.9 3350 3.10 46 1.57 1.7 4210 2.46 47 1.40 1.6 5290 1.96 48 1.24 1.4 6750 1.54 49 1.11 1.3 8420 1.23 50 0.99 1.1 10600 0.98 Note: mil = 2.54 x 10-3 cm mil = 2.54 x 10-3 cm 2001 Microchip Technology Inc. DS00710B-page 81 AN710 INDUCTANCE OF VARIOUS ANTENNA COILS An electric current element that flows through a conductor produces a magnetic field. This time-varying magnetic field is capable of producing a flow of current through another conductor - this is called inductance. The inductance / depends on the physical characteristics of the conductor. A coil has more inductance than a straight wire of the same material, and a coil with more turns has more inductance than a coil with fewer turns. The inductance L of inductor is defined as the ratio of the total magnetic flux linkage to the current I through the inductor: The inductance of a straight wound wire shown in Figure 7 is given by: EQUATION 18: 3 L = 0.002l log 2l - - --e ---a 4 (Henry) ( H ) where: l and a = length and radius of wire in cm, respectively. EXAMPLE 7: EQUATION 17: N L = -------I INDUCTANCE OF A STRAIGHT WOUND WIRE INDUCTANCE CALCULATION FOR A STRAIGHT WIRE: The inductance of a wire with 10 feet (304.8cm) long and 2 mm in diameter is calculated as follows: EQUATION 19: where: ( 304.8 ) 3 L = 0.002 ( 304.8 ) ln 2------------------- 0.1 - --4- N = number of turns I = current = the magnetic flux For a coil with multiple turns, the inductance is greater as the spacing between turns becomes smaller. Therefore, the tag antenna coil that has to be formed in a limited space often needs a multilayer winding to reduce the number of turns. Calculation of Inductance Inductance of the coil can be calculated in many different ways. Some are readily available from references[1-4]. It must be remembered that for RF coils the actual resulting inductance may differ from the calculated true result because of distributed capacitance. For that reason, inductance calculations are generally used only for a starting point in the final design. = 0.60967 ( 7.965 ) = 4.855 ( H ) INDUCTANCE OF THIN FILM INDUCTOR WITH A RECTANGULAR CROSS SECTION Inductance of a conductor with rectangular cross section as shown in Figure 12 is calculated as: FIGURE 12: A STRAIGHT THIN FILM INDUCTOR b l a EQUATION 20: 2l a + b L = 0.002l ln ------------ + 0.50049 + ------------ a + b 3l ( H ) where: D = width in cm E = thickness in cm O = length of conductor in cm DS00710B-page 82 2001 Microchip Technology Inc. AN710 INDUCTANCE OF A CIRCULAR COIL WITH SINGLE TURN The inductance of a circular coil shown in Figure 13 can be calculated by: FIGURE 13: A CIRCULAR COIL WITH SINGLE TURN INDUCTANCE OF N-TURN CIRCULAR COIL WITH MULTILAYER FIGURE 14: N-TURN CIRCULAR COIL WITH SINGLE LAYER N-turns coil b a a Center of coil X a d X b h Figure 14 shows an N-turn inductor of circular coil with multilayer. Its inductance is calculated by: EQUATION 21: 16a L = 0.01257 ( a ) 2.303log 10 --------- - 2 d ( H ) where: EQUATION 23: 2 0.31 ( aN ) L = ---------------------------------6a + 9h + 10b ( H ) where: a = mean radius of loop in (cm) d = diameter of wire in (cm) a = average radius of the coil in cm N = number of turns b = winding thickness in cm INDUCTANCE OF AN N-TURN CIRCULAR COIL WITH SINGLE LAYER h = winding height in cm The inductance of a circular coil with single layer is calculated as: EQUATION 22: 2 ( aN ) L = -------------------------------22.9l + 25.4a ( H ) where: N = number of turns l = length a = the radius of coil in cm 2001 Microchip Technology Inc. DS00710B-page 83 AN710 INDUCTANCE OF SPIRAL WOUND COIL WITH SINGLE LAYER INDUCTANCE OF N-TURN SQUARE LOOP COIL WITH MULTILAYER The inductance of a spiral inductor is calculated by: Inductance of a multilayer square loop coil is calculated by: EQUATION 24: EQUATION 25: 2 ( aN ) L = ---------------------8a + 11b ( H ) 2 a b+c L = 0.008aN 2.303log 10 ------------ + 0.2235 ------------ + 0.726 ( H ) b+c a FIGURE 15: A SPIRAL COIL where: N = number of turns a = side of square measured to the center of the rectangular cross section of winding b = winding length c = winding depth as shown in Figure 16 Note: a All dimensions are in cm FIGURE 16: N-TURN SQUARE LOOP COIL WITH MULTILAYER b b ri c a ro a where: a = (ri + ro)/2 b = ro - ri (a) Top View (b) Cross Sectional View ri = Inner radius of the spiral ro = Outer radius of the spiral Note: All dimensions are in cm DS00710B-page 84 2001 Microchip Technology Inc. AN710 INDUCTANCE OF A FLAT SQUARE COIL Inductance of a flat square coil of rectangular cross section with N turns is calculated by[4]: EQUATION 26: a2 2 2 0.2235 L = 0.0467aN log 10 2 ------------ - log 10 ( 2.414a ) + 0.02032aN 0.914 + ---------------- ( t + w ) t + w a where: L = in H a = side length in inches t = thickness in inches w = width in inches FIGURE 17: SQUARE LOOP INDUCTOR WITH A RECTANGULAR CROSS SECTION w a The formulas for inductance are widely published and provide a reasonable approximation for the relationship between inductance and the number of turns for a given physical size[1-4]. When building prototype coils, it is wise to exceed the number of calculated turns by about 10% and then remove turns to achieve a right value. For production coils, it is best to specify an inductance and tolerance rather than a specific number of turns. 2001 Microchip Technology Inc. DS00710B-page 85 AN710 CONFIGURATION OF ANTENNA CIRCUITS the resonance frequency. Because of its simple circuit topology and relatively low cost, this type of antenna circuit is suitable for proximity reader antenna. Reader Antenna Circuits On the other hand, a parallel resonant circuit results in maximum impedance at the resonance frequency. Therefore, maximum voltage is available at the resonance frequency. Although it has a minimum resonant current, it still has a strong circulating current that is proportional to Q of the circuit. The double loop antenna coil that is formed by two parallel antenna circuits can also be used. The inductance for the reader antenna coil for 13.56 MHz is typically in the range of a few microhenries (H). The antenna can be formed by aircore or ferrite core inductors. The antenna can also be formed by a metallic or conductive trace on PCB board or on flexible substrate. The reader antenna can be made of either a single coil, that is typically forming a series or a parallel resonant circuit, or a double loop (transformer) antenna coil. Figure 18 shows various configurations of reader antenna circuit. The coil circuit must be tuned to the operating frequency to maximize power efficiency. The tuned LC resonant circuit is the same as the bandpass filter that passes only a selected frequency. The Q of the tuned circuit is related to both read range and bandwidth of the circuit. More on this subject will be discussed in the following section. The frequency tolerance of the carrier frequency and output power level from the read antenna is regulated by government regulations (e.g., FCC in the USA). Choosing the size and type of antenna circuit depends on the system design topology. The series resonant circuit results in minimum impedance at the resonance frequency. Therefore, it draws a maximum current at 4. FCC limits for 13.56 MHz frequency band are as follows: 1. 2. 3. Tolerance of the carrier frequency: 13.56 MHz +/- 0.01% = +/- 1.356 kHz. Frequency bandwidth: +/- 7 kHz. Power level of fundamental frequency: 10 mv/m at 30 meters from the transmitter. Power level for harmonics: -50.45 dB down from the fundamental signal. The transmission circuit including the antenna coil must be designed to meet the FCC limits. FIGURE 18: VARIOUS READER ANTENNA CIRCUITS L L C C (a) Series Resonant Circuit (b) Parallel Resonant Circuit (secondary coil) C2 (primary coil) C1 To reader electronics (c) Transformer Loop Antenna DS00710B-page 86 2001 Microchip Technology Inc. AN710 Tag Antenna Circuits and detuned frequency is: The MCRF355 device communicates data by tuning and detuning the antenna circuit (see AN707). Figure 19 shows examples of the external circuit arrangement. EQUATION 28: The external circuit must be tuned to the resonant frequency of the reader antenna. In a detuned condition, a circuit element between the antenna B and VSS pads is shorted. The frequency difference (delta frequency) between tuned and detuned frequencies must be adjusted properly for optimum operation. It has been found that maximum modulation index and maximum read range occur when the tuned and detuned frequencies are separated by 3 to 6 MHz. The tuned frequency is formed from the circuit elements between the antenna A and VSS pads without shorting the antenna B pad. The detuned frequency is found when the antenna B pad is shorted. This detuned frequency is calculated from the circuit between antenna A and VSS pads excluding the circuit element between antenna B and VSS pads. In Figure 19 (a), the tuned resonant frequency is: EQUATION 27: 1 fo = --------------------2 L T C where: LT = L1 + L2 + 2LM = Total inductance between antenna A and VSS pads 1 f detuned = ---------------------2 L 1 C In this case, fdetuned is higher than f tuned . Figure 19(b) shows another example of the external circuit arrangement. This configuration controls C2 for tuned and detuned frequencies. The tuned and untuned frequencies are EQUATION 29: 1 f tuned = ---------------------------------------- C1C2 2 -------------------- L C 1 + C 2 and EQUATION 30: 1 f detuned = ---------------------2 LC 1 A typical inductance of the coil is about a few microhenry with a few turns. Once the inductance is determined, the resonant capacitance is calculated from the above equations. For example, if a coil has an inductance of 1.3 H, then it needs a 106 pF of capacitance to resonate at 13.56 MHz. L1 = inductance between antenna A and antenna B pads L2 = inductance between ant. B and VSS pads M = mutual inductance between coil 1 and coil 2 = k L L 1 2 k = coupling coefficient between the two coils C = tuning capacitance 2001 Microchip Technology Inc. DS00710B-page 87 AN710 CONSIDERATION ON QUALITY FACTOR Q AND BANDWIDTH OF TUNING CIRCUIT results in longer read range. However, the Q is also related to the bandwidth of the circuit as shown in the following equation. The voltage across the coil is a product of quality factor Q of the circuit and input voltage. Therefore, for a given input voltage signal, the coil voltage is directly proportional to the Q of the circuit. In general, a higher Q EQUATION 31: fo Q = ---B FIGURE 19: VARIOUS EXTERNAL CIRCUIT CONFIGURATIONS 1 ftuned = --------------------2 L T C 1 fdetuned = ---------------------2 L 1 C MCRF355 Ant. Pad A L1 L T = L 1 + L 2 + 2L m C L2 Ant. Pad B VSS L1 > L2 where: Lm K (a) Two inductors and one capacitor = mutual inductance = K L1 L2 = coupling coefficient of two inductors 0K1 MCRF355 Ant. Pad A C1 1 ftuned = ---------------------2 LCT fdetuned L Ant. Pad B C2 VSS C1 > C2 1 = --------------------2 LC 1 C1 C2 C T = -------------------C1 + C2 (b) Two capacitors and one inductor MCRF360 L1 L2 Ant. Pad A 1 ftuned = --------------------2 L T C C = 100 pF 1 fdetuned = ---------------------2 L 1 C Ant. Pad B VSS L T = L 1 + L 2 + 2L m L1 > L2 (c) Two inductors with one internal capacitor DS00710B-page 88 2001 Microchip Technology Inc. AN710 Bandwidth requirement and limit on circuit Q for MCRF355 Since the MCRF355 operates with a data rate of 70 kHz, the reader antenna circuit needs a bandwidth of at least twice of the data rate. Therefore, it needs: Parallel Resonant Circuit Figure 20 shows a simple parallel resonant circuit. The total impedance of the circuit is given by: EQUATION 35: jL Z ( j ) = --------------------------------------------- ( ) 2 L ( 1 - LC ) + j ------R EQUATION 32: B minimum = 140 kHz where is an angular frequency given as = 2f . Assuming the circuit is turned at 13.56 MHz, the maximum attainable Q is obtained from Equations 31 and 32: The maximum impedance occurs when the denominator in the above equation is minimized. This condition occurs when: EQUATION 33: EQUATION 36: fo Q max = ---- = 96.8 B 2 LC = 1 In a practical LC resonant circuit, the range of Q for 13.56 MHz band is about 40. However, the Q can be significantly increased with a ferrite core inductor. The system designer must consider the above limits for optimum operation. This is called a resonance condition, and the resonance frequency is given by: EQUATION 37: 1 f 0 = -----------------2 LC RESONANT CIRCUITS Once the frequency and the inductance of the coil are determined, the resonant capacitance can be calculated from: By applying Equation 36 into Equation 35, the impedance at the resonance frequency becomes: EQUATION 38: EQUATION 34: 1 C = ----------------------2 L ( 2f o ) In practical applications, parasitic (distributed) capacitance is present between turns. The parasitic capacitance in a typical tag antenna coil is a few (pF). This parasitic capacitance increases with operating frequency of the device. There are two different resonant circuits: parallel and series. The parallel resonant circuit has maximum impedance at the resonance frequency. It has a minimum current and maximum voltage at the resonance frequency. Although the current in the circuit is minimum at the resonant frequency, there are a circulation current that is proportional to Q of the circuit. The parallel resonant circuit is used in both the tag and the high-power reader antenna circuit. On the other hand, the series resonant circuit has a minimum impedance at the resonance frequency. As a result, maximum current is available in the circuit. Because of its simplicity and the availability of the high current into the antenna element, the series resonant circuit is often used for a simple proximity reader. 2001 Microchip Technology Inc. Z = R where R is the load resistance. FIGURE 20: PARALLEL RESONANT CIRCUIT R C L The R and C in the parallel resonant circuit determine the bandwidth, B, of the circuit. EQUATION 39: 1 B = --------------2RC ( Hz ) The quality factor, Q, is defined by various ways such as DS00710B-page 89 AN710 EQUATION 40: EQUATION 42: Energy Stored in the System per One Cycle Q = -----------------------------------------------------------------------------------------------------------------Energy Dissipated in the System per One Cycle . V o = 2f o NQSB o cos C = 2f 0 N R ---- SB 0 cos L reac tan ce = --------------------------resis tan ce L = ------r For inductance 1 = --------cr For capacitance The above equation indicates that the induced voltage in the tag coil is inversely proportional to the square root of the coil inductance, but proportional to the number of turns and surface area of the coil. Series Resonant Circuit A simple series resonant circuit is shown in Figure 21. The expression for the impedance of the circuit is: f0 = ---B EQUATION 43: Z ( j ) = r + j ( XL - XC ) where: = () 2f = angular frequency fo = resonant frequency B = bandwidth r = ohmic losses where: r = a DC ohmic resistance of coil and capacitor XL and XC = the reactance of the coil and capacitor, respectively, such that: By applying Equation 37 and Equation 39 into Equation 40, the Q in the parallel resonant circuit is: X L = 2fo L EQUATION 41: C Q = R ---L The Q in a parallel resonant circuit is proportional to the load resistance R and also to the ratio of capacitance and inductance in the circuit. When this parallel resonant circuit is used for the tag antenna circuit, the voltage drop across the circuit can be obtained by combining Equations 8 and 41: DS00710B-page 90 EQUATION 44: () EQUATION 45: 1 Xc = --------------2f o C () The impedance in Equation 43 becomes minimized when the reactance component cancelled out each other such that X L = X C . This is called a resonance condition. The resonance frequency is same as the parallel resonant frequency given in Equation 37. 2001 Microchip Technology Inc. AN710 FIGURE 21: SERIES RESONANCE CIRCUIT r C When the circuit is tuned to a resonant frequency such as XL = XC, the voltage across the coil becomes: EQUATION 48: Eo Ein jXL V o = -------- Vin r L 13.56 MHz = jQVin The half power frequency bandwidth is determined by r and L, and given by: EQUATION 46: r B = ---------2L ( Hz ) The quality factor, Q, in the series resonant circuit is given by: The above equation indicates that the coil voltage is a product of input voltage and Q of the circuit. For example, a circuit with Q of 40 can have a coil voltage that is 40 times higher than input signal. This is because all energy in the input signal spectrum becomes squeezed into a single frequency band. EXAMPLE 8: CIRCUIT PARAMETERS If the DC ohmic resistance r is 5 , then the L and C values for 13.56 MHz resonant circuit with Q = 40 are: EQUATION 49: f0 L 1 Q = ---- = ------- = ----------B r rC The series circuit forms a voltage divider, the voltage drops in the coil is given by: EQUATION 47: X L = Qr s = 200 XL 200 L = -------- = -------------------------------------- = 2.347 2f 2 ( 13.56MHz ) ( H ) 1 1 C = --------------- = ----------------------------------------------------- = 58.7 (pF) 2fXL 2 ( 13.56 MHz ) ( 200 ) jX L Vo = ------------------------------- Vin r + jX L - jX c 2001 Microchip Technology Inc. DS00710B-page 91 AN710 TUNING METHOD * S-parameter or Impedance Measurement Method using Network Analyzer: a) Set up an S-Parameter Test Set (Network Analyzer) for S11 measurement, and do a calibration. b) Measure the S11 for the resonant circuit. c) Reflection impedance or reflection admittance can be measured instead of the S11. d) Tune the capacitor or the coil until a maximum null (S11) occurs at the resonance frequency, fo. For the impedance measurement, the maximum peak will occur for the parallel resonant circuit, and minimum peak for the series resonant circuit. The circuit must be tuned to the resonance frequency for a maximum performance (read range) of the device. Two examples of tuning the circuit are as follows: * Voltage Measurement Method: a) Set up a voltage signal source at the resonance frequency. b) Connect a voltage signal source across the resonant circuit. c) Connect an Oscilloscope across the resonant circuit. d) Tune the capacitor or the coil while observing the signal amplitude on the Oscilloscope. e) Stop the tuning at the maximum voltage. FIGURE 22: VOLTAGE VS. FREQUENCY FOR RESONANT CIRCUIT V f fo FIGURE 23: FREQUENCY RESPONSES FOR RESONANT CIRCUIT Z S11 fo (a) f Z f fo f fo (b) (c) Note 1: (a) S11 Response, (b) Impedance Response for a Parallel Resonant Circuit, and (c) Impedance Response for a Series Resonant Circuit. 2: In (a), the null at the resonance frequency represents a minimum input reflection at the resonance frequency. This means the circuit absorbs the signal at the frequency while other frequencies are reflected back. In (b), the impedance curve has a peak at the resonance frequency. This is because the parallel resonant circuit has a maximum impedance at the resonance frequency. (c) shows a response for the series resonant circuit. Since the series resonant circuit has a minimum impedance at the resonance frequency, a minimum peak occurs at the resonance frequency. DS00710B-page 92 2001 Microchip Technology Inc. AN710 READ RANGE OF RFID DEVICES The read range of 13.56 MHz is relatively longer than that of 125 kHz device. This is because the antenna efficiency increases as the frequency increases. With a given operating frequency, the conditions (a - c) are related to the antenna configuration and tuning circuit. The conditions (d - e) are determined by a circuit topology of reader. The condition (f) is a communication protocol of the device, and (g) is related to a firmware software program for data detection. Read range is defined as a maximum communication distance between the reader and tag. In general, the read range of passive RFID products varies, depending on system configuration and is affected by the following parameters: a) b) c) d) e) f) g) h) Operating frequency and performance of antenna coils Q of antenna and tuning circuit Antenna orientation Excitation current Sensitivity of receiver Coding (or modulation) and decoding (or demodulation) algorithm Number of data bits and detection (interpretation) algorithm Condition of operating environment (electrical noise), etc. Assuming the device is operating under a given condition, the read range of the device is largely affected by the performance of the antenna coil. It is always true that a longer read range is expected with the larger size of the antenna with a proper antenna design. Figures 24 and 25 show typical examples of the read range of various passive RFID devices. FIGURE 24: READ RANGE VS. TAG SIZE FOR TYPICAL PROXIMITY APPLICATIONS* Tag 0.5-inch diameter s che n i .5 ~1 1-inch diameter Tag 4 inches 3 x 6 inch Reader Antenna Q tag 40 2-inch diameter 5 ~ 6 inches Tag 6 ~ 7 inc hes 2-inch x 3.5-inch" Tag (Credit Card Type) FIGURE 25: READ RANGE VS. TAG SIZE FOR TYPICAL LONG RANGE APPLICATIONS* 0.5-inch diameter Q tag 40 Tag 7~ n 9i es ch 1 20 x 55 inch Long Range Reader 1-inch diameter hes 1 inc 4~2 Tag 2-inch diameter 25 ~ 30 inches 35 ~ 4 0 inch Tag es Tag Note: 2-inch" x 3.5-inch (Credit Card Type) Actual results may be shorter or longer than the range shown, depending upon factors discussed above. 2001 Microchip Technology Inc. DS00710B-page 93 AN710 REFERENCES [1] V. G. Welsby, The Theory and Design of Inductance Coils, John Wiley and Sons, Inc., 1960. [2] Frederick W. Grover, Inductance Calculations Working Formulas and Tables, Dover Publications, Inc., New York, NY., 1946. [3] Keith Henry, Editor, Radio Engineering Handbook, McGraw-Hill Book Company, New York, NY., 1963. [4] James K. Hardy, High Frequency Circuit Design, Reston Publishing Company, Inc.Reston, Virginia, 1975. DS00710B-page 94 2001 Microchip Technology Inc. M MCRF355/360 REFERENCE DESIGN MCRF355/360 Reader Reference Design 1.0 INTRODUCTION 2.0 This chapter provides a reference guide for the 13.56 MHz reader designer. The schematic included in this chapter is for the 13.56 MHz Reference Reader included in the DV103003 microIDTM Developer's Kit. The circuit is designed for short read-range applications. The basic design can be modified for long-range or other applications with MCRF355/360 devices. An electronic copy of the PICmicro(R) microcontroller source code is available upon request. READER CIRCUITS The RFID reader consists of transmitting and receiving sections. It transmits a carrier signal (13.56 MHz), receives the backscattered signal from the tag, and performs data processing. The reader also communicates with an external host computer. A basic block diagram of a typical RFID reader is shown in Figure 2-1. The transmitting section contains a 13.56 MHz signal oscillator (74HC04), power amplifier (Q2), and RF tuning circuits. The tuning circuit matches impedance between the antenna coil circuit and the power driver at 13.56 MHz. The radiating signal strength from the antenna must comply with government regulations. For best performance, the antenna coil circuit must be tuned to the same frequency of the tag. The design for antenna circuits is given in Application Note AN710 (DS00710). The receiving section contains an envelope detector (D6), hi-pass filters, and amplifiers (U2 and U3). When the tag is energized, it transmits 154 bits of data that is encoded in Biphase-L (Manchester). In the Manchester encoding, data `1' is represented by a logic high-to-low level change at midclock, and data `0' is represented by a low-to-high level change at midclock. There is always a level change at middle of every bit clock. FIGURE 2-1: FUNCTIONAL BLOCK DIAGRAM OF TYPICAL RFID READER 13.56 MHz Signal Oscillator Power Amplifier Microcontroller Filter and Amplifier Tuning Circuit Envelope Detector Ant. Coil Serial Interface (RS-232) Host Computer 2001 Microchip Technology Inc. DS21311B-page 95 MCRF355/360 REFERENCE DESIGN FIGURE 2-2: SIGNAL WAVEFORMS ` 1' ` 1' `0' `1' ` 0' 14.285 s Tag Data Signal ... Signal Waveform in Reader Coil t After Envelope Detector t After Pulse Shaping t FIGURE 2-3: BIPHASE-L (MANCHESTER) SIGNAL V V t (a) Data `1' DS21311B-page 96 t (b) Data `0' 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN When the tag is energized by the reader's carrier signal, it transmits back with an amplitude modulated signal. This results in a perturbation in the voltage amplitude across the reader antenna coil. The envelope detector detects the changes in the voltage amplitude and passes it into an RC filter (R7, C11). The charged signal in the capacitor passes through active filters and amplifiers. The signal that is passing through this receiving section is the data signal. This filteredshaped data signal is fed into Pin 10 of the microcontroller for data processing. 2.1 FCC Specifications on Transmitting Signal 3.0 The reader circuit provided is designed for about a 5-inch read-range, using a 2-inch by 2-inch tag coil that is printed on PCB with the MCRF355. The read-range can be increased by increasing the reader power, sensitivity, and antenna size. A read-range of more than 30-inches can be achieved with the MCRF355 and an optimized reader. In order to optimize the reader circuit for long-range applications, the following aspects may be considered: 1. Each country limits the signal strength of the radio frequency signal that is intentionally radiated from the device. In the USA, the maximum signal strength that is radiated from the device is regulated by Federal Communication Commission (FCC). Any device operating at 13.56 MHz frequency band must comply with the FCC Part 15.225 of the federal regulation. FCC limits for 13.56 MHz frequency band are al follows: 1. 2. 3. 4. Tolerance of the carrier frequency: 13.56 MHz +/- 0.01% = +/- 7 kHz. Frequency bandwidth: +/- 7 kHz. Power level of fundamental frequency: 10 mv/m at 30 meters from the transmitter. Power level for harmonics: -50.45 dB down from the fundamental signal. The transmission circuit including the antenna coil must be designed to meet the FCC limits. OPTIMIZATION FOR LONGRANGE APPLICATIONS 2. 3. Optimize the output power level within FCC limits. The reader should provide a sufficient signal level to the tag. The tag needs about 4 VPP across the coil circuit for operation. The power level radiating from the reader antenna must comply to the government regulations such as FCC specifications in the USA. The FCC limits for 13.56 MHz band are described in Section 2.1. For long-range applications, the designer may start with about 50 VPP of antenna voltage and optimize the signal strength for a read-range within the government regulations. Increase the size of the antenna. The readrange, in general, is proportional to the size of the reader coil (see Equation 12 in Application Note 710). An optimum radius of antenna is 1.414 times of the read-range. Increase the Q of the antenna circuit. The read-range increases with Q of the antenna circuit. This is because the induced voltage is directly proportional to Q of the circuit. The recommended Q for long-range applications is as follows: 40 < Q < 96 40 < Q 2001 Microchip Technology Inc. for reader for tag DS21311B-page 97 MCRF355/360 REFERENCE DESIGN 4. 5. Optimize the input sensitivity of the reader. The sensitivity is a measure of how weak a signal can be and still be satisfactorily received. The sensitivity is proportional to the carrier power and square of the modulation index (1 for 100% modulation such as MCRF355). It is inversely proportional to the noise signal. The limit to the sensitivity of the receiving section of the reader is noise, both external and internal. The external noises may come from various sources such as computers, televisions, appliances, motors, power lines, transformers, etc. The internal noise is mostly due to a thermal noise of components. To reduce noise, the reader should be operated a distance away from the noise sources. The receiving section may have a 70 kHz bandpass filter to reduce the noises. The 70 kHz bandpass filter will pass only the 70 kHz data signal for processing. The receiving section should have sensitivity of about -120 dBm for long-range applications. Optimize the amplitude gain circuit. The receiving circuit amplifies the modulated signals before data processing. The input signal contains both real data and noise. Typically, op amplifiers are used for both as a gain amplifier and filter. The gain must be optimized within the circuit to obtain gains only at the real data signal. DS21311B-page 98 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN 4.0 READER SCHEMATIC 2001 Microchip Technology Inc. DS21311B-page 99 MCRF355/360 REFERENCE DESIGN 5.0 READER BILL OF MATERIALS Assembly # Line # Qty Part # 02-01523 1 1 02-01523-D 02-01523 2 1 02-01523 3 02-01523 Part Description Reference Designator PCB ASSY DWG, MCRF355 microID READER -- 03-01523 SCHEMATIC, MCRF355 microID READER -- 1 04-01523 PCB FABRICATION, MCRF355 microID READER -- 4 2 MM74HC04M IC, SMT, CMOS HEX INVERTER, 14P SOIC U1, U8 02-01523 5 1 LF347M IC, SMT, QUAD BI-FET OP AMP, 14P SOIC U2 02-01523 6 1 LM339M IC, SMT, LOW POWER LOW OFFSET VOLT QUAD COMPARATORS,14P SOIC U3 02-01523 7 1 02-01523 8 1 LM78L05ACM IC, REG, +5V 100 mA REGULATOR U5 02-01523 9 1 LM78L12ACM IC, REG, +12V 100 mA REGULATOR U6 02-01523 10 1 L7809CD2T IC, +9V, REG 1.5A TO-263 U7 02-01523 11 1 MMBT2907ALT1 TRANSISTOR, PNP, 2N2907A, SOT-23 Q1 Flip upside and bend legs toward the PCB 02-01523 12 1 IRL510 TRANSISTOR, N-CHANNEL HEX FET, TO220AB Q2 02-01523 13 6 RLS4148TE11C DIODE SMT, ROHM DIODE LL-34 SIG DIODE D1-D6 02-01523 14 1 ERJ-3GSYJ332V RES SMT, 3.3K OHM, 1/16W, 5%, 0603 R1 PIC16C558-20/SO IC, PIC16C558-20/SO EPROM-BASED 8-BIT CMOS MICROCONTROLLER U4 02-01523 15 1 ERJ-3GSYJ182V RES SMT, 1.8K OHM, 1/16W, 5%, 0603 R2 02-01523 16 5 ERJ-3GSYJ103V RES SMT, 10K OHM, 1/16 W, 5%, 0603 R3, R6, R15, R16, R21 02-01523 17 1 ERJ-3GSYJ223V RES SMT, 22K OHM, 5% 0603 R4 02-01523 18 1 ERJ-3GSYJ104V RES SMT, 100K OHM 1/16W 5% TYPE 0603 R5 02-01523 19 1 ERJ-3GSYJ681V RES SMT, 680 OHM 1/16W 5% 0603 R7 02-01523 20 3 ERJ-3GSYJ102V RES SMT, 1K OHM 1/16W 5% 0603 R8-R10 02-01523 21 1 ERJ-3GSYJ303V RES SMT, 30K OHM 1/16W 5% 0603 R11 02-01523 22 1 ERJ-3EKF7151V RES SMT, 7.15K OHM 1/16W 1% 0603 02-01523 23 1 MFR-25FRF 14K0 RES, 14K OHM 1/4W 1% MF 02-01523 24 2 RM73B1JT106J R12 R13, connected from U2 pin 12 to top pad of R13 RES SMT, 10M OHM 1/16W 5% 0603 R17, R20 02-01523 25 2 ERJ-3GSYJ100V RES SMT, 10 OHM 1/16W 5% 0603 R18, R19 02-01523 26 1 EVM-7JSX30B13 RES SMT, POT, 1K OHM 3MM SEALED, 3 TT VR1 02-01523 27 12 ECU-V1H104KBW CAP SMT, 0.1uF 50V 10%, X7R CER 1206 C1, C2, C12, C13, C16-18, C23-C26, C29 02-01523 28 3 ECU-V1H220JCV CAP SMT, 22 pF CERAMIC 5% 50V 0603 NPO C3, C4, C28 02-01523 29 2 ECU-V1H102KBV CAP SMT, 1000 pF 50V CERAMIC 10% 0603 X7R C6, C11 DS21311B-page 100 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN Assembly # Line # Qty Part # Part Description Reference Designator 02-01523 30 1 ECU-V1H271JCV CAP SMT, 270 pF 50V CERAMIC 5% 0603 NPO C7 02-01523 31 1 ECU-V1H152KBV CAP SMT, 1500 pF 50V CERAMIC 10% 0603 X7R C8 02-01523 32 1 GRM42CAP SMT, 470 pF 500V 2% 1206 C0G" 6C0G471G500AL C9 02-01523 33 1 GRM426C0G121J500AL C10 02-01523 34 2 ECU-V1H272KBV CAP SMT, 2700PF 50V CERAMIC 10% 0603 XR7 02-01523 35 4 ECE-A1EU220 02-01523 36 1 02-01523 37 1 02-01523 38 2 43LS477 INDUCTOR, 0.47 H L1, L2 02-01523 39 1 MCX0001 OSCILLATOR, CUSTOM 13.560 MHz, PARALLEL MODE, 22 pF LOAD, HC49 CASE, 30 PPM X1 02-01523 40 1 MDC-096 CONN, MINI-DIN, 6-PIN P1 02-01523 41 1 KF22-E9S-NJ CONN, D-SUB 9P RECPT RT ANGLE WITH JACK SCREWS DB9 02-01523 42 1 08-00170 LABEL, MCRF355 READER FIRMWARE, 355READ.HEX, 1/25/99, U4 @ U4 02-01523 43 1 ERJ-3GSYJ511V RES SMT, 510 OHM 1/16W 5% 0603 R14 2001 Microchip Technology Inc. CAP SMT, 120 pF 500V 5% 1206 C0G" C14, C15 CAP, 22UF 25V RADIAL ELECTROLYTIC 20% C19-C22 GRM426C0G100J500AL CAP SMT, 10 pF 500V 5% 1206 C0G C30 GRM426C0G220J500AL CAP SMT, 22 pF 500V 5% 1206 C0G C31 (AS NEEDED) DS21311B-page 101 MCRF355/360 REFERENCE DESIGN Software License Agreement The software supplied herewith by Microchip Technology Incorporated (the "Company") for its PICmicro(R) Microcontroller is intended and supplied to you, the Company's customer, for use solely and exclusively on Microchip PICmicro Microcontroller products. The software is owned by the Company and/or its supplier, and is protected under applicable copyright laws. All rights are reserved. Any use in violation of the foregoing restrictions may subject the user to criminal sanctions under applicable laws, as well as to civil liability for the breach of the terms and conditions of this license. THIS SOFTWARE IS PROVIDED IN AN "AS IS" CONDITION. NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. THE COMPANY SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. 6.0 READER SOURCE CODE FOR THE PICmicro(R) MCU ;receiver.asm ;Processor: PIC16C558 operating at 13.56 MHz ; Ti= 295 nsec processor 16c558 #include "P16c558.inc" __config h'3ff2' ;protection off,PWRT enabled,watchdog disabled,HS oscillator #define _CARRY #define _ZERO STATUS,0 STATUS,2 #define _125KHZ PORTA,1 #define _RS232TX PORTA,2 #define _RS232RX PORTA,3 #define _RS232 PORTA #define SIGNAL PORTB,4 invmask = h'2' ;................................................................ ;Define variables and constants here-delay =h'20' wait =h'21' acctime =h'22' ;accumulated sync interval sum--also used as halfbit interval threshold #define halfthr acctime ;halfbit interval threshold halfthr =acctime ;halfbit interval threshold recv_csumhi =h'23' ;2 bytes for storing received checksum recv_csumlo =h'24' bitcnt =h'25' ;RS232 bit counter cycle_cnt =h'26' halfthr =h'27' ;threshold value between halfbit and fullbit intervals ptr1 =h'28' ;temporary FSR storage ptr2 =h'29' ;temporary FSR storage TXchar =h'2a' ;character to transmit over RS232 temp =h'2b' ;temporary storage shiftcnt =h'2c' ;used to strip the framing `0' bits from the rec'd data array letters =h'2d' ;storage area for next character to send charcnt =h'2e' lastbit =h'2f' ;the LSb stores the last rec'd bit--flip it by complementing f ;;;!!!!!!!!!!!!!!!!!!!!!bit storage area--16 bytes of storage, indirectly addressed ;;;Note that s/w tests for MSb to detect end of area--be careful if move to different ;;;processor or relocate this storage area recvbits =h'40' ;32 bytes set aside for storing the received bits--actual number of bytes ;in transmission is 18 ;;Note that main loop uses bit tests to determine bit receive or runaway condition (to limit ;;processing time). Keep this in mind if recvbits storage area changed in the future. DS21311B-page 102 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN ;;40h-60h is reserved for received bits--actual bit receiving area 40h-51h, rest is overrun area ;;52h-73h ;;52h-60h ;; ;; ;; ;; ;; sendascii xfercnt set aside for ASCII conversion of received bytes before RS232 transmission. Note that contains no useful information from the use during receive of demodulated bits. Also, bits are not being received while the ASCII conversion and serial transmission are taking place. `G' 1st character: "go" Character 2-37: ASCII representation of received 18 bytes (until checksum used) Character 38: `\n' newline =h'52' =d'14' ;begin of storage area for ASCII conversion of received bytes ;defines number of received bytes to convert to ASCII & transmit ;........................................................................ ;............................................................................................ ;Overall function- To recover Manchester encoded RFID message after AM demodulation and ; comparator decision. The comparator input trips the interrupt on PORTB change. ;The steps are: ; ; 1- Initialize registers to seek synch field. ; 2- Determine bit width from synch field by averaging the periods between transitions ; over the synch field. TMR0 is cleared at each edge. If the timer overflows before ; the next edge, synch seek starts over. The synch field is composed of 9 bits. ; 3- Use the measured bit width to establish a threshold period between repeat bits and ; complement of previous bit. This is due to the Manchester encoding method. Since there ; is always a transition in the middle of each bit interval transmitted, a repeated bit ; will appear as a pair of edges that occur with a halfbit interval period. A bit that ; is the complement of the last received bit will appear as an interval between edges ; of a full bit interval period. ; 4- Shift in bits as they are received into the storage array. When the timer overflows, ; consider the data field over. The received data format is MSb to LSb, where the MSb ; is the first bit received. ; 5- There are 16 bytes in the message, followed by a 16 bit checksum of the message ; contents. The remaining bit is unused. ; 6- Compute the checksum of the received 16 byte message and compare to the received ; checksum. ; 7- If checksums match, convert the message and the checksum into ASCII form and transmit ; over the RS232 serial link. The message format is: ; "GG" :the go characters (start of message) ; 36 bytes which are the ASCII representation of the 18 bytes received ; "\n" : closing newline character ; The serial data rate is 9600 bps, 8 data bits, 1 stop, no parity ;............................................................................... org h'000' goto init org h'004' ;RESET vector location ;interrupt vector location ;========================================================================================== ;;isr(): interrupt service routine ; interrupts enabled for transition on PORTB ; ; 1- BEWARE! To minimize interrupt response time, the w & status register are NOT ; archived. ; 2- The isr execution path is determined by w register and uses calculated goto's. ; The w for next isr is set at end of current isr execution and is dependent on ; signal context (i.e. sync start, w/in sync, w/in data, etc.) ; Be very cautious here--must stay w/in 255 instructions for this to work! ; 3- Sync field processed as follows: ; -Ignore the first 4 transitions, they may be in response to tag power on reset ; -Accumulate the sum of next 8 intervals ; -Establish half bit width from full bit width threshold value based on ; average interval measured above. Due to Manchester encoding, repeat of previous 2001 Microchip Technology Inc. DS21311B-page 103 MCRF355/360 REFERENCE DESIGN ; bit will be a series of 2 halfbit width intervals, complement of previous bit ; will be a fullbit width interval. halfbit defined as 1.5x(average sync). ; -wait for interval over the fullbit threshold. This is end of sync. In accordance ; w/ Manchester encoding, the sync field will be: 1 1 1 1 1 1 1 1 0 ;========================================================================================== isr addwf PCL,f ;4 calculated goto ;first sync edge is calculated goto here clrf TMR0 ;5 movf PORTB,f ;6 must read PORTB before clearing RBIF bcf INTCON,RBIF ;7 just in case timer interrupt happened just at 1st edge bcf INTCON,T0IF ;8 movlw (first_cycle - isr-d'1') ;9 next isr calculated goto offset clrf lastbit ;10 lastbit @ end of sync = 0 retfie ;12 ;end of first cycle here. Note that first 4 transitions are ignored, because sync start is ;corrupted by tag power on reset. first_cycle clrf TMR0 ;5 movf PORTB,f ;6 must read PORTB before clearing RBIF bcf INTCON,RBIF ;7 movlw (second_cycle - isr-d'1') ;8 next isr calculated goto offset retfie ;10 ;end of 2nd cycle here. Note that first 4 transitions are ignored, because sync start is ;corrupted by tag power on reset. second_cycle clrf TMR0 ;5 movf PORTB,f ;6 must read PORTB before clearing RBIF bcf INTCON,RBIF ;7 movlw recvbits ;8 movwf FSR ;9 set up to store data bits movlw (third_cycle - isr-d'1') ;10 next isr calculated goto offset retfie ;12 ;end of 3rd cycle here. Note that first 4 transitions are ignored, because sync start is ;corrupted by tag power on reset. The 3rd cycle is the 4th transition, so from here we measure ;the longest interval in sync field. third_cycle clrf TMR0 ;5 movf PORTB,f ;6 must read PORTB before clearing RBIF bcf INTCON,RBIF ;7 clrf acctime ;8 reset accumulated sync interval for average movlw (fourth_cycle - isr-d'1') ;9 next isr calculated goto offset retfie ;11 ;end of 4th cycle here. Start looking for longest sync interval here. fourth_cycle movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 addwf acctime,f ;9 first measured sync cycle, must be the largest movlw (fifth_cycle - isr-d'1') ;10 retfie ;12 ;end of 5th cycle here. fifth_cycle movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 addwf acctime,f ;9 acctime = acctime + TMR0 movlw (sixth_cycle - isr-d'1') ;10 retfie ;12 ;end of 6th cycle here. sixth_cycle movf TMR0,w ;5 clrf TMR0 ;6 DS21311B-page 104 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN movf PORTB,f ;7 bcf INTCON,RBIF ;8 addwf acctime,f ;9 acctime = acctime + TMR0 movlw (seventh_cycle - isr-d'1') ;10 retfie ;12 ;end of 7th cycle here. seventh_cycle movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 addwf acctime,f ;9 acctime = acctime + TMR0 movlw (eighth_cycle - isr-d'1') ;10 retfie ;12 ;end of 8th cycle here. eighth_cycle movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 addwf acctime,f ;9 acctime = acctime + TMR0 movlw (nineth_cycle - isr-d'1') ;10 retfie ;12 ;end of 9th cycle here. nineth_cycle movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 addwf acctime,f ;9 acctime = acctime + TMR0 movlw (tenth_cycle - isr-d'1') ;10 retfie ;12 ;end of 10th cycle here. tenth_cycle movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 addwf acctime,f ;9 acctime = acctime + TMR0 movlw (eleventh_cycle - isr-d'1') ;10 retfie ;12 ;end of 11th cycle here. --this is last of sync cycles to be accumulated. Average the result ;and determine halfbit threshold in remaining sync cycles. eleventh_cycle movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 addwf acctime,f ;9 acctime = acctime + TMR0 movlw (twelfth_cycle - isr-d'1') ;10 retfie ;12 ;end of 12th cycle here. Start averaging the sync interval accumulated time twelfth_cycle movf PORTB,f ;5 bcf INTCON,RBIF ;6 rrf acctime,f ;7 acctime/2 rrf acctime,f ;8 acctime/4 rrf acctime,f ;9 avg interval = acctime/8 movlw h'1f' ;10 clear 3 MSbs that may have been set by carry andwf acctime,f ;11 movlw (cycle13 - isr-d'1') ;12 retfie ;14 ;end of 13th cycle here. Calculate the halfbit threshold = 1.5(sync interval avg) Note that ;that the threshold value will be kept in acctime (=halfthr) cycle13 2001 Microchip Technology Inc. DS21311B-page 105 MCRF355/360 REFERENCE DESIGN clrf movf bcf rrf addwf incf movlw bsf retfie TMR0 PORTB,f INTCON,RBIF acctime,w acctime,f acctime,f (sync_end PCLATH,0 ;5 ;6 ;7 ;8 half the sync interval avg ;9 halfthr = 1+1.5x(sync interval avg) ;10 h'100'-h'1'-isr) ;11 ;12 adjust for origin @ 100h ;14 org h'100' ;sync end wait. End of sync is distinguished by a fullbit interval. ( T > halfthr ) sync_end movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to detect end of sync field (halfthr - w) movlw (sync_end - h'100'-isr-d'1') ;10 btfss STATUS,C ;12 Carry set for halfthr >= w movlw (bit1 - h'100'-isr-h'1');12 If T > halfbit, end of sync detected. Proceed to data processing retfie ;14 ;rec'd bit processing here --bit1 is 1st bit of 8 bit block bit1 movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to determine bit. C = 1 for repeated bit btfsc STATUS,C ;11 goto halfabit1 ;12 ;fullbit processing here comf lastbit,f ;12 Complement lastbit for fullbit measurement rrf lastbit,w ;13 rlf INDF,f ;14 shift in the new bit movlw (bit2 - h'100'-isr-h'1') ;15 retfie ;17 halfabit1 ;repeated bit (1 of 8) rrf lastbit,w ;13 rlf INDF,f ;14 movlw (half21-h'100'-isr-h'1') ;15 retfie ;17 ;2nd half of bit interval processing half21 ;2nd half, bit1 clrf TMR0 ;5 movf PORTB,f ;6 bcf INTCON,RBIF ;7 movlw (bit2-h'100'-isr-h'1');8 retfie ;10 ;rec'd bit processing here --bit2 is 2nd bit of 8 bit block bit2 movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to determine bit. C = 1 for repeated bit btfsc STATUS,C ;11 goto halfabit2 ;12 ;fullbit processing here comf lastbit,f ;12 Complement lastbit for fullbit measurement rrf lastbit,w ;13 rlf INDF,f ;14 shift in the new bit DS21311B-page 106 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN movlw (bit3 - h'100'-isr-h'1') ;15 retfie ;17 halfabit2 ;repeated bit (2 of 8) rrf lastbit,w ;13 rlf INDF,f ;14 movlw (half22-h'100'-isr-h'1') ;15 retfie ;17 ;2nd half of bit interval processing half22 ;2nd half, bit2 clrf TMR0 ;5 movf PORTB,f ;6 bcf INTCON,RBIF ;7 movlw (bit3-h'100'-isr-h'1');8 retfie ;10 ;rec'd bit processing here --bit3 is 3rd bit of 8 bit block bit3 movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to determine bit. C = 1 for repeated bit btfsc STATUS,C ;11 goto halfabit3 ;12 ;fullbit processing here comf lastbit,f ;12 Complement lastbit for fullbit measurement rrf lastbit,w ;13 rlf INDF,f ;14 shift in the new bit movlw (bit4 - h'100'-isr-h'1') ;15 retfie ;17 halfabit3 ;repeated bit (3 of 8) rrf lastbit,w ;13 rlf INDF,f ;14 movlw (half23-h'100'-isr-h'1') ;15 retfie ;17 ;2nd half of bit interval processing half23 ;2nd half, bit3 clrf TMR0 ;5 movf PORTB,f ;6 bcf INTCON,RBIF ;7 movlw (bit4-h'100'-isr-h'1');8 retfie ;10 ;rec'd bit processing here --bit4 is 4th bit of 8 bit block bit4 movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to determine bit. C = 1 for repeated bit btfsc STATUS,C ;11 goto halfabit4 ;12 ;fullbit processing here comf lastbit,f ;12 Complement lastbit for fullbit measurement rrf lastbit,w ;13 rlf INDF,f ;14 shift in the new bit movlw (bit5 - h'100'-isr-h'1') ;15 retfie ;17 halfabit4 ;repeated bit (4 of 8) rrf lastbit,w ;13 rlf INDF,f ;14 movlw (half24-h'100'-isr-h'1') ;15 retfie ;17 ;2nd half of bit interval processing 2001 Microchip Technology Inc. DS21311B-page 107 MCRF355/360 REFERENCE DESIGN half24 ;2nd half, bit4 clrf TMR0 ;5 movf PORTB,f ;6 bcf INTCON,RBIF ;7 movlw (bit5-h'100'-isr-h'1');8 retfie ;10 ;rec'd bit processing here --bit5 is 5th bit of 8 bit block bit5 movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to determine bit. C = 1 for repeated bit btfsc STATUS,C ;11 goto halfabit5 ;12 ;fullbit processing here comf lastbit,f ;12 Complement lastbit for fullbit measurement rrf lastbit,w ;13 rlf INDF,f ;14 shift in the new bit movlw (bit6 - h'100'-isr-h'1') ;15 retfie ;17 halfabit5 ;repeated bit (5 of 8) rrf lastbit,w ;13 rlf INDF,f ;14 movlw (half25-h'100'-isr-h'1') ;15 retfie ;17 ;2nd half of bit interval processing half25 ;2nd half, bit5 clrf TMR0 ;5 movf PORTB,f ;6 bcf INTCON,RBIF ;7 movlw (bit6-h'100'-isr-h'1') ;8 retfie ;10 ;rec'd bit processing here --bit6 is 6th bit of 8 bit block bit6 movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to determine bit. C = 1 for repeated bit btfsc STATUS,C ;11 goto halfabit6 ;12 ;fullbit processing here comf lastbit,f ;12 Complement lastbit for fullbit measurement rrf lastbit,w ;13 rlf INDF,f ;14 shift in the new bit movlw (bit7 - h'100'-isr-h'1') ;15 retfie ;17 halfabit6 ;repeated bit (6 of 8) rrf lastbit,w ;13 rlf INDF,f ;14 movlw (half26-h'100'-isr-h'1') ;15 retfie ;17 ;2nd half of bit interval processing half26 ;2nd half, bit6 clrf TMR0 ;5 movf PORTB,f ;6 bcf INTCON,RBIF ;7 movlw (bit7-h'100'-isr-h'1') ;8 retfie ;10 ;rec'd bit processing here --bit7 is 7th bit of 8 bit block bit7 DS21311B-page 108 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to determine bit. C = 1 for repeated bit btfsc STATUS,C ;11 goto halfabit7 ;12 ;fullbit processing here comf lastbit,f ;12 Complement lastbit for fullbit measurement rrf lastbit,w ;13 rlf INDF,f ;14 shift in the new bit movlw (bit8 - h'100'-isr-h'1') ;15 retfie ;17 halfabit7 ;repeated bit (7 of 8) rrf lastbit,w ;13 rlf INDF,f ;14 movlw (half27-h'100'-isr-h'1') ;15 retfie ;17 ;2nd half of bit interval processing half27 ;2nd half, bit7 clrf TMR0 ;5 movf PORTB,f ;6 bcf INTCON,RBIF ;7 movlw (bit8-h'100'-isr-h'1') ;8 retfie ;10 ;rec'd bit processing here --bit8 is 8th bit of 8 bit block bit8 movf TMR0,w ;5 clrf TMR0 ;6 movf PORTB,f ;7 bcf INTCON,RBIF ;8 subwf halfthr,w ;9 Test interval to determine bit. C = 1 for repeated bit btfsc STATUS,C ;11 goto halfabit8 ;12 ;fullbit processing here comf lastbit,f ;12 Complement lastbit for fullbit measurement rrf lastbit,w ;13 rlf INDF,f ;14 shift in the new bit movlw (bit1 - h'100'-isr-h'1') ;15 incf FSR,f ;16 retfie ;18 halfabit8 ;repeated bit (8 of 8) rrf lastbit,w ;13 rlf INDF,f ;14 movlw (half28-h'100'-isr-h'1') ;15 retfie ;17 ;2nd half of bit interval processing half28 ;2nd half, bit8 clrf TMR0 ;5 movf PORTB,f ;6 bcf INTCON,RBIF ;7 movlw (bit1-h'100'-isr-h'1') ;8 incf FSR,f ;9 advance to next byte in recvbits storage array retfie ;11 ;The negative RS232 supply is generated by an inverter clocked at ~125 KHz by port pin RA1. ;first pump up the -5V, i.e. generate 125 KHz clock (T=8 usec, ~27 Ti) ;run for a total of 128 cycles before sending data ;put line at stop bit level alphabet 2001 Microchip Technology Inc. DS21311B-page 109 MCRF355/360 REFERENCE DESIGN clrwdt bcf INTCON,GIE movlw sendascii movwf FSR ;make sure interrupts are off movlw xfercnt ;# of ASCII represented received bytes to xfer addlw xfercnt ;x2 addlw h'3' ;plus 2 start character "G" and newline character at end movwf charcnt ;;set up registers in bank 1 bsf STATUS,RP0 ;point to bank 1 movlw h'8' movwf TRISA ;RA3 input, RA2-0 output movlw h'10' movwf TRISB ;RB7-5,3-0 output, RB4 input movlw b'00001100' ;set up timer option for internal clock, prescale-->watchdog/16 movwf OPTION_REG ;port B pullups enabled bcf STATUS,RP0 ;point back to bank 0 ;;done setting up registers in bank 1, back to bank 0 bsf _RS232TX ;default is mark mode call gen125khz ;start the test transmission sendA movf INDF,w movwf TXchar movlw d'8' movwf bitcnt ;stop bit last bsf _RS232TX call TX_RS232 ;stop bit = 3Ti call ;start bcf call call ti17 bit first _RS232TX TX_RS232 ti17 ;burn 17Ti (includes the 2Ti for the call) btfsc goto bcf goto TXchar,0 setbit _RS232TX nextbit ;1Ti ;3Ti bsf _RS232TX ;4Ti ;burn 17Ti (includes the 2Ti for the call, adjusts the bit timing) sendchar setbit nextbit call TX_RS232 rrf TXchar,f call ti10 decfsz bitcnt,f goto sendchar ;stop bit last bsf _RS232TX call TX_RS232 incf decfsz goto movlw movwf movlw movwf waiting call FSR,f charcnt,f inalpha d'255' charcnt d'10' bitcnt ;6Ti ;7Ti ;17Ti ;18Ti ;20Ti ;stop bit = 3Ti ;1 ;2 ;4 ti17 DS21311B-page 110 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN decfsz goto decfsz goto goto inalpha call goto charcnt,f waiting bitcnt,f waiting seekinit ti10 sendA ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;;subroutine--RS232 bit timing & 125 KHz voltage inverter maintenance ;; baud rate set to 9600 bps--this is a bit time of 104 usec ;; Timing for this subroutine: to104 loop is 5.605 usec, additional setup ;; overhead is 1.77 usec. If do 17 to104 loops, ;; that leaves 5.844 usec to make up in the calling ;; routine to meet 104 usec target. 5.844= 19.8 Ti ;; (20 Ti) ;; Note that 5.844 is not evenly divisible by the ;; instruction cycle time. Need to save one ;; instruction every 5th bit sent--w/ the stop & start ;; bit overhead, easier to save 2 extra instructions ;; every character sent (10 bits) ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;; TX_RS232 movlw d'17' ;time out 104 usec, Ti=295 nsec movwf wait to104 movlw invmask ;flip voltage inverter bit xorwf _RS232,f movlw d'4' movwf delay wait4usec decfsz delay,f ;4 usec is half inverter clock period goto wait4usec decfsz wait,f goto to104 movlw invmask xorwf _RS232,f nop nop nop return ;;================================================================================ ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;;subroutine--generates 128 cycles at ~125 KHz for the RS232 voltage inverter gen125khz movlw d'128' movwf cycle_cnt next125 bsf _125KHZ movlw d'4' movwf delay highside decfsz delay,f goto highside bcf _125KHZ movlw d'4' 2001 Microchip Technology Inc. DS21311B-page 111 MCRF355/360 REFERENCE DESIGN movwf delay lowside decfsz delay,f goto lowside decfsz cycle_cnt,f goto next125 return ;;end gen125khz subroutine;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;subroutine-ti17: burn 17 Ti--includes the 2Ti to call this subroutine ;; ti15: burn 15 Ti, including call ;; ti10: burn 10 Ti, including call ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ti17 movlw d'3' ;1 movwf delay ;2 burn9 decfsz delay,f goto burn9 ;11 clrwdt ;12 nop ;13 return ;15+2 for call ti17=17Ti ti15 movlw movwf d'3' delay ;1 ;2 burn9Ti decfsz delay,f goto burn9Ti return ;11 ;13+2 for call ti15=15Ti ti12 nop clrwdt ti10 goto dly1 ;2Ti goto dly2 ;4Ti dly1 dly2 goto leaveti10 ;6Ti leaveti10 return ;8Ti+2Ti=10Ti ;================= ;;initialization ;================= init ;1st set up the I/O configuration--note that setting PORTB 7,6,5,4,0 as outputs disables ;them as external interrupt sources. In this application PORTB-4 is utilized as an ;external interrupt source upon change of state. All other external interrupt sources are ;set as outputs to disable them as interrupts. ;;set up registers in bank bsf STATUS,RP0 movlw h'8' movwf TRISA movlw h'10' movwf TRISB movlw b'00001000' DS21311B-page 112 1 ;point to bank 1 ;RA3 input, RA2-0 output ;RB7-5,3-0 output, RB4 input ;set up timer option for internal clock, no prescaler 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN movwf OPTION_REG ;port B pullups enabled bcf STATUS,RP0 ;point back to bank 0 ;;done setting up registers in bank 1, back to bank 0 movlw HIGH isr movwf PCLATH ;setup for calculated goto's dependent on context when entering ;isr ;===================================================== ;;initialization for sync field search- done @ turn on & after data recovery complete (or failed) ;===================================================== seekinit clrwdt movlw d'19' movwf bitcnt ;clear the bit storage field movlw recvbits movwf FSR clrbits clrf INDF incf FSR,f decfsz bitcnt,f goto clrbits movlw recvbits movwf FSR ;start of the received bits field movf PORTB,w ;read PORTB before clearing INTCON to be sure RBIF=0 clrf INTCON clrf TMR0 ;================================================================================= ; From here on, the w register represents the PCL offset when answering the isr. ; It is to be used for no other purpose until interrupts are disabled. ;================================================================================= movlw d'0' clrf PCLATH bsf INTCON,RBIE ;enable portB change interrupt enable bsf INTCON,GIE ;global interrupts are now enabled. ;==================== ;;tag word search ;==================== ;The main loop monitors the T0IF flag to detect successfully received word (subject to ;checksum test). Tag word processing is isr driven. A calculated goto method is used for ;position context in tag word for speed. FOR THIS REASON, THE W REGISTER CANNOT BE USED ;BY THE MAIN LOOP! If the main loop detects a timer overflow, the w register is cleared to ;return processing to first sync edge search. ;Also, expect recvbits area to be @ 40h-52h while receiving data. The ptr will be tested to ;determine this bitwise (because w can't be used in the main loop). ;======================================================================================== seeksync bcf INTCON,RBIE movlw d'0' ;calculated goto offset for 1st sync edge processing clrf PCLATH clrf FSR ;FSR = 0 to indicate not gathering bits bsf INTCON,RBIE bcf INTCON,T0IF main clrwdt btfsc FSR,6 goto datamain ;receiving data, monitor progress btfsc INTCON,T0IF goto seeksync ;if TMR0 overflows w/o receiving bits, seeksync goto main ;check for done receiving bits using TMR0 overflow as indicator. Also test for overflow from ;proper bit storage area for runaway condition (non tag noise tripping comparator) datamain 2001 Microchip Technology Inc. DS21311B-page 113 MCRF355/360 REFERENCE DESIGN clrwdt btfsc INTCON,T0IF goto calc_checksum ;if timer overflows, calculate checksum of received data btfsc FSR,5 ;if bit 5 set, FSR > 5fh and has overrun its proper area. goto seeksync ;search for sync. goto datamain ;Data received at this point. Two processing tasks remain: ;1- the framing `0' bits must be removed from the received 14 data bytes and 16 bit checksum ;2- the checksum of the 14 data bytes must be calculated and compared to the received ; 16 bit checksum ;If checksums match, transmit data over RS232 link. calc_checksum clrf INTCON clrgie bcf INTCON,GIE btfsc INTCON,GIE ;make sure it's clear before proceeding goto clrgie movf PORTB,f clrf INTCON ;disable all interrupts while processing received data ;remove the framing `0' bits by bit shifting the data array left until all framing 0s are ;shifted out movlw d'17' movwf bitcnt movwf shiftcnt shiftout movlw recvbits+d'17' movwf FSR roll_left rlf INDF,f decf FSR,f decfsz shiftcnt,f goto roll_left ;rotate left shiftcnt # of bytes decfsz bitcnt,f goto next_RL goto framestripped ;bit shift left through the array (successively 1 byte less each time) next_RL movf bitcnt,w movwf shiftcnt goto shiftout framestripped ;1st check for all 0s in data--This is an illegal combination movlw recvbits movwf FSR movlw d'14' movwf bitcnt zerotest movf INDF,w btfss STATUS,Z goto nonzero decfsz bitcnt,f goto zerotest goto seekinit ;all zeros received. Ignore the message nonzero ;do 16 bit checksum of first 14 bytes received. It should match the last 2 bytes received. movlw recvbits movwf FSR movlw d'14' movwf bitcnt clrf recv_csumlo clrf recv_csumhi sumbytes DS21311B-page 114 2001 Microchip Technology Inc. MCRF355/360 REFERENCE DESIGN movf INDF,w addwf recv_csumlo,f btfsc STATUS,C incf recv_csumhi,f ;carry into high byte as necessary incf FSR,f ;point to next data byte decfsz bitcnt,f goto sumbytes ;now compare the received checksum w/ the calculated checksum. Transmit data if they match. movf recv_csumhi,w subwf INDF,f btfss STATUS,Z goto seekinit incf FSR,f ;point to received checksum LSB movf recv_csumlo,w subwf INDF,f btfss STATUS,Z goto seekinit ;message passes checksum. Convert to ASCII and transmit. ;now convert to ASCII form movlw recvbits movwf ptr1 ;keep track of where in conversion movlw sendascii movwf ptr2 movwf FSR movlw "G" movwf INDF incf ptr2,f incf FSR,f movwf INDF ;double "G" to indicate start incf ptr2,f ;next ascii character movlw xfercnt ;how many bytes to convert to ASCII movwf bitcnt movlw h'4' movwf PCLATH ;set up PCLATH for lookup table asciiconv movf ptr1,w movwf FSR swapf INDF,w andlw h'f' ;isolate the MSN call hex2ascii movwf temp ;hold the ASCII character movf ptr2,w movwf FSR movf temp,w ;store ASCII representation of received byte MSN movwf INDF incf ptr2,f ;advance ASCII ptr movf ptr1,w ;back to received bytes movwf FSR movf INDF,w andlw h'f' ;isolate the LSN call hex2ascii movwf temp movf ptr2,w movwf FSR movf temp,w ;store ASCII representation of received byte LSN movwf INDF incf ptr2,f ;advance ASCII ptr incf ptr1,f ;advance received byte ptr decfsz bitcnt,f goto asciiconv ;done data conversion, now indicate newline before sending movlw "\n" ;newline character incf FSR,f movwf INDF 2001 Microchip Technology Inc. DS21311B-page 115 MCRF355/360 REFERENCE DESIGN ;cleared for RS232 transmission goto alphabet ;hexadecimal to ASCII conversion table org h'3ff' hex2ascii addwf PCL,f retlw "0" ;ascii 0 retlw "1" ;ascii 1 retlw "2" ;ascii 2 retlw "3" ;ascii 3 retlw "4" ;ascii 4 retlw "5" ;ascii 5 retlw "6" ;ascii 6 retlw "7" ;ascii 7 retlw "8" ;ascii 8 retlw "9" ;ascii 9 retlw "A" ;ascii A retlw "B" ;ascii B retlw "C" ;ascii C retlw "D" ;ascii D retlw "E" ;ascii E retlw "F" ;ascii F end DS21311B-page 116 2001 Microchip Technology Inc. M MCRF45X REFERENCE DESIGN 13.56 MHz Reader Reference Design for the MCRF 450/451/452/455 Read/Write Devices 1.0 INTRODUCTION The anti-collision interrogator in the DV103005 Development Kit is for Microchip Technology Inc.'s 13.56 MHz RFID devices (MCRF35X/360 and MCRF45X devices). The interrogator is used in conjunction with the RFLab 3.2 or above. User must select device type in the RFLab Menu Bar for either MCRF35X/360 or MCRF45X device. In the MCRF35X/360 mode, the interrogator transmits 13.56 MHz carrier signal continuously and receives tag's responses. This is often called "tag talks first" (TTF). The interrogator is working as the reader in the DV103003 kit that is for read only device (MCRF35X and MCRF360). In the MCRF45X mode, the interrogator sends commands for reading or writing block data. Interrogator uses amplitude modulation for the commands. To initiate communications, the interrogator sends specially timed gap pulses: FRR (fast read request) and FRB (fast read bypass). These pulses consist of 5 gaps within 1.575 ms time span. Each gap pulse is 175 s wide with 100% modulation depth. Gap means an absence of RF field. See Figures 4-3 thru 4-8 in the MCRF45X data sheet for details. 1-of -16 PPM (pulse position modulation) is used for data and commands such as read/write command for block data, command to set/clear TF (tag talks first) and FR (fast read) bits, and command for end process. The 1-of-16 PPM signal consists of one gap pulse within 2.8 ms time span for a normal mode and 160 s for a fast mode. The gap's position within 16 possible locations determines its representation for hex value. See Figure 4-9 in the MCRF45X data sheet (DS40232) for details. The demo interrogator communicates with the device in conjunction with the RFLab. The RFLab is a menu driven software package. Once the "MCRF450" - "Continuous" - "Run" menus are selected, the interrogator transmits FRR command continuously. Tags responds to the FRR command with a maximum of 160 bits of data including its unique ID number (32 bits). To read or write a specific memory block, users must select the tag ID and block number. The demo interrogator along with the RFLab included in the DV103005 kit is made as a reference material for various applications. The demo interrogator is designed for a general purpose utilizing all possible features shown in the data sheet. Both firmware and schematics can be modified for each individual applications. The interrogator uses two PICmicro(R) microcontrollers (MCUs) to communicate with a host computer, to send commands and data to the tag, and to receive and process the data from the tag. The U17 includes the anti-collision algorithm shown in Figure 4-1 of the MCRF45X data sheet. It controls all functions of the interrogator except decoding the received Manchester data which is done by the U14. The circuit is designed for medium read/write range applications (about 15" with 2" x 2" tag). The circuit can be optimized for lower cost, or modified for long-range applications. Electronic copies of the PICmicro MCU source codes, schematics and Bill of Material (BOM) are included in the CD. The interrogator also sends a time reference pulse before the commands and data. This time reference signal consists of three gap pulses within 2.8 ms time span for a normal mode and 160 s for a fast mode. See Figure 4-10 in the MCRF45X data sheet for details. Figure 1-1 shows the read/write pulse sequence between the interrogator and device. 2001 Microchip Technology Inc. DS21654A-page 117 MCRF45X REFERENCE DESIGN FIGURE 1-1: READ/WRITE PULSE SEQUENCE To write 1 block (32 bits) in normal mode with TS = 1: ~ 78.014 ms To read 1 block (32 bits) in normal mode with TS = 1: ~ 42.214 ms FRR or FRB Command: 5 gap pulses = 1.575 ms. Interrogator Command (FRR/FRB) t TDECODE (2.8 ms) For FR Response: (Preamble (8 bits) + Tc (3 bits) + Tp (4 bits) + "0" + 32 bits of Tag ID + FRF (32-96 bits) + bits 0-15 in Block #0 = 160 bits max = 2.286 ms) For FRB Response: (Preamble (8 bits) + "00001" + "000" + 32-bit Tag ID (block 1 data) + SCRC (16 bits) = 64 bits = 0.914 ms) Time Slot (TS) Listening window (TLW) for 1 ms Tag Response (FR response) t Matching Code during listening window: MC code = Calibration pulse (1 symbol) + Matched Tag ID (8 bits) + MC code type (3 bits) + 1 Parity bit = Cal. pulse (1 symbol) + 12 bits = 4 symbols = 11.2 ms Interrogator Command (MC and Read/Write) t For Reading: Cal. pulse (1 symbol) + Read Command (MSN first) + Address (MSN first + Parity) = Cal. pulse + 3 symbols = 11.2 ms Twrite for EEPROM (5 ms) For Writing: Cal. pulse (1 symbol) + Write Command (MSN first) + Address (MSN first) + data (LSN first) + Parity/CRC (LSN first) = Cal. pulse (1 symbol) + 14 symbols = 42 ms Tag Response (to Read/Write) t Device Outputs: After a completion of write cycle: Preamble (8 bits) + written block # (5 bits) + "000" + written block data (32 bits) + CCRC/SCRC (16 bits) = 64 bits = 0.914 ms After read command: Preamble (8 bits) + block # (5 bits) + "000" + block data (32 bits) + CCRC/SCRC (16 bits) = 64 bits = 0.914 ms Interrogator Command (End Process) t End Process Command: Cal. pulse + End Process Command (111) + Address (01010) + Parity (1) = Cal. Pulse + 3 symbols = 11.2 ms Tag Response to End Process t Device Response: 8-bit preamble (11111110) (0.114 ms) DS21654A-page 118 2001 Microchip Technology Inc. MCRF45X REFERENCE DESIGN 2.0 INTERROGATOR CIRCUITS The interrogator circuit consists of (1) transmitting, (2) receiving and (3) command control/data processing sections. 2.1 RF Transmission Section U6:A and 13.56 MHz crystal form a crystal oscillator and output a 13.56 MHz signal. The output signal is fed into pin 1 of U7. The input signal on pin 2 of U7 is coming from U17 (Master Microcontroller). The following is the output of U17 for pin 2 of U7. The RF output voltage from U8 is fed into antenna circuit formed by C1, C2, C3, C4, C5 and antenna coil L. The demo unit has three different sizes of antenna. Each one has one turn inductor along the edge of the PCB board. The metal trace is embedded inside the PCB. Figure 2-1 shows the antenna circuit. The impedance of LC circuit is given by: EQUATION 2-1: * MCRF45X mode: Modulation signal for commands and block data for writing. * Stand by mode: Logic "HIGH". * MCRF35X/360 mode: Logic "HIGH". Therefore, U7 outputs (a) a modulated RF signal (for command or write data) or (b) continuous RF signals during the stand by and MCRF35X/360 operation. The output signal of the U7 is fed into the gate of RF power amplifier U8 through U6:D, E and F. Splitting the output of U6:C using U6:D, E and F is helpful for preventing excessive heat on U6. U4 is an adjustable voltage regulator and supplies the DC power supply voltage for U8. The U4 is controlled by U17 through U16 (DAC) and U3. The main idea of using the adjustable voltage regulator is to adjust the RF output signal level of U8. The power level is adjusted by the following procedure in the RFLab menu: "Configure" -> "Carrier Strength" User can select the "Carrier Strength" from 0% - 100% (from the above menu). Default is set to 100%. The interrogator outputs the maximum power level at this setting. RFLab sends the Carrier Strength information to U17 which adjusts U4's output voltage through U16 and U3. This corresponds to about 12.37 VDC at pin 2 of U4 for the 15 VDC input voltage. The purpose of adjusting the carrier signal level is to reduce a possible near-field problem which may result in an irregular clock rate of the RFID device. This is due to an excessive input voltage to the device when the tag is placed too close to the reader antenna. In this case, the output power level from the interrogator should be decreased. However, for a longer read range, it is often necessary to output higher power level so that it can detect tags in the far range. Adjusting the carrier signal level is an optional choice. Therefore, the circuit components (U16, U3 and U4) associated with this feature can be easily removal. In this case, +15 VDC or 9 VDC should be directly applied to L9 for U8. 1 1 ------ jL + ------------- C4 jC S Z ( ) = ---------------------------------------------2 1 1 - L + ------ + ------ C S C 4 where CS = C1 + C2 + C3 + C5 =2f f = output carrier frequency The resonant frequency of the antenna circuit in the interrogator is given by solving the impedance equation in Equation 2-1. In Equation 2-1, the impedance Z() has poles and zeroes. The poles are found at the condition when the denumerator goes to zero and the zeroes are found when the numerator goes to zero. The poles result in a maximum impedance, since the denumerate goes to zero. Therefore, the frequencies at the poles are the parallel resonant frequencies. The zeroes result in a minimum impedance since the number goes to zero. Thus, the frequencies at the zeroes are series resonant frequencies. FIGURE 2-1: ANTENNA CIRCUIT P1 VIN From: U8 C1 C2 C3 C5 C4 To: Receiving Channel P3 Antenna, L Antenna Voltage P2 Ground 2001 Microchip Technology Inc. DS21654A-page 119 MCRF45X REFERENCE DESIGN The resonant frequencies by solving the poles and zeroes are: EQUATION 2-2: fseries 1 1 = --------------------- = ----------------------------------------------------------------2 LC S 2 L ( C 1 + C 2 + C3 + C 5 ) and EQUATION 2-3: 1 fparallel = -----------------------------------------------CS 2 L C S 1 + ------ C 4 where 2.2 Receiving Section The receiving section receives 70 kHz Manchester data from tag in the field. D1, C4 and R3 collectively form an envelope detector. L1 and C3 forms a 70 kHz band pass filter. D4 and D2 are used to limit signal amplitude level which prevents U1:A going into a saturation condition. L3, C33 and C47 form a 13.56 MHz notch filter and by-pass the induced carrier signal into ground. FB1 is an RF choker that gives high attenuation to high frequency signal. U1:A is a gain amplifier that gives about 26 dB voltage gain. U1: B is a unit gain second-order high-pass filter. U1:C is a gain amplifier with about 29 dB voltage gain. U1:D is a unit gain second-order low-pass filter. U1:B and D result in a band-pass filter for the 70 kHz Manchester data. U11:A, B, T1 and T2 circuits are used to find a midpoint of the input data voltage. The resulting average voltage, (VP+ + VP-)/2, is used as a reference voltage for the voltage comparator U2. The output of U2 is fed into the PICmicro micrcontroller U17 for data decoding. 2.3 CS = C1 + C2 + C3 + C5 Equation 2-3 is used for the antenna circuit of the interrogator in the DEV103005 kit. The antenna voltage across the L is given: The interrogator uses two PICmicro MCUs (PIC16F876-20/SP) for the command controls, data decoding and communication with a host computer. The U17 includes PIC-code routines to follow the device's read/write anti-collision algorithm as shown in Figure 4-1 in the data sheet. The U14 performs bit timing calculation for the received Manchester code. EQUATION 2-4: jX L VAnt = ------------------------------------Vin r + j ( XL - XC ) S The U17 does the following tasks: a) b) where r = Ohmic resistance of L and C XL = 2 f L () XCS = (2 f CS)-1 () VIN = AC voltage at points between P1 and P2. The antenna voltage measured between P3 and P2 contributes the radiating RF field from the antenna. The voltage is about 60 VPP - 80 VPP. C5 can be adjusted to get the maximum voltage across the antenna. The current that flows along antenna L generates magnetic fields. Each interrogator unit may have a slightly different output parasitic capacitor. As a result, there will be a chance of tuning variation when the antenna is attached to the unit. This results in shorter read range. In this case, C5 in the circuit should be adjusted properly. DS21654A-page 120 Command Control and Data Decoding Section c) d) e) Communicate with a host computer Encode and transmit: FRR and FRB Commands Calculate/Send MC1 and MC2 Read/Write/End Commands Calibration Pulse Data and CRC Decode receiving data Calculate CRC for transmitting data and receiving data. CRC look-up table is used for the calculation. Give a received data stream to U14 for decoding of the Manchester data. The flow charts of the PICmicro microcontroller routines for U14 and U17 are shown in AN760 (DS00760). The source codes are included in the CD. Figure 2-2 shows the functional block diagram of the interrogator. 2001 Microchip Technology Inc. MCRF45X REFERENCE DESIGN FIGURE 2-2: FUNCTIONAL BLOCK DIAGRAM OF DEMO INTERROGATOR 13.56 MHz Signal Generator (U6: A) Modulator (U7) Tuning Circuit (C1, C2, C3, C4, C5) Power Amplifier (U8) Transmitting Section Ant. 20 MHz OSC Microcontroller (U17, U14) Host Computer (RFLab) 70 kHz LC Band Pass Filter (L1, C3) Amplifier (U1:A) 13.56 MHz LC Notch Filter (L3, C33, C47) High and Low Pass Filters (U1:B, U1:D) 2001 Microchip Technology Inc. Envelope Detector (D1) Receiving Section DS21654A-page 121 MCRF45X REFERENCE DESIGN FIGURE 2-3: DATA SIGNAL WAVEFORMS FROM TAG ` 1' ` 1' `0' `1' ` 0' 14.285 s Tag Data Signal ... Signal Waveform in Reader Coil t After Envelope Detector t After Pulse Shaping t FIGURE 2-4: BIPHASE-L (MANCHESTER) SIGNAL V V t (a) Data `1' DS21654A-page 122 t (b) Data `0' 2001 Microchip Technology Inc. MCRF45X REFERENCE DESIGN 2001 Microchip Technology Inc. DS21654A-page 123 MCRF45X REFERENCE DESIGN DS21654A-page 124 2001 Microchip Technology Inc. MCRF45X REFERENCE DESIGN 2001 Microchip Technology Inc. DS21654A-page 125 MCRF45X REFERENCE DESIGN DS21654A-page 126 2001 Microchip Technology Inc. MCRF45X REFERENCE DESIGN 2001 Microchip Technology Inc. DS21654A-page 127 MCRF45X REFERENCE DESIGN DS21654A-page 128 2001 Microchip Technology Inc. MCRF45X REFERENCE DESIGN 2001 Microchip Technology Inc. DS21654A-page 129 MCRF45X REFERENCE DESIGN DS21654A-page 130 2001 Microchip Technology Inc. M AN759 Interface Control Document for the 13.56 MHz MCRF450/451/452/455 Anti-Collision Interrogator SCOPE EXTERNAL INTERFACES This document specifies the external interface requirements for the MCRF45X and MCRF355/360 Reader/ Writer. A description of the RS232 interface messages, their bit fields and meanings are described in this document. Electrical Interfaces Identification This interface control document is applicable to the Microchip's 13.56 MHz RFID Reader/Writer. System Overview The RFID Reader/Writer will support both reading and writing of the MCRF355/360 and MCRF45X RFID devices. The RFID Reader/Writer will support communication for command and data via an RS232 interface using standard protocol settings. Document Organization This document is organized as follows: * SCOPE: Identifies the scope of this document * REFERENCE DOCUMENTS: Identifies any documents referenced by this specification by document number, revision and date * EXTERNAL INTERFACES: Identifies the specific external electrical and mechanical interfaces for the Support Electronics for the PDE SERIAL COMPUTER INTERFACE The RFID Reader/Writer will communicate with the external host computer via RS232 interface. The interface settings will be 19.2 Kbaud, 8 bits, no parity and one stop bit. All characters transmitted will be within the ASCII character set, ASCII value less than 127. TEST INTERFACE The RFID Reader/Writer will provide discrete LEDs that will provide simple status of the RFID Reader/Writer independent of attached PC. Communication Protocol/Messages The packet protocol for the RFID Reader/Writer is described in the following paragraphs. The protocol provides a robust, easily managed interface that supports debugging on a simple ASCII terminal in addition to providing a checksum for message validation. The general message format is as follows: Sync Char Command Data Checksum CR LF General Message Format Single byte character `@' denoting the beginning of a message REFERENCED DOCUMENTS Sync Char The following references are used for this document: Command Single byte character defining the command this message represents. See Table 1 for a list of commands [1] EIA Standard RS-232-C [2] RS-232A Specification Data A variable length field containing additional information support the command Checksum The two-byte checksum used for the message includes the Sync Char through the end of the Data field. See the following paragraph for more information on the checksum used CR LF 2001 Microchip Technology Inc. This two-byte field is the standard ASCII carriage return `0x0D' and the line feed `0x0A' DS00759A-page 131 AN759 TABLE 1: Command Char From To Description `2' R/W PC Data field contains MCRF355 data (14 bytes) `3' R/W PC Data field contains MCRF355 data (18 bytes) `4' R/W PC Data field contains MCRF450 data blocks (Read) `5' R/W PC Data field contains MCRF450 data blocks (Write) `6' R/W PC Data field contains MCRF450 FRB response data `7' R/W PC Data field contains MCRF450 FRR response data `F' R/W PC Firmware version `R' R/W PC Response message `R' PC R/W Reset request command `M' PC R/W Mode select command `N' PC R/W No operation `V' PC R/W Verbose read command `W' PC R/W Write command `C' PC R/W Configuration message `L' PC R/W Load command COMMAND OVERVIEW CHECKSUM LOAD MESSAGE The checksum is a two-character field. Adding the fields Sync Char through Data into an unsigned byte type and ignoring any overflow generated determines this value. The resultant value is then negated to provide a 2's complement checksum value. This 8-bit result is then converted to two hex characters to represent the checksum in the message (e.g. checksum byte value 00101100 results in a checksum of two ASCII bytes '2C' represented in the message). The load command provides a method to update the PIC 16F876 firmware in the field via the RS-232 interface. The Data Field length is zero. When the load command is received, the RFID Reader/Writer will transition to a 'loader', which will then accept hex record lines to be written to program memory. The format of the hex record will be the format generated by the Microchip assembler/linker. Each hex record line will be validated before writing to program memory. The RFID Reader/Writer will respond with 'Ready' response message upon successful write or an error message if unsuccessful. After the final line of the .HEX file is sent, the newly loaded program is entered using the POR vector at address 0000. See Response Message paragraphs. MESSAGE FORMATS The following paragraphs detail the individual commands and messages. 0x40 `L' Data Checksum CR LF LOAD MESSAGE FORMAT DS00759A-page 132 2001 Microchip Technology Inc. AN759 RESPONSE MESSAGE The response message is used to provide acknowledge and status response from the R/W to the external PC. The data field contains the specific response encoded as a 2-digit hexadecimal number. The responses supported are listed below. 0x40 `R' Response Number Checksum CR LF RESPONSE MESSAGE FORMAT Response Number Equivalent Text Description 00 "Ready" 01 "EEPROM Burn Failed" Previous write was read back and validated unsuccessfully Ready for the next message No processor instructions were given for ROM locations 0-3 02 "No Entry Point Specified" 03 "Invalid Address" A write to Program ROM was outside valid range 04 "Invalid Hex Data" The characters representing hex data were not in the range 0-9, A-F 05 "RS-232 Error" Characters were lost or garbled. Message should be repeated. 06 "Invalid Checksum" 07 "Undefined Command" Checksum did not verify 08 "Invalid Paramter" Contents of a command string are invalid 09 "Bad Processor" The Slave processor fails to communicate Command byte sent is not a known command RESPONSE MESSAGES RESET MESSAGE NOP MESSAGE The reset message is sent from the external PC to the Reader/Writer. It instructs the R/W to reset itself, and return to the just-powered-up state. In this state, the carrier is off, and the R/W is sending 'A' characters over the RS-232 line at a 50 Hz rate, looking for a PC-based application to communicate with. See the paragraph "Auto Detect Support" for a more complete description. The data field length is zero. The NOP message is a no operation message. It can be used as a 'heart-beat' message to maintain communication if needed. The Data Field length is zero. This command returns the "Ready" Response Message ('R'). Note that this and every command causes the Reader/Writer to stop its current operations to process the new command. After this command, the Reader/ Writer remains in the idle loop, waiting for the next command. 0x40 `R' Data Field Checksum CR LF 0x40 `N' Data Field Checksum CR LF RESET MESSAGE FORMAT NOP MESSAGE 2001 Microchip Technology Inc. DS00759A-page 133 AN759 MODE SELECT MESSAGE The mode select message is used to put the RFID Reader/Writer in a specific read mode as defined below. 0x40 `M' Data Field Checksum CR LF MODE SELECT MESSAGE The mode field contains a one-byte character that defines the specific mode to place the reader into. This byte is defined below. Mode Char Description `0' Read MCRF355/360 tags, returning the data in Microchip format. No anti-aliasing - all tag reads are reported `1' Read MCRF355/360 tags, returning raw tag data. No anti-aliasing - all tag reads are reported `2' Read MCRF355/360 tags, returning the data in Microchip format. Anti-aliasing enabled -- subsequent reads of the same tag are ignored. `3' Read MCRF355/360 tags, returning raw tag data. Anti-aliasing enabled -- subsequent reads of the same tag are ignored. `I' Inventory read mode. (FRR & FRB: tags are put to sleep after being identified) `C' Continuous read mode. (FRR & FRB) `A' Alarm mode. (FRR only) `S' Stop reading mode. (Leave carrier on) `F' Reader/writer off. (Turn carrier off) MODE SELECT CHARACTERS 355 DATA BLOCKS MESSAGE - MICROCHIP FORMAT This message contains the entire data block from the MCRF355/360 represented in ASCII hex format. It assumes the tag was written in Microchip format, which is: 10-bit header (9 ones, and 1 zero), followed by 14 8-bit bytes and a 2-byte checksum, with each byte separated by a zero bit, and written MSb first. The checksum of the block is verified before transmission. 0x40 `2' Data Block Checksum CR LF 355/360 DATA BLOCKS MESSAGE DS00759A-page 134 2001 Microchip Technology Inc. AN759 The format of the data block is as follows: T<time stamp>, <data> Where: Field name Description Time stamp The time stamp of when the device was read. This value consists of 2 bytes (4 ASCII hex characters), with the LSb = 819.2 S. The clock is a free-running counter with a rollover period of 53.7 seconds. The bytes are sent MSb first. Data The 14 data bytes represented in ASCII hex characters. Byte 13 is first; byte 0 is last. The checksum bytes are not transferred. 355/360 DATA BLOCKS MESSAGE DETAIL "Microchip Format" is defined by the MCRF 355/360 Contact Programmer, and is shown graphically below. Of the 154 bits in the tag, the first 9 are the preamble, and fixed as '1' bits. Following the preamble, and separating each byte, are spacer bits (zeros). All bytes are Most Significant bit (MSb) first. This format allows 14 data bytes followed by a 16-bit checksum (simple summation of all 14 bytes). 111111111 Bit 0 0 Byte 13 0 Bit 9 Byte 12 Bit 18 0 ... Bit 27 Byte 0 0 Chksum_MSb Bit 135 0 Chksum_LSb Bit 144 Bit 152 355 DATA BLOCKS MESSAGE - RAW FORMAT This message contains the data block from the MCRF355/360 represented in ASCII hex format. It assumes the tag was written in Microchip format, however the spacer bits which exist between every byte are not removed. Internally, the data is converted to Microchip format so that the block checksum can be calculated and verified before transmission. 0x40 `3' Data Block Checksum CR LF 355/360 Data Blocks Message The format of the Data Block is as follows: T<time stamp>, <data> Where: Field name Description Time stamp The time stamp of when the device was read. This value consists of 2 bytes (4 ASCII hex characters), with the LSb = 819.2 S. The clock is a free-running counter with a rollover period of 53.7 seconds. The bytes are sent MSb first. Data The 18 data bytes represented in ASCII hex characters. Byte 17 is sent first. 355/360 DATA BLOCKS MESSAGE DETAIL 2001 Microchip Technology Inc. DS00759A-page 135 AN759 The tag data is assumed to be as shown graphically below for purposes of displaying it in 'Raw Format'. It is similar to Microchip Format in that all bytes are Most Significant bit (MSb) first, and the first 10 bits are the fixed preamble (9 one-bits followed by a zero bit). The remaining 143 bits make up the 18 8-bit bytes. Note: The last byte has one missing bit. Its Least Significant bit (LSb) is fixed at zero. 111111111 Bit 0 0 Byte 17 Bit 9 Byte 16 ... Bit 18 Byte 1 Byte 0 Bit 138 Bit 146 Bit 152 MCRF45X DATA BLOCKS MESSAGE 0x40 `4' Data Block Checksum CR LF 45X DATA BLOCKS MESSAGE This message contains the data blocks returned from the MCRF450 in response to a Verbose Read command. All 32 blocks of the MCRF450 tag are included. The message elements are defined below. The format of the Data Block is: I<id>,<block>:<data>,<block>:<data>,...<block>:<data> Where: Field name Description I<id> The ASCII hex representation of the 4-byte tag ID. LSb first. Block Block number, represented by 2 ASCII hex characters. Its value ranges from 00 to 1F (31 decimal). Block numbers are followed by a colon. Data One data block (4 bytes) from the tag, represented in ASCII hex characters. Data blocks are separated by commas. A block which is unreadable (invalid CRC) will return "XXXX" for the data. In this case, it will be 4 characters instead of 8. The data is LSb first. 45X DATA BLOCKS MESSAGE DETAIL DS00759A-page 136 2001 Microchip Technology Inc. AN759 MCRF45X DATA BLOCKS WRITTEN MESSAGE 0x40 `5' Data Block Checksum CR LF 45X DATA BLOCKS MESSAGE This message contains the data blocks returned from the MCRF45X in response to a Verbose Write command. One message is returned per tag written. The message elements are defined below. The format of the Data Block is: I<id>,<block>:<data>,<block>:<data>,...<block>:<data> Where: Field name Description I<id> The ASCII hex representation of the 4-byte tag ID. LSb first. Block Block number, represented by 2 ASCII hex characters. Its value ranges from 00 to 1F (31 decimal). Block numbers are followed by a colon. Data One data block (4 bytes) from the tag, represented in ASCII hex characters. This data is what the tag returned following the write to this block. A block which is write-protected will return to "RO" for the data. In this case, it will be 2 characters instead of 8. A block which is unreadable (invalid CRC) will return "XXXX" for the data. The data is LSb first. 45X DATA BLOCKS MESSAGE DETAIL 450 FRB RESPONSE MESSAGE 0x40 `6' Data Block Checksum CR LF 45X FRB RESPONSE MESSAGE This message This message contains the data returned from the MCRF45X in response to an FRB command. The message elements are defined below. The format of the Data Block is: T<time stamp>,<TC/TP>,<ID>,<FRF> Where: Field name Description Time stamp The time stamp of when the device was read. This value consists of 2 bytes (4 ASCII hex characters), with the LSb = 819.2 S. The clock is a free-running counter with a rollover period of 53.7 seconds. The bytes are sent MSb first. ID One data block (4 bytes) represented in ASCII hex characters. The data is from Block #1, the tag's ID. The data is sent LSb first. 45X FRB RESPONSE MESSAGE DETAIL 2001 Microchip Technology Inc. DS00759A-page 137 AN759 MCRF45X FRR RESPONSE MESSAGE 0x40 `7' Data Block Checksum CR LF 45X FRR RESPONSE MESSAGE This message contains the data returned from the MCRF450 in response to an FRR command. The message elements are defined below. The format of the Data Block is: T<time stamp>,<TC/TP>,<ID>,<FRF> Where: Field name Description Time stamp The time stamp of when the device was read. This value consists of 2 bytes (4 ASCII hex characters), with the LSb = 819.2 S. The clock is a free-running counter with a rollover period of 53.7 seconds. The bytes are sent MSb first. TC/TP ID FRF One byte containing the TC and TP values from the tag, represented in ASCII hex characters. Bits 0-2 are the TC value; bits 3-7 are the TP (tag parameters) value. See the MCRF45X Data Sheet on the format of the TP field. One data block (4 bytes) represented in ASCII hex characters. The data is from Block #1, the tag's ID. The data is sent LSb first. The Fast Read Field, represented in ASCII hex characters. The data is from Blocks #3-5. The exact number of bytes in the FRF depends upon the 2 DF bits within the TP field, and can be 4, 6, 8 or 12. The LSb is sent first. 45X FRR RESPONSE MESSAGE DETAIL FIRMWARE VERSION RESPONSE MESSAGE 0x40 `F' Data Block Checksum CR LF FIRMWARE VERSION RESPONSE MESSAGE This message is sent once, immediately following connection establishment. The format of the Data Block is 2 ASCII digits indicating the major and minor revision numbers. The range of revision numbers supported is 1.0 thru 9.9. WRITE MESSAGE The write message provides the capability to program one or all MCRF45X devices with one to 16 blocks of data. If write-all-tags is selected, the Reader/Writer will look for all FRR and FRB parts in the field, writing them as soon as they are found, until the user places the Reader/Writer into another mode (or idle state). If onetag-write is selected, the carrier is turned off after the selected tag is found and written. The response to this message will be one or more 45X Data Blocks Written message ('5') - one per tag. Block 1 (the tag ID) should not be written. VERBOSE READ MESSAGE This message will terminate continuous read mode and initiate a read of a specific ID tag in the field. The response to this message will be a 450 Data Blocks message ('4'). 0x40 `V' Data Block Checksum CR LF VERBOSE READ MESSAGE The tag ID field contains the 4 tag ID bytes represented in ASCII hex format. DS00759A-page 138 If the starting block number is 0 or 2, the number of data blocks to be written is limited to 1 block. In order to prevent an FRR part from becoming inaccessible in case of a failed write to blocks 0, 3, 4 or 5, the Reader/Writer will turn an FRR part into an FRB part prior to writing these blocks, then return it into an FRR part only if all blocks were written correctly. When writing to block 0, bit 31 should be kept clear to keep from flagging a special case, described next. Two special cases of the Write Command exist: converting FRR tags into FRBs, and converting FRB tags into FRRs. 2001 Microchip Technology Inc. AN759 To turn devices into FRR parts, issue the Write Message for data block 0, with the two most-significant bits of the data (Fast Read and Talk First bits) set to '1'. The remaining 30 data bits are don't care. When the Reader/Writer sees this situation, it will calculate the correct FRR response CRC for the tag and write it to the low 16 bits of block 0. After successful write, it then sets the FR bit. A 45X Data Blocks Written message ('5') is returned for each tag which is changed from an FRB part to an FRR part. To turn devices into FRB parts, issue the Write Message for data block 0, with bit 31 of the data (Fast Read) set to '1', and bit 30 (Talk First) set to '0'. The remaining 30 data bits are don't care. The Reader/ Writer will clear the FR bit (bit 31 of block 0) without affecting any other tag memory bits. A 450 Data Blocks Written message ('5') is returned for each tag which is changed from an FRR part to an FRB part. The format of the message is as follows. 0x40 `W' Data Block Checksum CR LF WRITE MESSAGE The Data Block has the following format when writing to one selected tag. All characters not between braces ('<' '>') are necessary for a valid message. The total number of <data> fields must be 16 or less. I<id>,<block number>,<data>,...,<data> Where: Field name I<id> <block number> <data> Description The ASCII hex representation of the 4-byte tag ID. (LSb first) The beginning block number to write, represented in ASCII hex. A 4-byte block of data, LSB first, in ASCII hex representation. The Data Block has the following format to write to all devices in the R/W field. The total number of <data> fields must be 16 or less. *,<block number>,<data>,<data>,....,<data> Where: Field name Description * Replacing the I<id> field with a star character denotes all tags. <block number> The beginning block number to write, represented in ASCII hex. <data> A 4-byte block of data, LSB first, in ASCII hex representation. CONFIGURATION MESSAGE The configuration message provides a method to set specific attributes within the RFID Reader/Writer firmware. The format of the message is as follows. 0x40 `C' Data Block Checksum CR LF CONFIGURATION MESSAGE The Data Block consists of up to 7 parameters that may be set. The parameters are separated by commas and begin with an identifying character. Any parameter not included in the command retains the value it had before the Configuration Message. The order of the parameters is not important. T<ts>,M<tcmax>,S<speed>,P<ppm timing>,G<gap timing>,V<vpp>,I<audio> 2001 Microchip Technology Inc. DS00759A-page 139 AN759 Where: Field POR Value T<ts> 16 The ASCII hex representation of 1 byte: The number of Time Slots used in the tag's FRR command. Valid values are: 1, 16, 64. Description M<tcmax> 1 The ASCII hex representation of 1 byte: The TCMAX value to use in the tag's FRR command. Valid values are: 1, 2, 4. If TS = 64, then TCMAX must be 1. S<speed> 0 The ASCII hex representation of 1 byte: Whether to modulate the carrier at Normal Speed or Fast Speed for the PPM symbols. A value of 0 sets Normal Speed; a value of 1 sets Fast Speed. P<ppm timing> 0 The ASCII hex representation of an 8-bit signed integer: The relative timing to use for gap periods. Valid range is -6 to +6, with 0 being nominal (175 S Normal Speed/10 S Fast Speed). -6 corresponds to 20% reduction in time, and +6 corresponds to 20% increase in time. +/- 3 corresponds to +/-10%, etc. G<gap timing> 0 The ASCII hex representation of an 8-bit signed integer: The relative timing to use for gap widths. Valid range is -6 to +6, with 0 being nominal (100 S Normal Speed/6 S Fast Speed). -6 corresponds to 20% reduction in time, and +6 corresponds to 20% increase in time. +/- 3 corresponds to +/-10%, etc. V<vpp> FFh The ASCII hex representation of 1 byte: The relative strength of the carrier signal. A value of 0 sets no carrier; a value of FFh sets maximum carrier field strength. I<audio> 1 The ASCII hex representation of 1 byte: A value of 1 enables beeps when each tag is detected. A value of 0 disables audible indication. AUTO DETECT SUPPORT At power-up of the RFID Reader/Writer, the character 'A' will be continuously transmitted at a 50 Hz rate over the serial port. This provides a serial stream to support auto-detection of the device by a PC. When the Reader/Writer receives a 'B' character from the PC, it will cease transmission of the 'A' characters, and return a type 'F' Response Message (Firmware Version), thus establishing a positive confirmation of communication. The RS-232 parameters are: 19.2 Kbaud, 8 bits, no parity, and 1 stop bit. DS00759A-page 140 2001 Microchip Technology Inc. M AN760 PICmicro(R) Microcontroller Firmware Flow Chart of MCRF45X Demo Reader RFID Top-Level U17, Master processor MAIN POR A INITIALIZE WAIT FOR START OF COMMAND N = No operation C = Configuration message M = Mode select R = Reset request W = Write V = Verbose read L = Load GET COMMAND LETTER Yes NOP CMD = "N" SEND "READY" MESSAGE No DECODE AND CONFIGURE Yes CMD = "C" Yes EXECUTE SPECIFIED MODE Yes PERFORM "WRITE" COMMAND CMD = "M" No JUMP TO PROGRAM LOCATION "0000" Reset CMD = "R" CMD = "W" No PERFORM "READ" COMMAND Yes CMD = "V" Yes CMD = "L" No SEND ERROR MSG: "UNDEFINED" CMD JUMP TO LOADER Loads new firmware using RS-232 port FLUSH REST OF CMD LINE 2001 Microchip Technology Inc. DS00760A-page 141 AN760 CONFIGURE End of Line READ PARAMETER ID A READ PARAMETER VALUE Yes SET AUDIO ON/OFF Yes STORE DELTA GAP PERIOD Yes STORE TS Yes SET NEW CARRIER VOLTAGE ID = "I" No STORE DELTA GAP-WIDTH Yes ID = "G" ID = "P" No STORE TC MAX Yes ID = "M" ID = "T" No STORE NORMAL/FAST FLAG Yes ID = "S" ID = "V" No SEND ERROR MSG: "UNDEFINED" PARAMETER DS00760A-page 142 2001 Microchip Technology Inc. AN760 MODE READ MODE LETTER In case any tags were put to sleep in previous activity Yes NEED TO CYCLE THE CARRIER? No TURN OFF CARRIER WAIT 100 ms TURN ON CARRIER WAIT 250 ms TURN CARRIER OFF Yes MODE = "F" No TURN CARRIER ON Yes MODE = "S" No A MODE {0,1,2,3} Yes MCRF_355 A No MODE {I,A,C} No Yes MCRF_450 A SEND ERROR MSG: "UNKNOWN MODE" A 2001 Microchip Technology Inc. DS00760A-page 143 AN760 MODES 0, 1, 2, 3 Mode 0: Microchip Format, No Anti-Collision MCRF 355 Mode 1: Raw Format, No Anti-Collision TURN ON CARRIER Mode 2: Microchip Format, Anti-Collision CLEAR TAG DATABASE Mode 3: Raw Format, Anti-Collision B RECEIVED ANY RS-232? Yes No EXIT WAIT FOR TAG DATA No GOT 18 BYTES? Yes REMOVE `0' BITS BETWEEN EVERY BYTE ANY SPACE BITS = `1'? SET AUDIO ON/OFF No SEND TIME STAMP Yes MODE = 0,2 REVERSE BIT ORDER IN EACH BYTE Yes No CALCULATE CHECKSUM CHECKSUM CORRECT? STORE TAG'S CHECKSUM IN DATABASE No B Yes FINISH RESPONSE PACKET B DS00760A-page 144 TAG EXISTS IN DATABASE? No SEND 18 BYTES OF ORIGINAL (RAW) DATA SEND 14 BYTES OF CLEANED UP DATA Yes MODE = `0' OR `1'? No Yes 2001 Microchip Technology Inc. AN760 MODES A, I, C MCRF 450 Mode A: Look for FRR tag only C Mode I: Put tags to sleep when they are found Yes RECEIVED ANY RS-232 BYTES ? No Mode C: Look for FRR & FRB tags continuously EXIT SEND FOR GAP SEQUENCE WAIT FOR TAG DATA TIME-OUT? No Yes Yes MODE = `I'? Yes MODE = `A'? No No C SEND: CALIBRATION & MC1 SEND FRR RESPONSE PACKET TO PC SEND FRB GAP SEQUENCE WAIT FOR TAG DATA NOTE: This puts part to sleep for Inventory Mode Yes TIME-OUT? C Yes MODE = `I'? No SEND: CALIBRATION + MC1 + END PROCESS SEND FRB RESPONSE PACKET TO PC C 2001 Microchip Technology Inc. DS00760A-page 145 AN760 READ COMMAND GET TAG ID FROM PC Yes NEED TO CYCLE THE CARRIER? No TURN OFF CARRIER WAIT 100 ms TURN ON CARRIER WAIT 250 ms ACCESS A TAG BLK_NO = 0 READ BLOCK No Yes OK? Yes REPORT TO PC: BLK_NO: DATA BLK_NO = 0? No REPORT TO PC: DATA = "XXXX" ++BLK_NO = 32? No Yes TURN OFF CARRIER EXIT DS00760A-page 146 2001 Microchip Technology Inc. AN760 WRITE COMMAND GET TAG_ID, STARTING BLOCK_NO, BLOCK DATA FROM PC TAG_ID = '*'? Yes WR_ALL_TAGS = 1 No Yes BLOCK DATA BIT 31 = 1 BLOCK DATA BIT 30 = 1 Yes No START BLOCK =0 No MAKE_FRR = 1 MAKE_FRB = 1 NEED TO CYCLE THE CARRIER? Yes No CARRIER OFF FOR 100 ms CARRIER ON FOR 250 ms ACCESS A TAG MAKE INTO AN FRR PART Yes MAKE_FRR? No Yes MAKE_FRB? No IS THIS ON FRR TAG? Yes START BLOCK = 0,3,4,5? Yes No No SEND CLR_FR BIT COMMAND TO TAG READ BLOCK 2 WRITE BLOCKS PUT TAG TO SLEEP Yes 2001 Microchip Technology Inc. WR_ALL_TAGS? No TURN OFF CARRIER EXIT DS00760A-page 147 AN760 ACCESS A TAG D Return to Command Processor Yes RECEIVED ANY RS-232 BYTES ? No A Yes TIME-OUT? No EXIT SEND FRR GAP SEQUENCE WAIT FOR TAG DATA Yes No ANY DATA? WR_ALL_TAGS? SEND FRB GAP SEQUENCE No ID=DESIRED ID? Yes WAIT FOR TAG DATA No Yes SEND MC1 TO SLEEP THE PART SEND MC2 TO ACCESS THE TAG D No ANY DATA? Yes D WR_ALL_TAGS? Yes SEND MC2 TO ACCESS THE TAG EXIT No ID=DESIRED ID? No Yes SEND MC2 & END_PROCESS TO SLEEP THE PART D EXIT DS00760A-page 148 2001 Microchip Technology Inc. AN760 READ BLOCK RETRIES = 3 SEND READ BLOCK CMD FOR BLK_NO WAIT FOR TAG DATA Yes ANY DATA? No No MESSAGE CRC CORRECT? Yes Yes _ _ RETRIES > 0? EXIT No (PASS) EXIT (FAIL) 2001 Microchip Technology Inc. DS00760A-page 149 AN760 WRITE BLOCKS E BEGIN RESPONSE PACKET TO PC Yes IS THIS AN FRR PART? No MAKE FRB? MAKE FRR? No No No IS BLOCK 0 CRC CORRECT? No No Yes Yes MAKE FRR? Yes Yes ANY ERRORS SO FAR? Yes FINISH RESPONSE PACKET TO PC IS THIS BLOCK WRITE_ PROTECTED? EXIT No SEND SET_FR_BIT COMMAND TO TAG SEND WRITE_BLOCK COMMAND TO TAG SET-UP TO LOOP ONCE MORE RETRIES = 8 WAIT FOR TAG DATA No MAKE FRR? Yes TIME-OUT? No Yes No REPORT "RO" FOR BLOCK DATA REPORT "XXXX" FOR BLOCK DATA _ _ RETRIES > 0? Yes ADD BLOCK'S DATA TO RESPONSE PACKET SEND READ_BLOCK COMMAND TO TAG BLOCK_NO = BLOCK_NO + 1 Yes DS00760A-page 150 MORE BLOCKS TO WRITE? No E 2001 Microchip Technology Inc. AN760 MAKE AN FRR PART READ TAG'S BLOCK #0 FAIL? Yes No READ TAG'S BLOCK #2 FAIL? Yes No Yes IS THIS TAG AN FRR ALREADY? No READ TAG'S BLOCK #'S 3, 4, 5 FAIL? Yes No CALCULATE CORRECT CRC FOR FRR RESPONSE STORE CRC IN BLOCK 0 RAM BUFFER WRITE BLOCK #0 SEND END PROCESS CMD TO SLEEP THE TAG WR_ALL_TAGS? Yes No EXIT TURN CARRIER OFF A 2001 Microchip Technology Inc. Wait for command from PC DS00760A-page 151 AN760 SLAVE PROCESSOR U14 INITIALIZE STATE = 0 WAIT FOR FIRST EDGE OF MANCHESTER DATA ENABLE INTERRUPTS WAIT FOR END OF DATA STREAM DISABLE INTERRUPTS IS MASTER P BUSY? Yes No No WAIT FOR MASTER PROCESSOR READY ANY DATA RCV'D FROM TAG? WAIT FOR MANCHESTER LINE IDLE Yes ANY PARTIAL BYTE REMAINING? Yes No SEND PARTIAL BYTE OVER SPI BUS SEND # EMPTY BITS IN FINAL DATA BYTE OVER SPI BUS DS00760A-page 152 2001 Microchip Technology Inc. AN760 SLAVE PROCESSOR ISR CAPTURE CURRENT STATE OF MANCHESTER DATA CAPTURE TIME ELAPSED SINCE LAST EDGE ON MANCHESTER LINE STATE = 0 STATE = 1 IS THIS THE 4TH EDGE ? Yes STATE = 1 STATE = 2 ADD THE BIT TO BYTE-BUILDING BUFFER IS THIS A ZERO BIT ? Yes STATE = 3 8TH BIT? SEND FIRST BYTE (ALWAYS 7F) OVER SPI BUS HAS MASTER TAKEN PREVIOUS BYTE OFF SPID BUS? Yes FLAG: MASTER P IS BUSY SEND LATEST BYTE TO MASTER VIA SPI BUS EXIT ISR 2001 Microchip Technology Inc. DS00760A-page 153 AN760 NOTES: DS00760A-page 154 2001 Microchip Technology Inc. M microIDTM 13.56 MHZ DESIGN GUIDE Recommended Assembly Flows 1.0 WAFER ON FRAME ASSEMBLY FLOW Die Inspection A. Wafer thickness B. Visual inspection Die Attach A. Expoxy age/shelf life B. Expoxy voids C. Epoxy coverage D. Epoxy bleedout E. Dry past thickness F. Die shear G. Visual inspection Cure Condition A. Oven temperature profile B. Monitor cure time C. Package thickness Open/Short Testing Epoxy Cure A. Oven temperature profile B. Duration time C. Cure N2 flow rate Final Visual Inspection Wire Bond A. Cratering test B. Capillary C. Visual inspection D. Wirepull strength Visual Inspection Encapsulation A. B. C. D. Glob top life/storage Coating monitor Internal voids Wire sweep 2001 Microchip Technology Inc. DS21299D-page 155 microIDTM 13.56 MHZ DESIGN GUIDE 2.0 WAFER ASSEMBLY FLOW Die Inspection A. Wafer thickness B. Visual inspection Wafer Saw/Clean A. B. C. D. E. F. DI water resistivity DI bacteria count DI chlorine count DI particle count Cleaning pressure Kerf width Cure Condition A. Oven temperature profile B. Monitor cure time C. Package thickness Die Attach A. B. C. D. E. F. G. Expoxy age/shelf life Expoxy voids Epoxy coverage Epoxy bleedout Dry past thickness Die shear Visual inspection Open/Short Testing Final Visual Inspection Epoxy Cure A. Oven temperature profile B. Duration time C. Cure N2 flow rate Wire Bond A. B. C. D. Cratering test Capillary Visual inspection Wirepull strength Visual Inspection Encapsulation A. B. C. D. Glob top life/storage Coating monitor Internal voids Wire sweep DS21299D-page 156 2001 Microchip Technology Inc. microIDTM 13.56 MHz Design Guide NOTES: 2001 Microchip Technology Inc. DS21299D-page 157 microIDTM 13.56 MHZ DESIGN GUIDE NOTES: DS21299D-page 158 2001 Microchip Technology Inc. microIDTM 13.56 MHz Design Guide NOTES: 2001 Microchip Technology Inc. DS21299D-page 159 M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Japan Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Microchip Technology Japan K.K. Benex S-1 6F 3-18-20, Shinyokohama Kohoku-Ku, Yokohama-shi Kanagawa, 222-0033, Japan Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Rocky Mountain China - Beijing 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456 Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 New China Hong Kong Manhattan Bldg. No. 6 Chaoyangmen Beidajie Beijing, 100027, No. China Tel: 86-10-85282100 Fax: 86-10-85282104 Atlanta 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: 770-640-0034 Fax: 770-640-0307 Austin - Analog 8303 MoPac Expressway North Suite A-201 Austin, TX 78759 Tel: 512-345-2030 Fax: 512-345-6085 Boston 2 Lan Drive, Suite 120 Westford, MA 01886 Tel: 978-692-3848 Fax: 978-692-3821 Boston - Analog Unit A-8-1 Millbrook Tarry Condominium 97 Lowell Road Concord, MA 01742 Tel: 978-371-6400 Fax: 978-371-0050 Chicago 333 Pierce Road, Suite 180 Itasca, IL 60143 Tel: 630-285-0071 Fax: 630-285-0075 China - Chengdu Microchip Technology Consulting (Shanghai) Co., Ltd., Chengdu Liaison Office Rm. 2401, Ming Xing Financial Tower No. 88 TIDU Street Chengdu 610016, China Tel: 86-28-6766200 Fax: 86-28-6766599 China - Fuzhou Microchip Technology Consulting (Shanghai) Co., Ltd., Fuzhou Liaison Office Rm. 531, North Building Fujian Foreign Trade Center Hotel 73 Wusi Road Fuzhou 350001, China Tel: 86-591-7557563 Fax: 86-591-7557572 China - Shanghai 4570 Westgrove Drive, Suite 160 Addison, TX 75001 Tel: 972-818-7423 Fax: 972-818-2924 Microchip Technology Consulting (Shanghai) Co., Ltd. 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India Liaison Office Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O'Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 Dallas Detroit Tri-Atria Office Building 32255 Northwestern Highway, Suite 190 Farmington Hills, MI 48334 Tel: 248-538-2250 Fax: 248-538-2260 Los Angeles San Jose Microchip Technology Inc. 2107 North First Street, Suite 590 San Jose, CA 95131 Tel: 408-436-7950 Fax: 408-436-7955 Toronto 6285 Northam Drive, Suite 108 Mississauga, Ontario L4V 1X5, Canada Tel: 905-673-0699 Fax: 905-673-6509 Korea Microchip Technology Korea 168-1, Youngbo Bldg. 3 Floor Samsung-Dong, Kangnam-Ku Seoul, Korea 135-882 Tel: 82-2-554-7200 Fax: 82-2-558-5934 Singapore Microchip Technology Singapore Pte Ltd. 200 Middle Road #07-02 Prime Centre Singapore, 188980 Tel: 65-334-8870 Fax: 65-334-8850 Taiwan Microchip Technology Taiwan 11F-3, No. 207 Tung Hua North Road Taipei, 105, Taiwan Tel: 886-2-2717-7175 Fax: 886-2-2545-0139 EUROPE Denmark Microchip Technology Denmark ApS Regus Business Centre Lautrup hoj 1-3 Ballerup DK-2750 Denmark Tel: 45 4420 9895 Fax: 45 4420 9910 France Arizona Microchip Technology SARL Parc d'Activite du Moulin de Massy 43 Rue du Saule Trapu Batiment A - ler Etage 91300 Massy, France Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany Arizona Microchip Technology GmbH Gustav-Heinemann Ring 125 D-81739 Munich, Germany Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Germany - Analog Lochhamer Strasse 13 D-82152 Martinsried, Germany Tel: 49-89-895650-0 Fax: 49-89-895650-22 Italy Arizona Microchip Technology SRL Centro Direzionale Colleoni Palazzo Taurus 1 V. Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 06/01/01 DS21299D-page 160 2001 Microchip Technology Inc.