FN2867 Rev.10.01 Page 1 of 13
Mar 5, 2020
FN2867
Rev.10.01
Mar 5, 2020
ICM7555, ICM7556
General Purpose Timers
DATASHEET
The ICM7555 and ICM7556 are CMOS RC timers providing
significantly improved performance over the standard
SE/NE 555/556 and 355 timers, while at the same time being
direct replacements for those devices in most applications.
Improved parameters include low supply current, wide
operating supply voltage range, low Threshold, Trigger and
Reset currents, no crowbarring of the supply current during
output transitions, higher frequency performance and no
requirement to decouple Control Voltage for stable operation.
Specifically, the ICM7555 and ICM7556 are stable controllers
capable of producing accurate time delays or frequencies. The
ICM7556 is a dual ICM7555, with the two timers operating
independently of each other, sharing only V+ and GND. In the
one shot mode, the pulse width of each circuit is precisely
controlled by one external resistor and capacitor. For astable
operation as an oscillator, the free running frequency and the
duty cycle are both accurately controlled by two external
resistors and one capacitor. Unlike the regular bipolar
SE/NE 555/556 devices, the Control Voltage terminal need not
be decoupled with a capacitor. The circuits are triggered and
reset on falling (negative) waveforms, and the output inverter
can source or sink currents large enough to drive TTL loads, or
provide minimal offsets to drive CMOS loads.
Applications
•Precision timing
•Pulse generation
•Sequential timing
• Time delay generation
• Pulse width modulation
• Pulse position modulation
• Missing pulse detector
Features
• Exact equivalent in most cases for SE/NE 555/556 or
TLC555/556
• Low supply current
- ICM7555 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60µA
- ICM7556 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120µA
• Extremely low input currents . . . . . . . . . . . . . . . . . . . . . . 20pA
• High speed operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1MHz
• Guaranteed supply voltage range . . . . . . . . . . . . . . 2V to 18V
• Temperature stability . . . . . . . . . . . . . 0.005%/°C at +25°C
• Normal reset function - no crowbarring of supply during
output transition
• Can be used with higher impedance timing elements than
regular 555/556 for longer RC time constants
• Timing from microseconds through hours
• Operates in both astable and monostable modes
• Adjustable duty cycle
• High output source/sink driver can drive TTL/CMOS
• Outputs have very low offsets, HIGH and LOW
• Pb-free (RoHS Compliant)
Related Literature
For a full list of related documents, visit our website:
•ICM7555 and ICM7556 device pages
Pin Configurations
ICM7555
(8 LD PDIP, SOIC)
TOP VIEW
ICM7556
(14 LD PDIP)
TOP VIEW
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
8
7
6
5
VDD
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
DISCHARGE1
CONTROL
RESET1
OUTPUT1
TRIGGER1
GND
VDD
DISCHARGE2
THRESHOLD2
CONTROL
RESET2
OUTPUT2
TRIGGER2
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VOLTAGE2
VOLTAGE1
THRESHOLD1
ICM7555, ICM7556
FN2867 Rev.10.01 Page 2 of 13
Mar 5, 2020
Ordering Information
PART NUMBER PART MARKING
TEMP. RANGE
(°C)
TAPE AND REEL
(UNITS)
PACKAGE
(RoHS COMPLIANT) PKG. DWG. #
ICM7555CBAZ (Notes 2, 3) 7555 CBAZ 0 to +70 8 Ld SOIC M8.15
ICM7555CBAZ-T (Notes 1, 2, 3) 7555 CBAZ 0 to +70 2.5k 8 Ld SOIC M8.15
ICM7555IBAZ (Notes 2, 3) 7555 IBAZ -25 to +85 8 Ld SOIC M8.15
ICM7555IBAZ-T (Notes 1, 2, 3) 7555 IBAZ -25 to +85 2.5k 8 Ld SOIC M8.15
ICM7555IPAZ (Notes 2, 3) 7555 IPAZ -25 to +85 8 Ld PDIP E8.3
ICM7556IPDZ (Notes 2, 3) ICM7556IPDZ -25 to +85 14 Ld PDIP E14.3
NOTES:
1. Please refer to TB347 for details on reel specifications.
2. These Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate
plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Pb-free products are
MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J-STD-020.
3. For Moisture Sensitivity Level (MSL), please see product information page for ICM7555, ICM7556. For more information on MSL, please see tech brief
TB363.
ICM7555, ICM7556
FN2867 Rev.10.01 Page 3 of 13
Mar 5, 2020
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +18V
Input Voltage
Trigger, Control Voltage, Threshold,
Reset (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . V+ +0.3V to GND -0.3V
Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100mA
ESD Rating
Human Body Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2kV
Charged Device Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100V
Operating Conditions
Temperature Range
ICM7555C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C
ICM7555I, ICM7556I . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25°C to +85°C
Thermal Resistance (Typical, Notes 5, 6)θJA (°C/W) θJC (°C/W)
14 Ld PDIP Package* . . . . . . . . . . . . . . . . 115 46
8 Ld PDIP Package* . . . . . . . . . . . . . . . . . 130 69
8 Ld SOIC Package. . . . . . . . . . . . . . . . . . . 170 67
Maximum Junction Temperature (Hermetic Package) . . . . . . . . . . . .+175°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . -65°C to +150°C
* Pb-free PDIPs can be used for through-hole wave solder
processing only. They are not intended for use in Reflow solder
processing applications.
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than V+ +0.3V
or less than V- -0.3V may cause destructive latch-up. For this reason it is recommended that no inputs from external sources not operating from the
same power supply be applied to the device before its power supply is established. In multiple supply systems, the supply of the ICM7555 and
ICM7556 must be turned on first.
5. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications Applies to ICM7555 and ICM7556, unless otherwise specified.
PARAMETER SYMBOL TEST CONDITIONS
TA = +25°C
UNITMIN TYP MAX
Static Supply Current IDD ICM7555 VDD = 5V 40 200 µA
VDD = 15V 60 300 µA
ICM7556 VDD = 5V 80 400 µA
VDD = 15V 120 600 µA
Monostable Timing Accuracy RA = 10k, C = 0.1µF, VDD = 5V 2 %
µs
Drift with Temperature (Note 7)V
DD = 5V ppm/°C
VDD = 10V ppm/°C
VDD = 15V ppm/°C
Drift with Supply (Note 7)V
DD = 5V to 15V 0.5 %/V
Astable Timing Accuracy RA = RB = 10k, C = 0.1µF, VDD = 5V 2 %
µs
Drift with Temperature (Note 7)V
DD = 5V ppm/°C
VDD = 10V ppm/°C
VDD = 15V ppm/°C
Drift with Supply (Note 7)V
DD = 5V to 15V 0.5 %/V
Threshold Voltage VTH VDD = 15V 62 67 71 % VDD
Trigger Voltage VTRIG VDD = 15V 28 32 36 % VDD
Trigger Current ITRIG VDD = 15V 10 nA
Threshold Current ITH VDD = 15V 10 nA
Control Voltage VCV VDD = 15V 62 67 71 % VDD
Reset Voltage VRST VDD = 2V to 15V 0.4 1.0 V
ICM7555, ICM7556
FN2867 Rev.10.01 Page 4 of 13
Mar 5, 2020
Reset Current IRST VDD = 15V 10 nA
Discharge Leakage IDIS VDD = 15V 10 nA
Output Voltage VOL VDD = 15V, ISINK = 20mA 0.4 1.0 V
VDD = 5V, ISINK = 3.2mA 0.2 0.4 V
VOH VDD = 15V, ISOURCE = 0.8mA 14.3 14.6 V
VDD = 5V, ISOURCE = 0.8mA 4.0 4.3 V
Discharge Output Voltage VDIS VDD = 5V, ISINK = 15mA 0.2 0.4 V
VDD = 15V, ISINK = 15mA V
Supply Voltage (Note 7)V
DD Functional Operation 2.0 18.0 V
Output Rise Time (Note 7)t
RRL = 10M, CL = 10pF, VDD = 5V 75 ns
Output Fall Time (Note 7)t
FRL = 10M, CL = 10pF, VDD = 5V 75 ns
Oscillator Frequency (Note 7)f
MAX VDD = 5V, RA = 470Ω, RB = 270Ω,
C = 200pF
1MHz
NOTES:
7. These parameters are based upon characterization data and are not tested.
Electrical Specifications Applies to ICM7555 and ICM7556, unless otherwise specified. (Continued)
PARAMETER SYMBOL TEST CONDITIONS
TA = +25°C
UNITMIN TYP MAX
Functional Diagram
FIGURE 1. FUNCTIONAL DIAGRAM
+
-
THRESHOLD
CONTROL
VOLTAGE
6
53
1
+
-
TRIGGER
2
COMPARATOR
R
GND
B
COMPARATOR
A
R
VDD
8
OUTPUT
7
1
n
DISCHARGE
OUTPUT
DRIVERS
FLIP-FLOP
RESET
4
R
NOTE: This functional diagram reduces the circuitry down to its simplest equivalent components. Tie down unused inputs.
TRUTH TABLE
THRESHOLD VOLTAGE TRIGGER VOLTAGE RESET OUTPUT DISCHARGE SWITCH
Don’t Care Don’t Care Low Low On
>2/3(V+) >1/3(V+) High Low On
<2/3(V+) >1/3(V+) High Stable Stable
Don’t Care <1/3(V+) High High Off
NOTE: RESET will dominate all other inputs: TRIGGER will dominate over THRESHOLD.
ICM7555, ICM7556
FN2867 Rev.10.01 Page 5 of 13
Mar 5, 2020
Application Information
General
The ICM7555 and ICM7556 devices are, in most instances,
direct replacements for the SE/NE 555/556 devices. However,
it is possible to effect economies in the external component
count using the ICM7555 and ICM7556. Because the bipolar
SE/NE 555/556 devices produce large crowbar currents in the
output driver, it is necessary to decouple the power supply
lines with a good capacitor close to the device. The ICM7555
and ICM7556 devices produce no such transients (see
Figure 3).
The ICM7555 and ICM7556 produce supply current spikes of
only 2mA to 3mA instead of 300mA to 400mA and supply
decoupling is normally not necessary. Also, in most instances,
the Control Voltage decoupling capacitors are not required
since the input impedance of the CMOS comparators on chip
are very high. Thus, for many applications, two capacitors can
be saved using an ICM7555 and three capacitors with an
ICM7556.
POWER SUPPLY CONSIDERATIONS
Although the supply current consumed by the ICM7555 and
ICM7556 devices is very low, the total system supply current
can be high unless the timing components are high
impedance. Therefore, use high values for R and low values for
C in Figures 4, 5, and 6.
Schematic Diagram
FIGURE 2. SCHEMATIC DIAGRAM
RESET DISCHARGE
TRIGGER
THRESHOLD
GND
OUTPUT
CONTROL
VOLTAGE
R
NN
NPN
P
R
R
VDD
NNNNN
PP
NN
PP P
R = 100kΩ ±20% (TYP)
TIME (ns)
400 8006002000
0
100
200
300
400
500
SUPPLY CURRENT (mA)
SE/NE 555
TA = +25°C
ICM7555/556
FIGURE 3. SUPPLY CURRENT TRANSIENT COMPARED WITH A
STANDARD BIPOLAR 555 DURING AN OUTPUT
TRANSITION
GND
TRIGGER
OUTPUT
RESET
1
2
3
4
8
7
6
5
VDD
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
VDD
10k
ALTERNATE OUTPUT
OPTIONAL
CAPACITOR
C
VDD
R
FIGURE 4. ASTABLE OPERATION
ICM7555, ICM7556
FN2867 Rev.10.01 Page 6 of 13
Mar 5, 2020
OUTPUT DRIVE CAPABILITY
The output driver consists of a CMOS inverter capable of
driving most logic families including CMOS and TTL. As such, if
driving CMOS, the output swing at all supply voltages will equal
the supply voltage. At a supply voltage of 4.5V or more, the
ICM7555 and ICM7556 will drive at least two standard TTL
loads.
ASTABLE OPERATION
The circuit can be connected to trigger itself and free run as a
multivibrator, see Figure 4. The output swings from rail-to-rail,
and is a true 50% duty cycle square wave. Trip points and
output swings are symmetrical. Less than a 1% frequency
variation is observed over a voltage range of +5V to +15V.
The timer can also be connected as shown in Figure 5. In this
circuit, the frequency is as shown by Equation 2:
The duty cycle is controlled by the values of RA and RB, by
Equation 3:
MONOSTABLE OPERATION
In this mode of operation, the timer functions as a one-shot (see
Figure 6). Initially the external capacitor (C) is held discharged by
a transistor inside the timer. Upon application of a negative
Trigger pulse to pin 2, the internal flip-flop is set, which releases
the short-circuit across the external capacitor and drives the
Output high. The voltage across the capacitor now increases
exponentially with a time constant t = RAC. When the voltage
across the capacitor equals 2/3 V+, the comparator resets the
flip-flop, which in turn discharges the capacitor rapidly and also
drives the OUTPUT to its low state. Trigger must return to a high
state before the OUTPUT can return to a low state.
CONTROL VOLTAGE
The Control Voltage terminal permits the two trip voltages for
the Threshold and Trigger internal comparators to be
controlled. This provides the possibility of oscillation frequency
modulation in the astable mode or even inhibition of
oscillation, depending on the applied voltage. In the
monostable mode, delay times can be changed by varying the
applied voltage to the Control Voltage pin.
RESET
The Reset terminal is designed to have essentially the same
trip voltage as the standard bipolar 555/556, i.e., 0.6V to 0.7V.
At all supply voltages it represents an extremely high input
impedance. The mode of operation of the Reset function is,
however, much improved over the standard bipolar
SE/NE 555/556 in that it controls only the internal flip-flop,
which in turn controls simultaneously the state of the Output
and Discharge pins. This avoids the multiple threshold
problems sometimes encountered with slow falling edges in
the bipolar devices.
OUTPUT
1
2
3
4
8
7
6
5
VDD
OPTIONAL
CAPACITOR
C
VDD
RA
RB
FIGURE 5. ALTERNATE ASTABLE CONFIGURATION
f1
1.4 RC
------------------
=(EQ. 1)
f1.44R
A2RB
+()⁄C=(EQ. 2)
DR
ARB
+()RA2RB
+()⁄=(EQ. 3)
TRIGGER
OUTPUT
RESET
1
2
3
4
8
7
6
5
VDD
DISCHARGE
THRESHOLD
CONTROL
VOLTAGE
OPTIONAL
CAPACITOR C
VDD ≤18V
RA
ICM7555
tOUTPUT = -ln (1/3) RAC = 1.1RAC
FIGURE 6. MONOSTABLE OPERATION
ICM7555, ICM7556
FN2867 Rev.10.01 Page 7 of 13
Mar 5, 2020
Typical Performance Curves
FIGURE 7. MINIMUM PULSE WIDTH REQUIRED FOR TRIGGERING FIGURE 8. SUPPLY CURRENT vs SUPPLY VOLTAGE
FIGURE 9. OUTPUT SOURCE CURRENT vs OUTPUT VOLTAGE FIGURE 10. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
FIGURE 11. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE FIGURE 12. OUTPUT SINK CURRENT vs OUTPUT VOLTAGE
TA = +25°C
VDD = 2V
VDD = 18V
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%VDD)
VDD = 5V
MINIMUM PULSE WIDTH (ns)
010203040
0
1200
1100
1000
900
800
700
600
500
400
300
200
100
SUPPLY VOLTAGE (V)
TA = +25°C
SUPPLY CURRENT (ICM7555) (µA)
SUPPLY CURRENT (ICM7556) (µA)
TA = -20°C
TA = +70°C
0 2 4 6 8 10121416 18 20
0
200
180
160
140
120
100
80
60
40
20
400
360
320
280
240
200
160
120
80
40
0
T
A
= +25°C
VDD = 2V
VDD = 5V
VDD = 18V
OUTPUT SOURCE CURRENT (mA)
-100
-10.0
-1.0
-0.1
-0.01-0.1-1.0-10
OUTPUT VOLTAGE REFERENCED TO VDD (V)
TA = -20°C
OUTPUT LOW VOLTAGE (V)
VDD = 2V
VDD = 5V
VDD = 18V
OUTPUT SINK CURRENT (mA)
0.01 0.1 1.0 10.0
0.1
100
10.0
1.0
TA = +25°C
OUTPUT LOW VOLTAGE (V)
VDD = 2V
VDD = 5V
VDD = 18V
OUTPUT SINK CURRENT (mA)
0.01 0.1 1.0 10.0
0.1
100
10.0
1.0
TA = +70°C
OUTPUT LOW VOLTAGE (V)
VDD = 2V
VDD = 5V
VDD = 18V
OUTPUT SINK CURRENT (mA)
0.01 0.1 1.0 10.0
0.1
100
10.0
1.0
ICM7555, ICM7556
FN2867 Rev.10.01 Page 8 of 13
Mar 5, 2020
FIGURE 13. NORMALIZED FREQUENCY STABILITY IN THE ASTABLE
MODE vs SUPPLY VOLTAGE
FIGURE 14. DISCHARGE OUTPUT CURRENT vs DISCHARGE OUTPUT
VOLTAGE
FIGURE 15. PROPAGATION DELAY vs VOLTAGE LEVEL OF TRIGGER
PULSE
FIGURE 16. NORMALIZED FREQUENCY STABILITY IN THE ASTABLE
MODE vs TEMPERATURE
FIGURE 17. FREE RUNNING FREQUENCY vs RA, RB AND C FIGURE 18. TIME DELAY IN THE MONOSTABLE MODE vs
RA AND C
Typical Performance Curves (Continued)
SUPPLY VOLTAGE (V)
TA = +25°C
NORMALIZED FREQUENCY DEVIATION (%)
RA = RB = 10MΩ
0.1 1.0 10.0 100.0
8
8
6
4
2
0
2
4
6
C = 100pF
RA = RB = 10kΩ
C = 0.1µF
TA = +25°C
DISCHARGE LOW VOLTAGE (V)
VDD = 2V
VDD = 5V
VDD = 18V
DISCHARGE SINK CURRENT (mA)
0.01 0.1 1.0 10.0
0.1
100
10.0
1.0
TA = +25°C
LOWEST VOLTAGE LEVEL OF TRIGGER PULSE (%VDD)
VDD = 5V
PROPAGATION DELAY (ns)
010203040
0
600
500
400
300
200
100
TA = +70°C
TA = -20°C
TEMPERATURE (°C)
NORMALIZED FREQUENCY DEVIATION (%)
06080
-0.1
+0.1
0
RA = RB = 10kΩ
C = 0.1µF
4020-20
+0.2
+0.3
+0.4
+0.5
+0.6
+0.7
+0.8
+0.9
+1.0
VDD = 2V
VDD = 5V
VDD = 18V
VDD = 2V
TA = +25°C
FREQUENCY (Hz)
(RA + 2RB)1kΩ
10kΩ
100kΩ
1MΩ
10MΩ
100MΩ
100.1 1 100 1k 10k 100k 1M 10M
CAPACITANCE (F)
1.0
100m
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
TIME DELAY (s)
1kΩ
10kΩ
100kΩ
1MΩ
10MΩ
100MΩ
10µ
100n 1µ 100µ 1m 10m 100m 1 10
CAPACITANCE (F)
1.0
100m
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
RA
TA = +25°C
ICM7555, ICM7556
FN2867 Rev.10.01 Page 9 of 13
Mar 5, 2020
Revision History The revision history provided is for informational purposes only and is believed to be accurate, but not warranted.
Please go to the web to make sure that you have the latest revision.
DATE REVISION CHANGE
Mar 5, 2020 10.01 Added Related Literature section.
Removed CERDIP part information.
Added ESD information.
Removed About Intersil
Updated Disclaimer
Jun 28, 2016 10.00 Converted to new datasheet template.
Updated 14 Ld PDIP “Pin Configuration” on page 1 by adding “1” or “2” to pins that have same name.
Updated “Thermal Information” on page 3 by removing Maximum Lead Temperature and Adding TJC
values with corresponding note.
Updated “Ordering Information” table on page 2 by removing obsoleted parts, adding Tape and Reel
option column, adding MSL note and numbering notes accordingly.
Updated POD M8.15 to most current version. POD changes are as follows:
Changed in Typical Recommended Land Pattern the following:
2.41(0.095) to 2.20(0.087)
0.76 (0.030) to 0.60(0.023)
0.200 to 5.20(0.205)
Updated to new POD format by removing table and moving dimensions onto drawing and adding land
pattern
ICM7555, ICM7556
FN2867 Rev.10.01 Page 10 of 13
Mar 5, 2020
Package Outline Drawing
M8.15
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE
Rev 4, 1/12
DETAIL "A"
TOP VIEW
INDEX
AREA
123
-C-
SEATING PLANE
x 45°
NOTES:
1. Dimensioning and tolerancing per ANSI Y14.5M-1994.
2. Package length does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
3. Package width does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
4. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
5. Terminal numbers are shown for reference only.
6. The lead width as measured 0.36mm (0.014 inch) or greater above the
seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch).
7. Controlling dimension: MILLIMETER. Converted inch dimensions are not
necessarily exact.
8. This outline conforms to JEDEC publication MS-012-AA ISSUE C.
SIDE VIEW “A
SIDE VIEW “B”
1.27 (0.050)
6.20 (0.244)
5.80 (0.228)
4.00 (0.157)
3.80 (0.150)
0.50 (0.20)
0.25 (0.01)
5.00 (0.197)
4.80 (0.189)
1.75 (0.069)
1.35 (0.053)
0.25(0.010)
0.10(0.004)
0.51(0.020)
0.33(0.013)
8°
0°
0.25 (0.010)
0.19 (0.008)
1.27 (0.050)
0.40 (0.016)
1.27 (0.050)
5.20(0.205)
1
2
3
45
6
7
8
TYPICAL RECOMMENDED LAND PATTERN
2.20 (0.087)
0.60 (0.023)
For the most recent package outline drawing, see M8.15.
ICM7555, ICM7556
FN2867 Rev.10.01 Page 11 of 13
Mar 5, 2020
C
L
E
eA
C
eB
eC
-B-
E1
INDEX 12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AMBS
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2
of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be
perpendicular to datum .
7. eB and eC are measured at the lead tips with the leads
unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 -
1.14mm).
eA
-C-
E8.3 (JEDEC MS-001-BA ISSUE D)
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.210 -5.33 4
A1 0.015 -0.39 -4
A2 0.115 0.195 2.93 4.95 -
B0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C0.008 0.014 0.204 0.355 -
D0.355 0.400 9.01 10.16 5
D1 0.005 -0.13 -5
E0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB-0.430 -10.92 7
L0.115 0.150 2.93 3.81 4
N8 89
Rev. 0 12/93
For the most recent package outline drawing, see E8.3.
ICM7555, ICM7556
FN2867 Rev.10.01 Page 12 of 13
Mar 5, 2020
eA
-C-
E14.3 (JEDEC MS-001-AA ISSUE D)
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE (PDIP)
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A-0.210 -5.33 4
A1 0.015 -0.39 -4
A2 0.115 0.195 2.93 4.95 -
B0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8
C0.008 0.014 0.204 0.355 -
D0.735 0.775 18.66 19.68 5
D1 0.005 -0.13 -5
E0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
eA0.300 BSC 7.62 BSC 6
eB-0.430 -10.92 7
L0.115 0.150 2.93 3.81 4
N14 149
Rev. 0 12/93
For the most recent package outline drawing, see E14.3.
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