Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
xr XRT85L61
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
OCTOBER 2004 REV. 1.0.2
GENERAL DESCRIPTION
The XRT85L61 is an integrated E1, T1, 64KHz
Centralized Clock interface for T1 (1.544Mbps) 100Ω,
E1 (2.048Mbps) 75Ω or 120Ω applications.
The XRT85L61 extracts either 2048kHz or 1544 kHz
clock signals from an E1 (2.048 MHz), T1 (1.544
Mhz) inputs respectively or 64 KHz, 8kHz or 400 Hz
clock signals from the 64kHz reference clock input.
The XRT85L61 includes an on-chip crystal-less jitter
attenuator with 32 bit FIFO that can either be enabled
or disabled.
FEATURES
•Fully integrated single chip solution for E1,T1 or 64
kHz clock synchronization applications.
•Extracts 2048 kHz, 1544 kHz clock and data
components
• Extracts 64 KHz and 8 kHz, 400 Hz clock
information
•Line Code Violation alarms
•On-chip digital clock recovery circuit
•Supports 75Ω and 120Ω (E1), 100Ω (T1)
applications.
•Crystal-less digital jitter attenuator with 32-bit FIFO
that can either be enabled or disabled
•Receive loss of signal (RLOS) output
•Meets Telcordia GR-1244-CORE Section 3.4.1 R3-
27 specification
•Meets or exceeds T1 and E1 specifications in ITU
G.703, G.775
•Single +3.3V Supply Operation
•Logic inputs accept either 3.3 V or 5 V levels
•28 pin TSSOP package
APPLICATIONS
•Universal Clock Synchronization for G.703 Telecom
Formats
•T1/E1 Line Receiver with Clock and Data Recovery
•DSLAM
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61
Master Clock
Generator
Rx
Equalizer
MCLK1
(1.544 MHz for T1)
MCLK2
(2.048 MHz for E1
or 64 kbps)
Reference Inputs
RTIP
RRING
Line Side Peak Detector
and Slicer
Clock and
Data
Recovery
Jitter
Attenuator
Clock
Extractor
Line code
and clock
violation
Detector
RPOS
RNEG
RCLK
(64kHz,1544kHz or 2048kHz)
8 kHz (for 64 kbps)
400 Hz (for 64 kbps)
RCLK_LCV/AIS
8 kHz_LCV/BPV
400 Hz_LCV
LOS
Detector RLOS
Mode Select
T1, E1 or 64 kbps
S1
S2
S3
(T1 or E1 or 64 kbps input)
JAEN
DATAMUT
DATA_INV
RCLKINV
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ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT85L61IG 28 Lead TSSOP -40°C to +85°C
FIGURE 2. PIN OUT OF THE XRT85L61
MCLK1
MCLK2
JAEN
JAVDD
JAGND
ICT
RTIP
RRING
AVDD
AGND
S1
S2
S3
NC
RCLKINV
DATA_LCV
RCLK_LCV
8 KHz_LCV
400 Hz_LCV
8 KHz
400 Hz
RLOS
DVDD
DGND
RCLK
RPOS
RNEG
DATMUT
1
2
9
13
12
11
10
8
7
6
5
4
3
14
28
27
20
16
17
18
19
21
22
23
24
25
26
15
MCLK1
JAEN
MCLK2
JAVDD
JAGND
ICT
RTIP
RRING
AVDD
AGND
S1
S2
S3
NC
RCLKINV
DATA_INV
RCLK_LCV/ AIS
8 KHz_LCV/ BPV
400 Hz_LCV
8 KHz
400 Hz
RLOS
DVDD
DGND
RCLK
RPOS
RNEG
DATMUT
1
2
9
13
12
11
10
8
7
6
5
4
3
14
28
27
20
16
17
18
19
21
22
23
24
25
26
15
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TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT85L61 ............................................................................................................................... 1
ORDERING INFORMATION .................................................................................................................... 2
FIGURE 2. PIN OUT OF THE XRT85L61............................................................................................................................................ 2
PIN DESCRIPTIONS .......................................................................................................... 3
ELECTRICAL CHARACTERISTICS.................................................................................. 5
ABSOLUTE MAXIMUM RATINGS ............................................................................................................. 5
TABLE 1: DC Electrical Characteristics .................................................................................................. 5
TABLE 2: E1 RECEIVER SENSITIVITY................................................................................................................................................. 5
TABLE 3: T1 RECEIVER SENSITIVITY................................................................................................................................................. 6
TABLE 4: 64KBITS/SEC RECEIVER SENSITIVITY ................................................................................................................................. 6
FIGURE 3. TIMING DIAGRAM FOR SYSTEM INTERFACE ....................................................................................................................... 6
TABLE 5: AC ELECTRICAL SPECIFICATIONS....................................................................................................................................... 7
FUNCTIONAL DESCRIPTION ........................................................................................... 8
1.0 OPERATING MODE: ............................................................................................................................. 8
TABLE 6: OPERATING MODE SELECTION........................................................................................................................................... 8
1.1 64 KHZ CLOCK MODE: ................................................................................................................................... 8
TABLE 7: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT INPUT PORT ............................................................................... 8
TABLE 8: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT............................................................................ 9
1.1.1 64 KHZ + 8 KHZ CLOCK EXTRACTION...................................................................................................................... 9
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0)................................................................................... 9
1.1.2 64 KHZ + 8 KHZ + 400 HZ CLOCK EXTRACTION ...................................................................................................... 9
FIGURE 5. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1) ................................................................. 10
1.2 2048 KHZ RZ E1 MODE ................................................................................................................................. 10
FIGURE 6. E1 PULSE MASK (G.703) .............................................................................................................................................. 10
TABLE 9: G.703 SPECIFICATION E1 ............................................................................................................................................... 11
1.3 2048 KHZ NRZ MODE .................................................................................................................................... 12
FIGURE 7. E1 CLOCK SIGNAL WAVE SHAPE - G.703 ...................................................................................................................... 12
TABLE 10: G.703 2048 KHZ CLOCK INTERFACE ............................................................................................................................. 12
1.4 1544 KHZ T1 MODE ....................................................................................................................................... 13
FIGURE 8. G.703 DS1 WAVE FORM............................................................................................................................................... 13
2.0 AIS DETECTION TIMING ................................................................................................................... 14
FIGURE 9. AIS DETECTION FOR E1 MODE ...................................................................................................................................... 14
FIGURE 10. AIS DETECTION FOR T1 MODE .................................................................................................................................... 14
3.0 LOSS OF SIGNAL ............................................................................................................................... 14
4.0 APPLICATIONS ................................................................................................................................... 15
FIGURE 11. CEPT APPLICATION FOR TWISTED PAIR INTERFACE ..................................................................................................... 15
FIGURE 12. CEPT APPLICATION FOR COAXIAL INTERFACE.............................................................................................................. 15
FIGURE 13. T1 APPLICATION FOR TWISTED PAIR INTERFACE........................................................................................................... 15
FIGURE 14. 64KBPS APPLICATION FOR TWISTED PAIR...................................................................................................................... 16
TRANSFORMER RECOMENDATION ................................................................................................................. 16
FIGURE 15. CONNECTING THE PULSE ENGINEERING PE-65535 1:2CT TRANSFORMER TO THE XRT85L61 ...................................... 16
ORDERING INFORMATION .................................................................................................................. 17
REVISION HISTORY ............................................................................................................................ 18
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BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR REV. 1.0.2
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PIN DESCRIPTIONS
PIN # SYMBOL TYPE DESCRIPTION
1MCLK1 IReference T1 Clock input:
This signal is an independent 1544 kHz clock with accuracy better than
+ 32 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in T1 mode. This signal must be
available for the device to operate.
2JAEN IJitter Attenuator Enable:
Tie this pin “High” to enable the Jitter Attenuator. When enabled, a 32 bit
FIFO is included in the data path for all modes of operation.
NOTE: Internally Pulled down with 50 kΩ resistor
3MCLK2 IReference E1 and 64 kHz Clock Input:
This signal is an independent 2048 kHz clock with accuracy better than +
50 ppm and duty cycle within 40% to 60%. This clock provides timing
source for the PLL clock recovery circuit in E1 and 64 kHz mode. This
signal must be available for the device to operate.
NOTE: To reduce intrinsic jitter when JA is enabled, it is recommended to
have reference clock with an accuracy of ± 25 ppm or better.
4JAVDD *** VDD for Jitter Attenuator (3.3V ± 5%)
5JAGND *** Jitter Attenuator Ground
6ICT IIn circuit Testing
When this pin is grounded, all output pins are Tri-stated for testing pur-
poses.
NOTE: Internally Pulled up with 50 kΩ resistor
7RTIP IReceive Positive Input
8RRING IReceive Negative Input
9AVDD *** Analog VDD (3.3V ± 5%)
10 AGND *** Analog Ground
11 S1 IMode Select
NOTE: T1 NRZ or E1 NRZ means the output data at RPOS and RNEG
are 1 RCLK wide.
S2 S3
0 0
0 1
1 0
1 1
MODE
64 kHz + 8 kHz
64kHz+8kHz+400Hz
E1 RZ
E1 NRZ
S1
0
0
0
0
0 0
0 1
1
1 1
T1
T1 (output full width data)
E1 (output full width data)
Reserved
1
1
1
1
0
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12 S2 IMode Select
13 S3 IMode Select
14 NC *** This pin must be grounded for normal operation
15 DATMUT IData Muting:
Connect this pin “High” to mute data output to “Low” state at RPOS/
RNEG. The RLOS pin can be connected to this pin to mute the output
when RLOS occurs.
NOTE: Internally Pulled down with 50 kΩ resistor
16 RNEG OReceive Negative Data Output:
The data is half clock cycle wide.
17 RPOS OReceive Positive Data Output:
The data is half clock cycle wide
18 RCLK OReceive Clock Output
Outputs either 1.544 MHz or 2.048 MHz or 64 kHz clock
19 DGND *** Digital Supply Ground
20 DVDD *** Digital Supply Voltage (3.3V ± 5%)
21 RLOS OReceive Loss of Signal Output
22 400Hz O400 Hz Clock output for 64 kHz Operation
23 8 kHz O8 kHz clock output for 64 kHz Operation
24 400Hz_LCV OLine Code Violation for 400 Hz
This pin will stay “High” when 400 Hz is not in sync.
25 8 kHz_LCV/
BPV
OLine Code Violation for 8 kHz in 64 kHz operation
Bipolar Violation:
In E1RZ or T1 mode, every Bipolar violation valid or not valid is indicated
at this pin.
This pin will stay “High” when 8 kHz is not in sync.
26 RCLK_LCV/AIS OReceive Clock Violation.
In 64 kbps operation, every missing pulse will cause this pin to go “High”
for half the clock cycle
AIS Indication
In E1RZ or T1 mode, this output serves as an AIS indicator. AIS will stay
“High” for 250 µs in E1 RZ mode, and in T1 mode, AIS will stay “High” for
3 ms.
27 DATA_INV IData Invert:
Connect this pin “High” to output active “Low” data at RPOS/RNEG.
NOTE: Internally Pulled down with 50 kΩ resistor
28 RCLK_INV IReceive Clock Invert:
Connect this pin “High” to align the data to change at the falling edge of
RCLK.
NOTE: Internally Pulled down with 50 kΩ resistor
PIN DESCRIPTIONS
PIN #SYMBOL TYPE DESCRIPTION
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ELECTRICAL CHARACTERISTICS
NOTE: * Not applicable to pins with pull-down resistors.
ABSOLUTE MAXIMUM RATINGS
Storage Temperature - 65°C to + 150°C
Operating Temperature - 40°C to + 85°C
Supply Voltage Range -0.5V to +6.0V
ESD 2000 V
Theta-JA 68°C/W
Theta-JC 13°C/W
TABLE 1: DC Electrical Characteristics
(TA = -40°C TO 85°C, VDD = 3.3 V + 5%, unless otherwise specified)
SYMBOL PARAMETER MIN.TYP. MAX. UNITS
VDDD DC Supply Voltage (Digital) 3.135 3.3 3.465 V
VDDA DC Supply Voltage (Analog) 3.135 3.3 3.465 V
-Power Consumption 42 50 mW
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 VDD V
VOL Output Low Voltage, IOUT = -4.0mA 00.4 V
VOH Output High Voltage, IOUT = 4.0mA 2.4 VDD V
ILInput Leakage Current* ±10 µA
CIInput Capacitance 5pF
CLOutput Load Capacitance 25 pF
TABLE 2: E1 RECEIVER SENSITIVITY
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
PARAMETER
MIN
CABLE
LOSS
TYP MAX UNIT TEST CONDITION
Receiver Sensitivity with PBRS
223-1 pattern
NOTE: 0dB = 2.37Vp
9dB 9dB Cable Loss
6dB 6dB Cable Loss + 6dB Flat Loss
4dB 4dB Cable Loss + 8dB Flat Loss
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TABLE 3: T1 RECEIVER SENSITIVITY
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
PARAMETER
MIN
CABLE
LOSS
TYP MAX UNIT TEST CONDITION
Receiver Sensitivity with PBRS
215-1 pattern
NOTE: 0dB = 3.0Vp
9dB 9dB Cable Loss
6dB 6dB Cable Loss + 6dB Flat Loss
4dB 4dB Cable Loss + 8dB Flat Loss
TABLE 4: 64KBITS/SEC RECEIVER SENSITIVITY
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
PARAMETER MIN TYP MAX UNIT TEST CONDITION
Receiver Sensitivity with Bipo-
lar Violation Encoded "All 1’s"
Pattern
NOTE: 0dB = 1.0Vp
9dB 9dB Cable Loss
6dB 6dB Cable Loss + 6dB Flat Loss
4dB 4dB Cable Loss + 8dB Flat Loss
FIGURE 3. TIMING DIAGRAM FOR SYSTEM INTERFACE
RClk
RPOS/RNEG
RZ Mode
RPOS/RNEG
NRZ Mode
tDH
tDS
tRp tRp
RClk trRClk tf
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TABLE 5: AC ELECTRICAL SPECIFICATIONS
Vdd = 3.3V+5%, TA = -40°C to 85°C, Unless Otherwise Specified
SYMBOL PARAMETER MIN TYP MAX UNITS
-Receive Clock Duty Cycle 45 50 55 %
RClk tr/RClk tfReceive Clock Rise/Fall time (10 - 90%) -3.0 -ns
tRp RClk to RPOS/RNEG Delay 0 - 10 ns
tDS Receive Data Setup Time 20 - - ns
tDH Receive Data Hold Time 20 - - ns
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FUNCTIONAL DESCRIPTION
The XRT85L61 is an integrated BITS (Building Integrated Timing Supply) Clock Generator. Simplified block
diagram of the chip is shown in Figure 1.
The XRT85L61 extracts the clock signals from the following synchronization lines:
■ Balanced 100 Ω lines with 1544 kbps DS1 pattern.
■ Balanced 120 Ω or unbalanced 75 Ω lines with 2048 kbps RZ pattern.
■ Balanced 120 Ω or unbalanced 75 Ω line with 2048 kbps NRZ pattern.
■ Balanced 110 Ω line with 64 kbps having 8 kHz violations; a “64 kHz + 8 kHz sync pattern.
■ Balanced 110 Ω line with a 64 kbps pattern having both 8 kHz and 400 Hz violations; a “64 kHz + 8 kHz
+ 400 Hz” sync pattern.
1.0 OPERATING MODE:
The operating mode for the XRT85L61 is shown in Table 6.
1.1 64 kHz Clock Mode:
The XRT85L61 receives the 64 kbps ternary RZ signal. Two modes of 64 kHz operation is possible by
selecting S1, S2 and S3 as shown in Table 1.
TABLE 6: OPERATING MODE SELECTION
S1 S2 S3 MODE DATA OUTPUT AT
RPOS / RNEG
000 64 kHz + 8 kHz RZ
001 64 kHz + 8 kHz + 400 Hz RZ
010 E1RZ RZ
011 E1NRZ RZ
100 T1 RZ
101 T1 (full width) NRZ
110 E1 (full width) NRZ
111 Reserved
TABLE 7: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT INPUT PORT
FREQUENCY (A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ
Signal Format (a) AMI with 8 kHz Bipolar Violation
(b) AMI with 8 kHz Bipolar Violation removed at every 400 Hz.
Alarm Condition Alarm should not occur against the amplitude range from 0.63 V to 1.1 V
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1.1.1 64 kHz + 8 kHz Clock Extraction
The input data is shown in Figure 4. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar Violation.
Both the 64 kHz and 8 kHz components are extracted from the composite received signal and presented at the
64 kHz and 8 kHz output pins.
1.1.2 64 kHz + 8 kHz + 400 Hz Clock Extraction
Figure 4 shows the input data for this mode. The 64 kHz clock signal consist of AMI code with 8 kHz Bipolar
Violation removed every 400 Hz. The 64 kHz, 8 kHz and 400 Hz components are extracted from the composite
received signal and presented at the RClk, 8 kHz and 400 Hz output pins.
NOTE: The inputs are not aligned with all output signals. The above diagram is used to depict the output activity when the
input signals have errors.
TABLE 8: G.703 SPECIFICATION FOR THE 64 KHZ CLOCK SIGNAL AT OUTPUT PORT
FREQUENCY (A) 64 KHZ + 8 KHZ OR (B) 64 KHZ + 8 KHZ + 400 HZ
Load Impedance 110 Ω resistive
Transmission Media Symmetric Pair Cable
Pulse Width (FWHM) < 7.8 ± 0.78 µs
Amplitude < 1 V ± 0.1 V
FIGURE 4. INPUT DATA 64 KHZ + 8 KHZ OPERATION (S1 = 0, S2 = 0, S3 = 0)
V
VV
V
RTIP/
RRING
64kHz
Clock
RPOS
RNEG
8kHz Clock
RClk_LCV
8kH_LCV
Missing Pulse Missing Pulse or Wrong Polarity Pulse
Missing Pulse
Missing Pulse
Missing Pulse Not Valid Violation
Not Valid Violation
Missing Pulse or No Violation Bit
If Pulse Missing at RTIP/RRING
out of sync
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NOTES:
1. V1 and V2 indicate AMI code-rule violations, and give the 8kHz timing.
2. V1 and V2 have different violation polarity with respect to each other.
3. nV indicates no violation (violation stealing) and gives the 400 Hz timing.
1.2 2048 kHz RZ E1 Mode
In this mode, the XRT85L61 receives a standard E1 signal as shown in Figure 6. Table 4 gives the details of
the E1 pulse.
FIGURE 5. INPUT DATA 64 KHZ + 8 KHZ + 400 HZ OPERATION (S1 = 0, S2 = 0, S3 = 1)
FIGURE 6. E1 PULSE MASK (G.703)
V1
125µs
(8 kHz)
125µs
(8 kHz)
125µs
(8 kHz)
125µs
(8 kHz)
nV V2 V1 V2 nV
(8 kHz)
(400 Hz)
(400 Hz)
LCV
if nV is
Missing
10% 10%
10%10%
10% 10%
269 ns
(244 + 25 )
194 ns
(244–50)
244 ns
219 ns
(24 4 – 2 5)
488 ns
(244 + 244)
0%
50%
20%
V = 100%
Nominal pulse
Note – V corresponds to the nominal peak value.
20%
20%
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TABLE 9: G.703 SPECIFICATION E1
PULSE INTERFACE
Pulse Shape (nominally rectangular) All Marks of a valid signal must conform with the mask irrespective of
the sign. The value V corresponds to the nominal peak value.
Pair(s) in each direction One coaxial pair One symmetrical pair
Test Load Impedance 75 Ω Resistive 120 Ω Resistive
Nominal peak voltage of a mark (pulse) 2.37 V 3 V
Peak voltage of a space (no pulse) 0 ± 0.237 V 0 ± 0.3 V
Nominal Pulse Width 244 ns
Ratio of the amplitudes of positive and negative
pulses at the center of the pulse interval
0.95 to 1.05
Ratio of the widths of positive and negative
pulses at the nominal half amplitude
0.95 to 1.05
Maximum peak to peak jitter at an output port Refer to ITU-T G.823 specification
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1.3 2048 kHz NRZ Mode
In this mode, XRT85L61 receives 2048 kbps synchronization signal as shown in Figure 7.
FIGURE 7. E1 CLOCK SIGNAL WAVE SHAPE - G.703
TABLE 10: G.703 2048 KHZ CLOCK INTERFACE
PULSE INTERFACE
Frequency 2048 kHz ± 50 ppm
Pulse Shape The signal must conform with the mask.
The value V corresponds to maximum peak value
The value V1 corresponds to minimum peak value
Pair(s) in each direction Coaxial pair Symmetrical pair
Test Load Impedance 75 Ω Resistive 120 Ω Resistive
Maximum peak value (Vop)1.5 1.9
Minimum peak value (Vop)0.75 1.0
Maximum jitter at an output port 0.05 UI peak to peak measured within the frequency range f1 = 20 Hz
to f4 = 100 kHz
NOTE: This value is valid for network timing distribution equipment.
Other values may be specified for timing output ports of digital
links carrying the network timing.
T
30
T
30
T
30
T
30
T
30
T
30
T
4
T
4
T
4
T
4
T
+ V
+ V
– V
– V
0
1
1
T1818900-92
Shaded area in which
signal should be
monotonic
T Average period of
synchronizing signal
FIGURE 21/G.703
Wave sha
p
e at an out
p
ut
p
ort
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1.4 1544 kHz T1 Mode
In this mode, the XRT85L61 receives a standard DS1 signal as shown in Figure 8.
FIGURE 8. G.703 DS1 WAVE FORM
T1528670-98
N orm alized am plitude
T im e , in U n it In te rv als
1.5
1.0
0.5
0
–
0.5
–
1.0 1.51.00.50– 0.5– 1.0
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2.0 AIS DETECTION TIMING
In E1 mode, AIS is set when the received incoming signal has 2 or less Zero’s in a sequence of 512 bits. AIS
will stay “High” for 250 µs and AIS is cleared upon receiving three or more Zero’s in the subsequent 512 bits
(250µs) time-frame. Figure 9 shows the AIS timing.
In T1 mode, AIS is detected if the received input signal has 4 or less Zero’s in a sequence of 4632 bits (3ms)
and AIS is cleared when 5 or more Zero’s are detected in the subsequent 4632 bits (3 ms) time-frame.
Figure 10 shows the AIS timing for T1 mode.
3.0 LOSS OF SIGNAL
The XRT85L61 Receive Loss of Signal (RLOS) monitoring circuits consist of both analog and digital schemes.
Both E1 and T1 meet G.775 RLOS declare and clear criteria. In E1 and 64kb/s modes, RLOS will be set if the
input pattern exceeds 32 bit consecutive zeros. In T1 mode, RLOS will go "High" if the number of consecutive
zeros exceeds 175.
The XRT85L61 RLOS detection circuit also reports RLOS if the input signal level drops below 220mVp (typical)
and RLOS is cleared when the input signal level returns to more than 380mVp (typical) when the input pattern
meets 12.5% density over a 32 bit period.
FIGURE 9. AIS DETECTION FOR E1 MODE
FIGURE 10. AIS DETECTION FOR T1 MODE
E1
DATA
AIS
250µs250µs
00 000
3 ms 3 ms
T1
DATA
AIS
00000 00000
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4.0 APPLICATIONS
FIGURE 11. CEPT APPLICATION FOR TWISTED PAIR INTERFACE
FIGURE 12. CEPT APPLICATION FOR COAXIAL INTERFACE
FIGURE 13. T1 APPLICATION FOR TWISTED PAIR INTERFACE
1:1
120 Ω
RTP
Receive
Input
RRing
RPOS
RNEG
RxClk
DVDD
AVDD
0.1
uF
10
uF
+
XRT59L81
BITS
Clock Extractor
+3.3V
Twisted Pair
1:1
75 Ω
RTP
Receive
Input
RRing
RPOS
RNEG
RxClk
DVDD
AVDD
0.1
uF
10
uF
+
XRT59L81
BITS
Clock Extractor
+3.3V
75 Ω Coaxial
1:1
100 Ω
RTP
Receive
Input
RRing
RPOS
RNEG
RxClk
DVDD
AVDD
0.1
uF
10
uF
+
XRT59L81
BITS
Clock Extractor
+3.3V
Twisted Pair
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TRANSFORMER RECOMENDATION
For all applications a 1:1 transformer ratio is required. 64kbps applications require a larger Inductance
transformer. Although E1 and T1 can use lower inductance transformers, Exar reccomends the use of the
PULSE ENGINEERING PE-65535 1:2CT transformer in a 1:1 mode by using pins 1 & 3 for the Line input and
Pins 6 & 5 as the secondary input to the XRT85L61. See Figure 15 below. Smaller transformers will be
evaluated in the future and recommendations will be published at that time.
FIGURE 14. 64KBPS APPLICATION FOR TWISTED PAIR
FIGURE 15. CONNECTING THE PULSE ENGINEERING PE-65535 1:2CT TRANSFORMER TO THE XRT85L61
1:1
110 Ω
RTP
Receive
Input
RRing
RPOS
RNEG
RxClk
DVDD
AVDD
0.1
uF
10
uF
+
XRT59L81
BITS
Clock Extractor
+3.3V
Twisted Pair
1
5
43
6
to
XRT59L81
to Line
Input
PE-65535 leave open
XRT85L61 xr
BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR REV. 1.0.2
17
PACKAGE OUTLINE DRAWING
ORDERING INFORMATION
PART NUMBER PACKAGE OPERATING TEMPERATURE RANGE
XRT85L61IG 28 Lead TSSOP -40°C to +85°C
e
D
BA1
28 15
14
1
A
L
C
α
A2
E1E
Seating
Plane
SYMBOL MIN MAX MIN MAX
A 0.033 0.047 0.85 1.20
A1 0.002 0.006 0.05 0.15
A2 0.031 0.041 0.80 1.05
B 0.007 0.012 0.19 0.30
C 0.004 0.008 0.09 0.20
D 0.378 0.386 9.60 9.80
E 0.248 0.260 6.30 6.60
E1 0.169 0.177 4.30 4.50
e 0.0256 BSC 0.65 BSC
L 0.018 0.030 0.45 0.75
α0° 8° 0° 8°
MILLIMETERSINCHES
Note: The control dimension is in the millimeter column
xr XRT85L61
REV. 1.0.2 BITS (BUILDING INTEGRATED TIMING SUPPLY) CLOCK EXTRACTOR
18
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2004 EXAR Corporation
Datasheet October 2004.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
REVISION HISTORY
REVISION # DATE CHANGES
1.0.0 January 2004 Final Release
1.0.1 February 2004 Added description for MCLK1 and MCLK2
1.0.2 October 2004 Modified applications drawings. Added RLOS description. Added AC Electrical
characteristics. Added description for T1 AIS detection.
