19-4740; Rav 1; 10/93 MA MAIM 1Msps, .P-Compatible, 8-Bit ADC with 11A Power-Down General Description The MAX153 high-speed, microprocessor (uP)-com- patible, 8-bit analog-to-digital converter (ADC) uses a half-flash technique to achieve a 660ns conversion time, and digitizes at a rate of 1M samples per second (Msps). {t operates with single +5V or dual +5V supplies and accepts either unipolar or bipolar inputs. A POWER- DOWN pin reduces current consumption to a typical value of 1A (with 5V supply). The part returns from power-down to normal operating mode in less than 200ns, providing large reductions in supply current in applications with burst-mode input signals. The MAX153 is DC and dynamically tested. Its uP inter- face appears as a memory location or input/output port that requires no external interface logic. The data out- puts use latched, three-state buffered circuitry for direct connection to a wP data bus or system input port. The ADC's input/reference arrangement enables ratiometric operation. Applications Cellular Telephones Portable Radios Battery-Powered Systems Burst-Mode Data Acquisition Digital-Signal Processing Telecommunications High-Speed Servo Loops Functional Diagram Features @ 660ns Conversion Time @ Power-Up/Power-Down in 200ns @ Internal Track/Hold @ 1Msps Throughput @ Low Power: 40mW (Operating Mode) 5uw = (Powerdown Mode) @ 1MHz Full-Power Bandwidth @ 20-Pin Narrow DIP, SO and SSOP Packages @ No External Clock Required @ Unipolar/Bipolar Inputs @ Single +5V or Dual +5V Supplies Ratiometric Reference Inputs Ordering information PART TEMP. RANGE PIN-PACKAGE MAX153CPP 0C to +70C 20 Plastic DIP MAX153CWP OC to +70C 20 Wide SO MAX153CAP OC to +70C 20 SSOP*** MAX153C/D 0C to +70C Dice* MAX153EPP -40C to +85C 20 Plastic DIP MAX153EWP -40C to +85C 20 Wide SO MAX153EAP -40C to +85C 20 SSOP*** MAX153MJP -55C to +125C 20 CERDIP** * Contact factory for dice specifications. ** Contact factory for availability and processing to MIL-STD-883. ** Contact factory for availability of SSOP packages. Pin Configuration Von 20 veers VREF- VIN THREE- STATE DRIVERS 4-BIT FLASH ADC (4LSB) MAXLAA MAX153 TIMING AND CONTROL CIRCUITRY 10 7 6 143 '8 9 19 GND MODE WRRDY CS RD INT Vss TOP VIEW . Vin [4 | 20) Vop bo (LSB) [2 | 9] ss or | haaxies |e] PRON 02 [4 | 17] D7 (MsB) 03 [5 | 16 D6 WRIRDY [6 | [15] 05 MODE [7 | 4] D4 RD [8 | 13] CS iNT [9 | 2] VREF+ GND [10] 11] VREF- DIP/SO/SSOP MAAXIAA Maxim Integrated Products 1 Call toll free 1-800-998-8800 for free samples or literature. EStLXVWMAX153 1Msps, .P-Compatible, 8-Bit ADC with 11A Powerdown ABSOLUTE MAXIMUM RATINGS Vopto GND ..0 6. ee -0.3V to +7V Continuous Power Dissipation (Ta = +70C) VsstoGND 2000... ee +0.3V to -7V Plastic DIP (derate 11.41mW/C above +70C) ..... 889mWw Digital Input Voltage toGND ............ +0.3V, VpD + 0.3V Wide SO (derate 10.00mW/C above +70C) ....... 800mW Digital Output Voltage toGND ........... -0.3V, VoD + 0.3V SSOP (derate 8.00mW/C above +70C) .......... 600mW VREF+ toGND.............. 0000 Vss -0.3V to Vop + 0.3V CERDIP (derate 11.11mW/C above +70C)........ BB9mMW VREF-toGND ...............005. Vss -0.3V to Vob + 0.3V Operating Termperature Ranges: VINtOGND .... 6... cee eee Vss -0.3V to Vpp + 0.3V MAX153C eee 0C to +70C MAX153E ww ee -40C to +85C MAX153MJUP 200. ee -55C to +125C Storage Temperature Range .............. -65C to +150C Lead Temperature (soldering, 10sec)............-. +300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VoD = +5V +5%, GND = OV; Unipolar Input Range: Vss = GND, VREF+ = 5V, VREF- = GND; Bipolar Input Range: Vss = -BV +5%, VREF+ = 2.5V, VREF- = -2.5V; 100% production tested, specifications are given for RD Mode (Pin 7 = GND), Ta = TMIN to TMax, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS ACCURACY Resolution N 8 Bits Total Unadjusted Error TUE Unipolar range +1 LSB Differential Nonlinearity DNL No missing codes guaranteed +1 LSB Zero-Code Error Bipolar input range +1 LSB Full-Scale Error Bipolar input range +1 LSB DYNAMIC PERFORMANCE (Note 1) MAX153C/E, Signal-to-Noise Plus Distortion SN+D) fSAMPLE = 1MHz, fin = 195.8kHz 45 dB Ratio MAX153M, fsamPte = 740kHz, fin = 195.7KHZ MS SCTE . . =1 _fin = 195.8kH Total Harmonic Distortion THD SAMPLE 2 fIN = 198.8KFiz -50 dB MAX153M, fsamece = 740kHZz, fin = 195.7kHz MAX153C/E, . . . f = 1MHz, fin = 195.8kHz Peak Harmonic or Spurious Noise SAMPLE zIN -50 dB MAX153M, fSAMPLE = 740kHz, fin = 195.7kKHz Conversion Time (WR-RD Mode) towr Ta = +25C, tap < tint, CL = 20pF 660 ns (Note 2) Ta = +25C 700 Conversion Time (RD Mode) tcRD MAX153C/E 875 ns Ta = Tain to TMAX MAX153M 975 Full-Power Input Bandwidth VIN = 5Vp-p 1 MHz Input Slew Rate 3.14 15 V/s 2 MAXIA1Msps, .P-Compatible, 8-Bit ADC with 1:A Power-Down ELECTRICAL CHARACTERISTICS (continued) (Vpp = +5V 45%, GND = OV; Unipolar Input Range: Vss = GND, VREF+ = 5V, VREF- = GND; Bipolar Input Range: Vss = -5V 5%, VREF+ = 2.5V, VREF- = -2.5V; 100% production tested, specifications are given for RD Mode (Pin 7 = GND), Ta = TIN to TMAX, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS ANALOG INPUT Input Voltage Range VIN VREF- VREF+ V Input Leakage Current lIN -5V < Vin <= 5V +3 pA Input Capacitance Cin 22 pF REFERENCE INPUT Reference Resistance RREF 1 2 4 kQ VREF+ Input Voltage Range VREF- Vop Vv VREF- Input Voltage Range Vss VREF+ Vv LOGIC INPUTS Input High Voltage VINH CS, WR, RD, PWRON 2.4 V MODE 3.5 Input Low Voltage VINL CS. WR, RD, PWRON 08 Vv MODE 1.5 CS, RO, PWRON 1 Input High Current NINH WR 3 HA MODE 50 200 Input Low Current INL CS, WR, RD, PWRON +1 pA Input Capacitance (Note 3) CIN CS, RD, WR, PWRDN, MODE 6 8 pF LOGIC OUTPUTS Output Low Voltage VoL ISINK = 1.6mA, INT, DO-D7 0.4 V RDY, Isink = 2.6mA 0.4 Output High Voltage VOH ISOURCE = S6QHA, INT, DO-D7 4 Vv Floating State Current ILKG DO-D7, RDY +3 pA Floating Capacitance (Note 3) Cout (07-DO, RDY 5 8 pF POWER REQUIREMENTS VDD VoD +5% for specified accuracy 5 Vv Vsg (Unipolar Operation} Vss GND Vv Vss (Bipolar Operation) Vss +5% for specified accuracy 5 Vv CS=RD =v, MAX153C 8 15 Vpp Supply Current IDD PWRDN = 5V MAXIS3E/M 3 30 mA Power-Down Vpp Current CS = RD = 5V, PWRDN = OV (Note 4) 1 100 LA Vss Supply Current Iss CS = RD = OV, PWRDN = 5V 25 100 pA Power-Down Vss Current CS = RD = 5V, PWRDN = OV 12 100 LA Power-Supply Rejection PSR SO ee ee nipolar node +H/16 +1/4 | LSB Note 1: Bipolar input range, VIN = +2.5Vp-p, WR-RD mode Note 2: See Figure 1 for load circuit. Parameter defined as the time required for the output to cross +0.8V or +2.4V. Note 3: Guaranteed by design. Note 4: Tested with CS, RD, PWRDN at CMOS logic levels. Power-down current increases to several hundred pA at TTL levels. MAXIM 3 ESELXVIN1Msps, uP-Compatible, 8-Bit ADC with 11A Powerdown TIMING CHARACTERISTICS (Note 5) (VoD = +5V 5%, Vss = OV fer Unipolar Input Range, Vss = -5V 5% for Bipolar Input Range, 100% production tested, Ta = +25C, unless otherwise noted.) MAX153 PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CS to RD/WR Setup Time tcss 0 ns CS to RD/WR Hold Time 'csH 0 ns CS to RDY Del C= S0PF 70 O elay (Note 6) tRDY Ta = TMIN to TMAX, MAX153C/E 85 ns CL = SOpF MAX153M 100 CL = 20pF tcrp+25 Ta = TmINn to Tmax, MAX153C/E tcRD+30 Data-Access Time CL = 20pF (RD Mode) (Note 2) tacco MAX153M tcrp+35 | ns CL = 100pF tcrD+50 Ta = TMIN to TMAX, MAX153C/E tcRD+65 CL = 100pF MAX153M tcrD+75 , -_ C_ = 50pF 50 80 RD to INT Delay t 4 (RD Mode) INTH | Ta = TmIN to MAX, MAX 153C/E 85 s CL = SOpF MAX153M 90 Data-Hold Ti 60 ata-Hold Time 'DH MAX153C/E 70 ns (Note 7) Ta = TMIN to TMAX MAX153M 80 Delay Time Between 160 onversions t ns (Acquisition Time) Ta = TMIN to TMAX MAX153C/E 185 MAX 153M 260 0.250 10 Write Pulse Width twR MAX153C/E 0.280 10 Hs Ta = TMIN to TMAX MAX153M 0.400 10 Delay Time Bet 200 ay Time Between tRO MAX153C/E 350 ns WR and RD Pulses Ta = TIN to TMAX MAX153M 450 RD Pulse Width Figure 6 160 (WR-RD Mode) tREAD1 _ MAX 15. E 2 ns Determined by tacc1 i MN to TMAX, Sti 05 g MAX153M 240 MA AXLMM|1Msps, .P-Compatible, 8-Bit ADC with 11A Power-Down TIMING CHARACTERISTICS (Note 4) (continued) (Vpp = +5V 5%, Vss = OV for Unipolar Input Range, Vss = -5V +5% for Bipolar Input Range, 100% production tested, Ta = +25C, unless otherwise noted.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX | UNITS CL = 20pF, Figure 6 160 MAD Moc yme vA = Twin to T AX MAX153C/E 205 R-RD Mode L = 20pF, Figure (Note 2} tacc MAX153M 240 ns IRD < tINL CL = 100pF, Figure 6 185 Ta = TmIN to TMAX, MAX153C/E 235 CL = 100pF, Figure6 | yaayi53m 75 150 RD to INT Delay tri MAX 153C/E 185 ns Ta = TMIN to TMAX MAX153M 220 CL = 50pF 380 500 WR to INT Delay tINTL Ta = Twin to Tmax, MAX 153C/E 610 ns CL = 50pF MAX153M 700 RD Pulse Width Figure 5 65 (WR-RD Mode} Determined by tacce | READ2 | Ta= Tinto Twax. | MAXISSC/E 75 ns tRD > UNTL Figure 5 MAX153M 85 CL = 20pF, Figure 5 65 Fate aoe a A = Twine TMAX, MAX153C/E 75 R-R ode L = 20pF, Figure tAD > NTL CL = 100pF, Figure 5 90 Ta = TmIN to TMAX, MAX153C/E 110 C= 100pF, Figure 5 | yyax453m 130 WA to INT Del CL = S0pF 80 0 elay (Pipe-Lined Mode) tlHWR | Ta=TmintoTMax, | _MAX153C/E 100 ns CL = SOpF MAX153M 120 CL = 20pF 30 Data-A 7 TA = Tun to TMAX, MAX 153C/E a5 ata-Access Time L = 20p 1 After INT (Note 2) ip MAX153M 40_| ns CL = 100pF 45 Ta = TMIN to TMAX, MAX153C/E 60 CL = 100pF MAX153M 70 Note 5: Input control signals are specified with tr = tf = Sns, 10% to 90% of +5V and timed from a 1.6V voltage level. Note 6: RL = 5. 1kQ pull-up resistor. Note 7: See Figure 2 for load circuit. MAXIM Parameter defined as the time required for data lines to change 0.5V. EStEXVNMAX153 1Msps, uP-Compatible, 8-Bit ADC with 11A Powerdown +5V 3k DN t DN Tt + Deno = 1 DGND A. HIGH 2 T0 Vou B. HIGH Z TO Voi Figure 1. Load Circuits for Data-Access Time Test +8V = ON * + ON = I 10pF L 10pF = DGND I = ODGND A. Vou TO HIGH Z B. VoL TO HIGH Z Figure 2. Load Circuits for Data-Hold Time Test Typical Operating Characteristics CONVERSION TIME vs. AMBIENT TEMPERATURE VoD = +5.25V Yoo = + Icap (NORMALIZED TO VALUE AT +25C) -60 -20: 0 20 60 100140 TEMPERATURE (C) SIGNAL-TO-NOISE RATIO RATIO (dB) -80 -100 0 100 200 300 400 500 FREQUENCY {kHz} INPUT FREQUENCY = 195.8ksps (2.5V) SAMPLE FREQUENCY = 1MHz SNR = 49.1dB EFFECTIVE BITS vs. INPUT FREQUENCY, WR-RD MODE HOT +125C COLD -85C ROOM EFFECTIVE BITS fSAMPLE = 1MHz VIN = 2.5V 10 100 1000 FREQUENCY (kHz) INTERMODULATION DISTORTION Ta= 425C RATIO (dB) 0 50 100 150 200 250 FREQUENCY (kHz) INPUT FREQUENCY = 94.97kHz 84.72kKHz (+2.5V) SAMPLE FREQUENCY = 500kHz IMD: 2ND-GRDER TERMS = -66.20B 3RD-ORDER TERMS = -60.0dB MAXIAAPin Description PIN | NAME FUNCTION 1 VIN Analog Input. Range is VREF- < Vin s VREF+. 2 DO Three-State Data Output (LSB) 3-5 D1-D3 | Three-State Data Outputs 6 | WR/RDY | WRITE Control Input/READY Status Output* MODE Selection Input is internally pulled low with a 50uA current source. , MODE MODE = 0 activates read mode. MODE = (1 activates write-read mode 8 RD READ Input. must be low to access data. In INTERRUPT Output goes low to indicate 9 INT a end of conversion. 10 GND | Ground Lower limit of reference span. Sets the zero- 11 VREF- | code voltage. Range is Vss < VREF- < VREF+. Upper limit to reference span. Sets the 12. | VREF+ | full-scale input voltage. Range is VREF- < VREF+ < Vpp. cS CHIP SELECT Input must be low for the 1 device to recognize WR or RD inputs. 14-16 | D4-D6 | Three-State Data Outputs 17 D7 Three-State Data Output (MSB) POWERDOWN Input. reduces supply cur- 18 | PWRDN | rent when low. CS must be high during power-down, Negative Supply. Unipolar: Vss = OV, Bipolar: Vss = -5V 20 Vpp | Positive Supply, +5V * See Digital Interface section. 19 Vss Detailed Description Converter Operation The MAX153 uses a half-flash conversion technique (see Functional Diagram) in which two 4-bit flash ADC sec- tions achieve an 8-bit result. Using 15 comparators, the flash ADC compares the unknown input voltage to the reference ladder and provides the upper 4 data bits. An internal digital-to-analog converter (DAC) uses the 4 most significant bits (MSBs) to generate the analog result from the first flash conversion and a residue voltage that is the difference between the unknowntinput and the DAC voltage. The residue is then compared again with the flash comparators to obtain the lower 4 data bits (LSBs). MAXLA 1Msps, Power-Down Mode In burst-mode or low sample-rate applications, the MAX153 can be shut down between conversions, reduc- ing supply current to microamp levels. A TTLYCMOS logic low on the PWRDN pin shuts the device down, reducing supply current to typically 1wA when powered from a single 5V supply. CS must be high when power- down is used. A logic high on PWRDN wakes up the MAX153. Anew conversion can be started (WR asserted low) within 360ns of the PWRDN pin being driven high (200ns to power up plus 160ns for track/hold acquisition). If power-down made is not required, connect PWRDN to VDD. Once the MAX 153 is in power-down mode, lowest supply current is drawn with MODE low (RD mode) due to an internal SOQuA pull-down resistor at this pin. CS must remain high during shutdown because the MAX153 may attempt to start a conversion that it cannot complete. In addition, for minimum current consumption, other cigital inputs should remain stable in power-down. RDY, an open-drain output (in RD mode), will then fall and remain low throughout _power-down, sinking additional supply current unless CS remains high. Refer to the Reference section for information on reducing reference current during power-down. Digital interface The MAX153 has two basic interface modes set by the status of the MODE input pin. When MODE is low, the converter is in the RD mode; when MODE is high, the converter is set up for the WR-RD mode. Read Mode (MODE = 0) In RD mode, conversion control and data access are controlled by the RD input (Figure 4). The comparator inputs track the analog input voltage for the duration of tp. Aminimum of 160ns is required for the input to be acquired. A conversion is initiated by driving RD low. With uPs that can be forced into a wait state, hold RD low until output data appears. The uP starts the con- version, waits, and then reads data with a single read instruction. WR/RDY is configured as a status output (RDY) in RD mode, where it can drive the ready or wait input of a uP. RDY is an open-collector output (with no internal pull-up) that goes low after the falling edge of CS and goes high at the end of the conversion. If not used, the WR/RDY pin can be left unconnected. The INT output goes low at the end of the conversion and returns high on the rising edge of CS or RD. uP-Compatible, 8-Bit ADC with 11A Power-Down ESEXVINMAX153 1Msps, .P-Compatible, 8-Bit ADC with 1.A Powerdown Write-Read Mode (MODE = 1) Figures 5 and 6 show the operating sequence for the write-read (WR-RD) mode. The comparator inputs track the analog input voltage for the duration of tp. Aminimum of 160ns is required for the input voltage to be acquired. The conversion is initiated by a falling edge of WR. When WR returns high, the 4 MSBs flash result is latched into the output buffers and the 4 LSBs conversion begins. INT goes low about 380ns later, indicating conversion end, and the lower 4 data bits are latched into the output buffers. The data is then accessible 65ns to 130ns after RD goes low (see Timing Characteristics). lf an externally controlled conversion time is required, drive RD low 250ns after WR goes high. This latches the lower 4 data bits and outputs the conversion result on DO-D7. Aminimum 160ns delay is required from INT going low to the start of another conversion (WR going low). Options for reading data from the converter include the following: Using Internal Delay The pP waits for the INT output to go low before reading the data (Figure 5)._INT typically goes low 380ns after the rising edge of WR, indicating the conversion is com- plete, and the result is available in the output latch. With CS low, data outputs DO-D7 can be accessed by pulling RD low. INT is then reset by the rising edge of CS or RD. Fastest Conversion: Reading Before Delay An external method of controlling the conversion time is shown in Figure 6. The internally generated delay tiNTL WITH EXTERNAL PULL-UP tRoY NTH INT + tcrpd VALID DATA }e=====20e as | toh +| UNTH Sh INT N tINTL > 00-D7seeeeee eens enn nenseneernensons VALID DATA Je=== tacc2 >| + ton Figure 4, RD Mode Timing (MODE = 0) Figure 5. WR-RD Mode Timing (tap > tinn.) (MODE = 1 } ak L __ IWR V WhO) NA } css fe be trp ot __ [* tReap1 ee RD 5 | RI INT tINTH DO-D7 DATA VALID tacct a t le towe at oh rr Figure 6. WR-RD Mode Timing (tro < tintt), Fastest Operating Mode (MODE = 1) 8 tip DO-D7 OLD DATA NEW DATA Figure 7. Pipe-Lined Mode Timing (WR = RD) (MODE = 1) MAXLWVI1Msps, uP-Compatible, 8-Bit ADC with 114A Power-Down varies slightly with temperature and supply voltage, and can be overridden with RD to achieve the fastest conver- sion time. INT is ignored, and RD is brought low typically 250ns after the rising edge of WR. This completes the conversion and enables the output buffers (D0-D7) that contain the conversion result. INT also goes low after the falling edge of RD and is reset on the rising edge of RD or CS. The total conversion time is therefore: tcwrR = twR (250ns) + tCSH (Ons) to tRD (250ns) + tacc1 (160ns) = 660ns. Pipe-Lined Operation Besides the two standard WR-RD mode options, pipe- linea" operation can be achieved by connecting WR and RD together (Figure 7). With CS low, driving WR and RD low initiates a conversion and reads the result of the previous conversion concurrently. Analog Considerations Reference Figures 8a-8c show some reference connections. VREF+ and VREF- inputs set the full-scale and zero-input vol- tages of the ADC. The voltage at VREF- defines the input that produces an output code of all zeros, and the voltage at VREF+ defines the input that produces an output code of all ones. The internal resistances from VREF+ and VREF- may be as low as 1k2. Since current is still drawn by the refer- ence inputs during power-down, reference supply cur- rent can be reduced during shutdown by using the circuit shown in Figure 8d. A logic-level N-channel MOSFET, connected between VREF- and ground, disconnects the reference load when the ADC enters power-down 1 VINe VIN Vi p 4] GND AAAXLAA 1 VIN 10 MAAXLAA | 88 MAxI53 7 20 ViN+ mx5e4 | OTF 1] VReF- J 425V , |maam 12] vper. uF +5 e e _ 2 Vop MAX153 45Y @ e e Vop I | 121 REFS [ | Lay =) vars O4pF 4.7uF nove | il _ VREF- all Viv. 9 Tt UY per. 7 7 ~ oO t otmF] | Otue - "CURRENT PATH MUST STILL EXIST FROM Vin- TO GND. Figure 8a. Power Supply as Reference Figure 8c. Input Not Referenced to GND 20 + V Vine \ VIN + t aa BD r 0.4pF 10 = MAAXLAA Vi. -] 6ND AA AXLAA MAXIM > 12) REF = 2 MAX153 MX584 + 0.1yF * MAX153 +5V + OF voo : 11 VREF- 18 i "[-wr PWRDN Figure 8b. External Reference, +2.5V Full Scale MAXIM Figure 8d. An N-channel MOSFET switches off the reference load during power-down. ESLXVWNMAX153 1Msps, .P-Compatible, 8-Bit ADC with 1.:A Powerdown AN al vy RON VIN ipo = + T Figure 9. Equivalent Input Circuit R i] Vin 2k VIN AAA ]42eF _[10pF = AAAXIM MAX153 Figure 10. RC Network Equivalent Inout Model (PWRDN = low). The FET should have no more than 0.5 of on resistance to maintain accuracy. Bypassing A 4.7uF electrolytic in parallel with a 0.1pF ceramic capacitor should be used to bypass VDD to GND. These capacitors should have minimal lead length. The reference inputs should be bypassed with 0.1pF capacitors, as shown in Figures 8a-8c. Input Current Figure 9 shows the equivalent circuit of the converter input. When the conversion starts and WR is low, VIN is connected to 16 0.6pF capacitors. During this acquisi- tion phase, the input capacitors charge to the input voltage through the resistance of the internal analog switches (about 2kQ ), In addition, about 12pF of stray capacitance must be charged. The input can be modeled as an equivalent RC network (Figure 10). As source impedance increases, the capacitors take longer to charge. The typical 22pF input capacitance allows source resis- tance as high as 2.2kQ without setup problems. For 10 larger resistances, the acquisition time (tp) must be increased. Conversion Rate The maximum sampling rate (fmax) for the MAX153 is achieved in the WR-RD mode (tRD < tINTL) and is calcu- lated as follows: 4 f = max twR + tRD + tRI + tp 4 imax = 250ns + 250ns + 150ns + 160ns fmax = 1.23MHz where twr = Write pulse width tRD = Delay between WR and RD pulses tri = RD to INT delay tp = Delay time between conversions. Signal-to-Noise Ratio and Effective Number of Bits Signal-to-noise ratio (SNR) is the ratio of the RMS amplitude of the fundamental input frequency to the RMS amplitude of all other analog-to-digital output values. The output band is limited to one-half the A/D sample (con- version) rate. This ratio usually includes distortion as well as noise components. For this reason, the ratio is some- times referred to as "signal-to-noise + distortion." The theoretical minimum A/D noise is caused by quan- tization error and results directly from the ADC's resolu- tion: SNR = (6.02N + 1.76)dB, where N is the number of bits of resolution. Therefore, a perfect 8-bit ADC can do no better than 50dB. The FFT plot (Typical Operating Characteristics) shows the result of sampling a pure 200kHz sinusoid ata 1MHzrate. This FFT plot of the output shows the output level in various spectral bands. The effective resolution, or "effective number of bits," the ADC provides can be measured by transposing the equation that converts resolution to SNR: N = (SNR - 1.76)/6.02. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal {in the frequency band above DC and below one-half the sample rate) to the fundamental itself. This is expressed as: N(v2 7 4V374V4 e+ VN) | V4 where V1 is the fundamental RMS amplitude, and V2 to VN are the amplitudes of the 2nd through Nth harmonics. THD = 20 log MAXIM1Msps, u.P-Compatible, 8-Bit ADC with 1.A Power-Down Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is the ratio of the fundamental RMS amplitude to the amplitude of the next largest spectral component (in the frequency band above DC and below one-half the sample rate). Usually this peak occurs at some harmonic of the input frequency, but if the ADC is exceptionally linear, it may occur only at a random peak in the ADCs noise floor. Intermoduiation Distortion An FFT plot of intermodulation distortion (IMD) is generated by sampling an analog input applied to the ADC. This input consists of very low distortion sine waves at two frequencies. A 2048 point plot for IMD of the MAX153 is shown in the Typical Operating Charac- teristics. MAXIM Chip Topography DO Vin Vpp Vss | ____ | D1 PWRDN 32 : ao. oy zs D3 D } i j 0.104" (2.64mm) D5 WR/RDY 2 ; pa MODE aay cs j RD INT GND VREF- VREF+ 0.098" , (249mm) TRANSISTOR COUNT: 1856 SUBSTRATE CONNECTED 10 Vpp 11 ESELXVNNMAX153 1Msps, pP-Compatible, 8-Bit ADC with 1A Power-Down Package Information E DIM INCHES MILLIMETERS MIN | MAX | MIN | MAX i D _ [eat - | tor| A - 0.200 - 5.08 lL _ y A1 | 0.015 - 0.38 = 4 A | yy A3 A2 | 0.125 | 0.175 | 318 | 4.45 a A2 i A3 | 0.055 | 0.080 | 140 | 2.03 B | 0.016 | 0.022 | 0.41 | 0.56 B1 | 0.045 | 0.065 1.14 1.65 C | 6.008 | 0.012 0.20 0.30 L oat \ 0 15 y Di | 0.005 | 0.080 | 0.13 | 2.03 Y i ee E | 0300 | 0.325 | 7.62 | 8.26 co E1 | 0.240 | 0310 | 640 | 7.87 e BI eA > e | 0.100 - 2.54 - B eA | 0.300 ~ 7.62 - a eB eB | - 0.400 - 10.16 L |o115 | 0150 | 292 | 3.1 | ee gS AT ee eo P| . DIP PKG.| Dim |PINS INCHES MILLIMETERS astic " MIN | MAX | MIN | MAX PLASTIC P |b | 8 {0.348 0.390 | 8.84 | 9.91 DUAL-IN-LINE P D | 14 | 0.735 | 0.765 | 18.67 | 19.43 P | D | 16 |0.745 | 0.765 | 18.92 | 19.48 PACKAGE P | D | 18 |0.885 | 0.915 {22.48 | 23.24 peer AS ce (0.300 in.) P | D | 20 | 1.015 | 1.045 {25.78 | 26.54 N | D | 24 | 1.14 | 1265 [28.96 | 32.13 21-0043A DIM INCHES MILLIMETERS MIN | MAX | MIN | MAX A | 0.093 | o104 | 235 | 2.65 t Ai | 0.004 | 0.012 [ 0.10 | 0.30 o-8 | B | 0.014 | 0.019 | 0.35 | 0.49 by A _ \ c | 0.009 | 0.013 | 023 | 0.32 f 0.101mm E | 0.291 0.299 7.40 7.60 ele sf A fice + 4 e 0.050 1.27 L H | 0.394 | 0.419 | 10.00 | 10.65 L | 0.016 | o050 | 040 | 1.27 INCHES |MILLIMETERS . DIM |PINS Tain | MAX | MIN | MAX EH Wide SO D | 16 | 0.398 | 0.413 | 10.10 | 10.50 SMALL-OUTLINE D | 48 | 0.447 | 0.463 [11.35 | 11.75 PACKAGE D 120 | 0.496 | 0.512 | 12.60 | 13.00 . D | 24 | 0.598 | 0.614 | 15.20 | 15.60 (a6 6 o__F (0.300 in.) D | 28 | 0.697 | 0.713 | 17.70 | 18.10 21-0042A Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 1995 Maxim Integrated Products Printed USA MAXIMA js a registered trademark of Maxim Integrated Products.