74LVT16374ADGG,118 - NEXPERIA

74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Rev. 11 — 5 February 2019 Product data sheet

1. General description

The 74LVT16374A; 74LVTH16374A are high performance BiCMOS products designed for VCC

operation at 3.3 V.

This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state outputs. The

device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the

clock (nCP), the nQn outputs of the flip-flop take on the logic levels set up at the nDn inputs.

2. Features and benefits

•16-bit edge-triggered flip-flop

•3-state buffers

•Output capability: +64 mA and -32 mA

•TTL input and output switching levels

•Input and output interface capability to systems at 5 V supply

•Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs.

(74LVTH16374A only)

•Live insertion and extraction permitted

•Power-up reset

•Power-up 3-state

•No bus current loading when output is tied to 5 V bus

•Latch-up protection:

•JESD78B Class II exceeds 500 mA

•ESD protection:

•HBM JESD22-A114F exceeds 2000 V

•MM JESD22-A115-A exceeds 200 V

3. Ordering information

Table 1. Ordering information

PackageType number

Temperature range Name Description Version

74LVT16374ADL -40 °C to +85 °C SSOP48 plastic shrink small outline package; 48 leads;

body width 7.5 mm

SOT370-1

74LVT16374ADGG

74LVTH16374ADGG

-40 °C to +85 °C TSSOP48 plastic thin shrink small outline package;

48 leads; body width 6.1 mm

SOT362-1

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

4. Functional diagram

001aac369

1CP

1OE

1D0

1D1

1D2

1D3

1D4

1D5

1D6

2 3 5 6 8 9 11 12

1D7

1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7

2CP

2OE

2D0

2D1

2D2

2D3

2D4

2D5

2D6

13 14 16 17 19 20 22 23

2D7

2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7

Fig. 1. Logic symbol

001aaa254

37 12

1D7

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1Q7

1Q6

1Q5

1Q4

1Q3

1Q2

1Q0

1Q1

2D5

2D0

2D1

2D2

2D3

2D4

2Q5

2Q4

2Q3

2Q2

2Q1

2Q0

25 EN2

1OE 1EN1

1CP

2OE

2CP

48 C3

3D 1

2D7

2D6

2Q7

2Q6

Fig. 2. IEC logic symbol

001aac371

CP Q

nD0

nCP

nOE

nQ0

CP Q

nD1

nQ1

CP Q

nD2

nQ2

CP Q

nD3

nQ3

CP Q

nD4

nQ4

CP Q

nD5

nQ5

CP Q

nD6

nQ6

CP Q

nD7

nQ7

Fig. 3. Logic diagram

Product data sheet Rev. 11 — 5 February 2019 2 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

5. Pinning information

5.1. Pinning

74LVT16374A

74LVTH16374A

1OE 1CP

1Q0 1D0

1Q1 1D1

GND GND

1Q2 1D2

1Q3 1D3

VCC VCC

1Q4 1D4

1Q5 1D5

GND GND

1Q6 1D6

1Q7 1D7

2Q0 2D0

2Q1 2D1

GND GND

2Q2 2D2

2Q3 2D3

VCC VCC

2Q4 2D4

2Q5 2D5

GND GND

2Q6 2D6

2Q7 2D7

2OE 2CP

001aak263

Fig. 4. Pin configuration SOT370-1 (SSOP48) and SOT362-1 (TSSOP48)

5.2. Pin description

Table 2. Pin description

Symbol Pin Description

1OE, 2OE 1, 24 output enable input (active LOW)

1CP, 2CP 48, 25 clock input

1Q0, 1Q1, 1Q2, 1Q3, 1Q4, 1Q5, 1Q6, 1Q7 2, 3, 5, 6, 8, 9, 11, 12 data output

2Q0, 2Q1, 2Q2, 2Q3, 2Q4, 2Q5, 2Q6, 2Q7 13, 14, 16, 17, 19, 20, 22, 23 data output

GND 4, 10, 15, 21, 28, 34, 39, 45 ground (0 V)

VCC 7, 18, 31, 42 supply voltage

1D0, 1D1, 1D2, 1D3, 1D4, 1D5, 1D6, 1D7 47, 46, 44, 43, 41, 40, 38, 37 data input

2D0, 2D1, 2D2, 2D3, 2D4, 2D5, 2D6, 2D7 36, 35, 33, 32, 30, 29, 27, 26 data input

Product data sheet Rev. 11 — 5 February 2019 3 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

6. Functional description

Table 3. Function table

H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;

L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;

NC = no change; X = don’t care;

Z = high-impedance OFF-state; ↑ = LOW-to-HIGH clock transition.

Input OutputOperating mode

nOE nCP nDn

Internal register

nQ0 to nQ7

L ↑ l L LLoad and read register

L ↑ h H H

Hold L NC X NC NC

H NC X NC ZDisable outputs

H ↑ nDn nDn Z

7. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage -0.5 +4.6 V

VIinput voltage [1] -0.5 +7.0 V

VOoutput voltage output in OFF-state or HIGH-state [1] -0.5 +7.0 V

IIK input clamping current VI < 0 V -50 - mA

IOK output clamping current VO < 0 V -50 - mA

output in LOW-state - 128 mAIOoutput current

output in HIGH-state -64 - mA

Tstg storage temperature -65 +150 °C

Tjjunction temperature [2] - 150 °C

Ptot total power dissipation Tamb = -40 °C to +85 °C [3] - 500 mW

[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction

temperatures which are detrimental to reliability.

[3] Above 60 °C the value of Ptot derates linearly with 5.5 mW/K.

Product data sheet Rev. 11 — 5 February 2019 4 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

8. Recommended operating conditions

Table 5. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage 2.7 - 3.6 V

VIinput voltage 0 - 5.5 V

VIH HIGH-level input voltage 2.0 - - V

VIL LOW-level input voltage - - 0.8 V

IOH HIGH-level output current -32 - - mA

none - - 32 mAIOL LOW-level output current

current duty cycle ≤ 50 %; fi ≥ 1 kHz - - 64 mA

Tamb ambient temperature in free-air -40 - +85 °C

Δt/ΔV input transition rise and fall rate outputs enabled - - 10 ns/V

9. Static characteristics

Table 6. Static characteristics

At recommended operating conditions; voltages are referenced to GND (ground = 0 V).

Tamb = -40 °C to +85 °CSymbol Parameter Conditions

Min Typ [1] Max

Unit

VIK input clamping voltage VCC = 2.7 V; IIK = -18 mA -1.2 -0.85 - V

IOH = -100 μA; VCC = 2.7 V to 3.6 V VCC - 0.2 VCC - V

IOH = -8 mA; VCC = 2.7 V 2.4 2.5 - V

VOH HIGH-level output voltage

IOH = -32 mA; VCC = 3.0 V 2.0 2.3 - V

VCC = 2.7 V

IOL = 100 μA - 0.07 0.2 V

IOL = 24 mA - 0.3 0.5 V

VCC = 3.0 V

IOL = 16 mA - 0.25 0.4 V

IOL = 32 mA - 0.3 0.5 V

VOL LOW-level output voltage

IOL = 64 mA - 0.4 0.55 V

VOL(pu) power-up LOW-level output

voltage

VCC = 3.6 V; IO = 1 mA;

VI = VCC or GND

[2] - 0.1 0.55 V

control pins

VCC = 3.6 V; VI = VCC or GND - 0.1 ±1 μA

VCC = 0 V or 3.6 V; VI = 5.5 V - 0.4 10 μA

input data pins [3]

VCC = 0 V or 3.6 V; VI = 5.5 V - 0.4 10 μA

VCC = 3.6 V; VI = VCC - 0.1 1 μA

IIinput leakage current

VCC = 3.6 V; VI = 0 V -5 -0.4 - μA

IOFF power-off leakage current VCC = 0 V; VI or VO = 0 V to 4.5 V - 0.1 ±100 μA

IBHL bus hold LOW current VCC = 3 V; VI = 0.8 V 75 135 - μA

IBHH bus hold HIGH current VCC = 3 V; VI = 2.0 V - -135 -75 μA

IBHLO bus hold LOW overdrive

current

input data pins; VI = 0 V to 3.6 V;

VCC = 3.6 V

[4] 500 - - μA

Product data sheet Rev. 11 — 5 February 2019 5 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Tamb = -40 °C to +85 °CSymbol Parameter Conditions

Min Typ [1] Max

Unit

IBHHO bus hold HIGH overdrive

current

input data pins; VI = 0 V to 3.6 V;

VCC = 3.6 V

[4] - - -500 μA

ILO output leakage current output in HIGH-state when VO > VCC;

VO = 5.5 V; VCC = 3.0 V

- 50 125 μA

IO(pu/pd) power-up/power-down output

current

VCC ≤ 1.2 V; VO = 0.5 V to VCC;

VI = GND or VCC; nOE = don’t care

[5] - 1 ±100 μA

VCC = 3.6 V; VI = VIH or VIL

output HIGH: VO = 3.0 V - 0.5 5 μA

IOZ OFF-state output current

output LOW: VO = 0.5 V -5 0.5 - μA

VCC = 3.6 V; VI = GND or VCC; IO = 0 A

outputs HIGH - 0.07 0.12 mA

outputs LOW - 4.0 6.0 mA

ICC supply current

outputs disabled [6] - 0.07 0.12 mA

ΔICC additional supply current per input pin; VCC = 3.0 V to 3.6 V;

one input at VCC - 0.6 V,

other inputs at VCC or GND

[7] - 0.1 0.2 mA

CIinput capacitance input pins; VI = 0 V or 3.0 V - 3 - pF

COoutput capacitance output pins nQn; outputs disabled;

VO = 0 V or VCC

- 9 - pF

[1] Typical values are measured at VCC = 3.3 V and at Tamb = 25 °C.

[2] For valid test results, data must not be loaded into the flips-flops (or latches) after applying power.

[3] Unused pins at VCC or GND.

[4] This is the bus hold overdrive current required to force the input to the opposite logic state.

[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms.

From VCC = 1.2 V to VCC = 3.3 V ± 0.3 V a transition time of 100 μs is permitted. This parameter is valid for Tamb = 25 °C only.

[6] ICC is measured with outputs pulled to VCC or GND.

[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.

10. Dynamic characteristics

Table 7. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V); for test circuit see Fig. 8.

Tamb = -40 °C to +85 °CSymbol Parameter Conditions

Min Typ [1] Max

Unit

fmax maximum frequency nCP; VCC = 3.3 V ± 0.3 V; see Fig. 5 150 - - MHz

nCP to nQn; see Fig. 5

VCC = 3.3 V ± 0.3 V 1.5 2.9 5.0 ns

tPLH LOW to HIGH propagation

delay

VCC = 2.7 V - - 5.6 ns

nCP to nQn; see Fig. 5

VCC = 3.3 V ± 0.3 V 1.5 3.0 5.0 ns

tPHL HIGH to LOW propagation

delay

VCC = 2.7 V - - 5.6 ns

nOE to nQn; see Fig. 6

VCC = 3.3 V ± 0.3 V 1.5 3.2 4.8 ns

tPZH OFF-state to HIGH

propagation delay

VCC = 2.7 V - - 6.0 ns

nOE to nQn; see Fig. 6

VCC = 3.3 V ± 0.3 V 1.5 3.0 4.6 ns

tPZL OFF-state to LOW

propagation delay

VCC = 2.7 V - - 5.2 ns

Product data sheet Rev. 11 — 5 February 2019 6 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Tamb = -40 °C to +85 °CSymbol Parameter Conditions

Min Typ [1] Max

Unit

nOE to nQn; see Fig. 6

VCC = 3.3 V ± 0.3 V 1.5 3.9 5.4 ns

tPHZ HIGH to OFF-state

propagation delay

VCC = 2.7 V - - 6.0 ns

nOE to nQn; see Fig. 6

VCC = 3.3 V ± 0.3 V 1.5 3.4 4.6 ns

tPLZ LOW to OFF-state

propagation delay

VCC = 2.7 V - - 5.0 ns

nDn to nCP; HIGH or LOW; see Fig. 7

VCC = 3.3 V ± 0.3 V 2.0 0.7 - ns

tsu set-up time

VCC = 2.7 V 2.0 - - ns

nDn to nCP; HIGH or LOW; see Fig. 7

VCC = 3.3 V ± 0.3 V 0.8 0 - ns

thhold time

VCC = 2.7 V 0.1 - - ns

nCP HIGH; see Fig. 5

VCC = 3.3 V ± 0.3 V 1.5 0.6 - ns

VCC = 2.7 V 1.5 - - ns

nCP LOW; see Fig. 5

VCC = 3.3 V ± 0.3 V 3.0 1.6 - ns

tWpulse width

VCC = 2.7 V 3.0 - - ns

[1] All typical values are measured at VCC = 3.3 V and Tamb = 25 °C.

10.1. Waveforms and test circuit

001aaa256

nCP input

nQn output

tPHL tPLH

VOH

GND

VOL

1/fmax

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 5. Propagation delay clock input to output, clock pulse width and maximum clock frequency

Product data sheet Rev. 11 — 5 February 2019 7 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

001aae464

tPZL

nYn output

nOE input

VOL

VOH

3.0 V

GND

0 V

tPLZ

tPZH tPHZ

Measurements points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

Fig. 6. Enable and disable times

001aaa257

GND

tsu

VOH

VOL

nQn output

nCP input

nDn input

Measurement points are given in Table 8.

VOL and VOH are typical voltage output levels that occur with the output load.

The shaded areas indicate when the input is permitted to change for predictable output performance.

Fig. 7. Data set-up and hold times

Table 8. Measurement points

Input Output

VMVMVXVY

1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V

Product data sheet Rev. 11 — 5 February 2019 8 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

VEXT

VCC

VIVO

001aae235

DUT

PULSE

GENERATOR

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

Test data is given in Table 9.

Definitions test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

VEXT = Test voltage for switching times.

Fig. 8. Test circuit for measuring switching times

Table 9. Test data

Input Load VEXT

VIfitWtr, tfCLRLtPHZ, tPZH tPLZ, tPZL tPLH, tPHL

2.7 V ≤ 10 MHz 500 ns ≤ 2.5 ns 50 pF 500 Ω GND 6 V open

Product data sheet Rev. 11 — 5 February 2019 9 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

11. Package outline

UNIT A

1 A

2 A

3 b

p c D

(1) E

(1) e H

E L L

p Q Z y w v θ

REFERENCES

OUTLINE

VERSION

EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.4

0.2

2.35

2.20 0.25 0.3

0.2

0.22

0.13

16.00

15.75

7.6

7.4 0.635 1.4 0.25

10.4

10.1

1.0

0.6

1.2

1.0

0.85

0.40

0.18 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT370-1 99-12-27

03-02-19

(1)

w M

v M A

48 25

MO-118

detail X

(A )

pin 1 index

0 5 10 mm

scale

SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1

max.

2.8

Fig. 9. Package outline SOT370-1 (SSOP48)

Product data sheet Rev. 11 — 5 February 2019 10 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

References

Outline

version

European

projection Issue date

IEC JEDEC JEITA

SOT362-1 MO-153

sot362-1_po

03-02-19

13-08-05

Unit

max

nom

min

0.15 0.28 0.2 12.6

0.5

0.8

Dimensions (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1

A1A2

1.05

A3bpc D(1)

8°

θE(2) e HEL

LpQ v w

1.2 0.25 0.10.25 0.08

y Z

7.9 0.46.0 0.350.05 0.17 0.1 12.4 0.4 0°

0.85

8.3 0.86.2 0.50

pin 1 index

v A

1 24

48 25

detail X

(A3)

0 5 mm

scale

2.5

Fig. 10. Package outline SOT362-1 (TSSOP48)

Product data sheet Rev. 11 — 5 February 2019 11 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

12. Abbreviations

Table 10. Abbreviations

Acronym Description

BiCMOS Bipolar Complementary Metal Oxide Semiconductor

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

MM Machine Model

TTL Transistor-Transistor Logic

13. Revision history

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVT_LVTH16374A v.11 20190205 Product data sheet - 74LVT_LVTH16374A v.10

Modifications: •The format of this data sheet has been redesigned to comply with the identity guidelines

of Nexperia.

•Legal texts have been adapted to the new company name where appropriate.

•Type numbers 74LVT16374AEV (SOT702-1) and

74LVTH16374ABX (SOT1134-2) removed.

•Package outline drawing SOT362-1 (TSSOP48) updated.

74LVT_LVTH16374A v.10 20120402 Product data sheet - 74LVT_LVTH16374A v.9

Modifications: •For type number 74LVTH16374ABX the sot code has changed to SOT1134-2.

74LVT_LVTH16374A v.9 20111122 Product data sheet - 74LVT_LVTH16374A v.8

Modifications: •Legal pages updated.

74LVT_LVTH16374A v.8 20110620 Product data sheet - 74LVT_LVTH16374A v.7

74LVT_LVTH16374A v.7 20100322 Product data sheet - 74LVT_LVTH16374A v.6

74LVT_LVTH16374A v.6 20100118 product data sheet - 74LVT16374A v.5

74LVT16374A v.5 20040916 product data sheet - 74LVT16374A v.4

74LVT16374A v.4 20021101 product specification - 74LVT16374A v.3

74LVT16374A v.3 19991018 product specification - 74LVT16374A v.2

74LVT16374A v.2 19980219 product specification - -

Product data sheet Rev. 11 — 5 February 2019 12 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

14. Legal information

Data sheet status

Document status

[1][2]

Product

status [3]

Definition

Objective [short]

data sheet

Development This document contains data from

the objective specification for

product development.

Preliminary [short]

data sheet

Qualification This document contains data from

the preliminary specification.

Product [short]

data sheet

Production This document contains the product

specification.

[1] Please consult the most recently issued document before initiating or

completing a design.

[2] The term 'short data sheet' is explained in section "Definitions".

[3] The product status of device(s) described in this document may have

changed since this document was published and may differ in case of

multiple devices. The latest product status information is available on

the internet at https://www.nexperia.com.

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Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

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products are for illustrative purposes only. Nexperia makes no representation

or warranty that such applications will be suitable for the specified use

without further testing or modification.

Customers are responsible for the design and operation of their applications

and products using Nexperia products, and Nexperia accepts no liability for

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Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those

given in the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Terms and conditions of commercial sale — Nexperia products are

sold subject to the general terms and conditions of commercial sale, as

published at http://www.nexperia.com/profile/terms, unless otherwise agreed

in a valid written individual agreement. In case an individual agreement is

concluded only the terms and conditions of the respective agreement shall

apply. Nexperia hereby expressly objects to applying the customer’s general

terms and conditions with regard to the purchase of Nexperia products by

customer.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from competent authorities.

Non-automotive qualified products — Unless this data sheet expressly

states that this specific Nexperia product is automotive qualified, the

product is not suitable for automotive use. It is neither qualified nor tested in

accordance with automotive testing or application requirements. Nexperia

accepts no liability for inclusion and/or use of non-automotive qualified

products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards,

customer (a) shall use the product without Nexperia’s warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

Nexperia’s specifications such use shall be solely at customer’s own risk,

and (c) customer fully indemnifies Nexperia for any liability, damages or failed

product claims resulting from customer design and use of the product for

automotive applications beyond Nexperia’s standard warranty and Nexperia’s

product specifications.

Translations — A non-English (translated) version of a document is for

reference only. The English version shall prevail in case of any discrepancy

between the translated and English versions.

Trademarks

Notice: All referenced brands, product names, service names and

trademarks are the property of their respective owners.

Product data sheet Rev. 11 — 5 February 2019 13 / 14

Nexperia 74LVT16374A; 74LVTH16374A

3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

Contents

1. General description......................................................1

2. Features and benefits.................................................. 1

3. Ordering information....................................................1

4. Functional diagram.......................................................2

5. Pinning information......................................................3

5.1. Pinning.........................................................................3

5.2. Pin description............................................................. 3

6. Functional description................................................. 4

7. Limiting values............................................................. 4

8. Recommended operating conditions..........................5

9. Static characteristics....................................................5

10. Dynamic characteristics............................................ 6

10.1. Waveforms and test circuit........................................ 7

11. Package outline........................................................ 10

12. Abbreviations............................................................ 12

13. Revision history........................................................12

14. Legal information......................................................13

For more information, please visit: http://www.nexperia.com

For sales office addresses, please send an email to: salesaddresses@nexperia.com

Date of release: 5 February 2019

Product data sheet Rev. 11 — 5 February 2019 14 / 14