10-8
August 1997
AD7523, AD7533
8-Bit, Multiplying D/A Converters
Features
• 8-Bit, 9-Bit and 10-Bit Linearity
• Low Gain and Linearity Temperature Coefficients
• Full Temperature Range Operation
• Static Discharge Input Protection
• TTL/CMOS Compatible
• Supply Range. . . . . . . . . . . . . . . . . . . . . . . .+5V to +15V
• Fast Settling Time at 25oC . . . . . . . . . . . . 150ns (Max)
• Four Quadrant Multiplication
• AD7533 Direct AD7520 Equivalent
Description
The AD7523 and AD7533 are monolithic, low cost, high
performance, 8-bit and 10-bit accurate, multiplying digital-to-
analog converter (DAC), in a 16 pin DIP.
Intersil’ thin film resistors on CMOS circuitry provide 10-bit
resolution (8-bit, 9-bit and 10-bit accuracy), with TTL/CMOS
compatible operation.
The AD7523 and AD7533s accurate four quadrant
multiplication, full military temperature range operation, full
input protection from damage due to static discharge by
clamps to V+ and GND, and very low power dissipation
make it a very versatile converter.
Low noise audio gain controls, motor speed controls,
digitally controlled gain and digital attenuators are a few of
the wide range of applications of the AD7523 and AD7533.
Ordering Information
PART NUMBER LINEARITY (INL, DNL) TEMP. RANGE (oC) PACKAGE PKG. NO.
AD7523JN, AD7533JN 0.2% (8-Bit) 0 to 70 16 Ld PDIP E16.3
AD7523KN, AD7533KN 0.1% (9-Bit) 0 to 70 16 Ld PDIP E16.3
AD7523LN, AD7533LN 0.05% (10-Bit) 0 to 70 16 Ld PDIP E16.3
Pinout
AD7523, AD7533
(PDIP)
TOP VIEW
NOTE:
1. NC for AD7523 only.
Functional Block Diagram
NOTE: Switches shown for digital inputs “High”
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
IOUT1
IOUT2
GND
BIT 1 (MSB)
BIT 2
BIT 3
BIT 5
BIT 4
RFEEDBACK
V+
NC/BIT 10
NC/BIT 9
BIT 8
BIT 7
BIT 6
VREF IN
(NOTE 1)
(NOTE 1)
MSB
(4)
20kΩ
(3)
BIT 3BIT 2
VREF IN
20kΩ20kΩ20kΩ20kΩ20kΩ
10kΩ10kΩ10kΩ10kΩ
SPDT
NMOS
10kΩ
IOUT2 (2)
IOUT1 (1)
RFEEDBACK
(15)
SWITCHES
(16)
(5) (6)
File Number 3105.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
10-9
Absolute Maximum Ratings Thermal Information
Supply Voltage (V+ to GND). . . . . . . . . . . . . . . . . . . . . . . . . . . +17V
VREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25V
Digital Input Voltage Range . . . . . . . . . . . . . . . . . . . . . . .V+ to GND
Output Voltage Compliance . . . . . . . . . . . . . . . . . . . . -100mV to V+
Operating Conditions
Temperature Range
JN, KN, LN Versions . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to 70oC
Thermal Resistance (Typical, Note 1) θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature . . . . . . . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified
PARAMETER TEST CONDITIONS
AD7523 AD7533
UNITS
TA 25oCT
A MIN-MAX TA 25oCT
A MIN-MAX
MIN MAX MIN MAX MIN MAX MIN MAX
SYSTEM PERFORMANCE
Resolution 8 - 8 - 10 - 10 - Bits
Nonlinearity J -10V ≤ VREF ≤ +10V
VOUT1 = VOUT2 = 0V
(Notes 2, 3, 6)
-±0.2 - ±0.2 - ±0.2 - ±0.2 % of
FSR
K, T - ±0.1 - ±0.1 - ±0.1 - ±0.1 % of
FSR
L-±0.05 - ±0.05 - ±0.05 - ±0.05 % of
FSR
Monotonicity Guaranteed Guaranteed
Gain Error All Digital Inputs High
(Note 3) -±1.5 - ±1.8 - ±1.4 - ±1.8 % of
FSR
Nonlinearity Tempco -10V ≤ VREF ≤ + 10V
(Notes 3, 4) -±2-±2-±2-±2 ppm of
FSR/oC
Gain Error Tempco - ±10 - ±10 - ±10 - ±10 ppm of
FSR/oC
Output Leakage Current
(Either Output) VOUT1 = VOUT2 = 0 - ±50 - ±200 - ±50 - ±200 nA
DYNAMIC CHARACTERISTICS
Power Supply Rejection V+ = 14.0V to 15.0V
(Note 3) -±0.02 - ±0.03 - ±0.005 - ±0.008 % of
FSR/%
of ∆V+
Output Current Settling Time To 0.2% of FSR,
RL = 100Ω (Note 4) - 150 - 200 - 600 - 800 ns
Feedthrough Error VREF = 20VP-P, 200kHz
Sine Wave, All Digital
Inputs Low (Note 4)
-±1/2 - ±1-±0.05 - ±0.1 LSB
REFERENCE INPUTS
Input Resistance (Pin 15) All Digital Inputs High
IOUT1 at Ground (Note 4) 5-5-5-5-kΩ
- 20 - 20 - 20 - 20 kΩ
Temperature Coefficient - -500 - -500 - -300 - -300 ppm/οC
AD7523, AD7533
10-10
Definition of Terms
Nonlinearity: Error contributed by deviation of the DAC
transfer function from a “best straight line” through the actual
plot of transfer function. Normally expressed as a
percentage of full scale range or in (sub)multiples of 1 LSB.
Resolution: It is addressing the smallest distinct analog
output change that a D/A converter can produce. It is
commonly expressed as the number of converter bits. A
converter with resolution of n bits can resolve output changes
of 2-N of the full-scale range, e.g., 2-N VREF for a unipolar
conversion. Resolution b y no means implies linearity.
Settling Time: Time required for the output of a DAC to
settle to within specified error band around its final value
(e.g., 1/2 LSB) for a given digital input change, i.e., all digital
inputs LOW to HIGH and HIGH to LOW.
Gain Error: The diff erence betw een actual and ideal analog
output values at full-scale range, i.e., all digital inputs at
HIGH state. It is expressed as a percentage of full scale
range or in (sub)multiples of 1 LSB.
Feedthrough Error: Error caused by capacitive coupling
from VREF to IOUT1 with all digital inputs LOW.
Output Capacitance: Capacitance from IOUT1, and IOUT2
terminals to ground.
Output Leakage Current: Current which appears on
IOUT1, ter minal when all digital inputs are LOW or on IOUT2
terminal when all digital inputs are HIGH.
For further information on the use of this device, see the
following Application Notes:
ANALOG OUTPUT
Output Capacitance COUT1 All Digital Inputs High
(Note 4) - 100 - 100 - 100 - 100 pF
COUT2 - 30 - 30 - 35 - 35 pF
COUT1 All Digital Inputs Low
(Note 4) - 30 - 30 - 35 - 35 pF
COUT2 - 100 - 100 - 100 - 100 pF
DIGITAL INPUTS
Low State Threshold, VIL - 0.8 - 0.8 - 0.8 - 0.8 V
High State Threshold, VIH 2,4 - 2,4 - 2.4 - 2.4 - V
Input Current (Low or High),
IIL, IIH VIN = 0V or + 15V - ±1-±1-±1-±1µA
Input Coding See Tables 1 and 3 Binary/Offset Binary Binary/Offset Binary
Input Capacitance (Note 4) - 4 - 4 - 4 - 4 pF
POWER SUPPLY CHARACTERISTICS
Power Supply Voltage Range (Note 6) +5 to +16 +5 to +16 V
I+ All Digital Inputs High or
Low (Excluding Ladder
Network)
- 2 - 2.5 - 2 - 2.5 mA
NOTES:
2. Full Scale Range (FSR) is 10V for unipolar and ±10V for bipolar modes.
3. Using internal feedback resistor, RFEEDBACK.
4. Guaranteed by design or characterization and not production tested.
5. Accuracy not guaranteed unless outputs at ground potential.
6. Accuracy is tested and guaranteed at V+ = +15V, only.
Electrical Specifications V+ = +15V, VREF = +10V, VOUT1 = VOUT2 = 0V, Unless Otherwise Specified (Continued)
PARAMETER TEST CONDITIONS
AD7523 AD7533
UNITS
TA 25oCT
A MIN-MAX TA 25oCT
A MIN-MAX
MIN MAX MIN MAX MIN MAX MIN MAX
NOTE # DESCRIPTION AnswerFAX
DOC. #
AN002 “Principles of Data Acquisition and
Conversion” 9002
AN018 “Do’s and Don’ts of Applying A/D
Converters” 9018
AN042 “Interpretation of Data Conversion
Accuracy Specifications” 9042
AD7523, AD7533
10-11
Detailed Description
The AD7523 and AD7533 are monolithic multiplying D/A
converters. A highly stable thin film R-2R resistor ladder
network and NMOS SPDT switches form the basis of the
converter circuit, CMOS level shifters permit low power
TTL/CMOS compatible operation. An external voltage or
current reference and an operational amplifier are all that is
required for most voltage output applications.
A simplified equivalent circuit of the DAC is shown in the
Functional Diagram. The NMOS SPDT switches steer the
ladder leg currents between IOUT1 and IOUT2 buses which
must be held at ground potential. This configuration main-
tains a constant current in each ladder leg independent of
the input code.
Converter errors are further reduced by using separate
metal interconnections between the major bits and the out-
puts. Use of high threshold switches reduce offset (leakage)
errors to a negligible level.
The le v el shifter circuits are comprised of three inv erters with
positive feedback from the output of the second to the first,
see Figure 1. This configuration results in TTL/CMOS
compatible operation over the full military temperature
range. With the ladder SPDT switches driven by the level
shifter, each switch is binarily weighted for an ON resistance
proportional to the respective ladder leg current. This
assures a constant voltage drop across each switch,
creating equipotential terminations for the 2R ladder
resistors and high accurate leg currents.
Typical Applications
Unipolar Binary Operation - AD7523 (8-Bit DAC)
The circuit configuration for operating the AD7523 in
unipolar mode is shown in Figure 2. With positive and
negative VREF values the circuit is capable of 2-Quadrant
multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 1.
NOTES:
1. R1 and R2 used only if gain adjustment is required.
2. CF1 protects AD7523 and AD7533 against negative transients.
FIGURE 2. UNIPOLAR BINARY OPERATION
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V ±1mV (Max) at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (11/28) reading.
3. To increase VOUT, connect a series resistor , R2, (0Ω to
250Ω) in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor , R1, (0Ω to
250Ω) between the reference voltage and the VREF
terminal.
V+
TTL/
CMOS INPUT
13 4
5
6
72
89
TO LADDER
IOUT2 IOUT1
FIGURE 1. CMOS SWITCH
TABLE 1. UNlPOLAR BINARY CODE - AD7523
DIGITAL INPUT
MSB LSB ANALOG OUTPUT
11111111
10000001
10000000
01111111
00000001
00000000
NOTE:
1. .
15 16
1
4
11 3 2
AD7523/
MSB
LSB
14
+15V
VREF
GND
OUT1
OUT2 6
VOUT
-
+
RFEEDBACK
DATA
INPUTS AD7533
±10V
R2
CR1
VREF 255
256
----------
–
VREF 129
256
----------
–
VREF 128
256
----------
–VREF
2
-----------------–=
VREF 127
256
----------
–
VREF 1
256
----------
–
VREF 0
256
----------
–0=
1 LSB 2 8–
()VREF
()1
256
----------
VREF
()==
AD7523, AD7533
10-12
Unipolar Binary Operation - AD7533 (10-Bit DAC)
The circuit configuration for operating the AD7533 in
unipolar mode is shown in Figure 2. With positive and
negative VREF values the circuit is capable of 2-Quadrant
multiplication. The “Digital Input Code/Analog Output Value”
table for unipolar mode is given in Table 2.
Zero Offset Adjustment
1. Connect all digital inputs to GND.
2. Adjust the offset zero adjust trimpot of the output
operational amplifier for 0V ±1mV (Max) at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1 - 1/210) reading.
3. To increase VOUT, connect a series resistor , R2, (0Ω to
250Ω) in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor , R1, (0Ω to
250Ω) between the reference voltage and the VREF
terminal.
Bipolar (Offset Binary) Operation - AD7523
The circuit configuration for operating the AD7523 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage
values, Four-Quadrant multiplication can be realized. The
“Digital Input Code/Analog Output Value” table for bipolar
mode is given in Table 3.)
A “Logic 1” input at any digital input f orces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic
0” input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity
of IOUT2 current and the transconductance amplifier at IOUT
output sums the two currents. This configuration doubles the
output range. The difference current resulting at zero offset
binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is
corrected by suing an external resistor, (10MΩ), from VREF
to IOUT2 (Figure 3).
TABLE 2. UNlPOLAR BINARY CODE - AD7533
DIGITAL INPUT
MSB LSB (NOTE 1)
NOMINAL ANALOG OUTPUT
1111111111
1000000001
1000000000
0111111111
0000000001
0000000000
NOTES:
1. VOUT as shown in the Functional Diagram.
2. Nominal Full Scale for the circuit of Figure 2 is given by:
.
3. Nominal LSB magnitude for the circuit of Figure 2 is given by:
.
VREF 1023
1024
-------------
–
VREF 513
1024
-------------
–
VREF 512
1024
-------------
–VREF
2
---------------–=
VREF 511
1024
-------------
–
VREF 1
1024
-------------
–
VREF 0
1024
-------------
–0=
FS VREF 1023
1024
-------------
–=
LSB VREF 1
1024
-------------
=
TABLE 3. BlPOLAR (OFFSET BINARY) CODE - AD7523
DIGITAL INPUT
MSB LSB ANALOG OUTPUT
11111111
10000001
10000000 0
01111111
00000001
00000000
NOTE:
1. .
VREF 127
128
----------
–
VREF 1
128
----------
–
+VREF 1
128
----------
+VREF 127
128
----------
+VREF 128
128
----------
1 LSB 2 7
–
()VREF
()
1
128
----------
VREF
()==
IOUT2 6
RFEEDBACK
6
-
+
IOUT1
CR1
15 16
1
4
13 32
AD7523/
MSB
LSB
14
+15
V
VREF
DATA
INPUTS AD7533
±10
V
R3 5KR4 5K VOUT
R2
CR2
R1
R6 10MΩ
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
-
+
AD7523, AD7533
10-13
Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Connect all digital inputs to “Logic 1”.
3. Adjust IOUT2 amplifier offset adjust trimpot for 0V±1mV at
IOUT2 amplifier output.
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to
“Logic 0”.
5. Adjust IOUT1 amplifier offset adjust trimpot for 0V±1mV
at VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (11/28) volts reading.
3. To increase V OUT, connect a series resistor , R2, of up to
250Ω between VOUT and RFEEDBACK.
4. To decrease VOUT, connect a series resistor , R1, of up to
250Ω between the reference voltage and the VREF
terminal.
Bipolar (Offset Binary) Operation - AD7533
The circuit configuration for operating the AD7533 in the
bipolar mode is given in Figure 3. Using offset binary digital
input codes and positive and negative reference voltage val-
ues, 4-Quadrant multiplication can be realized. The “Digital
Input Code/Analog Output Value” table for bipolar mode is
given in Table 4.
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic 0”
input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity of
IOUT2 current and the transconductance amplifier at IOUT1
output sums the two currents. This configuration doubles the
output range. The difference current resulting at zero offset
binary code, (MSB = “Logic 1”, all other bits = “Logic 0”), is cor-
rected by using an external resistor, (10MΩ), from VREF to
IOUT2.
TABLE 4. UNlPOLAR BINARY CODE - AD7533
DIGITAL INPUT
MSB LSB (NOTE 1)
NOMINAL ANALOG OUTPUT
1111111111
1000000001
1000000000 0
0111111111
0000000001
0000000000
NOTES:
1. VOUT as shown in the Functional Diagram.
2. Nominal Full Scale for the circuit of Figure 6 is given by:
.
3. Nominal LSB magnitude for the circuit of Figure 3 is given by:
.
-VREF 511
512
----------
-VREF 1
512
----------
+VREF 1
512
----------
+VREF 511
512
----------
+VREF 512
512
----------
FSR VREF 1023
512
-------------
=
LSB VREF 1
512
----------
=
FIGURE 4. 10-BIT AND SIGN MULTIPLYING DAC
OUT2 6
-
+
RFEEDBACK
6
-
+
OUT1
15 16
1
4
13 32
AD7533
MSB
LSB
14
V+
VREF
MAGNITUDE
BITS
±10V
VOUT
10K
GND
SIGN BIT
DIGITAL
INPUT
BIPOLAR
ANALOG INPUT
10K
1/2 IH5140
5K
AD7523, AD7533
10-14
Offset Adjustment
1. Adjust VREF to approximately +10V.
2. Connect all digital inputs to “Logic 1”.
3. Adjust IOUT2 amplifier offset adjust trimpot for 0V±1mV at
IOUT2 amplifier output.
4. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
5. Adjust IOUT1 amplifier offset adjust trimpot for 0V±1mV at
VOUT.
Gain Adjustment
1. Connect all digital inputs to V+.
2. Monitor VOUT for a -VREF (1 - 2-9) volts reading.
3. T o increase VOUT, connect a series resistor of up to 250Ω
between VOUT and RFEEDBACK.
4. To decrease VOUT, connect a series resistor of up to 250Ω
between the ref erence v oltage and the VREF terminal.
FIGURE 5. PROGRAMMABLE FUNCTION GENERATOR
VOUT = -VIN/D
Where:
FIGURE 6. DIVIDER (DIGITALLY CONTROLLED GAIN) FIGURE 7. MODIFIED SCALE FACTOR AND OFFSET
6
-
+
OUT1
15 16
1
4
13 32
AD7523/
MSB
LSB
14
NC
DIGITAL FREQUENCY
CONTROL WORD AD7533
+15V
VDD
A1
C1
CALIBRATE
10K
6.8V
(2) 6
-
+
A2
10K 1% 10K 1%
4.7K
TRIANGULAR
WAVE
SQUARE
WAVE
1K
OUT2
6
-
+
OUT2 14
24
11
3
1
AD7523/ MSB
LSB
16
+15V
VIN
DIGITAL
INPUT
AD7533
15 BIT 8 (10) (AD7533)
BIT 1
“D”
VREF
VOUT
OUT1
RFB
DBit 1
21
------------- Bit 2
22
------------- …Bit 8
22
-------------
++=
0D255
256
----------
≤≤
6
-
+
15 16
1
4
13 32
AD7523/
MSB
LSB
14
R1
AD7533
+15V
6
-
+
BIT 1
BIT 8
DIGITAL
INPUT
“D”
R2
VREF
VOUT
(10) (AD7533)
VOUT VREF R2
R1R2
+
----------------------
R1D
R1R2
+
----------------------
–
=
Where D Bit 1
21
------------Bit 2
22
------------…Bit 8
28
------------
++=
0D255
256
----------
≤≤
AD7523, AD7533
10-15
Die Characteristics
DIE DIMENSIONS:
101 mils x 103 mils (2565micrms x 2616micrms)
METALLIZATION:
Type: Pure Aluminum
Thickness: 10 ±1kÅ
PASSIVATION:
Type: PSG/Nitride
PSG: 7 ±1.4kÅ
Nitride: 8 ±1.2kÅ
PROCESS:
CMOS Metal Gate
Metallization Mask Layout
AD7523, AD7533
PIN 3
GND
PIN 2
IOUT2
PIN 1
IOUT1
PIN 16
RFEEDBACK
PIN 15
VREF
PIN 14
V+
NCNCNCNC
PIN 4
BIT 1
(MSB)
PIN 5
BIT 2
PIN 6
BIT 3
PIN 7
BIT 4
PIN 11
BIT 8
(LSB)
PIN 10
BIT 7
PIN 9
BIT 6
PIN 8
BIT 5
(PIN 12, BIT 9, AD7533) (PIN 13, BIT 10, AD7533)
AD7523, AD7533
10-16
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate
and reliable . However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (407) 724-7000
FAX: (407) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
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Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
AD7523, AD7533
