LMH6522
LMH6522 High Performance Quad DVGA
Literature Number: SNOSB53B
LMH6522
September 14, 2011
High Performance Quad DVGA
General Description
The LMH6522 contains four, high performance, digitally con-
trolled variable gain amplifiers (DVGA). It has been designed
for use in narrowband and broadband IF sampling applica-
tions. Typically, the LMH6522 drives a high performance ADC
in a broad range of mixed signal and digital communication
applications such as mobile radio and cellular base stations
where automatic gain control (AGC) is required to increase
system dynamic range.
Each channel of LMH6522 has an independent, digitally con-
trolled attenuator and a high linearity, differential output, am-
plifier. All circuitry has been optimized for low distortion and
maximum system design flexibility. Power consumption is
managed by a three-state enable pin. Individual channels can
be disabled or placed into a Low Power Mode or a higher
performance, High Power Mode.
The LMH6522 digitally controlled attenuator provides precise
1dB gain steps over a 31dB range. The digital attenuator can
be controlled by either a SPI™ Serial bus or a high speed
parallel bus.
The output amplifier has a differential output, allowing large
signal swings on a single 5V supply. The low impedance out-
put provides maximum flexibility when driving a wide range
filter designs or analog to digital converters. For applications
which have very large changes in signal level LMH6522 can
support up to 62dB of gain range by cascading channels.
The LMH6522 operates over the industrial temperature range
of −40°C to +85°C. The LMH6522 is available in a 54-Pin,
thermally enhanced, LLP package.
Features
■OIP3: 49dBm @ 200MHz
■Noise Figure: 8.5dB
■Voltage Gain: 26dB
■1dB Gain Steps
■−3dB bandwidth of 1400 MHz
■Gain Step Accuracy: 0.2 dB
■Disable function for each channel
■Parallel and Serial gain control
■Low Power Mode for power management flexibility
■Small footprint LLP package
Applications
■Cellular base stations
■Wideband and narrowband IF sampling receivers
■Wideband direct conversion
■ADC Driver
Performance Curve
OIP3 vs Filter Input Resistance
50 100 150 200 250 300
0
10
20
30
40
50
60
5
10
15
20
25
30
35
OIP3 (dBm)
FILTER INPUT RESISTANCE (Ω)
POWER GAIN (dB)
f = 200 MHz
VOUT = 2VPPD
@ filter input
30127381
SPI™ is a trademark of Motorola, Inc.
© 2011 National Semiconductor Corporation 301273 www.national.com
LMH6522 High Performance Quad DVGA
Block Diagram
30127332
www.national.com 2
LMH6522
Table of Contents
General Description .............................................................................................................................. 1
Features .............................................................................................................................................. 1
Applications ......................................................................................................................................... 1
Performance Curve ............................................................................................................................... 1
Block Diagram ...................................................................................................................................... 2
Absolute Maximum Ratings .................................................................................................................... 4
Operating Ratings (Note 1).................................................................................................................... 4
Connection Diagram ............................................................................................................................. 6
Ordering Information ............................................................................................................................. 6
Typical Performance Characteristics ....................................................................................................... 9
Application Information ........................................................................................................................ 16
INTRODUCTION ......................................................................................................................... 16
BASIC CONNECTIONS ............................................................................................................... 18
INPUT CHARACTERISTICS ......................................................................................................... 18
OUTPUT CHARACTERISTICS ..................................................................................................... 19
CASCADE OPERATION .............................................................................................................. 20
DIGITAL CONTROL .................................................................................................................... 21
PARALLEL INTERFACE .............................................................................................................. 21
SPI COMPATIBLE SERIAL INTERFACE ........................................................................................ 21
SPISU2 SPI CONTROL BOARD AND TINYI2CSPI SOFTWARE ....................................................... 24
THERMAL MANAGEMENT .......................................................................................................... 24
INTERFACING TO AN ADC ......................................................................................................... 24
ADC Noise Filter .................................................................................................................. 24
POWER SUPPLIES ..................................................................................................................... 25
DYNAMIC POWER MANAGEMENT, USING LOW POWER MODE ................................................... 25
COMPATIBLE HIGH SPEED ANALOG TO DIGITAL CONVERTERS ................................................. 26
Physical Dimensions ........................................................................................................................... 27
3 www.national.com
LMH6522
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ESD Tolerance (Note 2)
Human Body Model 2 kV
Machine Model 200V
Charged Device Model 750V
Positive Supply Voltage (Pin 3) −0.6V to 5.5V
Differential Voltage between Any
Two Grounds <200 mV
Analog Input Voltage Range −0.6V to 5.5V
Digital Input Voltage Range −0.6V to 5.5V
Output Short Circuit Duration
(one pin to ground) Infinite
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Soldering Information
Infrared or Convection (30 sec) 260°C
Operating Ratings (Note 1)
Supply Voltage (Pin 3) 4.75V to 5.25V
Differential Voltage Between Any
Two Grounds <10 mV
Analog Input Voltage Range,
AC Coupled 0V to V+
Temperature Range (Note 3) −40°C to +85°C
Package Thermal
Resistance (Note 9)
(θJA) (θJC)
54pin LLP 23°C/W 4.7°C/W
5V Electrical Characteristics (Note 4)
The following specifications apply for single supply with V+ = 5V, Maximum Gain (0 Attenuation), RL = 200Ω, VOUT = 4VPPD, fin =
200 MHz, High Power Mode, Boldface limits apply at temperature extremes.
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)Units
Dynamic Performance
3dBBW −3dB Bandwidth VOUT= 2 VPPD 1.4 GHz
Output Noise Voltage Source = 100Ω 30 nV/√Hz
NF Noise Figure Source = 100Ω 8.5 dB
OIP3 Output Third Order Intercept Point f = 100 MHz, VOUT = 4 dBm per tone 53 dBm
Output Third Order Intercept Point f = 200 MHz, VOUT = 4 dBm per tone 49
OIP2 Output Second Order Intercept
Point
POUT= 4 dBm per Tone, f1 =101 MHz,
f2=203 MHz
78 dBm
IMD3 Third Order Intermodulation
Products
f = 100 MHz, VOUT = 4 dBm per tone −98 dBc
Third Order Intermodulation
Products
f = 200 MHz, VOUT = 4 dBm per tone −90
P1dB 1dB Compression Point 17 dBm
HD2 Second Order Harmonic Distortion f = 100 MHz, VOUT =2 VPPD −88 dBc
HD2 Second Order Harmonic Distortion f = 200 MHz, VOUT =2 VPPD −78 dBc
HD3 Third Order Harmonic Distortion f = 100 MHz, VOUT =2 VPPD −99 dBc
HD3 Third Order Harmonic Distortion f = 200 MHz, VOUT =2 VPPD −75 dBc
CMRR Common Mode Rejection Pin = −15 dBm −35 dBc
Analog I/O
RIN Input Resistance Differential, Measured at DC 97 Ω
VICM Input Common Mode Voltage Self Biased 2.5 V
Maximum Input Voltage Swing Volts peak to peak, differential 5.5 VPPD
Maximum DIfferential Output
Voltage Swing
Differential, f < 10MHz 10 VPPD
ROUT Output Resistance Differential, Measured at DC 20 Ω
XTLK Channel to Channel Crosstalk Maximum Gain, f=200MHz −65 dBc
Gain Parameters
Maximum Voltage Gain Attenuation code 00000 25.74 dB
Minimum Gain Attenuation code 11111 −4.3 dB
Gain Steps 32
Gain Step Size 1.0 dB
Channel Matching Gain error between channels ±0.15 dB
www.national.com 4
LMH6522
Symbol Parameter Conditions Min
(Note 6)
Typ
(Note 5)
Max
(Note 6)Units
Gain Step Error Any two adjacent steps over entire range ±0.5 dB
Gain Step Error Any two adjacent steps, 0 dB attenuation
to 23 dB attenuation
±0.1 dB
Gain Step Phase Shift Any two adjacent steps over entire range ±3 Degrees
Gain Step Phase Shift Any two adjacent steps, 0dB attenuation
to 23 dB attenuation
±2 Degrees
Gain Step Switching Time 20 ns
Enable/ Disable Time Settled to 90% level 200 ns
Power Requirements
ICC Supply Current 465 485 mA
P Power 2.3 2.43 W
IBIAS Output Pin Bias Current External inductor, no load, VOUT< 200 mV 36 mA
ICC Disabled Supply Current 74 mA
All Digital Inputs Except Enables
Logic Compatibility TTL, 2.5V CMOS, 3.3V CMOS, 5V CMOS
VIL Logic Input Low Voltage 0 0.4 V
VIH Logic Input High Voltage 2.0 5.0 V
IIH Logic Input High Input Current Digital Input Voltage = 2.0V −9 μA
IIL Logic Input Low Input Current Digital Input Voltage = 0.4V −47 μA
Enable Pins
VIL Logic Input Low Voltage Amplifier disabled 0 0.4 V
VIM Logic Input Mid Level Amplifier Low Power Mode 0.6 1.9 V
VIH Logic Input High Level Amplifier High Power Mode 2.2 5 V
VSB Enable Pin Self Bias Voltage No external load 1.37 V
IIL Input Bias Current, Logic Low Digital input voltage = 0.2V −200 µA
IIM Input Bias Current, Logic Mid Digital input voltage = 1.5V 28 µA
IIH Input Bias Current, Logic High Digital input voltage = 3.0V 500 µA
Parallel Mode Timing
tGS Setup Time 3 ns
tGH Hold Time 3 ns
Serial Mode
fCLK SPI Clock Frequency 50% duty cycle, ATE tested @ 20MHz 20 50 MHz
Low Power Mode
(Enable pins are self biased)
ICC Total Supply Current all four channels in low power mode 370 398 mA
IBIAS Output Pin Bias Current External Inductor, No Load, VOUT<
200mV
26 mA
ICC Disabled Supply Current Enable Pin < 0.4V 74 mA
OIP3 Output Intermodulation Intercept
Point
f = 200 MHz, V OUT = 4 dBm per tone 44 dBm
P1dB 1dB Compression Point 16 dBm
HD2 Second Order Harmonic Distortion f = 100 MHz, VOUT =2 VPPD −90 dBc
HD2 Second Order Harmonic Distortion f = 200 MHz,VOUT = 2 VPPD −79 dBc
HD3 Third Order Harmonic Distortion f = 100 MHz, VOUT = 2 VPPD −91 dBc
HD3 Third Order Harmonic Distortion f = 200 MHz, VOUT = 2 VPPD −79 dBc
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables.
Note 2: Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)
Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
5 www.national.com
LMH6522
Note 3: The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Note 4: Electrical Table values apply only for factory testing conditions at the temperature indicated. No guarantee of parametric performance is indicated in the
electrical tables under conditions different than those tested
Note 5: Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will
also depend on the application and configuration. The typical values are not tested and are not guaranteed on shipped production material.
Note 6: Limits are 100% production tested at 25°C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality
Control (SQC) methods.
Note 7: Negative input current implies current flowing out of the device.
Note 8: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change.
Note 9: Junction to ambient (θJA) thermal resistance measured on JEDEC 4 layer board. Junction to case (θJC) thermal resistance measured at exposed thermal
pad; package is not mounted to any PCB.
Connection Diagram
54-Pin LLP
30127303
Top View
Ordering Information
Package Part Number Package Marking Transport Media NSC Drawing
54-Pin LLP LMH6522SQE L6522 250 Units Tape and Reel SQA54A
LMH6522SQ 2k Units Tape and Reel
www.national.com 6
LMH6522
Pin Descriptions
Pin Number Symbol Pin Category Description
Analog I/O
2, 3 INA+, INA - Analog Input Differential inputs channel A
44, 43 OUTA+, OUTA- Analog Output Differential outputs Channel A
7, 8 INB+, INB - Analog Input Differential inputs channel B
39, 38 OUTB+, OUTB- Analog Output Differential outputs Channel B
11, 12 INC+, INC - Analog Input Differential inputs channel C
35, 34 OUTC+, OUTC- Analog Output Differential outputs Channel C
16, 17 IND+, IND - Analog Input Differential inputs channel D
30, 29 OUTD+, OUTD- Analog Output Differential outputs Channel D
Power
1, 4, 6, 9, 10, 13, 14,
15, 18
GND Ground Ground pins. Connect to low impedance ground
plane. All pin voltages are specified with respect
to the voltage on these pins. The exposed
thermal pad is internally bonded to the ground
pins.
31, 33, 40, 42 +5VD, +5VC, +5VB,
+5VA
Power Power supply pins. Valid power supply range is
4.75V to 5.25V.
Exposed Center
Pad
Thermal/ Ground Thermal management/ Ground
Digital Inputs
5 MODE Digital Input 0= Parallel Mode, 1 = Serial Mode
Parallel Mode Digital Pins, MODE = Logic Low
49, 48, 47, 46, 45 A0, A1, A2, A3, A4 Digital Input Channel A attenuator control
41 ENBA Digital Input Channel A enable pin
54, 53, 52, 51, 50 B0, B1, B2, B3, B4 Digital Input Channel B attenuator control
37 ENBB Digital Input Channel B enable pin: pin has three states:
Low, Mid, High
19, 20, 21, 22, 23 C0, C1, C2, C3, C4 Digital Input Channel C attenuator control
36 ENBC Digital Input Channel C enable pin
24, 25, 26, 27, 28 D0, D1, D2, D3, D4 Digital Input Channel D attenuator control
32 ENBD Digital Input Channel D enable pin
Serial Mode Digital Pins, MODE = Logic High
SPI Compatible
45 SDO Digital Output- Open Collector Serial Data Output (Requires external bias.)
46 SDI Digital Input Serial Data In
47 CSb Digital Input Chip Select
48 CLK Digital Input Clock
7 www.national.com
LMH6522
Pin List
Pin Description Pin Description
1 GND 28 D4
2 INA+ 29 OUTD−
3 INA− 30 OUTD+
4 GND 31 +5VD
5 MODE 32 ENBD
6 GND 33 +5VC
7 INB+ 34 OUTC−
8 INB− 35 OUTC+
9 GND 36 ENBC
10 GND 37 ENBB
11 INC+ 38 OUTB−
12 INC− 39 OUTB+
13 GND 40 +5VB
14 GND 41 ENBA
15 GND 42 +5VA
16 IND+ 43 OUTA−
17 IND− 44 OUTA+
18 GND 45 A4 / SDO
19 C0 46 A3 / SDI
20 C1 47 A2 / CSb
21 C2 48 A1 / CLK
22 C3 49 A0
23 C4 50 B4
24 D0 51 B3
25 D1 52 B2
26 D2 53 B1
27 D3 54 BO
www.national.com 8
LMH6522
Typical Performance Characteristics (TA = 25°C, V+ = 5V, RL = 200Ω, Maximum Gain, High Power, f=
200MHz; LMH6522 soldered onto LMH6522EVAL evaluation board, Unless Specified).
Frequency Response, 2dB Steps
30127340
OIP3 vs Attenuation
0 4 8 12 16 20 24 28 32
32
36
40
44
48
52
OIP3 (dBm)
ATTENUATION (dB)
POUT= 4dBm / Tone
High Power Mode
Low Power Mode
30127353
OIP3 vs Output Power
0 2 4 6 8 10 12
28
32
36
40
44
48
52
OIP3 (dBm)
OUTPUT POWER, EACH TONE (dBm)
30127361
OIP3 vs Load Resistance
0 100 200 300 400 500 600
30
35
40
45
50
55
OIP3 (dBm)
LOAD RESISTANCE (Ω)
VOUT= 4VPPD
High Power Mode
Low Power Mode
30127365
OIP3 vs Frequency
100 200 300 400 500
32
36
40
44
48
52
56
OIP3 (dBm)
FREQUENCY (MHz)
POUT=4dBm / Tone
High Power Mode
Low Power Mode
30127356
OIP3 vs Supply Voltage
4.50 4.75 5.00 5.25 5.50
36
40
44
48
52
OIP3 (dBm)
SUPPLY VOLTAGE (V)
High Power Mode
Low Power Mode
30127355
9 www.national.com
LMH6522
OIP3 vs Temperature
-45 -30 -15 0 15 30 45 60 75 90
40
44
48
52
56
OIP3 (dBm)
TEMPERATURE (Degrees C)
High Power Mode
Low Power Mode
30127373
Supply Current vs Supply Voltage
4.50 4.75 5.00 5.25 5.50
300
350
400
450
500
550
SUPPLY CURRENT (mA)
SUPPLY VOLTAGE (V)
High Power Mode
Low Power Mode
30127354
Supply Current vs Temperature
-45 -30 -15 0 15 30 45 60 75 90
350
375
400
425
450
475
500
SUPPLY CURRENT (mA)
TEMPERATURE (Degrees C)
High Power Mode
Low Power Mode
30127358
Maximum Gain vs Temperature
-45 -30 -15 0 15 30 45 60 75 90
24.0
24.5
25.0
25.5
26.0
26.5
27.0
27.5
28.0
MAXIMUM GAIN (dB)
TEMPERATURE (Degrees C)
High Power Mode
Low Power Mode
30127359
HD2 vs Frequency, High Power Mode
0 100 200 300 400 500
-90
-80
-70
-60
-50
-40
-30
-20
HD2 (dB)
FREQUENCY (MHz)
POUT=10dBm
Ch A
Ch B
Ch C
Ch D
30127324
HD3 vs Frequency, High Power Mode
0 100 200 300 400 500
-100
-90
-80
-70
-60
-50
-40
-30
-20
HD3 (dBc)
FREQUENCY (MHz)
POUT=10dBm
Ch A
Ch B
Ch C
Ch D
30127325
www.national.com 10
LMH6522
HD2 vs Frequency, Low Power Mode
0 100 200 300 400 500
-100
-90
-80
-70
-60
-50
-40
-30
HD2 (dBc)
FREQUENCY (MHz)
POUT= 10dBm
Ch A
Ch B
Ch C
Ch D
30127326
HD3 vs Frequency, Low Power Mode
0 100 200 300 400 500
-90
-80
-70
-60
-50
-40
-30
-20
HD3 (dBc)
FREQUENCY (MHz)
POUT=10dBm
Ch A
Ch B
Ch C
Ch D
30127327
HD2 vs Attenuation
0 4 8 12 16 20 24 28 32
-90
-80
-70
-60
-50
-40
HD2 (dBc)
ATTENUATION (dB)
POUT= 4dBm
High Power Mode
Low Power Mode
30127363
HD3 vs Attenuation
0 4 8 12 16 20 24 28 32
-90
-80
-70
-60
-50
-40
HD3 (dBc)
ATTENUATION (dB)
POUT= 4dBm
High Power Mode
Low Power Mode
30127364
HD2 vs Output Power
-4 0 4 8 12 16 20
-100
-90
-80
-70
-60
-50
-40
-30
-20
HD2 (dBc)
OUTPUT POWER (dBm)
High Power Mode
Low Power Mode
30127320
HD3 vs Output Power
-4 0 4 8 12 16 20
-100
-90
-80
-70
-60
-50
-40
-30
-20
HD3 (dBc)
OUTPUT POWER (dBm)
High Power Mode
Low Power Mode
30127321
11 www.national.com
LMH6522
Isolation, Adjacent Channels
10 100 1000
-90
-80
-70
-60
-50
-40
-30
-20
ISOLATION (dBc)
FREQUENCY (MHz)
IN A OUT B
IN B OUT A
IN B OUT C
IN C OUT B
IN C OUT D
IN D OUT C
30127371
Isolation, Non-Adjacent Channels
10 100 1000
-110
-100
-90
-80
-70
-60
-50
-40
ISOLATION (dBc)
FREQUENCY (MHz)
IN A OUT C
IN A OUT D
IN B OUT D
IN C OUT A
IN D OUT A
IN D OUT B
30127372
Channel Matching, Maximum Gain
10 100 1000
-2
-1
0
1
2
3
4
GAIN MATCHING (dB)
FREQUENCY (MHz)
A to B
A to C
A to D
30127374
Channel Matching
Attenuation Code 10000
10 100 1000
-2
-1
0
1
2
3
4
GAIN MATCHING (dB)
FREQUENCY (MHz)
A to B
A to C
A to D
30127335
Gain Step Amplitude Error
1 6 11 16 21 26 31
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
AMPLITUDE ERROR (dB)
ATTENUATION (dB)
50 MHz
200 MHz
300 MHz
30127336
Gain Step Phase Error
1 6 11 16 21 26 31
-8
-6
-4
-2
0
2
4
PHASE ERROR (Degrees)
ATTENUATION (dB)
50 MHz
200 MHz
300 MHz
30127339
www.national.com 12
LMH6522
Cumulative Amplitude Error
1 6 11 16 21 26 31
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
AMPLITUDE ERROR (dB)
ATTENUATION (dB)
50 MHz
200 MHz
300 MHz
30127337
Cumulative Phase Error
1 6 11 16 21 26 31
-16
-14
-12
-10
-8
-6
-4
-2
0
2
4
PHASE ERROR (Degrees)
ATTENUATION (dB)
50 MHz
200 MHz
300 MHz
30127338
Noise Figure vs Attenuation
0 4 8 12 16 20 24 28 32
8
12
16
20
24
28
32
36
40
NOISE FIGURE (dB)
ATTENUATION (dB)
30127350
Noise Figure vs Frequency
0 100 200 300 400
7
8
9
10
11
12
13
14
NOISE FIGURE (dB)
FREQUENCY (MHz)
30127351
Enable Timing, High Power
0 100 200 300 400 500 600 700 800
-2
-1
0
1
2
3
0
1
2
3
4
5
VOUT (V)
TIME (ns)
ENA PIN (V)
Output
Enable Pin
30127348
Enable Timing, Low Power
0 100 200 300 400 500 600 700 800
-2
-1
0
1
2
3
-2
-1
0
1
2
3
VOUT (V)
TIME (ns)
ENA PIN (V)
Output
Enable Pin
30127349
13 www.national.com
LMH6522
Gain Step Timing, 16dB Step
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
0
1
2
3
4
5
VOUT (V)
TIME (ns)
A4 PIN (V)
Output
A4 Pin
30127342
Gain Step Timing, 8dB Step
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
0
1
2
3
4
5
VOUT (V)
TIME (ns)
A3 PIN (V)
Output
A3 Pin
30127343
Gain Step Timing, 4dB Step
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
0
1
2
3
4
5
VOUT (V)
TIME (ns)
A2 PIN (V)
Output
A2 Pin
30127344
Gain Step Timing, 2dB Step
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
0
1
2
3
4
5
VOUT (V)
TIME (ns)
A1 PIN (V)
Output
A1 Pin
30127345
Gain Step Timing, 1dB Step
0 10 20 30 40 50 60 70 80
-2
-1
0
1
2
3
0
1
2
3
4
5
VOUT (V)
TIME (ns)
A0 PIN (V)
Output
A0 Pin
30127346
CMRR vs Frequency
1 10 100 1000
-80
-70
-60
-50
-40
-30
-20
-10
CMRR (dBc)
FREQUENCY (MHz)
Maximum Gain
16dB Attenuation
30127341
www.national.com 14
LMH6522
Input Impedance
0 100 200 300 400 500
-100
-50
0
50
100
150
200
250
300
INPUT IMPEDANCE (Ω)
FREQUENCY (MHz)
Z = R + jX
R
jX
|Z|
30127375
Output Impedance
0 100 200 300 400 500
-50
-25
0
25
50
75
100
125
150
OUTPUT IMPEDANCE (Ω)
FREQUENCY (MHz)
Z = R +jX
R
jX
|Z|
30127376
Power Sweep, High Power Mode
-30 -25 -20 -15 -10 -5 0
-4
0
4
8
12
16
20
OUTPUT POWER (dBm)
INPUT POWER (dBm)
100 MHz
200 MHz
300 MHz
30127385
Power Sweep, Low Power Mode
-30 -25 -20 -15 -10 -5 0
-4
0
4
8
12
16
20
OUTPUT POWER (dBm)
INPUT POWER (dBm)
100 MHz
200 MHz
300 MHz
30127386
15 www.national.com
LMH6522
Application Information
30127334
FIGURE 1. LMH6522 Typical Application
INTRODUCTION
The LMH6522 is a fully differential amplifier optimized for sig-
nal path applications up to 400 MHz. The LMH6522 has a
100Ω input and a low impedance output. The gain is digitally
controlled over a 31 dB range from +26dB to −5dB. The
LMH6522 is optimized for accurate gain steps and minimal
phase shift combined with low distortion products. This makes
the LMH6522 ideal for voltage amplification and an ideal ana-
log to digital converter (ADC) driver where high linearity is
necessary.
www.national.com 16
LMH6522
30127332
FIGURE 2. LMH6522 Block Diagram
17 www.national.com
LMH6522
BASIC CONNECTIONS
A voltage between 4.75 V and 5.25 V should be applied to the
supply pin labeled +5V. Each supply pin should be decoupled
with a low inductance, surface-mount ceramic capacitor of
0.01uF as close to the device as possible. Additional bypass
capacitors of 0.1uF and 1nF are optional, but would provide
bypassing over a wider frequency range.
The outputs of the LMH6522 need to be biased to ground
using inductors and output coupling capacitors of 0.01uF are
recommended. The input pins are self biased to 2.5V and
should be ac-coupled with 0.01uF capacitors as well. The
output bias inductors and ac-coupling capacitors are the main
limitations for operating at low frequencies. Larger values of
inductance on the bias inductors and larger values of capac-
itance on the coupling capacitors will give more low frequency
range. Using bias inductors over 1 uH, however, may com-
promise high frequency response due to unwanted parasitic
loading on the amplifier output pins.
Each channel of the LMH6522 consists of a digital step at-
tenuator followed by a low distortion 26 dB fixed gain amplifier
and a low impedance output stage. The attenuation is digitally
controlled over a 31 dB range from 0dB to 31dB. The
LMH6522 has a 100Ω differential input impedance and a low,
20Ω, output impedance.
Each channel of the LMH6522 has an enable pin. Grounding
the enable pin will put the channel in a power saving shutdown
mode. Additionally, there are two “on” states which gives the
option of two power modes. High Power Mode is selected by
biasing the enable pins at 2.0 V or higher. The LMH6522 en-
able pins will self bias to the Low Power State, alternatively
supplying a voltage between 0.6V and 1.8V will place the
channel in Low Power Mode. If connected to a TRI-STATE
buffer the LMH6522 enable pins will be in shutdown for a logic
0 output, in High Power Mode for a logic 1 state and they will
self bias to Low Power Mode for the high impedance state.
30127301
FIGURE 3. LMH6522 Basic Connections Schematic
INPUT CHARACTERISTICS
The LMH6522 input impedance is set by internal resistors to
a nominal 100Ω. Process variations will result in a range of
values. At higher frequencies parasitic reactances will start to
impact the impedance. This characteristic will also depend on
board layout and should be verified on the customer’s system
board.
At maximum gain the digital attenuator is set to 0 dB and the
input signal will be much smaller than the output. At minimum
gain the output is 5 dB or more smaller than the input. In this
configuration the input signal will begin to clip against the ESD
protection diodes before the output reaches maximum swing
limits. The input signal cannot swing more than 0.5V below
the negative supply voltage (normally 0V) nor should it ex-
ceed the positive supply voltage. The input signal will clip and
cause severe distortion if it is too large. Because the input
stage self biases to approximately mid rail the supply voltage
will impose the limit for input voltage swing.
At higher frequencies the LMH6522 input impedance is not
purely resistive. In Figure 4 a circuit is shown that matches
the amplifier input impedance with a source that is 100Ω. This
would be the case when connecting the LMH6522 directly to
a mixer. For an easy way to calculate the L and C circuit val-
ues there are several options for online tools or down-load-
able programs. The following tool might be helpful.
Excel can also be used for simple circuits; however, the “Anal-
ysis ToolPak” add-in must be installed to calculate complex
numbers.
http://www.circuitsage.com/matching/matcher2.html
www.national.com 18
LMH6522
30127369
FIGURE 4. Differential LC Conversion Circuit
OUTPUT CHARACTERISTICS
The LMH6522 has a low impedance output very similar to a
traditional Op-amp output. This means that a wild range of
loads can be driven with good performance. Matching load
impedance for proper termination of filters is as easy as in-
serting the proper value of resistor between the filter and the
amplifier. This flexibility makes system design and gain cal-
culations very easy.
By using a differential output stage the LMH6522 can achieve
very large voltage swings on a single 5V supply. This is illus-
trated in Figure 5. This figure shows how a voltage swing of
5VPPD is realized while only swinging 2.5 VPP on each output.
The LMH6522 can swing up to 10 VPPD which is sufficient to
drive most ADCs to full scale while using a matched
impedance anti alias filter between the amplifier and the ADC.
The LMH6522 has been designed for AC coupled applica-
tions and has been optimized for operation above 5 MHz.
30127362
FIGURE 5. Differential Output Voltage
Like most closed loop amplifiers the LMH6522 output stage
can be sensitive to capacitive loading. To help with board lay-
out and to help minimize sensitivity to bias inductor capaci-
tance the LMH5522 output lines have internal 10Ω resistors.
These resistors should be taken into account when choosing
matching resistor values. This is shown in as using 40.2 Ω
resistors instead of 50 Ω resistors to match the 100 Ω differ-
ential load. Best practise is to place the external termination
resistors as close to the DVGA output pins as possible. Due
to reactive components between the DVGA output and the
filter input it may be desirable to use even smaller value re-
sistors than a simple calculation would indicate. For instance,
at 200 MHz resistors of 30 Ohms provide slightly better OIP3
performance on the LMH6522EVAL evaluation board and
may also provide a better match to the filter input.
The LMH6522 output pins require a DC path to ground. On
the evaluation board, inductors are installed to provide proper
output biasing. The bias current is approximately 36mA per
output pin. The resistance of the output bias inductors will
raise the output common mode slightly. An inductor with low
resistance will keep the output bias voltage close to zero, so
the DC resistance of the inductor chosen will be important. It
is also important to make sure that the inductor can handle
the 36mA of bias current.
In addition to the DC current in the inductor there will be some
AC current as well. With large inductors and high operating
frequencies the inductor will present a very high impedance
and will have minimal AC current. If the inductor is chosen to
have a smaller value, or if the operating frequency is very low
there could be enough AC current flowing in the inductor to
become significant. The total current should not exceed the
inductor current rating.
Another reason to choose low resistance bias inductors is that
due to the nature of the LMH6522 output stage, the output
offset voltage is determined by the output bias components.
The output stage has an offset current that is typically 3mA
and this offset current, multiplied by the resistance of the out-
put bias inductors will determine the output offset voltage.
The ability of the LMH6522 to drive low impedance loads
while maintaining excellent OIP3 performance creates an op-
portunity to greatly increase power gain and drive low
impedance filters. Figure 6 shows the OIP3 performance of
the LMH6522 over a range of filter impedances. Also on the
same graph is the power gain realized by changing load
impedance. The power gain reflects the 6dB of loss caused
by the termination resistors necessary to match the amplifier
output impedance to the filter characteristic impedance. The
graphs shows the ability of the LMH6522 to drive a constant
voltage to an ADC input through various filter impedances
with very little change in OIP3 performance. This gives the
system designer much needed flexibility in filter design.
50 100 150 200 250 300
25
30
35
40
45
50
55
10
15
20
25
30
35
40
OIP3 (dBm)
FILTER INPUT RESISTANCE (Ω)
POWER GAIN (dB)
Power Gain @ Load
VOUT= 4VPPD
f = 200 MHz
OIP3 High Power Mode
OIP3 Low Power Mode
30127379
FIGURE 6. OIP3 and Power Gain vs Filter Impedance
19 www.national.com
LMH6522
OIP3 and Gain Measured at Amplifier Output, Filter Back
Terminated
Printed circuit board (PCB) design is critical to high frequency
performance. In order to ensure output stability the load
matching resistors should be placed as close to the amplifier
output pins as possible. This allows the matching resistors to
mask the board parasitics from the amplifier output circuit. An
example of this is shown in figure Figure 7. If the FIilter is a
bandpass filter with no DC path the 0.01µF coupling capaci-
tors can be eliminated. The LMH6522EVAL evaluation board
is available to serve a guide for system board layout.
30127368
FIGURE 7. Output Configuration
CASCADE OPERATION
30127383
FIGURE 8. Schematic for Cascaded Amplifiers
With four amplifiers in one package the LMH6522 is ideally
configured for cascaded operation. By using two amplifiers in
series additional gain range can be achieved. The schematic
in Figure 8 shows one way to connect two stages of the
LMH6522. The resultant frequency response is shown below
in Figure 9. When using the LMH6522 amplifiers in a cascade
configuration it is important to keep the signal level within
reasonable limits at all nodes of the signal path. With over
40dB of total gain it is possible to amplify signals to clipping
levels if the gain is not set correctly.
1 10 100 1000
-20
-10
0
10
20
30
40
50
GAIN @ LOAD (dB)
FREQUENCY (MHz)
30127384
FIGURE 9. Frequency Response of Cascaded Amplifiers
www.national.com 20
LMH6522
DIGITAL CONTROL
The LMH6522 will support two modes of control, parallel
mode and serial mode (SPI compatible). Parallel mode is
fastest and requires the most board space for logic line rout-
ing. Serial mode is compatible with existing SPI compatible
systems.
The LMH6522 has gain settings covering a range of 31 dB.
To avoid undesirable signal transients the LMH6522 should
not be powered on with large inputs signals present. Careful
planning of system power on sequencing is especially impor-
tant to avoid damage to ADC inputs.
The LMH6522 was designed to interface with 2.5V to 5V
CMOS logic circuits. If operation with 5V logic is required care
should be taken to avoid signal transients exceeding the DV-
GA supply voltage. Long, unterminated digital signal traces
are particularly susceptible to these transients. Signal volt-
ages on the logic pins that exceed the device power supply
voltage may trigger ESD protection circuits and cause unre-
liable operation.
Some pins on the LMH6522 have different functions depend-
ing on the digital control mode. These functions will be de-
scribed in the sections to follow.
Pins with Dual Functions
Pin MODE = 0 MODE = 1
45 A4 SDO*
46 A3 SDI
47 A2 CSb
48 A1 CLK
Pin 45 requires external bias. See Serial Mode Section for Details.
PARALLEL INTERFACE
Parallel mode offers the fastest gain update capability with the
drawback of requiring the most board space dedicated to
control lines. When designing a system that requires very fast
gain changes parallel mode is the best selection. To place the
LMH6522 into parallel mode the MODE pin (pin 5) is set to
the logical zero state. Alternately the MODE pin can be con-
nected directly to ground.
The attenuator control pins are internally biased to logic high
state with weak pull up resistors. The MODE pin has a weak
internal resistor to ground. The enable pins bias to a mid logic
state which is the Low Power Mode.
The LMH6522 has a 5-bit gain control bus. Data from the gain
control pins is immediately sent to the gain circuit (i.e. gain is
changed immediately). To minimize gain change glitches all
gain pins should change at the same time. In order to achieve
the very fast gain step switching time the internal gain change
circuit is very fast. Gain glitches could result from timing skew
between the gain set bits. This is especially the case when a
small gain change requires a change in state of three or more
gain control pins. If necessary the DVGA could be put into a
disabled state while the gain pins are reconfigured and then
brought active when they have settled.
ENA and ENB pins are provided to reduce power consump-
tion by disabling the highest power portions of the LMH6522.
The gain register will preserve the last active gain setting dur-
ing the disabled state. These pins will float high and can be
left disconnected if they won't be used. If the pins are left dis-
connected a 0.01uF capacitor to ground will help prevent
external noise from coupling into these pins. See the Typical
Performance section for disable and enable timing informa-
tion.
30127317
FIGURE 10. Parallel Mode Connection
SPI COMPATIBLE SERIAL INTERFACE
Serial interface allows a great deal of flexibility in gain pro-
gramming and reduced board complexity. Using only 4 wires
for both channels allows for significant board space savings.
The trade off for this reduced board complexity is slower re-
sponse time in gain state changes. For systems where gain
is changed only infrequently or where only slow gain changes
are required serial mode is the best choice. To place the
LMH6522 into serial mode the MODE pin (Pin 5) should be
put into the logic high state. Alternatively the MODE pin an be
connected directly to the 5V supply bus.
The LMH6522 serial interface is a generic 4-wire syn-
chronous interface that is compatible with SPI type interfaces
that are used on many microcontrollers and DSP controllers.
The serial mode is active when the mode pin is set to a logic
1 state. In this configuration the pins function as shown in the
pin description table. The SPI interface uses the following
signals: clock input (CLK), serial data in (SDI), serial data out,
and serial chip select (CSb). The chip select pin is active low.
The enable pins are inactive in the serial mode. These pins
can be left disconnected for serial mode.
The CLK pin is the serial clock pin. It is used to register the
input data that is presented on the SDI pin on the rising edge;
and to source the output data on the SDO pin on the falling
edge. User may disable clock and hold it in the low state, as
long as the clock pulse-width minimum specification is not vi-
olated when the clock is enabled or disabled.
The CSb pin is the chip select pin. The b indicates that this
pin is actually a “NOT chip select” since the chip is selected
in the logic low state. Each assertion starts a new register
access - i.e., the SDATA field protocol is required. The user
is required to deassert this signal after the 16th clock. If the
CSb pin is deasserted before the 16th clock, no address or
data write will occur. The rising edge captures the address
just shifted-in and, in the case of a write operation, writes the
addressed register. There is a minimum pulse-width require-
ment for the deasserted pulse - which is specified in the
Electrical Specifications section.
The SDI pin is the input pin for the serial data. It must observe
setup / hold requirements with respect to the SCLK. Each cy-
cle is 16-bits long
The SDO pin is the data output pin. This output is normally at
a high impedance state, and is driven only when CSb is as-
serted. Upon CSb assertion, contents of the register ad-
dressed during the first byte are shifted out with the second 8
SCLK falling edges. Upon power-up, the default register ad-
dress is 00h. The SDO pin requires external bias for clock
speeds over 1MHz. See Figure 12 for details on sizing the
external bias resistor. Because the SDO pin is a high
impedance pin, the board capacitance present at the pin will
21 www.national.com
LMH6522
restrict data out speed that can be achieved. For a RC limited
circuit the frequency is ~ 1/ (2*Pi*RC). As shown in the figure
resistor values of 300 to 2000 Ohms are recommended.
Each serial interface access cycle is exactly 16 bits long as
shown in Figure 11. Each signal's function is described below.
the read timing is shown in Figure 13, while the write timing
is shown in figure Figure 14.
30127312
FIGURE 11. Serial Interface Protocol (SPI compatible)
30127314
FIGURE 12. Internal Operation of the SDO pin
www.national.com 22
LMH6522
R/Wb Read / Write bit. A value of 1 indicates a read
operation, while a value of 0 indicates a write
operation.
Reserved Not used. Must be set to 0.
ADDR: Address of register to be read or written.
DATA In a write operation the value of this field will be
written to the addressed register when the chip
select pin is deasserted. In a read operation this
field is ignored.
30127311
FIGURE 13. Read Timing
Read Timing
Data Output on SDO Pin
Parameter Description
tCSH Chip select hold time
tCSS Chip select setup time
tOZD Initial output data delay
tODZ High impedance delay
tOD Output data delay
30127310
FIGURE 14. Write Timing
Data Written to SDI Pin
23 www.national.com
LMH6522
Write Timing
Data Input on SDI Pin
Parameter Description
tPL Minimum clock low time (clock duty dycle)
tPH Minimum clock high time (clock duty cycle)
tSU Input data setup time
tHInput data hold time
Serial Word Format for LMH6522
C7 C6 C5 C4 C3 C2 C1 C0
1= read
0=write
0 0 0 0 000= CHA
001=CHB
010=CHC
011=CHD
100=Fast Adjust
CH A through D Register Definition
7 6 5 4 3 2 1 0
Reserved,
=0
Power
Level: 0=
Low
1=High
Enable: 0
= OFF
1= ON
Attenuation Setting:
00000 = Maximum
Gain
11111 = Minimum Gain
Fast Adjust Register Definition
7 6 5 4 3 2 1 0
CH D CH C CH B CH A
Fast Adjust Codes
Code Action
00 No Change
01 Decrease Attenuation by 1 Step (1dB)
10 Increase Attenuation by 1 Step (1dB)
11 Reserved, action undefined
SPISU2 SPI CONTROL BOARD AND TINYI2CSPI
SOFTWARE
Also available separately from the LMH6522EVAL evaluation
board is a USB to SPI control board and supporting software.
The SPISU2 board will connect directly to the LMH6522 eval-
uation board and provides a simple way to test and evaluate
the SPI interface. For more details refer to the LMH6522EVAL
user's guide. The evaluation board user's guide provides in-
structions on connecting the SPISU2 board and for configur-
ing the TinyI2CSPI software.
THERMAL MANAGEMENT
The LMH6522 is packaged in a thermally enhanced package.
The exposed pad is connected to the GND pins. It is recom-
mended, but not necessary, that the exposed pad be con-
nected to the supply ground plane. In any case, the thermal
dissipation of the device is largely dependent on the attach-
ment of this pad to the system printed circuit board (PCB).
The exposed pad should be attached to as much copper on
the PCB as possible, preferably external copper. However, it
is also very important to maintain good high speed layout
practices when designing a system board. Please refer to the
LMH6522 evaluation board for suggested layout techniques.
The LMH6522EVAL evaluation board was designed for both
signal integrity and thermal dissipation. The LMH6522EVAL
has eight layers of copper. The inner copper layers are two
ounce copper and are as solid as design constraints allow.
The exterior copper layers are one ounce copper in order to
allow fine geometry etching. The benefit of this board design
is significant. The JEDEC standard 4 layer test board gives a
θJA of 23°C/W. The LMH6522EVAL eight layer board gives a
measured θJA of 15°C/W (ambient temperature 25°C, no
forced air). With the typical power dissipation of 2.3W this is
a temperature difference of 18 degrees in junction tempera-
ture between the standard 4 layer board and the enhanced 8
layer evaluation board. In a system design the location and
power dissipation of other heat sources may change the re-
sults observed compared with the LMH6522EVAL board.
Applying a heat sink to the package will also help to remove
heat from the device. The ATS-54150K-C2–R0 heat sink,
manufactured by Advanced Thermal Solutions, provided
good results in lab testing. Using both a heat sink and a good
board thermal design will provide the best cooling results. If
a heat sink will not fit in the system design, the external case
can be used as a heat sink.
Package information is available on the National web site.
http://www.national.com/packaging/folders/sqa54a.html
INTERFACING TO AN ADC
The LMH6522 was designed to be used with high speed
ADCs such as the ADC16DV160. As shown in the Typical
Application on page 1, AC coupling provides the best flexibility
especially for IF sub-sampling applications.
The inputs of the LMH6522 will self bias to the optimum volt-
age for normal operation. The internal bias voltage for the
inputs is approximately mid rail which is 2.5V with the typical
5V power supply condition. In most applications the LMH6522
input will need to be AC coupled.
The output pins require a DC path to ground that will carry the
~36 mA of bias current required to power the output transis-
tors. The output common mode voltage should be established
very near to ground. This means that using RF chokes or RF
inductors is the easiest way to bias the LMH6522 output pins.
Inductor values of 1μH to 400nH are recommended. High Q
inductors will provide the best performance. If low frequency
operation is desired, particular care must be given to the in-
ductor selection because inductors that offer good perfor-
mance at very low frequencies often have very low self
resonant frequencies. If very broadband operation is desired
the use of conical inductors such as the BCL–802JL from
Coilcraft may be considered. These inductors offer very
broadband response, at the expense of large physical size
and a high DC resistance of 3.4 Ohms.
ADC Noise Filter
Below are schematics and a table of values for second order
Butterworth response filters for some common IF frequen-
cies. These filters, shown in Figure 15, offer a good compro-
mise between bandwidth, noise rejection and cost. This filter
topology is the same as is used on the ADC14V155KDRB
High IF Receiver reference design board. This filter topology
works best with the 12, 14 and 16 bit analog to digital con-
verters shown in the table.
Filter Component Values
Center Frequency 75 MHz 150 MHz 180 MHz 250 MHz
Bandwidth 40 MHz 60 MHz 75 MHz 100 MHz
R1, R2 90Ω 90Ω 90Ω 90Ω
L1, L2 390 nH 370 nH 300 nH 225 nH
C1, C2 10 pF 3 pF 2.7 pF 1.9 pF
www.national.com 24
LMH6522
C3 22 pF 19 pF 15 pF 11 pF L5 220 nH 62 nH 54 nH 36 nH
R3, R4 100Ω 100Ω 100Ω 100Ω
Resistor values are approximate, but have been reduced due to the internal
10 Ohms of output resistance per pin.
30127313
FIGURE 15. Sample Filter
POWER SUPPLIES
The LMH6522 was designed primarily to be operated on 5V
power supplies. The voltage range for V+ is 4.75V to 5.25V.
Power supply accuracy of 2.5% or better is advised. When
operated on a board with high speed digital signals it is im-
portant to provide isolation between digital signal noise and
the LMH6522 inputs. The SP16160CH1RB reference board
provides an example of good board layout.
DYNAMIC POWER MANAGEMENT, USING LOW POWER
MODE
The LMH6522 offers the option of a reduced power mode of
operation referred to as Low Power Mode. In this mode of
operation power consumption is reduced by approximately
20%. In many applications the linearity of the LMH6522 is fully
adequate for most signal conditions. This would apply for a
radio in a noise limited environment with no close-in blocker
signals. During these conditions the LMH6522 can be oper-
ated in the low power mode. When a blocking signal is de-
tected, or when system dynamic range needs to be increased,
the LMH6522 can be rapidly switched from the Low Power
Mode to the standard, High Power Mode.
The output response shown in Figure 16 is for a 2 MHz
switching frequency pulse applied to the enable pin with a 50
MHz input signal. Analysis with a spectrum analyzer showed
that the power mode switching spurs created by the switching
signal were −80dBc with respect to the 50 MHz tone signal.
This shows that rapid switching of power modes has virtually
no impact on the signal quality.
0.0 0.1 0.2 0.3 0.4 0.5
-3
-2
-1
0
1
2
0
1
2
3
4
5
VOUT (V)
TIME (μS)
ENABLE (V)
High Power Mode Low Power Mode
Enable
VOUT
30127367
FIGURE 16. Signal Output During Mode Change
from High Power Mode to Low Power Mode
25 www.national.com
LMH6522
COMPATIBLE HIGH SPEED ANALOG TO DIGITAL CONVERTERS
Product Number Max Sampling Rate (MSPS) Resolution Channels
ADC12L063 62 12 SINGLE
ADC12DL065 65 12 DUAL
ADC12L066 66 12 SINGLE
ADC12DL066 66 12 DUAL
CLC5957 70 12 SINGLE
ADC12L080 80 12 SINGLE
ADC12DL080 80 12 DUAL
ADC12C080 80 12 SINGLE
ADC12C105 105 12 SINGLE
ADC12C170 170 12 SINGLE
ADC12V170 170 12 SINGLE
ADC14C080 80 14 SINGLE
ADC14C105 105 14 SINGLE
ADC14DS105 105 14 DUAL
ADC14155 155 14 SINGLE
ADC14V155 155 14 SINGLE
ADC16V130 130 16 SINGLE
ADC16DV160 160 16 DUAL
ADC08D500 500 8 DUAL
ADC08500 500 8 SINGLE
ADC08D1000 1000 8 DUAL
ADC081000 1000 8 SINGLE
ADC08D1500 1500 8 DUAL
ADC081500 1500 8 SINGLE
ADC08(B)3000 3000 8 SINGLE
ADC08L060 60 8 SINGLE
ADC08060 60 8 SINGLE
ADC10DL065 65 10 DUAL
ADC10065 65 10 SINGLE
ADC10080 80 10 SINGLE
ADC08100 100 8 SINGLE
ADCS9888 170 8 SINGLE
ADC08(B)200 200 8 SINGLE
ADC11C125 125 11 SINGLE
ADC11C170 170 11 SINGLE
www.national.com 26
LMH6522
Physical Dimensions inches (millimeters) unless otherwise noted
54-Pin Package
NS Package Number SQA54A
27 www.national.com
LMH6522
Notes
LMH6522 High Performance Quad DVGA
For more National Semiconductor product information and proven design tools, visit the following Web sites at:
www.national.com
Products Design Support
Amplifiers www.national.com/amplifiers WEBENCH® Tools www.national.com/webench
Audio www.national.com/audio App Notes www.national.com/appnotes
Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns
Data Converters www.national.com/adc Samples www.national.com/samples
Interface www.national.com/interface Eval Boards www.national.com/evalboards
LVDS www.national.com/lvds Packaging www.national.com/packaging
Power Management www.national.com/power Green Compliance www.national.com/quality/green
Switching Regulators www.national.com/switchers Distributors www.national.com/contacts
LDOs www.national.com/ldo Quality and Reliability www.national.com/quality
LED Lighting www.national.com/led Feedback/Support www.national.com/feedback
Voltage References www.national.com/vref Design Made Easy www.national.com/easy
PowerWise® Solutions www.national.com/powerwise Applications & Markets www.national.com/solutions
Serial Digital Interface (SDI) www.national.com/sdi Mil/Aero www.national.com/milaero
Temperature Sensors www.national.com/tempsensors SolarMagic™ www.national.com/solarmagic
PLL/VCO www.national.com/wireless PowerWise® Design
University
www.national.com/training
THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION
(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY
OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO
SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,
IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS
DOCUMENT.
TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT
NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL
PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR
APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND
APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE
NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.
EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO
LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE
AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR
PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY
RIGHT.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and
whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected
to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform
can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other
brand or product names may be trademarks or registered trademarks of their respective holders.
Copyright© 2011 National Semiconductor Corporation
For the most current product information visit us at www.national.com
National Semiconductor
Americas Technical
Support Center
Email: support@nsc.com
Tel: 1-800-272-9959
National Semiconductor Europe
Technical Support Center
Email: europe.support@nsc.com
National Semiconductor Asia
Pacific Technical Support Center
Email: ap.support@nsc.com
National Semiconductor Japan
Technical Support Center
Email: jpn.feedback@nsc.com
www.national.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are
sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard
warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where
mandated by government requirements, testing of all parameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and
applications using TI components. To minimize the risks associated with customer products and applications, customers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,
or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information
published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a
warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual
property of the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied
by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive
business practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional
restrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all
express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not
responsible or liable for any such statements.
TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonably
be expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governing
such use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, and
acknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their products
and any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may be
provided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in
such safety-critical applications.
TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are
specifically designated by TI as military-grade or "enhanced plastic."Only products designated by TI as military-grade meet military
specifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at
the Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.
TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are
designated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designated
products in automotive applications, TI will not be responsible for any failure to meet such requirements.
Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products Applications
Audio www.ti.com/audio Communications and Telecom www.ti.com/communications
Amplifiers amplifier.ti.com Computers and Peripherals www.ti.com/computers
Data Converters dataconverter.ti.com Consumer Electronics www.ti.com/consumer-apps
DLP®Products www.dlp.com Energy and Lighting www.ti.com/energy
DSP dsp.ti.com Industrial www.ti.com/industrial
Clocks and Timers www.ti.com/clocks Medical www.ti.com/medical
Interface interface.ti.com Security www.ti.com/security
Logic logic.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt power.ti.com Transportation and Automotive www.ti.com/automotive
Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video
RFID www.ti-rfid.com
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community Home Page e2e.ti.com
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright ©2011, Texas Instruments Incorporated
