1 of 15
GENERAL DESCRIPTION
The DS1672 incorporates a 32-bit counter and
power-monitoring functions. The 32-bit counter
is designed to count seconds and can be used to
derive time-of-day, week, month, month, and
year by using a software algorithm. A prec is io n,
temperature-compensated reference and
comparator circuit monitors the status of VCC.
When an out-of-tolerance condition occurs, an
int e r nal po w er -fail sig nal is g enerat ed that fo rces
the reset to the active st ate. When VCC returns to
an in-tolerance condit io n, the reset signal is kept
in the active state for a period of time to allow
t he power supply a nd pro cessor to st abiliz e.
FEATURES
32-Bit Counter
I2C Ser ial Int erface
Automat ic Power -Fa il Det ect and Switch
Circuitry
Power-Fail R eset O utp ut
Low-Vo ltage Osc i llator Op er ation
( 1.3V min)
Trickle-Charge Capability
Underwriter s La bo r at or ies (U L) Recogn ized
-40°C to +85°C Operating Range
PIN CONFIGURATION
.
TYPICAL OPERATING CIRCUIT
PDIP
SO
µ
SOP
TOP VIE W
1
2
3
4
8
7
6
5
V
CC
RST
SCL
SDA
X1
X2
VBACKUP
GND
DS1672
DS1672
I
2
C 32-Bit Binary Counter RTC
19-6032; Rev 9/11
DS1672
2 of 15
ORDERING INFORMATION
PART T E MP RANGE VOLT AGE (V) PIN-PACKAGE TO P MARK*
DS1672-2+ -40°C to +85°C 2.0 8 PDIP (300 mils) DS1672-2
DS1672-3+ -40°C to +85°C 3.0 8 PDIP (300 mils) DS1672-3
DS1672-33+ -40°C to +85°C 3.3 8 PDIP (300 mils) DS1672-33
DS1672S-2+ -40°C to +85°C 2.0 8 SO (150 mils) D1672-2
DS1672S-3+ -40°C to +85°C 3.0 8 SO (150 mils) D1672-3
DS1672S-33+ -40°C to +85°C 3.3 8 SO (150 mils) D167233
DS1672S-3+T&R -40°C to +85°C 3.0
8 SO (150 mils)/Ta pe
and Reel
D1672-3
DS1672S-33+T&R -40°C to +85°C 3.3
8 SO (150 mils)/Ta pe
and Reel
D167233
DS1672U-2+ -40°C to +85°C 2.0 8 µSOP(3mm)
1672
rr -2
DS1672U-3+ -40°C to +85°C 3.0 8 µSOP(3mm)
1672
rr -3
DS1672U-33+ -40°C to +85°C 3.3 8 µSOP(3mm)
1672
rr -33
DS1672U-33+T&R -40°C to +85°C 3.3
8 µSOP(3mm)/Tape
and Reel
1672
rr -33
+ De no tes a lead-free/RoHS-compliant device.
* A “+” a ny wh er e on the t o p mark de not es a lea d-free device. rr = 2-digit alphanumeri c revision code.
DS1672
3 of 15
ABSOLUTE MAXIMUM RATINGS
Vo ltage Range o n An y Pin Relative to Gro und……………………………………………..-0.5V to +6.0V
Operating Temperat ure Range (no ncondensing) ...…………………………………………-40°C to +85°C
Storage Temperat ur e Range……………………… ………………………………………. -55°C to +125°C
So ldering Temperatur e (reflow)………………………………………….…………………. +260°C
Lead Temperat ure ( solder ing, 10s) ……………………………………………………………….. +260°C
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification i s not i mplied. Exposure to absolute maximum rating conditions for extended periods of time can affect device
reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = -40°C to +85°C) (Note 1)
PARAMETER SYMBOL MIN TYP MAX UNITS
Supply
Voltage
DS1672-2
VCC
1.8
2.0
5.5
V
DS1672-3
VCC
2.7
3.0
5.5
DS1672-33
VCC
2.97
3.3
5.5
Logic 1
VIH
0.7 x VCC
VCC + 0.5
V
Logic 0
VIL
-0.5
+0.3 x VCC
V
Backup Supply Voltage
VBACKUP
1.3
3.0
3.63
V
Note 1: All voltages referenced to ground.
DC ELECTRICAL CHARACTERISTICS
(VCCMIN < VCC < VCCMAX, TA = -40°C to +85°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Act ive Supply Current
( No te 2)
I
CCA
-2: VCC = 2. 2V
600
µA
-3: VCC = 3. 3V
-33: VCC = 3.63V
S ta ndby Current
( No te 3)
I
CCS
-2: VCC = 2. 2V
500
µA
-3: VCC = 3. 3V
-33: VCC = 3.63V
Power-Fail V oltage
V
PF
-2:
2.70
2.88
2.97
V
-3:
2.45
2.60
2.70
-33:
1.58
1.70
1.80
VBACKUP Leakage Curren t
IBACKUPLKG
25
50
nA
Logic 0 Output (Note 4)
IOL
VOL = 0.4V
3
mA
Logic 0 Output (Note 4,
DS1672-2 Only)
I
OL
VCC > 2V; VOL = 0.4V
3
mA
V
CC
< 2V; V
OL
= V
CC
* 0.2
Note 1: All voltages referenced to ground.
Note 2: ICCA specified with SCL clocking at max frequency ( 400kHz), trickle charger disabled.
Note 3: ICCS specified with VCC = V CCTYP and SDA, SCL = VCCTYP, t rickle charger disabled.
Note 4: SDA and RST.
DS1672
4 of 15
DC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C.) ( Note 5)
PARAMETER SYMBOL MIN TYP MAX UNITS
VBACKUP Current (O scillat or On)
IBACKUPOSC
0.425
1
µA
VBACKUP C urrent (Osc illa t or O ff)
IBACKUP
200
nA
Note 5: Using the recommended crystal on X1 and X2.
CRYSTAL SPECIFICATIONS*
PARAMETER SYMBOL MIN TYP MAX UNITS
Nomina l Freque ncy
fO
32.768
kHz
Series Resist ance
ESR
45
kΩ
Load Capacitance
CL
6
pF
*The crystal, traces, and crystal input pins should be isolated from RF generating signals. Refer to Application Note 58: Crystal
Con siderations for D al las Re al-Ti m e C locks for additional specifications
DS1672
5 of 15
AC ELECTRICAL CHARACTERISTICS
(VCC = 0V, TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock
Frequency fSCL Fa st mode 100 400 kHz
S ta ndard mode 100
Bus Free Ti m e
B etwee n a STOP a nd
START Condi tion
tBUF F a st mode 1.3 µs
S ta ndard mode 4.7
Ho ld Time
( Repeated ) START
Condition (Note 6)
tHD:STA Fa st mode 0.6 µs
S ta ndard mode 4.0
LOW Period of SC L
Clock tLOW
Fast mode
1.3
µs
S ta ndard mode 4.7
HIGH Period of SCL
Clock tHIGH F a st mode 0.6 µs
S ta ndard mode 4.0
Setup Time for a
Repeated START
Condition
tSU:STA F a st mode 0.6 µs
S ta ndard mode 4.7
Dat a H old Tim e
( No tes 7 , 8) tHD:DAT Fa st mode 0 0.9 µs
S ta ndard mode 0
Data Setup Time
( No te 9) tSU:DAT F a st mode 100 ns
S ta ndard mode 250
R is e Time of Both
S DA and SC L
Signals (N ote 10)
tR Fast mode 20 + 0.1CB 300 ns
S ta ndard mode 1000
F all Time of Both
S DA and SC L
Signals (N ote 10)
tF Fast mode 20 + 0.1CB 300 ns
S ta ndard mode 300
Setu p Tim e for S TOP
Condition tSU:STO F a st mode 0.6
µs
S ta ndard mode 4.0
C apa citive L oad for
Each Bus Line
(Not e 10)
CB 400 pF
I/O Capacitance CI/O 10 pF
Note 6: After this period, the first clock pulse is generated.
Not e 7: A device must internally provide a hold time of at least 300ns for the SDA signal (referenced to the VIHMIN of the SCL signal) in
or der to brid ge t he undef ine d region of the f allin g e dge of SC L.
Note 8: The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SC L signal .
Note 9: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥ to 250ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW
period of the SCL signal, it must output the next data bit to the SDA line tR ma x + t SU:DAT = 1000 + 250 = 1250ns before the SCL
line is rel eased .
Note 10: CB–Total capacitance of one bus line in pF.
DS1672
6 of 15
POWER-UP/POWER-DOWN CHARACTERISTICS
(TA = -40°C to +85°C)
PARAMETER SYMBOL MIN TYP MAX UNITS
VCC Detec t t o RST (VCC Falling) tRPD 10 µs
V
CC
Detect to RST (V
CC
Rising)
(Not e 11)
tRPU 250 ms
VCC Fall Ti me; VPF(MAX) t o VPF(MIN) tF 300 µs
VCC R ise Time; VPF(MIN) to V PF(MAX) tR 0 µs
Note 11: If the EOSC bit in the control register is set to logic 1, tRPU is equal to 250ms plus the startup time of the crystal oscillator.
Warning: Negative undershoots below –0.3V while the part is in battery-backed mode can cause
loss of data.
Fig ur e 1. Ti m i ng Dia gr am
SCL
START
SDA
STOP
t
BUF
REPEATED
START
t
HD:STA
t
LOW
t
HD:STA
t
HD:DAT
t
SU:DAT
t
HIGH
t
SU:STA
t
F
t
SU:STO
Figure 2. Power-Up/Power-Down Ti ming
OUTPUTS
V
CC
VPF(max)
INPUTS
HIGH I MPEDANCE
RST
DON'T CARE
VALID
RECOGNIZED
RECOGNIZED
VALID
t
RPD
VPF(min)
tF
tPD
tR
tRPU
DS1672
7 of 15
PIN DESCRIPTION
PIN NAME FUNCTION
1, 2 X1, X2
Connectio ns for Standard 32.768kHz Quartz Crystal. T he int er nal o sci llator
circu itry is desig ned for oper ation wit h a crystal having a specified load
capac ita nce (CL) of 6pF. For more informat ion about cryst al se lectio n and
cryst al layout co nsiderations, refer t o A pplication Note 58: Crystal
Consideration s with Dallas Real-Time Clo cks. T he DS1672 can also be dr iven
by a n external 32.768kHz oscillator. I n t his co nfigur atio n, the X1 pin is
connected t o t he exte rnal o scil la tor s ignal and the X2 pin is left u ncon nect ed
.
3 VBACKUP
Batt er y Input fo r An y Standard 3V Lithiu m Cel l or Ot her Energy Sour ce.
Batt ery volt age mu st be he ld bet wee n 1.3V and 3.63V for pro per operatio n.
D iodes placed in series bet ween t he po wer sou r ce and the VBACKUP p in ma y
result in impro per oper atio n. If a backup supp ly is not r equired, VBACKUP must
be grounded. UL reco gnized t o ensure against r everse charg ing cur r ent whe n
used in conju nction with a lithium bat tery (charger disabled). See “Cond it io ns
o f Accep tab il it y” at www.maxim-ic.com/qa/info/ul.
4 GND Ground.
5 SDA
Serial-Data Input/O utput. SDA is the input/ outp ut pin for the I2C serial
int erfa ce. The SDA pin is open dra in and requires an ext er nal pullup r es ist or.
6 SCL
I2C Serial-Clo ck Input. S CL is used to synchronize data movement on the
ser ial interfac e and requires an ext er nal pullup r es i stor.
7 RST
Active-Low Reset Output. It functio ns as a micro processo r reset sig na l. T his
pin is an open-dra in o utput and requires an ext er nal pu llup resisto r.
8 VCC
Power p in for Primary Powe r Supp ly. W hen V
CC
is a pplied within nor mal
limits, the device is full y access ib le and dat a can b e wr itten and read. Whe n
VCC is below V PF, r eads and writes are inhibited.
Figure 3. Recommended Layout for Crystal
LOCAL GROUND PLANE (LAYER 2)
CRYSTAL
X1
X2
GND
DS1672
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Detailed Description
The DS1672 provides a 32-bit counter that increments once-per-second. The counter data is accessible
via an I2C serial interface. A precision, temperature-compensated, voltage reference and comparator
circu it mo nit ors VCC. When VCC drops below VPF, RST becomes active and the interface is disabled to
prevent data corruption. The device switches to the backup supply input, which maintains oscillator and
counter o perat ion w hile VCC is a b se nt. When VCC r ises above VPF, RST remains low for a period of time
(tRPU) to allow VCC to stabilize.
The block diagram in Figure 4 shows the main elements of the DS1672. As shown, communications to
and from t he DS1672 o ccur ser ia lly over a I2C, b id irect ional bus. T he DS16 72 o perat es as a s lave devic e
on the I2C bus. Access is obtained by implementing a START condition and providing a device
ident ific at io n code fo llowed b y a r egist er addr ess. Su bsequ e nt reg ister s can be accessed seque nt ia lly unt i l
a ST OP co nditio n is executed.
Figure 4. Block Diagram
Oscillator Circuit
The DS1672 uses an e xternal 32. 768kH z crystal. The osc illat or circuit does not req uire any exter nal
res ist or s or capacitor s to op er ate. Table 1 specifies several cryst al par ameters for t he externa l crystal.
Figure 4 show s a functiona l schematic o f the oscillator circuit. I f using a crystal with t he speci f ied
charact eristics, the startup time is usuall y less t han o ne second.
Table 1. Crystal Specifications*
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Nomi nal Frequenc y
FO
32.768
kHz
Series Resistance
ESR
45
kΩ
Load Capaci tance
CL
6
pF
* The crystal , traces, and crystal input pin s should be isolated from RF generating signals. Refer t o Application Note 58:
Cloc k Acc ur acy
The accuracy of the clock is dependent upon the accuracy of the crystal and the accuracy of the match
between the capacitive load of the oscillator circuit and the capacitive load for which the crystal was
32-Bit Counter
(4 Bytes)
I
2
C Interface
Power Control
Address Regi ster
Control Logic
1Hz
V
CC
V
BACKUP
GND
SCL
SDA
Control
Trick l e Charger
X1 X2
RST
Dallas
Semiconductor
DS1672
C
L
C
L
N
Oscillator
and
divider
DS1672
9 of 15
trimmed. Addit io nal erro r will be added by cryst al freque ncy drift caused by te mp erat ure shifts. E xterna l
circuit noise coupled into the oscillator circuit may result in the clock running fast. Refer to Application
Note 5: “Crystal Considerations with Dallas Real-Ti me Clo cks” for de tailed informa tio n.
Address Map
The counter is accessed by reading or writing the first 4 bytes of the DS1672 (00h–03h). The control
reg ist er a nd tr ick le char ger ar e acces sed by r ead ing o r wr it ing th e appro priat e reg ist er bytes as illu st rat ed
in Ta ble 2. I f t he master co nt inu es t o send o r request mo re dat a aft er the address point er has reached 05h,
t he address pointer will wrap ar ou nd to locatio n 00h.
Table 2. Registers
ADDRESS
B7
B6
B5
B4
B3
B2
B1
B0
FUNCTION
00h
LSB
C ounter Byte 1
01h
C ounter Byte 2
02h
C ounter Byte 3
03h
MSB
C ounter Byte 4
04h
EOSC
Control
05h
TCS
TCS
TCS
TCS
DS
DS
RS
RS
T ri ckle Ch arg er
Power Control
The device is fully accessible and data can be written and ready only when VCC is greater than VPF.
Ho wever , whe n VCC falls below VPF, (po int at which wr it e prot ectio n occurs) the internal clo ck registers
are blocked from any access. If VPF is less than VBACKUP, the device power is switched from VCC to
VBACKUP whe n VCC drops below VPF. I f VPF is greater than VBACKUP, the device power is switched from
VCC to VBACKUP when VCC drops below VBACKUP. Oscillator and counter operation are maintained fro m
the V BACKUP source u ntil V CC is returned to nominal levels (s ee Table 3).
Table 3. Power Control
SUPPLY CONDITION
READ/WRITE
ACCESS
RST
POWERED BY
VCC < VPF, VCC < VBACKUP
No
Active
VBACKUP
VCC < VPF, VCC > VBACKUP
No
Active
VCC
VCC > VPF, VCC < VBACKUP
Yes
Inactive
VCC
VCC > VPF, VCC > VBACKUP
Yes
Inactive
VCC
Oscillator Control
The EOSC b it ( bit 7 o f the control register) contro ls t he o scillato r when in back-up mode. This bit when
set to logic 0 will start the oscillator. When this bit is set to a logic 1, the oscillator is stopped and the
DS1672 is p laced into a low-po wer st andby mo de ( IBACKUP) w hen in b ack-up mo de. Whe n t he DS1672 is
power ed by VCC, the oscil lat o r is alwa ys on regar dl ess of t he statu s of the EOSC b it; ho w eve r, the counter
is incremented only when EOSC is a logic 0.
Microprocessor Monitor
A temperature-compensated comparator circuit monitors the level of VCC. Whe n VCC falls to the power-
fail trip point, the RST signal (open drain) is pulled active, and read/write access is inhibited. When VCC
r et ur ns to nomin a l leve ls, th e RST s ignal is k ept in the active st at e fo r t RPU (typically) to allow the power
supply a nd microprocessor to stabilize. Not e, however, t hat if the EOSC bit is set to a logic 1 (to disable
the oscillator during write protection), the reset signal will be kept in an active state for tRPU plus the
st art u p t ime of the o scillator.
DS1672
10 of 15
Trickle Charger
The trickle charger is controlled by the trickle charge register. The simplified schematic of Figure 5
sho ws t he bas ic co mponent s of t he tr ick le char ger. The t r ick le c har ge se lect ( TCS) bit (bit s 4 –7) cont rols
the selection of the trickle charger. In order to prevent accidental enabling, only a pattern on 1010 will
enable the t r ick le charger. All ot her patt erns will d isable the trick le c harger. The DS1672 po wers up with
the trickle charger disabled. The diode select (DS) bits (bits 2, 3) select whether or not a diode is
co nnect ed bet ween VCC a nd VBACKUP. I f DS is 01, no d iode is se lect ed or if DS is 10, a d iode is select ed.
The RS bits (bit s 0, 1) select whet her a r es ist or is co nnected bet ween VCC and VBACKUP and what the valu e
of t he resisto r is. The resistor selected by the resistor select (RS) bits and the diode selected by the diod e
select ( DS ) bits ar e as follow s:
TCS TCS TCS TCS DS DS RS RS FUNCTION
X
X
X
X
0
0
X
X
Disabled
X
X
X
X
1
1
X
X
Disabled
X
X
X
X
X
X
0
0
Disabled
1
0
1
0
0
1
0
1
No diode, 250Ω resistor
1
0
1
0
1
0
0
1
One diode, 250Ω resistor
1
0
1
0
0
1
1
0
No diode, 2kΩ resistor
1
0
1
0
1
0
1
0
One diode, 2kΩ resistor
1
0
1
0
0
1
1
1
No diode, 4kΩ resistor
1
0
1
0
1
0
1
1
One diode, 4kΩ resistor
0
0
0
0
0
0
0
0
In itial default value--disabled
War ning: T he resistor value of 250Ω must not be selected whenever VCC is greater
than 3.63V.
D iode and resistor selection is det er mined by the user acco r d ing to t he max imu m curr ent d es ired for
batter y or super cap charging. The maximu m c harging current can be calculat ed as illustrated in the
following example. As s ume that a s ys tem power su pply of 3V is applied to VCC and a super cap is
conn ected to VBACKUP. Also assu me t hat t he trickle charger has been ena bled w ith a diode and res ist or R2
betw een VCC and V BACKUP. The maximum current IMAX would, t herefore, be calculated as follow s:
IMAX = (5. 0 V - diode drop) / R1 ≈ (5.0V - 0.6V) / 2kΩ ≈ 2.2mA
As t he super cap changes, the voltage drop bet ween VCC and VBACKUP will decr ease a nd, therefore, the
charge curr ent will decr ease.
DS1672
11 of 15
Figure 5. Programmable Trickle Charger
I2C Serial Data Bus
The DS1672 supports a bidirectional I2C bus and data transmission protocol. A device that sends data
o nto the bus is de fine d as a t rans mit t er and a de vice r eceiving d at a as a receiver . The de vice that contro ls
t he message is ca lle d a master . T he devices t hat are co nt rolled by the master ar e slaves. T he bus must be
co nt ro lled by a master d evice that g enerates the serial clock ( S CL), cont ro ls t he bu s acces s, and g ener ates
t he ST ART a nd ST OP cond itions. T he DS167 2 operates as a sla ve on the I2C bus . Connections to the bus
are made via the open-drain I/O lines SDA and SCL. Within the bus specifications, a standard mode
(100kHz maximum clo ck rat e) and a fa st mode (400kHz ma ximum clo ck rate) are defined. The DS1672
operate s in both mode s .
T he follo w ing bus protocol has be e n defined (Figu r e 6):
Data transfer may be i nitia te d only when the bus is not bu sy.
During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in
the d ata line wh ile the clo c k line is h igh will be inter pr eted as contro l signals.
Acc ordingl y, the followin g bus conditio ns have been defined :
Bus not busy: Bot h dat a and clock lines rema in H I GH.
Start data transfer: A change in the state of the dat a line from hig h to low, w hile the clock line is
high, d efines a START co nd it ion.
Stop dat a t ransfer: A change in the state of the d ata line from low to hig h, while the clock l ine i s
high, defines a STOP condit ion.
1 OF 16 SELE CT
NOTE: ONLY 1010 ENABLES
1 O F 2
SELECT
1 O F 3
SELECT
TCS
TCS
TCS
TCS
DS
DS
RS
RS
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
250Ω
R1
R2
TRI CK LE CHARGE REGISTE R
TCS =
TRICKLE CHARGER SELECT
DS =
DIODE SELECT
RS =
RESISTOR SELEC T
V
CC
V
BACKUP
2kΩ
R3
4k
Ω
DS1672
12 of 15
Data valid: The state of the data line represents valid data when, after a START condition, the
dat a line is st able for the durat ion o f the high per iod of the c lock s ig nal. The dat a o n the line must
be changed during the low perio d o f the clock s igna l. There is one clock pulse per bit of data.
Each data transfer is initiated with a START condition and terminated with a STOP condition.
The nu mber of data b ytes tr ansferr ed bet ween t he S T ART a nd the STOP condit ions is no t limit ed,
and is determined by the master device. The information is transferred byte-wise and each
receiver acknowledges with a ninth bit. Within the I2C bus specifications a standard mode
(100kHz clock rate) and a fast mo de (400kHz clo c k r ate) are defined.
Acknowledge: Each receiving device, when addressed, is obliged to generate an acknowledge
after the reception of each byte. The master device must generate an extra clock pulse that is
associated with t h is acknow ledge bit.
A device that acknowledges must pull dow n the SDA line during t he acknowledge clock pu lse in
such a way that the SDA line is stable LOW during the HIGH per iod o f the acknowledge re lat ed
clock pu lse. O f co urse, setu p and ho ld t imes must be t aken int o account . A ma ster must sig nal a n
end of data to the slave by not generating an acknowledge bit on the last byte that has been
clocked out of the sla ve. In t h is case, the s la ve mu st lea ve t he d ata line HIGH to enable the ma ster
to generate the ST OP co nd ition.
Figures 7 and 8 detail how dat a t r ansfer is accomplished on the I2C bus. Depending upon the state of the
R/W bit, two types o f data t r ansfer are poss ible:
1) Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the
master is the slave address. Next fo llows a number of data bytes. T he slave returns an acknowledge
bit after each received byte.
2) Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is
transmitt ed by t he master. The slave then returns an acknow ledge bit. Next fo llo ws a number of d ata
bytes transmitt ed by t he slave to the master. The master returns an acknow ledge bit aft er all rece ived
byt es other t han the la st b yte. At t he end of the last r eceived byte, a “no t ack no wledge” is r etu r ned.
The master device generates all of the serial clock pulses and the START and STOP conditions. A
transfer is e nded w it h a STOP co ndit io n or with a repeated START condition. Since a repeated START
condition is also t he be ginnin g of the next se rial tran sfer, the bus wi l l not be releas ed.
The DS1672 can operate in t he following two mo des:
1) Slave receiver mode (DS1672 write mode): Serial data and clock are received through SDA and
SCL. After each byt e is rece ived, an ackno wledge bit is t r ansmit ted. START and STOP conditio ns ar e
recognized as the beginning and end of a serial transfer. Address recognition is performed by
hardware after r ecep tion of the slave addr ess a nd d irection bit ( F igure 7 ) . T he slave addr ess b yte is th e
first byte received after the START condition is generated by the master. The slave address byte
contains the 7-bit DS1672 address, which is 1101000, follo wed by the direct ion bit (R/W), wh ich for
a write is a 0. After receiving and decoding the slave address byte the DS1672 outputs an
acknowledge on the SDA line. After the DS1672 acknowledges the slave address + write bit, the
master trans mits a wor d address to the DS1672. This w ill set t he r egist er po int er o n t he DS 1672, w ith
the DS1672 acknowledging the transfer. The master may then transmit zero or more bytes of data,
DS1672
13 of 15
with the DS1672 acknowledging each byte received. The register pointer will increment after each
byt e is t r ansferred. T he master will ge n er ate a sto p co ndition t o t er minate t he dat a wr ite.
2) Slave t ransmitter mode (DS1672 read mode): The fir st byte is rec eived and handled as in the slave
receiver mode. However, in this mode, the direction bit will indicate that the transfer direction is
reversed. Serial data is transmitted on SDA by the DS1672 while the serial clock is input on SCL.
START and STOP conditions are reco gnized as t he beginning and end of a serial transfer (Figure 8).
The slave addr ess b yte is t he fir st byte received aft er the START cond it ion is generated by t he mast er .
The slave address byte contains the 7-bit DS1672 address, which is 1101000, followed by the
d irect io n bit (R/ W), which for a read is a 1. After receiving and decoding the slave address byte the
DS1672 outputs an acknowledge on the SDA line. The DS1672 then begins to transmit data starting
with the register address pointed to by the register pointer. If the register pointer is not written to
before the initiation of a read mode the first address that is read is the last one stored in the register
po inter . The DS1672 must r eceive a “not ack no wledge” to end a read.
Figure 6. Data Transfer on I2C Serial Bus
MSB slave address R/W
direction
bit
SDA
SCL
START
CONDITION
1 2 6 7 8 9 1 2 8 9
STOP CONDITION
OR
REPEATED
START CONDITION
3 - 8
acknowledgement
signal from receiver
acknowledgement
signal from receiver
ACK ACK
repeated if more bytes
are transferred
Figure 7. Data Write: Slave Receiver Mode
AXXXXXXXXA1101000S 0 XXXXXXXX AXXXXXXXX AXXXXXXXX A P
<Slave Address> <Word Address (n)> <Data(n) <Data(n+1)> <Data(n+X)>
S - START
A - ACKNOWLEDGE
P - STOP
<RW>
R/W - REA D/WRIT E OR DIRE CT ION BI T ADDRESS = D0H
DATA TR ANSFERRED
(X+1 BYTES + ACKNOWLED GE)
DS1672
14 of 15
Figure 8. Data Read: Slave Transmitter Mode
THERMAL INFORMATION
PACKAGE
THETA-JA
THETA-JC
8 PD IP ( 30 0 mils )
110°C/W
40°C/W
8 SO (150 mils)
128.4°C/W
36°C/W
8 µSO P (3mm)
206.3°C/W
42°C/W
PACKAGE INFORMATION
For the latest package outline informati on and land patterns (footprints), go to www.maxim-ic.com/packages. Note
that a “+”, “#”, or “-“ i n the pack age c ode indic ates RoHS status only . Package drawings may show a different suf fix
character, but the dr awing per tains to t he pac k age r egardl ess of RoHS status.
PACKAGE TYPE PACK AG E CODE OUTLIN E N O . LAND PATTERN NO.
8 PD IP ( 30 0 mils )
P8+1
21-0043
—
8 SO (150 mils)
S8+5
21-0041
90-0096
8 µSO P (3mm)
U8+1
21-0036
90-0092
AXXXXXXXXA1101000S 1 XXXXXXXX AXXXXXXXX AXXXXXXXX A P
<Slave Address> <Data(n)> <Data(n+1) <Data(n+2)> <Data(n+X)>
S - START
A - ACKNOWLEDGE
P - STOP
A - NOT A CKNOWLEDGE
<RW>
R/W - REA D/WRIT E OR DIRE CT ION BI T ADDRESS = D1H
DATA TR ANSFERRED
(X+1 BYTES + ACKNOWLED GE); NOTE: LAST DATA BYTE IS
FOLLOWED BY A NOT ACKNOWL EDGE (A) SIGNAL)
DS1672
15 of 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a r egis t ered tr ad em ar k of Ma xi m Integrated P roduc t s , Inc .
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
9/11
Updated the Ordering Information, Absolute Maximum Ratings,
Recommended Operating Conditions, DC Electrical Characteristics, AC
Electrical Characteristics, Pin Description, T rickle Cha rger, Thermal
Information, a nd Package Inf ormation
2, 3, 5, 7,
10, 15
