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©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0
RFP50N06
N-Channel Power MOSFET
60V, 50A, 22 m
These N-Channel power MOSFETs are manufactured using
the MegaFET process. This process, which uses feature
sizes approaching those of LSI integrated circuits gives
optimum utilization of silicon, resulting in outstanding
performance. They were designed for use in applications
such as switching regulators, switching converters, motor
drivers, and relay drivers. These transistors can be operated
directly from integrated circuits.
Formerly developmental type TA49018.
Features
50A, 60V
•r
DS(ON) = 0.022
Temperature Compensating PSPICE® Model
Peak Current vs Pulse Width Curve
UIS Rating Curve
175oC Operating Temperature
Symbol
Packaging
Ordering Information
PART NUMBER PACKAGE BRAND
RFP50N06 TO-220AB RFP50N06
G
D
S
JEDEC TO-220AB
DRAIN
(FLANGE)
SOURCE
DRAIN
GATE
Data Sheet September 2013
©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0
RFP50N06
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
RFP50N06 UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VDSS 60 V
Drain to Gate Voltage (RGS = 20k) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR 60 V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Continuous Drain Current (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
50
(Figure 5)
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS (Figure 6)
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
131
0.877
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG -55 to 175 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, see Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Tpkg
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 150oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = 250µA, VGS = 0V (Figure 11) 60 - - V
Gate to Source Threshold Voltage VGS(TH) VGS = VDS, ID = 250µA (Figure 10) 2 - 4 V
Zero Gate Voltage Drain Current IDSS VDS = 60V,
VGS = 0V
TC = 25oC--1µA
TC = 150oC--50µA
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance rDS(ON) ID = 50A, VGS = 10V (Figures 9) - - 0.022
Turn-On Time tON VDD = 30V, ID = 50A
RL = 0.6, VGS = 10V
RGS = 3.6
(Figure 13)
--95 ns
Turn-On Delay Time td(ON) -1
2- ns
Rise Time tr-5
5- ns
Turn-Off Delay Time td(OFF) -3
7- ns
Fall Time tf-1
3- ns
Turn-Off Time tOFF --75 ns
Total Gate Charge Qg(TOT) VGS = 0 to 20V VDD = 48V, ID = 50A,
RL = 0.96
Ig(REF) = 1.45mA
(Figure 13)
-125 150 nC
Gate Charge at 10V Qg(10) VGS = 0 to 10V -67 80 nC
Threshold Gate Charge Qg(TH) VGS = 0 to 2V -3.7 4.5 nC
Input Capacitance CISS VDS = 25V, VGS = 0V
f = 1MHz
(Figure 12)
-2020 - pF
Output Capacitance COSS -600 - pF
Reverse Transfer Capacitance CRSS -200 - pF
Thermal Resistance Junction to Case RθJC (Figure 3) -- 1.14 oC/W
Thermal Resistance Junction to Ambient RθJA TO-220 --62 oC/W
---- -
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Source to Drain Diode Voltage VSD ISD = 50A --1.5 V
Reverse Recovery Time trr ISD = 50A, dISD/dt = 100A/µs--125 ns
©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0
Typical Performance Curves Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. PEAK CURRENT CAPABILITY
1.2
1.0
0.8
0.6
0.4
0.2
0
0 25 50 75 100 125 150 175
POWER DISSIPATION MULTIPLIER
TC, CASE TEMPERATURE (oC)
50
40
30
20
10
0
25 50 75 100 125 150 175
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
60
1
0.1
0.01
10-5 10-4 10-3 10-2 10-1 100101
t1, RECTANGULAR PULSE DURATION (s)
PDM
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
t1t2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
0.01
0.02
0.05
0.1
0.2
0.5
2
400
100
10
11 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V)
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1ms
100µs
10ms
100ms
DC
VDSS(MAX) = 60V
ID, DRAIN CURRENT (A)
TC = 25oC
TJ = MAX RATED
SINGLE PULSE
10-3 10-2 10-1 100101102103104
102
103
t, PULSE WIDTH (ms)
VGS = 20V
VGS = 10V
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
II
25
175 TC
150
------------------------



=
IDM, PEAK CURRENT (A)
40
TC = 25oC
RFP50N06
©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0
NOTE: Refer to Fairchild Application Notes 9321 and 9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING CAPABILITY FIGURE 7. SATURATION CHARACTERISTICS
FIGURE 8. TRANSFER CHARACTERISTICS FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFP50N06
Typical Performance Curves Unless Otherwise Specified (Continued)
STARTING TJ = 150oC
STARTING TJ = 25oC
300
100
10
1
0.01 0.1 1 10
tAV , TIME IN AVALANCHE (ms)
If R = 0
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
If R 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
IAS, AVALANCHE CURRENT (A)
125
100
75
50
25
0
0 1.5 3.0 4.5 6.0 7.5
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 10V
VGS = 8V
VGS = 7V
VGS = 6V
VGS = 5V
VGS = 4V
PULSE DURATION = 80µs
TC = 25oC
DUTY CYCLE = 0.5% MAX
012345678910
VGS , GATE TO SOURCE VOLTAGE (V)
ID, DRAIN CURRENT (A)
125
100
75
50
25
0
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX -55oC
175oC
25oC
VDD = 15V
2.5
2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
PULSE DURATION = 80µs
VGS = 10V, ID = 50A
ON RESISTANCE
DUTY CYCLE = 0.5% MAX
2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 160120 200
THRESHOLD VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED GATE
VGS = VDS, ID = 250µA
2.0
1.5
1.0
0.5
0
-80 -40 0 40 80 120 160 200
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
TJ, JUNCTION TEMPERATURE (oC)
ID = 250µA
©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
FIGURE 16. SWITCHING TIME TEST CIRCUIT FIGURE 17. SWITCHING WAVEFORMS
RFP50N06
Typical Performance Curves Unless Otherwise Specified (Continued)
CISS
COSS
CRSS
4000
3000
2000
1000
0
0 5 10 15 20 25
C, CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = 0V, f = 1MHz
CISS = CGS + CGD
CRSS = CGD
COSS = CDS + CGD
60
45
30
15
0
10
7.5
5.0
2.5
0
20
Ig(REF)
Ig(ACT)
80
Ig(REF)
Ig(ACT)
t, TIME (µs)
VDD = BVDSS VDD = BVDSS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
0.75 BVDSS
0.50 BVDSS
0.25 BVDSS
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS , GATE TO SOURCE VOLTAGE (V)
RL = 1.2
Ig(REF) = 1.45mA
VGS = 10V
tP
VGS
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RGS
DUT
+
-
VDD
VDS
VGS
tON
td(ON)
tr
90%
10%
VDS 90%
10%
tf
td(OFF)
tOFF
90%
50%
50%
10% PULSE WIDTH
VGS
0
0
©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0
FIGURE 18. GATE CHARGE TEST CIRCUIT FIGURE 19. GATE CHARGE WAVEFORMS
RFP50N06
Test Circuits and Waveforms (Continued)
RL
VGS +
-
VDS
VDD
DUT
Ig(REF)
VDD
Qg(TH)
VGS = 2V
Qg(10)
VGS = 10V
Qg(TOT)
VGS = 20V
VDS
VGS
Ig(REF)
0
0
©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0
PSPICE Electrical Model
.SUBCKT RFP50N06213
REV 2/22/93
*NOM TEMP = 25oC
CA 12 8 3.68e-9
CB 15 14 3.625e-9
CIN 6 8 1.98e-9
DBODY 7 5 DBDMOD
DBREAK 5 11DBKMOD
DPLCAP 10 5 DPLCAPMOD
EBREAK 11 7 17 18 64.59
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTO 20 6 18 8 1
IT 8 17 1
LDRAIN 2 5 1e-9
LGATE 1 9 5.65e-9
LSOURCE 3 7 4.13e-9
MOS1 16 6 8 8 MOSMOD M=0.99
MOS2 16 21 8 8 MOSMOD M=0.01
RBREAK 17 18 RBKMOD 1
RDRAIN 5 16 RDSMOD 1e-4
RGATE 9 20 0.690
RIN 6 8 1e9
RSOURCE 8 7 RDSMOD 12e-3
RVTO 18 19 RVTOMOD 1
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
VBAT 8 19 DC 1
VTO 21 6 0.678
.MODEL DBDMOD D (IS=9.85e-13 RS=4.91e-3 TRS1=2.07e-3 TRS2=2.51e-7 CJO=2.05e-9 TT=4.33e-8)
.MODEL DBKMOD D (RS=1.98e-1 TRS1=2.35E-4 TRS2=-3.83e-6)
.MODEL DPLCAPMOD D (CJO=1.42e-9 IS=1e-30 N=10)
.MODEL MOSMOD NMOS (VTO=3.65 KP=35 IS=1e-30 N=10 TOX=1 L=1u W=1u)
.MODEL RBKMOD RES (TC1=1.23e-3 TC2=-2.34e-7)
.MODEL RDSMOD RES (TC1=5.01e-3 TC2=1.49e-5)
.MODEL RVTOMOD RES (TC1=-5.03e-3 TC2=-5.16e-6)
.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-6.75 VOFF=-2.5)
.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.5 VOFF=-6.75)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2.7 VOFF=2.3)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=2.3 VOFF=-2.7)
.ENDS
NOTE: For further discussion of the PSPICE model consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global Temperature
Options; authors, William J. Hepp and C. Frank Wheatley.
10
DPLCAP RDRAIN
DBREAK
LDRAIN
DRAIN
SOURCE
LSOURCE
DBODY
RBREAK
RVTO
VBAT
+
-
19IT
RSOURCE
EBREAK
MOS2
EDSEGS
RIN CIN
VTO
ESG
S1A S2A
S2BS1B
CBCA
EVTO
RGATE
GATE
LGATE
5
2
1817
7
11
21
8
6
16
209
1
12 15
14
13
13
8
14
13
+
-
+
-
+
-
+
-+
-
+
-
MOS1
3
6
8
5
8
18
8
6
8
17
18
RFP50N06
TRADEMARKS
The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not
intended to be an exhaustive list of all such trademarks.
*Trademarks of System General Corporation, used under license by Fairchild Semiconductor.
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PRODUCT STATUS DEFINITIONS
Definition of Terms
AccuPower
AX-CAP®*
BitSiC™
Build it Now™
CorePLUS™
CorePOWER™
CROSSVOLT
CTL™
Current Transfer Logic™
DEUXPEED®
Dual Cool™
EcoSPARK®
EfficentMax™
ESBC™
Fairchild®
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FACT Quiet Series™
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QFET®
QS™
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RapidConfigure™
Saving our world, 1mW/W/kW at a time™
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SMART START™
Solutions for Your Success™
SPM®
STEALTH
SuperFET®
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
SupreMOS®
SyncFET™
Sync-Lock™
®*
TinyBoost®
TinyBuck®
TinyCalc™
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TINYOPTO™
TinyPower™
TinyPWM™
TinyWire™
TranSiC™
TriFault Detect™
TRUECURRENT®*
SerDes™
UHC®
Ultra FRFET™
UniFET™
VCX™
VisualMax™
VoltagePlus™
XS™
®
Datasheet Identification Product Status Definition
Advance Information Formative / In Design Datasheet contains the design specifications for product development. Specifications
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Rev. I66
tm
®
RFP50N06
©2002 Fairchild Semiconductor Corporation RFP50N06 Rev. C0
www.onsemi.com
1
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