1/104
PRELIMINARY DATA
November 2003
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Rev. 1.5
PSD4256G6V
Flash In-System Programmable (ISP)
Peripherals for 8-bit or 16-bit MCUs
FEATURES SUMMARY
DUAL BANK FLASH MEM ORIES
8Mbits of Primary Flash Memory (16 uniform
sectors, 64K byte)
512Kb its of Seconda ry Flash Mem ory with 4
sectors
Con current o peration: RE AD from one mem -
ory whi le erasing and writing the other
256 KBITS OF SRAM (BATTERY-BA CKED)
PLD WITH MACROCE LLS
Over 3000 Gates of PLD: CPLD and DPLD
CPLD with 16 Output Macrocells (OMCs) and
24 Input Macrocells (I MCs)
DPLD - user defined internal chip select de-
coding
SEVEN I/O PORTS WITH 52 I/O PINS:
52 individually configurable I/O port pins that
can be used for the following functions:
MCU I/Os
–PLD I/Os
Latched MCU address output
Special function I/Os
l/O ports may be configured as open-drain
outputs
IN-SYST EM PROGR AMMING (I SP) WI TH
JTAG
Built-in JTAG compl iant s erial por t allows full-
chip In-Sy stem Programmability
Efficient manufacturing allow easy product
testing and program mi ng
Use low cost FlashLINK cable with PC
PAGE REG ISTER
Internal page register that can be used to ex-
pand the microcont roller address space by a
facto r of 256
PROGRAMM ABLE POWER MANAG EMENT
Figure 1. Package
HIGH ENDURANCE:
100,000 Erase/Write Cycles of Flash Memory
1,000 Eras e/W rite Cycles of PLD
15 Year Data Retention
SI NGLE SU PPL Y VO LT AG E
3V (+20%/ –10%)
MEMORY SPEED
100ns Flash memory and SRAM access time
for VCC = 3V (+2 0%/– 10%)
90ns Flash memory and SRAM access time
for VCC = 3.3V (+/–10% )
TQFP80 (U)
PSD4256G6V
2/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
TABLE OF CONT ENTS
SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSDsoft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
MCU Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
In-Application Programming (IAP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5
DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6
PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
REGISTER BIT DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Memory Blo cks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Primary Flash Memory and Secondary Flash memo ry Descr iption. . . . . . . . . . . . . . . . . . . . . 24
Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4
Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Power-up Conditio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
READ Memory Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
READ Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
READ Memory Sector Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Data Polling (DQ7) - DQ15 for Motoro la . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Toggle Flag (DQ6) – DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Error Flag (DQ5) – DQ13 for Motorola. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Erase T ime-out Flag (DQ3) – DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
PROGRAMMING FLASH MEM ORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2
Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2
Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset (RESET) Pin. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4
Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
C onfiguration Mod es for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 35
C ombine d Space M od es. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
80C31 Memory Map Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6
MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DECODE PL D (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
COMPLEX PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1
Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
PSD4256G6V
4/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2
The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4
External Ch ip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MCU BUS INT ERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6
PSD Interface to a Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
PSD Interface to a Non-Mul tiplexed, 16-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Data Byte Enable Reference for a 16-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
16-bit MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
80C196 and 80C186. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
H8/300. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4
MM C2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
C 16x Fami ly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5
8-bi t MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
80C51XA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
I/O PORTS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
General Port Architectu re. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3
Port O perating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3
MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
PLD I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
A ddr ess Ou t Mod e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
A ddress In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Data Port M ode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Peripheral I/O Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
JTAG In-System Pr ogramming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
5/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MCU RESET Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Drive Select R egister. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9
Port Da ta Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Output Macrocells (O MC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Mask Macrocell Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0
Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Ports A , B and C – Functio nality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Port D – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Port E – Functionality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Port F – Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Port G – Function ality and Structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5
Automatic Po wer-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Power-down Mo de. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7
PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7
SRAM Standb y Mode (Battery Backu p) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
PSD Chip Selec t Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77
Input Clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
RESET of Flash Memory Erase and Program Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PROGRAMMING IN-CIRCUIT US ING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 80
Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0
JTAG Extensio ns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Security a nd Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
INITIAL DELIVERY STATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
MAXIMU M RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
REVISIO N HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
SUMMARY DESCRIPTION
The PSD family of memory syst e ms for micro co n-
trollers (MCUs) bri n gs I n-System-Programmabi l ity
(ISP) to Flash memory and programmable logic.
The result is a simple and flexible solution for em-
bedded designs. PSD devices combine many of
the peripheral functions found in MCU-based ap-
plications (8-bit or 16-bit), such as configurable
memories, PLD logic, and I/O.
PSD devices integrate an optimized Macrocell log-
ic architecture. The Macrocell was created to ad-
dress the unique requirements of embedded
system designs. It allows direct connection be-
tween the system address/ data bus, and the int er-
nal PSD registers, to simplify communication
between the MCU and other supporting devices.
The PSD family offers two methods to program the
PSD Flash memory while the PSD is sold ered to
the circuit board: In-System Programming (ISP)
via JTAG, and In-Application Programming (IAP).
In-System Pr ogrammi ng (ISP) via JTAG
An IEEE 1149.1 compliant JTAG In-System Pro-
gramming (ISP) interface is included o n the PSD
enabling the en tire dev ice (Flas h m emories, PLD,
configuration) to be rapidly programmed whi le sol -
dered to the circuit board. This requires no MCU
participation, which means the PSD can be pro-
grammed anytime, even when com pletely blank.
The innovative J T AG interface to Flash mem ories
is an industry first, solving key problems faced by
designers and manuf acturin g houses, such as:
First time programming. How do I get firmware
into the Flash memory the very first time? JTAG is
the answer. Program the blank PS D with no MCU
involvement.
Inventory build-up of pre-programmed devic-
es. How do I maintain an accurate count of pre-
programmed Flash memory and PLD devices
based on customer demand? How many and what
version? JTAG is t he answer. Build your hardware
with blank PSDs soldered directly to the board and
then custom program just before they are shipped
to the custome r. No more labels on chips, and no
more wasted inventory.
Expensive sockets. How do I eliminate the need
for expensive and unreliable sockets? JTAG is the
answer. Solder the PSD directly to the circuit
board. Program first time and subsequent times
with JTAG. No need to handle devices and b end
the fragile leads.
In-Application Programming (IAP)
Two independent Flash memory arrays are includ-
ed so that the MCU can execute code from one
while erasing a nd program m ing the o the r. Robust
product firm ware updat es in the f iled are possible
over any communication channel (e.g., CAN,
Ethernet, UART, J1850) using this unique archi-
tecture. Designers are relieved of th ese problems:
Simultaneous READ and WRITE to Flash mem-
ory. How can the MCU program the same memo-
ry from which it executing code? It cannot. The
PSD allows the MCU to operate the two Flash
memory blocks concurrently, reading code from
one while erasing and programming the ot her dur-
ing IAP.
Compl ex memory mappi ng. How can I map
these two memories efficiently? A programmable
Decode PLD (DPLD) is embedded in the PSD
MODULE. The concurrent PSD me mories can be
mapped anywhere in MCU address space, seg-
ment by segment with ext remely high address res-
olution. As an option, the secondary Flash
memory can be swapped ou t of the s ystem mem-
ory map when IAP is complete. A built-in page reg-
ister breaks t he M CU address limit.
Separa te Program an d Data space. How can I
write to Flash m em ory while it reside s in Program
space during field firmware updates? My
80C51XA will not allow it. The PSD provides
means t o reclassify F lash m em ory as Data space
during IAP, then back to Program space when
complete.
PSDsoft
PSDsoft, a software development tool from ST,
guides you through the design process step-by-
step making it poss ible to complete an embed ded
MCU design capable of ISP/IAP in just hours. Se-
lect your MCU and PSDsof t t akes you through the
remainder of the design with point and click entry,
covering PSD selection, pin definitions, program-
mable logic inputs and output s, MCU memory map
definition, ANS I-C code generat ion for you r MCU,
and merging your MCU f irmware wi th the PSD de-
sign. When complete, two different device pro-
grammers are supported directly from PSDsoft:
FlashLINK ( JTAG) and PSDpro.
PSD4256G6V
8/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 2. Logic Diagram Tabl e 1. Pin Names
AI04916
16
AD0-AD15
PF0-PF7
VCC
PSD4xxxGx
VSS
8
PG0-PG7
8
PB0-PB7
8
PA0-PA7
8
3
CNTL0-
CNTL2
RESET
PD0-PD3
4
PC0-PC7
8
PE0-PE7
8
PA0-PA7 Port-A
PB0-PB7 Port-B
PC0-PC7 Port-C
PD0-PD3 Port-D
PE0-PE7 Port-E
PF0-PF7 Port-F
PG0-PG7 Port-G
AD0-AD15 Address/Data
CNTL0-CNTL2 Control
RESET Reset
VCC Supply Voltage
VSS Ground
9/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figu re 3. TQ FP80 Con ne ct i ons
60 CNTL1
59 CNTL0
58 PA7
57 PA6
56 PA5
55 PA4
54 PA3
53 PA2
52 PA1
51 PA0
50 GND
49 GND
48 PC7
47 PC6
46 PC5
45 PC4
44 PC3
43 PC2
42 PC1
41 PC0
PD2
PD3
AD0
AD1
AD2
AD3
AD4
GND
VCC
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PD1
PD0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
GND
VCC
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
VCC
GND
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
RESET
CNTL2
AI04943
PSD4256G6V
10/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 2. TQFP80 Pin Description
Pin Name Pin Type Description
ADIO0-
ADIO7 3-7
10-12 I/O
This is the lower Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If you r MCU has a m ultiplexed ad dress/data bus where th e data is multi plexed with
the lower address bits, connect AD0-AD7 to this port.
2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this
port.
3. If yo u are usin g an 80C 51XA in b urst mode , connect A4/D0 thro ugh A11/D 7 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks has been selected. The addresses on this
port are passed to the PLDs.
ADIO8-
ADIO15 13-20 I/O
This is the upper Address/Data port. Connect your MCU address or address/data bus
according to the following rules:
1. If you r MCU has a m ultiplexed ad dress/data bus where th e data is multi plexed with
the address bits, connect A8-A15 or AD8-AD15 to this port.
2. If you r MCU does n ot have a mu ltiplexed ad dress/data bus , connect A8 -A15 to this
port.
3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this
port.
ALE or AS latches the address. The PSD drives data out only if the READ signal is
active and one of the PSD functional blocks has been selected. The addresses on this
port are passed to the PLDs.
CNTL0 59 I
The following control signals can be connected to this pin, based on your MCU:
1. WR – active Low, WRITE Strobe input.
2. R_W – active High, READ/active Low WRITE input.
3. WRL – active Low, WRITE to Low-byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equat ions.
CNTL1 60 I
The following control signals can be connected to this pin, based on your MCU:
1. 1RD – active Low, READ Strobe input.
2. E – E clock input.
3. DS – active Low, Data Strobe input.
4. LDS – active Low, Strobe for low data byte.
This pin is connected to the PLDs. Therefore, these signals can be used in decode and
other logic equat ions.
CNTL2 40 I
READ or other Control input pin, with multiple configurations. Depending on the MCU
interface selected, this pin can be:
1. PSEN – Program Select Enable, active Low in code retrieve bus cycle (80C51XA
mode).
2. BHE – High-byte enable, 16-bit data bus.
3. UDS – active Low, Strobe for high data byte, 16-bit data bus mode.
4. SIZ0 – Byte enable input.
5. LSTRB – Low Strobe input.
This pin is also connected to the PLDs.
RESET 39 I Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration
Registers and JTAG registers. Must be Low at Power-up. RESET also abort s any Flash
memory Program or Erase cycle that is currently in progress.
PA0-PA7 51-58
I/O
CMOS
or
Open
Drain
These pins make up Port A. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellA0-McellA7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16
and above).
11/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PB0-PB7 61-68
I/O
CMOS
or
Open
Drain
These pins make up Port B. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. CPLD Macrocell (McellB0-McellB7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16
and above).
PC0-PC7 41-48 I/O
CMOS
These pins make up Port C. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs.
3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16
and above).
PD0 79
I/O
CMOS
or
Open
Drain
PD0 pin of Port D. This port pin can be configured to have the following functions:
1. ALE/AS input – latches address on ADIO0-ADIO15.
2. AS input – latches address on ADIO0-ADIO15 on the rising edge.
3. MCU I/O – standard output or input port.
4. Transparent PLD input (can also be PLD input for address A16 and above).
PD1 80
I/O
CMOS
or
Open
Drain
PD1 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. CLKIN – clock input to the CPLD Macrocells, the APD Unit’s Power-down counter,
and the CPLD AND Array.
PD2 1
I/O
CMOS
or
Open
Drain
PD2 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and
I/O. When High, the PSD memory blocks are disabled to conserve power. The falling
edge of this signal can be used to get the device out of Power-down mode.
PD3 2
I/O
CMOS
or
Open
Drain
PD3 pin of Port D. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Transparent PLD input (can also be PLD input for address A16 and above).
3. WRH – for 16-bit data bus, WRITE to high byte, active low.
PE0 71
I/O
CMOS
or
Open
Drain
PE0 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TMS Input for the JTAG Serial Interface.
PE1 72
I/O
CMOS
or
Open
Drain
PE1 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TCK Input for the JTAG Serial Interface.
PE2 73
I/O
CMOS
or
Open
Drain
PE2 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDI input for the JTAG Serial Interface.
PE3 74
I/O
CMOS
or
Open
Drain
PE3 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TDO output for the JTAG Serial Interface.
Pin Name Pin Type Description
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Note: Si gnal names that have mul tiple names or fu nctions a re defined using PS Dsoft.
PE4 75
I/O
CMOS
or
Open
Drain
PE4 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TSTAT output for the JTAG Serial Interface.
4. Ready/Busy output for parallel In-System Programming (ISP).
PE5 76
I/O
CMOS
or
Open
Drain
PE5 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. TERR active Low output for the JTAG Serial Interface.
PE6 77
I/O
CMOS
or
Open
Drain
PE6 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. VSTBYSRAM standby voltage input for SRAM battery backup.
PE7 78
I/O
CMOS
or
Open
Drain
PE7 pin of Port E. This port pin can be configured to have the following functions:
1. MCU I/O – standard output or input port.
2. Latched address output.
3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the exter-
nal battery.
PF0-PF7 31-38
I/O
CMOS
or
Open
Drain
These pins make up Port F. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD.
3. Latched address outputs.
4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded)
5. Data bus port (D0-D7) in a non-multiplexed bus configuration.
6. Peripheral I/O mode.
7. MCU RESET Mode.
PG0-PG7 21-28
I/O
CMOS
or
Open
Drain
These pins make up Port G. These port pins are configurable and can have the
following functions:
1. MCU I/O – standard output or input port.
2. Latched address outputs.
3. Data bus port (D8-D15) in a non-multiplexed, 16-bit bus configuration.
4. MCU RESET Mode.
VCC 9, 29,
69 Supply Voltage
GND 8, 30,
49,
50, 70 Ground pins
Pin Name Pin Type Description
13/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 4. PSD Block Diagram
Note: Additio nal address lines can be brought in to the devic e via Port A, B, C, D, or F.
PROG.
MCU BUS
INTRF.
ADIO
PORT
CNTL0,
CNTL1,
CNTL2
AD0 – AD15
CLKIN
CLKIN
CLKIN
PLD
INPUT
BUS
PROG.
PORT
PORT
A
PROG.
PORT
PORT
B
POWER
MANGMT
UNIT
8 MBIT PRIMARY
FLASH MEMORY
16 SECTORS
VSTDBY
PA0 – PA7
PB0 – PB7
PROG.
PORT
PORT
C
PROG.
PORT
PORT
D
PC0 – PC7
PD0 – PD3
ADDRESS/DATA/CONTROL BUS
PORT A & B
8 EXT CS TO PORT C or F
24 INPUT MACROCELLS
PORT A ,B & C
82
82
512 KBIT SECONDARY
FLASH MEMORY
(BOOT OR DATA)
4 SECTORS
256 KBIT BATTERY
BACKUP SRAM
RUNTIME CONTROL
AND I/O REGISTERS
SRAM SELECT
PERIP I/O MODE SELECTS
MACROCELL FEEDBACK OR PORT INPUT
CSIOP
FLASH ISP CPLD
(CPLD) 16 OUTPUT MACROCELLS
FLASH DECODE
PLD (DPLD)
PLD, CONFIGURATION
& FLASH MEMORY
LOADER
JTAG
SERIAL
CHANNEL
(PE6)
PAGE
REGISTER EMBEDDED
ALGORITHM
SECTOR
SELECTS
SECTOR
SELECTS
GLOBAL
CONFIG. &
SECURITY
AI04917
8
PROG.
PORT
PORT
E
PE0 – PE7
PORT F
PROG.
PORT
PORT
F
PF0 – PF7
PROG.
PORT
PORT
G
PG0 – PG7
PSD4256G6V
14/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD ARCHITECTURAL OVERVIEW
PSD devices contain several major functional
blocks. Figure 4, page 13 shows the architecture
of the PSD device family. The functions of each
block are described briefly in the following sec-
tions. Many of the blocks perform multiple func-
tions and are user configurable.
Memory
Each of the memory blocks is briefly discussed in
the following paragrap hs. A m ore det ailed di scus-
sion can be found in the section ent itled “Memory
Blocks“ on page 23.
The 8Mbit primary Flash memory is the main
memory of the PSD. It is divided into 16 equally-
sized sectors that are individually selec table.
The 512Kbit secondary Flash memory is divided
into 4 sectors. Each sector is individually select-
able.
The 256Kbit SRAM is intended for use as a
scratch-pad memory or as an extension to the
MCU SRAM. If an external battery is connected to
the PSD’s Voltage Standby (VSTBY, PE6) signal,
data is retained in the eve nt of power failure.
Each memory block can be located in a different
address space as defined by the user. The access
times for all memory types includes the address
latching and DPLD decoding time.
PLDs
The device contains two PLD blocks, the Decode
PLD (DPLD) and the Complex PLD (CPLD), as
shown in Table 2, page 10, each optimized for a
different function. T he f unct ional part itioning of the
PLDs reduces power consumption, optimizes
cost/performance, and eases design entry.
The DPLD is used to decode addresses and to
generate Sector Select signals for the PSD inter-
nal memory a nd regis ters. The DPLD has com bi-
natorial outputs, while the CPLD can implement
more general user-defined logic functions. The
CPLD has 16 Output Macrocells (OMC) and 8
combinatorial outputs. The PSD also has 24 Input
Macrocells (IMC) that can be configured as i nputs
to the PLDs. The PLDs receive their inputs from
the PLD Inp ut Bus and are differentiated by their
output destinati ons, number of product terms, and
Macrocells.
The PLDs consume minimal power. The speed
and power consumption of the PLD is controlled
by the Turbo Bit in PMMR0 and other bits in
PMMR2. These registers are set by the MCU at
run-time. There is a slight penalty to PLD propaga-
tion time when not in the Turbo mode.
I/O Port s
The PSD has 52 I/O pins divided among seven
ports (Port A, B, C, D, E, F, and G). Each I/O pin
can be individually configured for different func-
tions. Ports can be configured as standard MCU I /
O ports, PLD I/O, or latched address outputs for
MCUs using multiplexed address/data bus es.
The JTAG pins can be enabled on Port E for In-
System Program ming (ISP ).
MCU Bus Interface
The PSD easily interfaces with most 8-bit or 16-bit
MCUs, either with multiplexed or non-multiplexed
address/data buses. The device is configured to
respond t o the MCU’ s control pins, whic h are al so
used as inputs to the PLDs.
I SP vi a JTA G Port
In-System Programming (ISP) can be performed
through the J TAG signals on Port E. This seri al in-
terface allows compl ete progr ammi ng of t he entire
PSD MODULE device. A blank device can be
completely programmed. The JTAG signals (TMS,
TCK, TSTAT, TERR, TDI, TDO) can be multi-
plexed with other functions on Port E. Table 3 indi-
cat e s th e JTAG pin assi gnm ent s.
Table 3. PL D I/O
Table 4. JTAG Signals on Port E
Name Inputs Outputs Pro duct
Terms
Decode PLD (DPLD) 82 17 43
Complex PLD (CPLD) 82 24 150
Port E Pins JTAG Signal
PE0 TMS
PE1 TCK
PE2 TDI
PE3 TDO
PE4 TSTAT
PE5 TERR
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
In-System Progr a mming ( ISP)
Using the JTAG signals on Port E, the entire PSD
device (memory, lo gic, configuration) can be pro-
grammed or erased without the use of the MCU.
In-Application Programming (IAP)
The primary Flash memory can also be pro-
grammed, or re-programmed, in-system by the
MCU executing the programming algorithms out of
the secondary Flash memory, or SRAM . The sec-
ondary Flash memory can be programmed the
same way by executing out of the primary Flash
memory. Table 5, page 15 indicates which pro-
gramming methods can program different func-
tional blocks of the PSD.
Page Re gi st er
The 8-bit Page Register expands the address
range of the MCU by up to 256 times. The pa ged
address can be used as part of the address space
to access external memory and peripherals, or in-
ternal memory and I/O. The Page Register can
also be used to change the address mapping of
the Flash memory blocks into different memory
spaces for IAP.
Power Manageme nt Unit (PMU)
The Power Management Unit (PMU) gives the
user control of the power consumption on selected
functional blocks based on system requirements.
The PMU includes an Automatic Power-down
(APD) Unit that turns off device functions during
MCU inactivity. The APD Unit has a Power-down
m ode that helps redu ce power consum pti on.
The PSDals o has some bits that are configured at
run-time by the MCU to reduce power consump-
tion of the CPLD. The Turbo Bit in PMMR0 can be
reset to '0' and the CPLD latches its outputs and
goes to S tan dby Mode un til the next transition on
its inputs.
Additionally, bits in PMMR2 can be set by the
MCU to block signals from entering the CPLD to
reduce power consumption. See the section enti-
tled “POWER MANAGEMENT” on page 75 for
more details.
Tabl e 5. Methods of Programming Different Functional Blocks of the PSD
Functional Block JTAG-ISP Device Programmer IAP
Primary Flash Memory Yes Yes Yes
Second ary Flash memo ry Yes Ye s Ye s
PLD Array (DPLD and CPLD) Yes Yes No
PSD Configuration Yes Yes No
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
DE VELOPMENT SYST EM
The PSD family is supported by PSDsoft, a Win-
dows-based software development tool (Win-
dows-95, Windows-98, Windows-NT). A PSD
design is quickly and easily produced in a point
and click environment. The designer does not
need to enter Hardware Description Language
(HDL) equations, unless desired, to define PSD
pin functions and memory map information. The
general design flow is shown in Figure 5. PSDsoft
is available from our web site (the address is given
on the back page of this data sheet ) or other dis tri-
bution channel s.
PSDsoft directl y suppor ts two low cost dev ice pro-
grammers form ST: PSDpro and FlashLINK
(JTAG). Both of these progra mmers may be pur-
chased through your local distributor/representa-
tive, or directly from our web site using a credit
card. The PSD is also supported by third part y de-
vice programmers. See our web site for the current
list.
Figure 5. PSDsoft Devel opment Tool
Merge MCU Firmware
with PSD Configuration
PSD Programmer
*.OBJ FILE
PSDPro, or
FlashLINK (JTAG)
A composite object file is created
containing MCU firmware and
PSD configuration
C Code Generation
GENERATE C CODE
SPECIFIC TO PSD
FUNCTIONS
USER'S CHOICE OF
MICROCONTROLLER
COMPILER/LINKER
*.OBJ FILE
AVAILABLE
FOR 3rd PARTY
PROGRAMMERS
(CONVENTIONAL or
JTAG-ISC)
MCU FIRMWARE
HEX OR S-RECORD
FORMAT
AI04919
Define General Purpose
Logic in CPLD
Point and click definition of combin-
atorial and registered logic in CPLD.
Access HDL is available if needed
Define PSD Pin and
Node Functions
Point and click definition of
PSD pin functions, internal nodes,
and MCU system memory map
Choose MCU and PSD
Automatically configures MCU
bus interface and other
PSD attributes
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD REGISTER DESCRIPTI ON AND ADDRESS OFFSETS
Table 6 shows the offset addresses to the PSD
registers relative to the CSIOP base address. The
CSIOP space is the 256 bytes of address that is al-
located by the user to the internal PSD registers.
Table 6 provides brief descriptions of the registers
in CSIOP space. The following sections give a
more detailed description.
Table 6. Register Address Offset
Note: 1. Other registers that are not part of t he I /O ports.
Register Name Port
A Port
B Port
C Port
D Port
E Port
F Port
G Other(1) Description
Data In 00 01 10 11 30 40 41 Reads Port pin as input, MCU I/O input mode
Control 32 42 43 Selects mode between MCU I/O or Address
Out
Data Out 04 05 14 15 34 44 45 Stores data for output to Port pins, MCU I/O
output mode
Direction 06 07 16 17 36 46 47 Configures Port pin as input or output
Drive Select 08 09 19 38 49 Configures Port pins as either CMOS or
Open Drain
Input Macrocell 0A 0B 1A Reads Input Macrocells
Enable Out 0C 0D 1C 4C Reads the status of the output enable to the I/
O Port driver
Output
Macrocells A 20 READ – reads output of Macrocells A
WRITE – loads Macrocell Flip-flops
Output
Macrocells B 21 READ – reads output of Macrocells B
WRITE – loads Macrocell Flip-flops
Mask
Macrocells A 22 Blocks writing to the Output Macrocells A
Mask
Macrocells B 23 Blocks writing to the Output Macrocells B
Flash Memory
Protection 1 C0 Read only – Primary Flash Sector Protection
Flash Memory
Protection 2 C1 Read only – Primary Flash Sector Protection
Flash Boot
Protection C2 Read only – PSD Security and Secondary
Flash memory Sector Protection
JTAG Enable C7 Enables JTAG Port
PMMR0 B0 Power Management Register 0
PMMR2 B4 Power Management Register 2
Page E0 Page Register
VM E2
Places PSD memory areas in Program and/
or Data space on an individual basis.
Memory_ID0 F0 Read only – SRAM and Primary memory size
Memory_ID1 F1 Read only – Secondary memory type and
size
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
REGISTE R BIT DEFINITION
All the registers of the PSD are included here, for
reference. Detailed descriptions of these registers
can be found in the following sections.
Table 7. Data-In Registers - Ports A, B, C, D, E, F, and G
No te : Bit Def i ni tion s (R ead only registers):
READ Port pi n statu s w hen Port is in M CU I/ O i nput mode.
Table 8. Data-Out Registers - Ports A, B, C, D, E, F, and G
Not e: Bit Definitio ns :
Latched data for out put to Port pi n when pi n i s configured in M CU I/O output mode.
Table 9. Direction Registers - Ports A, B , C, D, E, F, and G
Not e: Bit Definitio ns :
Por tpin < i> 0 = Po rt pin <i > i s c onfigured in Input m ode (defa ul t).
Por tpin < i> 1 = Port pin <i> is configured in Output mode.
Table 10. Control Registers - Ports E, F, and G
Not e: Bit Definitio ns :
Por tpin < i> 0 = Po rt pin <i > i s c onfigured in MCU I/O m ode (default ).
Por tpin < i> 1 = Po rt pin <i > i s c onfigured in Latched Address Out m ode.
Table 11. Drive Registers - Po rts A, B, D, E, and G
Not e: Bit Definitio ns :
Por tpin < i> 0 = Port pin <i> is configured for CMOS Output driver (default ).
Por tpin < i> 1 = Port pin <i> i s c onfigured for Open Drain output dri ver.
Table 12. Enable-Out Registers - Ports A, B, C, and F
No te : Bit Def i ni tion s (R ead only registers):
Por tpin < i> 0 = Port pin <i> is in tri-state driver (default).
Por tpin < i> 1 = Port pin <i> is enabled.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0
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Table 13. Input Macrocells - Ports A, B, and C
No te : Bit Def i ni tion s (R ead only registers):
READ Input Macroc ell (IMC7-IMC0) status on Ports A, B, and C.
Table 14. Output Macrocells A Register
Not e: Bit Definitio ns :
WRITE Register : Load MCellA7-MCe l l A0 with '0' or '1.'
READ Register: Read MCe l lA7-MC el l A0 outp ut stat us.
Table 15. Out Macrocells B Register
Not e: Bit Definitio ns :
WRITE Register : Load MCellB7-MCe l l B0 with '0' or '1.'
READ Register: Read MCe l lB7-MC el l B0 outp ut stat us.
Table 16. Mask Macrocells A Register
Not e: Bit Definitio ns :
McellA<i>_Prot 0 = Allow MC el l A <i > flip-flop to be loaded by MCU (default ).
McellA<i>_Prot 1 = Pre vent MCellA<i> fli p-f l op from b eing load ed by MCU.
Table 17. Mask Macrocells B Register
Not e: Bit Definitio ns :
McellB<i>_Prot 0 = Allo w MC e llB<i> flip-flop t o be loaded by MCU ( d efault).
McellB<i>_Prot 1 = Pre vent MCell B<i> fli p-flop from bein g l oaded by M CU.
Table 18. Flash Mem ory Prote ction Register 1
No te : Bit Def i ni tion s (R ead only register):
Sec<i>_Prot 1 = Primar y Fl ash mem ory Secto r <i > i s wr i te prote ct ed.
Sec<i>_Prot 0 = Primar y Fl ash mem ory Secto r <i > i s not write protected.
Table 19. Flash Mem ory Prote ctions Register 2
No te : Bit Def i ni tion s (R ead only register):
Sec<i>_Prot 1 = Primar y Fl ash mem ory Secto r <i > i s wr i te prote ct ed.
Sec<i>_Prot 0 = Primar y Fl ash mem ory Secto r <i > i s not write protected.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
IMcell 7 IMcell 6 IMcell 5 IMcell 4 IMcell 3 IMcell 2 IMcell 1 IMcell 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Sec15_Prot Sec14_Prot Sec13_Prot Sec12_Prot Sec11_Prot Sec10_Prot Sec9_Prot Sec8_Prot
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Table 20. Flash Boot Protection Register
Not e: Bit Definitio ns :
Sec<i>_Prot 1 = Second ary Flas h m em ory Se ct or <i > is write prot ected .
Sec<i>_Prot 0 = Second ary Flas h m em ory Se ct or <i > is not write protected.
Security_Bit 0 = Se curity Bi t in device has not b een set.
Security_Bit 1 = Se curity Bi t in device has been set .
Table 21. JTAG Enable Register
Not e: Bit Definitio ns :
JTAGEnable 1 = JTAG Po rt is enabled .
JTAGEnable 0 = JTAG Po rt is di s abl ed.
Table 22. Page Register
Not e: Bit Definitio ns :
Configure Page input to PLD. Default is PGR7-PGR0 = '0.'
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used not used not used not used not used not used not used JTAGEnable
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PGR 7 PGR 6 PGR 5 PGR 4 PGR 3 PGR 2 PGR 1 PGR 0
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Table 23. PMMR0 Register
Note: The bits of this register are cleared to zero following power-up. Subsequent Reset (RESET) pul ses do not clear the registers.
Bit Defin i tio ns :
APD Enable 0 = Automatic Power-down (APD) is disabled.
1 = Automatic Power-down (APD) is enabled.
PLD Turbo 0 = P LD T urbo is on.
1 = PLD Turbo is off, saving power.
PLD Array CLK 0 = CLKIN to the PLD A ND array is connected. Eve ry CLKI N change powers up the PLD when Tur bo B it is off.
1 = CLKI N to t he PLD AND array is disconnec ted, savi ng power.
PLD MCells CLK 0 = CL KI N to t he PLD Macrocel l s is connected.
1 = CLKI N to t he PLD Macrocel l s is disconnected, sav i ng power.
Table 24. PMMR2 Register
No te : For Bit 4, Bit 3, Bit 2: See T abl e 35, page 46 for the signals that are bloc ked on pi ns CNTL0-CNTL2.
Bit Defin i tio ns :
PLD Array Addr 0 = Addr ess A7-A0 are connected t o the PLD array.
1 = Address A7-A0 are b l ocked from the PLD array, sa ving power.
Note: In X A Mode, A3 -A 0 come from PF3-P F 0, and A7 -A 4 come from A DIO7-A DIO4.
PLD Array CNTL2 0 = CNTL2 in put to the PL D AND arr ay is connect ed.
1 = CNT L2 input to the PLD AND array is di sconne cted, saving po wer.
PLD Array CNTL1 0 = CNTL1 in put to the PL D AND arr ay is connect ed.
1 = CNT L1 input to the PLD AND array is di sconne cted, saving po wer.
PLD Array CNTL0 0 = CNTL0 in put to the PL D AND arr ay is connect ed.
1 = CNT L0 input to the PLD AND array is di sconne cted, saving po wer.
PLD Array ALE 0 = ALE in put to the P LD AND ar ray is connected.
1 = ALE in put to the PLD AND array i s disconnected, sav i ng powe r.
PLD Array WRH 0 = WRH/DBE input to the P LD AND array is con nected.
1 = WRH/DBE input to the P LD AND array is disconnec ted, saving power.
Table 25. VM Register
Not e: On R ESET, Bits 1-4 are loaded to configurations that are selected by the user in PSDsoft. Bit 0 and B it 7 are always cleared on RESET.
Bit 0-4 are active onl y when the dev i ce is confi gured in 8 051 Mode .
Bit Defin i tio ns :
SR_code 0 = PSEN cannot access SRAM in 80C51XA modes.
1 = PSEN can a ccess SRAM in 80 C5 1 X A mod es.
Boot_Code 0 = PSEN cannot ac cess Sec ondary NVM in 80 C51XA mo des.
1 = PSEN can a ccess Secon d ar y NV M i n 80C51XA modes.
FL_Code 0 = PSEN cannot access Prim ary Flas h m emory i n 80C51XA m odes.
1 = PSEN can acces s Pr i mary Flash memory in 80C51XA m odes.
Boot_data 0 = RD ca nnot access Secondary NV M i n 80C5 1X A modes.
1 = RD can access Secondary NVM in 80C51XA modes.
FL_data 0 = RD cannot access Primary Flash m emory i n 80C51XA m odes.
1 = RD can access Primary Flash memory in 80C51XA modes.
Peripheral mode 0 = Perip heral mode of Port F is di sabled .
1 = Peripheral m ode of Por t F is enabled.
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) not used
(set to 0) PLD
MCells CLK PLD
Array CLK PLD
Turbo not used
(set to 0) APD
Enable not used
(set to 0)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) PLD
Array WRH PLD
Array ALE PLD Array
CNTL2 PLD Array
CNTL1 PLD Array
CNTL0 not used
(set to 0) PLD
Array Addr
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Peripheral
mode not used
(set to 0) not used
(set to 0) FL_data Boot_data FL_code Boot_code SR_code
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 26. Memory_ID0 Regi ster
Not e: Bit Definitio ns :
F_size[3:0] 0h = Th ere is no P ri m ary Flash me m ory
1h = Primary Flash memory size is 256Kbit
2h = Primary Flash memory size is 512Kbit
3h = Primary Flash memory size is 1Mbit
4h = Primary Flash memory size is 2Mbit
5h = Primary Flash memory size is 4Mbit
6h = Primary Flash memory size is 8Mbit
S_size[3:0] 0h = There i s no SRAM
1h = SRAM size is 16Kbit
2h = SRAM size is 32Kbit
3h = SRAM size is 64Kbit
4h = SRAM size is 128Kbit
5h = SRAM size is 256Kbit
Table 27. Memory_ID1 Regi ster
Not e: Bit Definitio ns :
F_size[3:0] 0h = Th ere is no S econdar y NVM
1h = Sec ondary N VM size is 128Kbit
2h = Sec ondary N VM size is 256Kbit
3h = Sec ondary N VM size is 512Kbit
S_size[3:0] 0h = Secon dary NVM is Flash mem ory
1h = Secondary NVM is EEPROM
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
S_size 3 S_size 2 S_size 1 S_size 0 F_size 3 F_size 2 F_size 1 F_size 0
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
not used
(set to 0) not used
(set to 0) B_type 1 B_type 0 B_size 3 B_size 2 B_size 1 B_size 0
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PSD4256G6V
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DETAIL ED OPERATIO N
As shown in Fi gure 4, page 13, the P SD consists
of six maj or types of functional blocks:
Memory Blocks
MCU Bus I n terface
I/O Ports
Power Managem ent Unit (PMU)
JTAG-ISP Interface
The functions of each block are described in the
followi ng sections. Many of the blocks perform
multiple functions , and are user configurable.
Memory Blocks
The PSD has the following memo ry blocks:
Primary Flash memory
Secondary Flash m em ory
–SRAM
The Memory Select signals for these blocks origi-
nate from the De code PLD (DP LD) and are user-
defined in PSDsoft.
Table 28 summarizes th e sizes and org anizations
of the mem ory blocks.
Table 28. Memory Block Size and Organization
Primary Flash Memory Secondary Flash Memory SRAM
Sector
Number Sector Size
(Bytes) Sector Select
Signal Sector Size
(Bytes) Sector Select
Signal SRAM Size
(Bytes) SRAM Select
Signal
0 64K FS0 16K CSBOOT0 32K RS0
1 64K FS1 8K CSBOOT1
2 64K FS2 8K CSBOOT2
3 64K FS3 32K CSBOOT3
4 64K FS4
5 64K FS5
6 64K FS6
7 64K FS7
8 64K FS8
9 64K FS9
10 64K FS10
11 64K FS11
12 64K FS12
13 64K FS13
14 64K FS14
15 64K FS15
Total 1024K 16 Sectors 64K 4 Sectors 32K
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Primary Flash M emory and Secondary Flash memory Descri ption
The primar y Flash memory is divided ev enly into 8
sectors. The secondary Flash memory is divided
into 4 sectors of different size. Each sector of ei-
ther memory block can be separately protected
from Program and Erase cycles.
Flash memory may be erased on a sector-by-sec-
tor basis, and programmed word-by-word. Flash
sector erasure may be suspended while data is
read from other sectors of the block and th en re-
sumed after reading.
During a Program or Erase cycle in Flash memory,
the status can be output on the Ready/Busy pin
(PE4). This pin is set up using PSDsoft.
Memory Block Select Signals
The DPLD g enerates the Select sig nals for all the
internal memory blocks (see the section entitled
“PLDs”, on page 37). Each of the sectors of the pri-
mary Flash memory has a Select signal (FS0-
FS15) which can contain up to three product
terms. Each of the sectors of the sec ondary Flash
memory has a Select signal (CSBOOT0-
CSBOOT3) which can contai n up to three product
terms. Having three produc t terms for each Selec t
signal allows a given sector to be mapped in differ-
ent areas of syste m memory. When using a MCU
with separate Program and Data space
(80C51XA), these flexible Select signals allow dy-
namic re-mapping of sectors from one memory
space to the other before and after IAP. The
SRAM block has a single Select signal (RS0).
Ready/Busy (PE4)
This si gnal can be used to output the Ready/Busy
status of the PSD. The output is a '0' (Busy) when
a Flash memory block is being written to,
or
when
a Flash memory block is being erased. The output
is a '1' (Ready) when no W R ITE or E ras e c ycle is
in progress.
Mem ory Op eration
The primary Flash memory and secondary Flash
memory are addressed thro ugh the MCU Bus In-
terface. The MCU can access these memories in
one of two ways:
The MCU can execute a typical bus WRITE or
READ
operation
just as it would if accessing a
RAM or ROM device using standard bus cycles.
The MCU can execute a s pecific instruction that
consists of several WRITE and READ
operations. This involves writing specific data
patterns to special addresses within the Flash
memory to inv oke an embedded algorithm.
These instr uctions are summarized in Table 29,
page 25.
Typically, the MCU can read Flash memory using
READ operations, just as it would read a ROM de-
vice. However, Flash m em ory can only be erased
and programmed using specific instructions. For
example, the MCU cannot write a single byte di-
rectly to Flash memory as one would write a b yte
to RAM. To program a word into Flash memory,
the MCU must execute a Program instruction, then
test the status of the Programming event. This s ta-
tus test is achieved by a READ operation or polling
Ready/Busy (PE4).
Flash memory can also be read by using special
instructions to retrieve particular Flash device in-
formation (sector protect status and ID).
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Table 29. 16-bit Instructi ons
No te : 1. All bus cycles are WRITE bus cycl es, except the ones with t he “Read” label
2. All v al ues are in hexadec i mal:
X = “Don’t care .” Addresses of the fo rm XXXXh, i n this table, must be even addresses
RA = Ad dress of the memor y l ocation to be read
RD = Dat a read from location RA during the READ cyc le
PA = Address of the memory location to be programmed. A ddresses are latched on the falling edge of WRITE Strobe (WR, CN TL0) .
PA is an even ad dress fo r P SD in word programmin g mode.
PD = Dat a word to be program med at loc ation PA. Dat a i s la tc hed on the risi ng edge of WRITE Str obe (WR, CNTL0)
SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS15 or CSBOOT0-CSBOOT3) of the sector to be
erased, o r verified, must be Active (High).
3. Sector Select (FS0 to FS15 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft.
4. Only address bits A11-A0 are used in i nstruction decoding.
5. No Unl ock or instruction cycl es are requir ed when the dev i ce is in the READ Mode
6. The R ESET ins truc tion i s re quir ed to ret urn t o the REA D M ode af ter rea ding the Fl ash ID, or af ter r ead ing the Sec tor P r otec tion
Status, or if the Error Fla g B i t (DQ5/DQ13) goes Hi gh.
7. Additional sectors to be erased must be wr i tten a t the end of the Sec tor Erase i nstru ct i on withi n 80µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1, A0) = (1 ,0).
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The U nl ock Bypass Reset Fl ash inst ruction is required to retu rn to reading m emory data whe n the dev i ce is in the Unlock Bypass
mode.
11. The sy stem may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when i n the Suspend Sec tor Erase m ode. The S uspend S ector Erase inst ruction is valid only during a Sec tor Era se cycl e.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
1 3. The MCU can not inv oke the se in stru ction s wh ile exe cu ting cod e from the sa me Fla sh me mory as that fo r whic h the i nstr uctio n is
intend ed. Th e M CU m ust retr iev e, for ex amp le, t he code from th e sec on dary Flas h me mor y when rea ding the Sec tor P r otec tion
Status of the pri m ary Fla sh memory.
14. A ll W RI TE b us c ycles in an ins tr uctio n are b yt e-WRITE to an ev en a d dre ss (X AAAh o r X5 54h ). A Fl ash memory Pr o gra m bus cy cle
writ es a word t o an e ven address.
Instruction(14) FS0-FS15 or
CSBOOT0-
CSBOOT3 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
READ(5) 1“Read”
RD @ RA
READ Main Flash
ID(6, 13) 1AAh@
XAAAh 55h@
X554h 90h@
XAAAh Read ID
@ XX02h
READ Secto r
Protection(6,8,13) 1AAh@
XAAAh 55h @
X554h 90 h@
XAAAh
Read 00h
or 01h @
XX04h
Program a Flash
Word(13) 1AAh@
XAAAh 55h@
X554h A0h@
XAAAh PD@ PA
Flash Sector
Erase(7,13) 1AAh@
XAAAh 55h@
X554h 80h@
XAAAh AAh@
XAAAh 55h@
X554h 30h@
SA 30h(7)@
next SA
Flash Bulk Erase(13) 1AAh@
XAAAh 55h@
X554h 80h@
XAAAh AAh@
XAAAh 55h@
X554h 10h@
XAAAh
Suspend Sector
Erase(11) 1B0h@
XXXXh
Resume Sector
Erase(12) 130h@
XXXXh
RESET(6) 1F0h@
XXXXh
Unlock Bypass 1 AAh@
XAAAh 55h@
X554h 20h@
XAAAh
Unlock Bypass
Program(9) 1A0h@
XXXXh PD@ PA
Unlock Bypass
Reset(10) 190h@
XXXXh 00h@
XXXXh
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 30. 8-bit In structions
No te : 1. All bus cycles are WRITE bus cycl es, except the ones with t he “Read” label
2. All v al ues are in hexadec i mal:
X = “Don’t care .” Addresses of the fo rm XXXh , in t his tabl e, must be even address es
RA = Ad dress of the memor y l ocation to be read
RD = Dat a read from location RA during the READ cyc le
PA = Address of the memory location to be programmed. A ddresses are latched on the falling edge of WRITE Strobe (WR, CN TL0) .
PA is an even ad dress fo r P SD in word programmin g mode.
PD = Dat a word to be program med at loc ation PA. Dat a i s la tc hed on the risi ng edge of WRITE Str obe (WR, CNTL0)
SA = Addres s of the se ctor to be erased or verified. Th e Sector Selec t (FS0- FS7 or CSBOOT0-CSBO OT3) of the se ctor to be
erased, o r verified, must be Active (High).
3. Sector Select (FS 0 to FS7 or CSBOOT0 to C SBOOT3) si gnals are act i ve Hi gh, and are defined in PSDsoft.
4. Only address bits A11-A0 are used in i nstruction decoding.
5. No Unl ock or instruction cycl es are requir ed when the dev i ce is in the READ Mode
6. The R ESET ins truc tion i s re quir ed to ret urn t o the REA D M ode af ter rea ding the Fl ash ID, or af ter r ead ing the Sec tor P r otec tion
Status, or if the Error Fla g B i t (DQ5/DQ13) goes Hi gh.
7. Additional sectors to be erased must be wr i tten a t the end of the Sec tor Erase i nstru ct i on withi n 80µs.
8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and
(A1, A0) = (1 ,0).
9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction.
10. The U nl ock Bypass Reset Fl ash inst ruction is required to retu rn to reading m emory data whe n the dev i ce is in the Unlock Bypass
mode.
11. The sy stem may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status
when i n the Suspend Sec tor Erase m ode. The S uspend S ector Erase inst ruction is valid only during a Sec tor Era se cycl e.
12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode.
1 3. The MCU can not inv oke the se in stru ction s wh ile exe cu ting cod e from the sa me Fla sh me mory as that fo r whic h the i nstr uctio n is
intend ed. Th e M CU m ust retr iev e, for ex amp le, t he code from th e sec on dary Flas h me mor y when rea ding the Sec tor P r otec tion
Status of the pri m ary Fla sh memory.
1 4. All WR ITE bus cycles i n an instruction are byte -WRITE to an even address (555h or AAAh). A F l ash memory Program bus cyc l e
writ es a word t o an e ven address.
Instruction(14) FS0-FS7 or
CSBOOT0-
CSBOOT3 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7
READ(5) 1“Read”
RD @ RA
READ Main Flash
ID(6, 13) 1AAh@
555h 55h@
AAAh 90h@
555h READ
ID@ 01h
READ Secto r
Protection(6,8,13) 1AAh@
555h 55h @
AAAh 90 h@
555h
Read 00h
or 01h @
02h
Program a Flash
Word(13) 1AAh@
555h 55h@
AAAh A0h@
555h PD@ PA
Flash Sector
Erase(7,13) 1AAh@
555h 55h@
AAAh 80h@
555h AAh@
555h 55h@
AAAh 30h@
SA 30h(7)@
next SA
Flash Bulk Erase(13) 1AAh@
555h 55h@
AAAh 80h@
555h AAh@
555h 55h@
AAAh 10h@
555h
Suspend Sector
Erase(11) 1B0h@
XXXh
Resume Sector
Erase(12) 130h@
XXXh
RESET(6) 1F0h@
XXXh
Unlock Bypass 1 AAh@
555h 55h@
AAAh 20h@
555h
Unlock Bypass
Program(9) 1A0h@
XXXh PD@ PA
Unlock Bypass
Reset(10) 190h@
XXXh 00h@
XXXh
27/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
INSTRUCTIONS
An instruction consists of a sequence of specific
operations. Each received byte is sequenti ally de-
coded by the PSD and not executed as a st andard
WRITE operation. The instruction is executed
when the correct number of bytes are properly re-
ceived and the time between two consecutive
bytes is shorter than the t i me-out period. Some in-
structions are structured to include READ opera-
tions after the initial WRITE operations.
The instruction must be followed exactly. Any in-
valid combination of instruction bytes or time-out
between two consecutive bytes while addressing
Flash memory resets the device logic into READ
Mode (Fl ash memory is read like a ROM device).
The PSD su pports the instru ctions sum ma rized in
Table 29, page 25:
Erase memory by chip or sector
Suspend or resume sector erase
Program a Word
RESET to READ Mode
READ Primary Flash Id entifier value
READ Sector Protection Status
Bypass
These instructions a re de tailed in Table 29, page
25. For efficient decoding of the instructions, the
first two bytes of an instruction are the coded cy-
cles and ar e followed by an instruction byte or con-
firmation byte. The coded cycles consist of writi ng
the data AAh to address XAAAh during the first cy-
cle and data 55h to address X554h during the sec-
ond cycle (unless the Bypass instruction feature is
used, as described later). Address signals A15-
A12 are “Don’t care” dur ing the instruction WRITE
cycles. However, the appropriate Sector Select
signal (FS0-FS15, or CSBOOT0-CSBOOT3) must
be selected.
The primary and secondary Flash memorie s have
the same instruct ion set (except for READ Primary
Flash Identifier). The Sector Select signals deter-
mine which Flash memory is to receive and exe-
cute the instruction. The primary Flash memory is
selected if any one of its Sector Select signals
(FS0-FS15) is High, and the secondary Flash
memory is selected if any on e of its Sector Sele ct
signals (CSBOOT0-CSBO OT3) is High.
Power-up Condition
The PSD internal logic is rese t upon Power-up to
the READ Mode. Sector Select (FS0-FS15 and
CSBOOT0-CSBOOT3) must be held Low, and
WRITE Strobe (WR/WRL, CNTL0) High, during
Power-up for maximum security of the data con-
tents and to remove the possibility of data being
written on the first edge of WRITE Strobe (WR/
WRL, CNTL0). Any WRITE cycle initiation is
locked when VCC is below VLKO.
READ
Under typical conditions, the MCU may read the
primary Flash memory, or se condary Flash mem-
ory, using READ operations just as it would a
ROM or RAM device. Alternately, the MCU may
use REA D operations t o ob tain s tatus informat ion
about a Program or Erase cycle that is currently in
progress. Lastly, the MCU may use instructions to
read special data from these m em ory blocks. The
following sections describe these READ functions.
READ M emory Conten ts
Primary Flash memory and secondary Flash
memory are placed in the READ Mode after Pow-
er-up, chip reset, or a Reset Flash instr uction (see
Table 29, page 25). The MCU can read th e mem-
ory contents of the primary Flash memory, or the
secondary Flash memory by using READ opera-
tions any time the READ operation is not part of an
instruction.
READ Primary Flash Identifier
The primary Flash memory identifier is read with
an instruction composed of 4 operations: 3 specific
WRITE operations and a READ operation (see Ta-
ble 29, page 25). The identifier for the primary
Flash memory is E7h. The secondar y Flash mem-
ory does not support this ins truction.
READ Memory Sect or Protection Status
The Flash memory Sector Protection Status is
read with an instruction composed of four opera-
tions: three specific WRITE operations and a
READ operation (see Table 29, page 25). The
READ operation produces 01h i f the Flash memo-
ry sector is protected, or 00h if the sector is not
protected.
The sector protection status for all NVM blocks
(primary Fl ash memory, or secondary Flash m em-
ory) can be read by the MCU accessing the Flash
Protection and Flash Boot Protection registers in
PSD I/O space. See the section entitled “Flash
Memory Sector Protect”, on page 33, for register
definitions.
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Reading the Erase/Pr ogram Status Bits
The PSD provides several status bits to be used
by the MCU to confi rm the completion of an Erase
or Pro gram cycle of Flash memory. These status
bits minimize the time that the MCU spends per-
forming these tasks and are defined in Table 31.
The status byte resides in an even location, and
can be read a s many times as needed. Also note
that DQ15-DQ8 is an even byte for Motorola
MCUs with a 16-bit data bus.
For Flash memory, the MCU can perform a READ
operation to obtain these status bits while an
Erase or Program instruction is being executed by
the embedded algo rithm. S ee the se ction entitled
“PROGRAMMING FLASH MEMORY”, on page
30, for deta ils.
Table 31. Status Bits
Table 32. Status Bits for Motoro la 16-bit MCU
Not es:X = Not guaranteed value, can be read either '1' or '0.'
DQ 15-DQ0 repres ent the Da ta Bus bits , D 15-D0.
FS0-FS15/CS BOOT0-CSBOOT3 are active H ig h.
DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
Data Polling Toggle Flag Error Flag X Erase Time-
out XXX
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8
Data Polling Toggle Flag Error Flag X Erase Time-
out XXX
29/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Data Polling (DQ7) - DQ15 for Motorola
When erasing or programming in Flash memory,
the Data Polling Bit (DQ7/DQ15) outputs the com-
plement of the bit being entered fo r programm ing/
writing on the DQ7/DQ15 Bit. Once the Program
instruction or the WRITE operation is completed,
the true logic val ue is read on the Data P ol ling Bit
(DQ7/DQ15) (in a READ operation).
Data Polling is effective after the fourth WRITE
pulse (for a Program in struction) or aft er the
sixth WRITE pulse (for an Erase instruction). It
must be performed at the address being
programmed or at an address within the Flash
memo ry sector being erased.
Durin g an Erase cycl e , the Data Polling Bi t
(DQ7/DQ15) outputs a '0.' After completion of
the cycl e , the Data Poll i n g Bit (DQ7/ DQ15)
outputs the last bit programmed (it is a '1' after
erasing).
If the loca tion to be programmed is in a
protected Flash memory sector, the inst ruction
is ignored.
If all the Flash memory s ectors to be erased are
protected, the Data Polling Bit (DQ7/DQ15) is
reset to '0' for about 100µs, and then returns to
the value from the previously addressed
location. No erasure is performed.
Toggle Flag (DQ6) – DQ14 for Moto rola
The PSD offers another way f o r det ermining when
the Flash memory Program cycle is completed.
During the internal WRITE operation and when ei-
ther FS0-FS15 or CSBOOT0-CSBOOT3 is true,
the Toggl e Flag Bi t (DQ6/DQ14) toggles from 0 to
'1' and '1' to '0' on subsequent attempts to read any
wo r d of t he memory.
When the internal cycle is complete, the toggling
stops and the data read on the Data Bus D0-D7 i s
the value from the addressed memory location.
The device is n ow accessible f or a new READ or
WRITE operation . The cycle is finished when two
successive READ s yield the same output data.
The Toggle Flag Bit (DQ6/DQ14) is eff ective
after the fourth WRITE pulse (for a Program
instruction) or after the sixth WRITE pulse (for
an Erase instruction).
If the l ocation to be programmed belongs to a
protected Flash memory sector, the instruction
is ignored.
If all the Flash me mory sectors selected for
erasure are protected, the Toggle Flag Bit
(DQ6/DQ14) toggles to '0' for about 100µs and
then returns to the value from the previously
addressed location.
Error Flag (DQ5) – DQ13 for Motorola
During a normal Program or Era se cycle, t he Error
Flag Bit (DQ5/DQ13) is reset to '0.' This bit is set
to '1' when there is a failure during a Flash memory
Progr am, Sector Erase, or Bulk Erase cycle.
In the c as e of Flash memory programming, the Er-
ror Flag Bit (DQ5/DQ13) indicates the attempt to
program a Flash memory bit, or bits, from the pro-
grammed st at e, 0, to the erased state, '1,' whic h i s
not a valid operation. The Error Flag Bit (DQ5/
DQ13) may also indicate a Time-out condition
while attempting to program a word.
In case of an error in a Flash memory Sector Erase
or Word Program cycle, the Flash memory se ctor
in which the error occurred or to which the pro-
grammed location belongs must no longer be
used. Other Flash memory sectors may still be
used. The Error Flag Bit (DQ5/DQ13) i s reset after
a RESET instruction. A RESET instruction is re-
quired after detecting an error on the E rror Flag Bit
(DQ5/DQ13).
Erase Ti me-out Flag (DQ3) – DQ11 for Motorola
The Erase Tim e-out Fl ag B it (DQ3/ DQ11) reflects
the time-out period allowed between two consecu-
tive Sector Erase instruc tions . The Erase Time-out
Flag Bit (DQ3/DQ11) is reset to '0' after a Sector
Erase cycle for a period of 100µs + 20% unless an
additional Sector Erase instruction is decoded. Af -
ter this per iod, or when the additional Sector Erase
instruction is decoded, the Erase Time-out Flag Bit
(DQ3/DQ11) is set to '1.'
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PROGRAMMING FLASH MEMORY
Flash memory m ust be erased prior to being pro-
grammed . The M CU m ay erase Fl ash m emo ry a ll
at once or by-sector. Although erasing Flash mem-
ory occurs on a sector or device basis, program-
ming Flash memory occurs on a word basis.
The primary and secondary Flash memories re-
quire the MCU to send an instruction to program a
word or to erase sectors (see Table 29, page 25).
Once the MCU issues a Flash m emory Program or
Erase instruction, it must check t he status bits for
completion. T he embedded algorit hms that are in-
voked inside the PSD support several means to
provide status to the MCU. Status may be checked
using any of three methods: Data Polling, Data
Toggle, or Ready/Busy (PE4) signal.
Data Polling
Polling on the Data Polling Bit (DQ7/DQ15) is a
method of checking whether a Program or Erase
cycle is in progress or has completed. Figure 6
shows the Data Polling algorithm.
When th e MCU issue s a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location of the word to be pro-
grammed in Flash memory to check the status.
The Data Polling Bit (DQ7/DQ15) becomes the
complement of the corresponding bit of the original
data word to be programmed. The MCU continues
to poll this location, comparing data and monitor-
ing the Error Flag Bit (DQ5/ DQ13). When the Data
Polling Bit (DQ7/DQ15) matches the correspond-
ing bit of the original data, and the Error Flag Bit
(DQ5/DQ13) rema ins '0,' the emb edded algo rithm
is complet e. If the Error Flag Bit (DQ5/DQ13) is '1,'
the MCU should test the Data Polling Bit (DQ7/
DQ15) again since the Data Polling Bit (DQ7/
DQ15) may have changed simultaneously with the
Error Flag Bit (DQ5/DQ13) (s ee Figure 6).
The Error Flag Bit (DQ5/DQ13) is set if either an
internal time-out occurred while the embed ded al-
gorithm attempted to program the location or if the
MCU attempted to program a '1' to a bit that was
not erased (not erased is logic '0').
It is suggest ed (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written t o the Flash memory with the
word that was intended to be written.
When using the Data Polling method during an
Erase cycle, Figure 6 still applies. However, the
Data Poll ing Bit (DQ7/ DQ15) is '0 ' until the Erase
cycle is complete. A '1' on the Error Flag Bit (DQ5/
DQ13) indicates a time-out condition on the Erase
cycle, a 0 indicates no error. The MCU can read
any even loc ation within the sector being erased to
get the Data Poll ing Bit (DQ7/DQ15) and the Error
Flag Bit (DQ5/ DQ13).
PSDsoft generates ANSI C code functions that im-
plement these Data Polling algorithms.
Figu re 6. Da ta Po lli ng Flowchart
READ DQ5 and DQ7
(DQ13 and DQ15)
at Valid Even Address
START
READ DQ7
(DQ15)
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
AI04920
Yes
No
Yes
No
DQ5
(DQ13)
= 1
DQ7
(DQ15)
=
Data7
(Data15)
Yes
No
Issue RESET
instruction
DQ7
(DQ15)
=
Data7
(Data15)
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Da ta Toggle
Checking the Toggle Flag Bit (DQ6/DQ14) is an-
other method of determining whether a Progr am or
Erase cycle is in progress or has completed. Fig-
ure 7 shows the Data Toggle algorithm.
When th e MCU issue s a Program instruction, the
embedded algorithm within the PSD begins. The
MCU then reads the location t o be programmed in
Flash memory to check the status. The Toggle
Flag Bit (DQ6/DQ14 ) toggles each time the MCU
reads this locati on unt il the embedded algorithm is
complete. The MCU continues to read this loca-
tion, checking the Toggle Flag Bit (DQ6/DQ14)
and monitoring the Error Flag Bit (DQ5/DQ13).
When th e T oggle Fl ag B it (DQ 6/DQ 14) s tops t og-
gling (two consecutive READs yi eld the same val-
ue), and the Error Flag Bit (DQ5/DQ13) remains
'0,' the embedded algori thm is complete. If the E r-
ror Flag Bit (DQ5/DQ13) is '1,' the MCU should
test the Toggle Flag Bit (DQ6/DQ 14) again, since
the Toggle Flag Bit (DQ6/DQ14) may have
changed simultaneously with the Error Flag Bit
(DQ5/DQ13) (see Figu re 7).
The Error Flag Bit (DQ5/DQ13) is set if either an
internal time-out occurred while the embed ded al-
gorithm attempted to program, or if the MCU at-
tempted to program a '1' to a bit that was not
erased (not erased is logic '0').
It is suggest ed (as with all Flash memories) to read
the location again after the embedded program-
ming algorithm has completed, to compare the
word that was written to Flash memory with the
word that was intended to be written.
When using the Data Toggle method after an
Erase cycle, Figure 7 still applies. the Toggle Flag
Bit (DQ6/DQ14) toggles until the Erase cycle is
complete. A '1' on the Error Flag Bit (DQ5/DQ13)
indicates a tim e-out condition o n th e Erase cycle,
a '0' indicates no error. The MCU can read any
even locat ion within the sector being erased to get
the Toggle Flag Bit (DQ6/DQ14) and the Error
Flag Bit (DQ5/ DQ13).
PSDsoft generates ANSI C code functions which
implement these Data Toggling algori thms.
Unlock Bypass
The Unlock Bypass instruction allows the system
to program words to the Flash memories faster
than using the standard Program instruction. The
Unlock Bypass mode is entered by first initiating
two Unlock cycles. This is followed by a third
WRITE cycle containing the Unlock Bypass com -
mand, 20h (as shown in Table 29, page 25). The
Flash memory then enters the Unlock Bypass
mode.
A two-cycle Unlock Bypa ss Program instruction is
all that is required to program in this mode. The
first cycle in this instruction contains the Unlock
Bypass Program command , A0h. The second cy-
cle contain s the program address and dat a. A ddi-
tional data is programmed in the same manner.
This mode dispense wit h the initial two Unlock cy-
cles requ ired in the standard P rogram inst ruction,
resulting in faster total programming time.
During the unlock bypass mode, only the Unlock
Bypass Program and Unlock Bypass Reset in-
structions are valid.
To e xi t the Unlock Bypass mode, the system must
issue the two-cycle Unlock Bypass Reset instruc-
tion. The first cy cle must contai n the data 90h; the
second cycle the data 00h. Addresses are “Don’t
care” for both cycles. The Flash memory then re-
turns to READ Mode.
Figu re 7. Da ta To ggl e Fl owchar t
START
READ DQ6
(DQ14)
AI04921
No
No
Yes
Yes
No
Yes
Program
or Erase
Cycle failed
Program
or Erase
Cycle is
complete
Issue RESET
instruction
READ DQ5 and DQ6
(DQ13 and DQ14)
at Valid Even Address
DQ5
(DQ13)
= 1
DQ6
(DQ14)
=
Toggle
DQ6
(DQ14)
=
Toggle
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ERASING FLASH MEMORY
Flash Bulk Erase
The Flash Bulk Erase inst ruction uses six WRITE
operations followed by a READ operation of the
status register, as described in Table 29, page 25.
If any byte o f the Bulk Era se instruction is wrong,
the Bulk Erase instruction aborts and the device is
reset to the READ Memo ry mode.
During a Bulk Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5/
DQ13), the Toggle F lag Bit (D Q6/DQ14), an d the
Data Polling Bit (DQ7/DQ15), as detailed in the
section entitled “PROGRAMMING FLASH MEM-
ORY”, on page 30. The Error Flag Bit (DQ5/DQ13)
returns a '1' if there has been an Erase Failure
(maxi mum number of Erase cycl es have be en ex-
ecuted).
It is not necessary to program the memory with
00h because the PSD automatically does this be-
fore erasing to 0FFh.
During execut ion of the Bulk Erase inst ruction, the
Flash mem ory does not accept any instructions.
Flash Sector Erase
The Sector E rase instruction uses six WRI TE op-
erations, as descr ibed in Table 29, page 25. Addi -
tional Fla sh S ecto r E ras e conf irm com m ands and
Flash memory sector addresses can be written
subsequently to erase other Flash memory sec-
tors in parallel, without further coded cycles, if the
additional commands are transm itted in a shorter
time than the time -out pe riod of about 100µ s . The
input of a new Sector Erase command rest ar ts the
time-out period.
The status of the internal timer can be monitored
through the level of the Erase Time-out Flag Bit
(DQ3/DQ11). If the Erase Time-out Flag Bit (DQ3/
DQ11) is '0,' the Sec tor Erase instruction has been
received and the time-out period is counting. If the
Erase Time-out Flag Bit (DQ3/DQ11) is '1,' the
time-out period has expired and the PSD is busy
erasing the Flash memory sector(s). Before and
during Erase time-out, any instruction other than
Suspend Sector Erase and Resume Sector Erase,
abort the cycle that is current ly in progress, and re-
set the dev ice to READ Mod e. It is not necessary
to program the Flash memory sector with 00h as
the PSD does thi s automatically before erasing.
During a Sector Erase, the memory status may be
checked by reading the Error Flag Bit (DQ5/
DQ13), the Toggle F lag Bit (D Q6/DQ14), an d the
Data Polling Bit (DQ7/DQ15), as detailed in the
section entitled “PROGRAMMING FLASH MEM-
ORY”, on page 30.
During execution of the Erase cycle, the Flash
memory accepts only RESET and Suspend Sec-
tor Erase instructions. Erasure of one Flash mem-
ory sector may be suspended, in order to read
data from another Flash m em ory sector, and then
resumed.
Suspend Sector Erase
When a Sector Erase cycle is in progress, the Sus-
pend Sector Erase instruction can be used to sus-
pend the cycle by writing 0B0h to any even
address when an approp riate Sector Select (FS0-
FS15 or CS B OO T0-CSBOO T3) is Hi gh. (S ee Ta-
ble 29, page 25). This allows reading of data from
another Flash mem ory sector after the Erase cycle
has been suspended. Suspend Sector Erase is
accepted only during the Flash Sector Erase in-
struction executi on and defaults to READ Mode. A
Suspend Sector Erase instruction executed during
an Erase time-o ut pe riod, in addition to suspend-
ing the Er as e cycle, terminates t he t ime out period.
The Toggle Flag Bit (DQ6/DQ14) stops toggling
when the PSD internal logic is suspended. The
status of th is bit m ust be m onitored at an address
within the F lash memory sector bei ng erased. The
Toggle Flag Bit (DQ6/DQ14) stops toggling be-
tween 0.1µs and 15µs after the Suspend Sector
Erase instruction has been ex ecuted. The PSD is
then automatically set to READ Mode.
If an Suspend Sector Erase instruction was exe-
cuted, the following rules apply:
Attempting to read from a Flas h memory sector
that was being erased outputs invalid data.
Reading from a Flash memory sector that was
not
b eing erased is valid.
The Flash memory
cannot
be program med, and
only responds t o Resume Sec tor Erase and RE-
SET instructions (READ is an operation and is
allowed).
–If a RESET
instruction is received, data in the
Flash memory sector that was being erased is
invalid.
Resume Sector Erase
If a Suspend Sector Erase instruction was previ-
ously executed , th e Erase cycle may be resum ed
with this inst ruction. The Resume Sect or E rase i n-
struction consis ts o f writing 030h t o any even ad-
dress while an appropriate Sector Select (FS0-
FS15 or CS B OO T0-CSBOO T3) is Hi gh. (See Ta-
ble 29, page 25.)
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
SPECIF IC FEATURES
Flash Memory Sector Protect
Ea ch sect o r o f P r i mar y or Seco nda ry F lash mem-
ory can be separately protected against Program
and Erase cycles. Sector Protection provides ad-
ditional data security because it disables all Pro-
gram or Erase cycles. This mode can be activated
(or deactivated) through the JTAG-ISP Port or a
Device Pro g ra mmer.
Sector protection c an be selected for each sector
using the PSDsoft program. This automatically
protects selected sectors when the device is pro-
grammed through the JTAG Port or a Device Pro-
grammer. Flash memory sectors can be
unprotected to allow updating of their contents us-
ing the JTAG Port or a Device Programmer. The
MCU can read (but cannot change) the sector pro-
tection bits.
Any att empt to progr am or erase a protected Flash
memory sector is ignored by the dev ice. The Ver if y
operation results in a READ of the protected dat a.
This allows a guarantee of the r etention of the Pro-
tection status.
The sector protection status can be read by the
MCU through the Flash memory protection and
Secondary Flash memory protection registers (in
the CSIOP block) or us e the RE AD Sector Protec-
tion instruction. See Table 18, page 19 to Table
20, page 20.
RESET
The RESET instruction consis ts of one WRITE cy-
cle (see Table 29, page 25). It c an also be option-
ally preceded by the standard two WRITE
decoding cycles (writing AAh to AAAh, and 55h to
554h).
The RESET instruction must be ex ecuted after:
Reading the Flash Protection Stat us or Flash ID
An Err or conditi on has occurred (and t he device
has set the Error Flag Bit (DQ5/DQ13) to '1')
during a Flash mem or y Program or Erase cycle.
The RESET instruction immediately puts the Flash
memory back into normal READ M ode. However,
if there is an error condit ion (with the Er ror Flag Bit
(DQ5/DQ13) set to '1') the Flash memory will re-
turn to the READ M ode in 25µs after the RESET
instruction is issued.
The RESET instruction is ignored when it is issued
during a Progr am or Bu l k Era se cycle of th e Fla sh
memory. The RESET instruction aborts any on-
going Sector Erase cycle, and returns the Flash
memory to the normal READ Mode in 25µs.
Reset (R ESET) Pin
A pul se o n t he Reset (RESET) pin aborts any cy-
cle that is in progress, an d rese ts the Flas h mem-
ory to the READ Mode. When the reset occurs
during a P rogram or E rase cycle, the Flash mem -
ory takes up to 25 µs to return to the READ Mode.
It is recomm ended that the Reset (RESET) pulse
(except for Power On Reset, as described on page
79) be at least 25µs so that the Flash memory is
always ready for the MCU to retrieve t he bootstrap
instructions after the RESET cycle is complete.
SRAM
The SRAM is enabled when SRAM Select (RS0)
from the DPLD is High. SRAM Select (RS0) can
contain up to three product terms, allowi ng flexibl e
mem o ry map p ing .
The SRAM can be backed up using an external
battery. The external battery should be connected
to the Voltage Standby (VSTBY, PE6) line. If you
have an external battery connected to the PSD,
the content s of the SRAM are retained in the event
of a power loss. T he contents of the S RAM are re-
tained so long as the battery voltage remains at 2V
or greater. If the supply voltage f alls below the bat-
tery voltage, an internal power switch-over to the
battery occurs.
PE7 can be configured as an output that indicates
when pow er is being drawn from the ex ternal ba t-
tery. This Battery-on Indicator (VBATON, PE7) sig-
nal is High when the supply voltage fal ls bel ow the
battery voltage and th e b attery on Vol tage S t and-
by (VSTBY, PE6) is suppl ying power to the int ernal
SRAM.
SRAM Select (RS0), Voltage Standby (VSTBY,
PE6) and Battery-on Indicator (VBATON, PE7 ) are
all configured using PSDso ft.
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MEMORY SELECT S IGNALS
The Primary Flash Memory Sector Select (FS0-
FS15), Secondary Flash Memory Sector Select
(CSBOOT0-CSBOOT3) and SRAM Select (RS0)
signals are all outputs of the DPLD. They are de-
fined using PSDsoft. The following rules apply to
the equat ions for these signals:
1. Primary Flash memory and secondary Flash
memory Sector Select signals must
not
be larg -
er than the physical se ctor size.
2. Any primary F lash memory sector must
not
be
mapped in the s ame memory space as anot her
Flash memory sector.
3. A secondary Flash me mory sector must
not
be
mapped in the s ame memory space as anot her
secondary Flash mem ory sector.
4. SRAM, I/O, and Peripheral I/O spaces must
not
overlap.
5. A secondary Flash m emo ry sector
may
overlap
a primary Flash m emory sect or. In case of over-
lap, priority is given to the secondary Flash
memory sector.
6. SRAM, I/O, and Peripheral I/O spaces
may
overlap any ot her mem ory sector. Priority is giv-
en to the SRAM, I/O, or Peripheral I/O.
Example
FS0 is valid when the address is in the range of
8000h to BFFFh, CSBOOT0 is v al id from 8000h to
9FFFh, and RS0 is valid from 8000h to 87FFh.
Any address i n the range of RS0 alway s accesses
the SRAM. Any address in the range of CSBOOT0
greater than 87FFh (and less than 9FFFh) auto-
matically addresses secondary Flash memory
segment 0. Any address greater than 9FFFh ac-
cesses the primary Flash memory segment 0. You
can see that half of the pr imary Flash memory seg-
ment 0 and one-fourth of secondary Flash memory
segment 0 cannot be accessed in this example.
Also note that an equation that defined FS1 to any-
where in the range of 8000h to BFFFh would
not
be valid.
Figure 8 shows the priority levels for all memory
components . Any component on a higher level can
overlap and has priority over any component on a
lower level. Components on the same level must
not
overlap. Level 1 has the highest priority and
level 3 has the lowest.
Memory Select Configuration for MCUs with
Separa te Program an d Data Spaces
The 80C31 and compat ible family of MCUs can be
configured to have separate address spaces for
Program memory (s ele cted using Program S el ect
Enable (PSEN, CNTL2)) and Data memory (se-
lected using READ Strobe (RD, CNTL1)). Any of
the mem ories within the PSD ca n reside in either
space or both spaces. This is controlled through
manipulatio n of the VM registe r that resides in the
CSIOP space.
The VM register is set using PSDsoft to have an
initial value. It can subsequently be changed by
the MCU so that memory mapping can be
changed on-the-fly.
For example, you may wish to have SRAM and pri-
mary Flash memory in the Data space at Boot-up,
and secondary Flash memory in the Program
space at Boot-up, and later swap the secondary
Flash memory and prim ary Flash m emory. This is
easily done with the VM regist er by using PSDsoft
to configure it for Boot-up and having the MCU
change i t when des ired.
Table 25, page 21 describes the VM Register.
Figure 8. Priority Level of Memory and I/O
Components
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary
Non-Volatile Memory
Highest Priority
Lowest Priority
Level 3
Primary Flash Memory
AI02867D
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Configuration Modes for MCUs with Separate Program and Data Spaces
Separat e Space Modes. Program space is sep-
arated from Data space. For example, Program
Select Enable (PSEN, CNTL2) is used to access
the program code from the primary Flash memory,
while READ Strobe (RD, CNTL1) is used to ac-
cess data from the secondary Flash memory,
SRAM and I/O Port bl ocks. This configuration re-
quires the VM register t o be set to 0Ch (see Figure
9).
Combined Space Mo des
The P rogram and Data spaces are combined into
one memory space that allows the primary Flash
memory, sec ondary F lash m em ory, an d S RAM t o
be accessed by either Program Select Enable
(PSEN, CNTL2) or READ Strobe (RD, CNTL1).
For example, to configure t he primary Flash mem-
ory in Combined space, Bits 2 and 4 of t he VM reg-
ister are set to 1 (see Fi gure 10).
80C31 Memory Map Example
See the Application Notes for examples.
Figure 9. 8031 Memor y Mod ules – Separate S pac e
Figure 10. 8031 Memor y Mo dules – Comb ined S pace
Primary
Flash
Memory
DPLD Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS15 CS CSCS
OE OE
RD
PSEN
OE
AI04922
Primary
Flash
Memory
DPLD Secondary
Flash
Memory
SRAM
RS0
CSBOOT0-3
FS0-FS15
RD
CS CSCS
RD
OE OE
VM REG BIT 2
PSEN
VM REG BIT 0
VM REG BIT 1
VM REG BIT 3
VM REG BIT 4
OE
AI04923
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PA GE REG ISTER
The 8-bit Page Register increas es the addressing
capability of the MCU by a factor of up to 256. The
contents of the register can also be read by the
MCU. The outputs of the Page Register (PGR0-
PGR7) are inputs to the DPLD decoder and can be
included in the Sector Select (FS0-FS15,
CSBOOT0-CSBOOT3), and SRAM Select (RS0)
equations.
If memo ry pa ging is not needed, or if not all eight
page register bits are ne eded f or m em ory paging,
these bits may be used in the CPLD for general
logic. See Application Note
AN1154
.
Table 22, pa ge 20 and Figure 11 show the Page
Register. The eight flip-flops in the register are
connected to the internal data bus (D0-D7). The
MCU can write to or read from the Page Register.
The Page Register can be accessed at address lo-
c at ion C SIO P + E0h.
Figure 11. Page Register
MEMORY ID REGISTERS
The 8-bit “Read only” Memory Status Registers
are included in the CSIOP space. The user can
determine the memory configuration of the PSD
device by reading the Memory ID0 and Memory
ID1 registers. The content of the registers is de-
fined as shown in Table 26, page 22 and Table 27,
page 22.
RESET
D0-D7
R/W
D0 Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D1
D2
D3
D4
D5
D6
D7
PAGE
REGISTER
PGR0
PGR1
PGR2
PGR3 DPLD
AND
CPLD
INTERNAL
SELECTS
AND LOGIC
PLD
PGR4
PGR5
PGR6
PGR7
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PLDS
The PLDs bring programmable logic functionality
to the PSD. After specifying the logic for the PLDs
using PSDsoft, the logic is programmed into the
device and available upon P ower-up.
The PSD contains two PLDs: the Decode PLD
(DPLD), and the Complex PLD (CPLD). The PLDs
are briefly di scussed in the next few paragraphs,
and in more detail in the following sections. Figure
12, page 38 shows the configurati on of t he PLDs.
The DPLD performs address decoding for internal
components, such as memory, registers, and I/O
ports Select signals.
The CPLD can be us ed for logic funct ions, such as
loadable counters and shift registers, state ma-
chines, and encoding and decoding logic. These
logic functions can be constructed using the 16
Output Macrocells (OMC), 24 Input Macrocells
(IMC), and the AND Array. The CPLD can also be
used to generate External Chip Select (ECS0-
ECS2) signals.
The AND Array is used to form product terms.
These product terms are specified using PSDsoft.
An I nput Bus consisting of 82 signals is connected
to the PLDs. The signal s are shown in Table 33.
The Turb o B it in PS D
The PLDs in the µPSD3200 Family can minimize
power consum ption by switching to standby when
inputs rem ain unchanged for an ex tended time of
about 70 ns . Res etting th e T urbo B it t o '0 ' (B it 3 of
the PMMR0 register) automatically places the
PLDs into standby if no inputs are changing. Turn-
ing the Turbo m ode of f increases propag ation de-
lays while reducing power consumption. See the
section entitled “POWER MANAGEMENT”, on
page 75, on how to set the Turbo Bit.
Additionally, five bits are available in the PMMR2
register to block MCU control signals from entering
the PLDs. This reduces power consumption and
can be used only when these MCU control signals
are not used in PLD logic equations.
Each of the two PLDs has unique characteristics
suited for its applications. They are described in
the following sections.
Tab le 33. D PL D and C P LD I nputs
Note: 1. The ad dress inputs ar e A1 9-A4 in 80C51XA m ode.
Input Source Input Name Number
of
Signals
MCU Address Bus(1) A15-A0 16
MCU Control Signals CNTL0-CNTL2 3
Reset RST 1
Power-down PDN 1
Port A Input
Macrocells PA7-PA0 8
Port B Input
Macrocells PB7-PB0 8
Port C Input
Macrocells PC7-PC0 8
Port D Inputs PD3-PD0 4
Port F Inputs PF7-PF0 8
Page Register PGR7-PGR0 8
Macrocell A Feedback MCELLA.FB7-FB0 8
Macrocell B Feedback MCELLB.FB7-FB0 8
Flash memory
Program Status Bit Ready/Busy 1
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 12. PLD Diagram
PLD INPUT BUS
8
INPUT MACROCELL and INPUT PORTS
DIRECT MACROCELL INPUT TO MCU DATA BUS
CSIOP SELECT
SRAM SELECT
SECONDARY NON-VOLATILE MEMORY SELECTS
DECODE PLD
PAGE
REGISTER
PERIPHERAL SELECTS
JTAG SELECT
CPLD
PT
ALLOC.
MCELLA
MCELLB
DIRECT MACROCELL ACCESS FROM MCU DATA BUS
24 INPUT MACROCELL
(PORT A,B,C)
16 OUTPUT
MACROCELL
I/O PORTS
PRIMARY FLASH MEMORY SELECTS
12 PORT D and PORT F INPUTS
TO PORT A
TO PORT B
DATA
BUS
16
8
8
4
3
1
2
1
EXTERNAL CHIP SELECTS
TO PORT C or PORT F
8
82
16
82
24
OUTPUT MACROCELL FEEDBACK
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
DECODE PLD (DPL D)
The DPLD, shown in Figure 13, is used for decod-
ing the address for internal and external compo-
nents. The DPLD can be used to generate the
following decode signals:
8 Se ctor Select (FS0-FS15) signals for the
primary Flash memory (three product terms
each)
4 Sec tor Select ( CSBOOT0-CSBOOT3) signals
for t he secondary Flash memory ( three product
terms each)
1 internal SRAM Select (RS0) signal (three
product terms)
1 internal CSIOP Select (PSD Configuration
Register) signal
1 JTAG Select signal (enables JTAG-ISP on
Port E)
2 internal Peripheral Select signals (Peripheral
I/O mode).
Figure 13. DPLD Logic Array
Note: 1. The ad dress inputs ar e A1 9-A4 whe n i n 80C51XA mode
2. Additional address li nes can be brought in the PSD v i a Port A, B, C , D, or F.
(INPUTS)
(32)
(8)
(16)
(1)
PDN (APD OUTPUT)
I/O PORTS (PORT A,B,C,F)
(8)
PGR0 -PGR7
(8)
MCELLA.FB [7:0] (FEEDBACKS)
MCELLB.FB [7:0] (FEEDBACKS)
A[15:0]*
(4)
(3)
PD[3:0] (ALE,CLKIN,CSI)
CNTRL[2:0]
(READ/WRITE CONTROL SIGNALS)
(1)
(1)
RESET
RD_BSY
RS0
CSIOP
PSEL0
PSEL1
16 PRIMARY
FLASH
MEMORY
SECTOR
SELECTS
SRAM SELECT
I/O DECODER
SELECT
PERIPHERAL I/O
MODE SELECT
CSBOOT 0
CSBOOT 1
CSBOOT 2
CSBOOT 3
FS0
FS15
3
3
3
3
3
3
3
3
3
3
3
3
3
JTAGSEL
AI04925B
˚
˚
˚
˚
˚
˚
1
1
1
1
4 SECONDARY
FLASH
MEMORY
SECTOR
SELECTS
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
COMPLEX PLD (CPLD)
The CPLD can be used to implement system logic
functions, such as loadable count ers and shift reg-
isters, system m ailboxes, ha ndshaking protocols,
state machines, and random logic. The CPLD can
also be used to generate e ight External Chip Se-
lect (ECS0-ECS7), routed to Port C or Port F.
Although External Chip Select (ECS0-ECS7) can
be produced by any Output Macrocell (OMC),
these ei ght Exter nal Chi p Select (E CS0-EC S 7) o n
Port C or Port F do not consume any Output Mac-
roce l l s (O M C).
As shown in Figure 14, the CPLD has the following
blocks:
24 Input Macroc ells (IMC)
16 Output Macroc ells (OMC )
Product Term A llocator
AND Array capable of generating up to 196
product terms
Four I/O Ports .
Each of the blocks are described in the sections
that follo w .
The Input Macrocells (IMC) and Output Macrocells
(OMC) are connected to the PSD internal data bus
and can be directly accessed by the MCU. This
enables the MCU software to load data into the
Output Macrocells (OMC) or read data from both
the Input and Output Macrocells ( IMC and OMC).
This feature allows efficient implementation of sy s-
tem logic an d eliminates the need to connect the
data bus to the AND Array as required in most
standard PLD macrocell architectures.
Figure 14. Macrocell and I/O Port
I/O PORTS
CPLD MACROCELLS
INPUT MACROCELLS
LATCHED
ADDRESS OUT
MUX
MUX
MUX
MUX MUX
D
D
Q
Q
Q
G
D
QD
WR
WR
PDR
DATA
PRODUCT TERM
ALLOCATOR
DIR
REG.
SELECT
INPUT
PRODUCT TERMS
FROM OTHER
MACROCELLS
POLARITY
SELECT
UP TO 10
PRODUCT TERMS
CLOCK
SELECT
PR DI LD
D/T
CK
CL
Q
D/T/JK FF
SELECT
PT CLEAR
PT
CLOCK
GLOBAL
CLOCK
PT OUTPUT ENABLE (OE)
MACROCELL FEEDBACK
I/O PORT INPUT
ALE/AS
PT INPUT LATCH GATE/CLOCK
MCU LOAD
PT PRESET MCU DATA IN
COMB.
/REG
SELECT
PLD INPUT BUSPLD INPUT BUS
MCU ADDRESS/ DATA BUS
MACROCELL
OUT TO
MCU
DATA
LOAD
CONTROL
AND ARRAY
CPLD OUTPUT
I/O PIN
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Outp ut Macrocell (OMC )
Eight of the Output Macrocells (OMC) are con-
nected to Port s A pins and are named as McellA0-
McellA7. The other eight Macrocells are connect-
ed to Ports B pins and are named as McellB0-
McellB7.
The Output Macrocell (OMC) architecture is
shown in Figure 15, page 43. As shown in the f ig-
ure, there are nat ive prod uc t terms avail able from
the AND Array, and borrowed product terms avail -
able (if unused) from other Output Macrocells
(OMC). The polarity of the product term is con-
trolled by the XOR gate. The Output Macrocell
(OMC) can implement either sequential logic, us-
ing the flip-flop element, or combinatorial logic.
The multiplexe r selects betw een th e sequent ial or
combinatorial logic outputs. The multiplexer output
can drive a port pin and has a feedback path t o the
AND Array input s.
The flip-flop i n the Output Mac rocell (OM C) block
can be configured as a D, T, JK, or SR type in the
PSDsoft program. The flip-flop’s clock, preset, and
clear input s may be driven from a product term of
the AND Array. Alternatively, the external CLKIN
(PD1) signal can be used f or the clock input to the
flip-flop. The flip-flop is clocked on the rising e dge
of CLKIN (PD1). The preset and clear are active
High inputs. Each clear input can use up to two
product terms.
Table 34. Outp ut Macrocell Port and Data Bit Assignme nts
N ote: 1. D7 - D 0 are used f or l o adin g or readi n g i n 8-bit mo de.
Output
Macrocell Port
Assignment Native Product
Terms
Maximum
Borrowed
Product Terms
16-bit MCU
Loading or
Reading(1)
Motorola 16-bit
MCU for
Loading or
Reading
McellA0 Port A0 3 6 D0 D8
McellA1 Port A1 3 6 D1 D9
McellA2 Port A2 3 6 D2 D10
McellA3 Port A3 3 6 D3 D11
McellA4 Port A4 3 6 D4 D12
McellA5 Port A5 3 6 D5 D13
McellA6 Port A6 3 6 D6 D14
McellA7 Port A7 3 6 D7 D15
McellB0 Port B0 4 5 D8 D0
McellB1 Port B1 4 5 D9 D1
McellB2 Port B2 4 5 D10 D2
McellB3 Port B3 4 5 D11 D3
McellB4 Port B4 4 6 D12 D4
McellB5 Port B5 4 6 D13 D5
McellB6 Port B6 4 6 D14 D6
McellB7 Port B7 4 6 D15 D7
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Product Term A l lo cat or
The CPLD has a Product Term Allocator. PSDsoft,
uses the Product Term Allocator to borrow and
place product terms from one Macroc ell to anoth-
er. The following list summarizes how product
terms are al located:
McellA0-M ce llA7 all have three native product
terms and may borrow up to six more
McellB0-M ce llB3 all have four native product
terms and may borrow up to five more
McellB4-M ce llB7 all have four native product
terms and may borrow up to six m ore.
Each Macrocell may only borrow product terms
from certain other Macrocells. Product terms al-
ready in use by one Macrocell are not available for
another Macrocell.
If an equation requires more product terms than
are available to it, then “external” product terms
are required, which consum e other Output Macro-
cells (OMC). If external product terms are used,
extra delay is added for the equation that required
the extra product terms. This is called product term
expansion. PSDsoft performs this expansion as
needed.
Loading and Reading the Ou tput Macroc ells
(OMC)
The Output Macrocells (OMC) block occupies a
memory location in the MCU address space, as
defined by the CSIOP (see Figure 21 to Figure 30
for examples of the basic connections between the
PSD and some popular MCUs). The PSD Control
input pins are l abeled as to the MCU function for
which they are confi gur ed. The MCU bus interface
is specified using t he PSDsoft Express Configura-
tion. The flip-flops in eac h of the 16 Out put Macro-
cells (OMC) can be loaded from the data bus by a
MCU. Loading the O utput Macr ocells (OMC ) with
data from the MCU takes priority over internal
functions. As such, the preset, clear, and clock in-
puts to the flip-flop can be overridden by the MCU.
The ability to load the flip-flops and read them
back is useful in such applications as loadable
counters and shift registers, mailboxes, and hand-
shaking protocols.
Data is l oaded to t he Output Macrocells (OMC) on
the trailing edge of WRITE Strobe (WR/WRL,
CNTL0).
The OMC Mask Register
There is one Mask Register for each of the two
groups of eight Output Macrocells (OMC). The
Mask Registers can be used to block the load ing
of data to individual Output Macrocells (OMC).
The default value for the Mask Registers is 00h,
which allows loading of the Output Macrocells
(OMC). When a given bit in a Mask Register is set
to a 1, the MCU is blocked fr om writing to the as-
sociated Output Macrocells (OMC). For example,
suppose McellA0-McellA3 are being used for a
state machine. You would not want a MCU WRITE
to McellA to overwrite the state machine registers.
Therefore, you would want to load the M ask Reg-
ister for McellA (Mask Macroc ell A ) with t he value
0Fh.
The Outp ut Enable of the OM C
The Output Macrocells (OMC) can be connected
to an I/O port pin as a PLD output. Th e output en-
able of each port pin driver is cont rolled by a single
product term from the AND Array, ORed with the
Direction Register output. The pin is enabled upon
Power-up if no output enable equation is defined
and if the pin is declared as a PLD output in PSD-
soft.
If the Output Macrocell (OMC) output is decl ared
as an internal node and not as a po rt pin outpu t in
the PSDabel file, then the port pin can be used for
other I/O functions. The internal node feedback
can be routed as an input to the AND Array.
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figu re 15. CP LD Output M acrocell
PT
ALLOCATOR
MASK
REG.
PT CLK
PT
PT
PT
CLKIN
FEEDBACK (.FB)
PORT INPUT
AND ARRAY
PLD INPUT BUS
MUX
MUX
POLARITY
SELECT
LD
IN
CLR
Q
PRDIN
COMB/REG
SELECT
PORT
DRIVER
INPUT
MACROCELL
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
CLEAR (.RE)PROGRAMMABLE
FF (D/T/JK/SR)
WR
ENABLE (.OE)
PRESET(.PR)
RD
MACROCELL CS
AI04946
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Input Macro cells (IMC)
The CPLD has 24 Input Macroc ells (IMC), one for
each pin on Ports A, B, and C. The archi tecture of
the Input Macroce lls (IMC) is shown in Figure 16.
The Input Mac rocells (IMC) are indi vidual ly config-
urable, and can be used as a latch, register, or to
pass incoming Port signals prior to driving them
onto the PLD input bus. The outputs of the Input
Macrocells (IMC) can be read by the MCU through
the internal data bus.
The enable for t he latch a nd cloc k f or the regi ster
are driven by a multiplexer whose inputs are a
product term from the CPLD AND Array or the
MCU Address Strobe (ALE/AS). Each product
term output is used to latch or clock four Input
Macrocells (IMC). Port inputs 3-0 can be con-
trolled by one product term and 7-4 by another.
Configurations for the Input Macrocells (IMC) are
specified by PSDsoft (see Application Note
AN1171
). Outputs of the Input Macrocells (IMC)
can be re ad by the MCU via the IMC buffer. See
Figure 21, p age 51 to Figure 30, pa ge 61 for ex-
amples of the basic connections between the PSD
and some popular MCUs. The PSD Control input
pins are la beled as to the MCU f unction for which
they are configured. The MCU bus interface is
specified using the “I/O Ports ”, on page 14.
Input Macrocells (IMC) can use Address Strobe
(ALE/AS, PD0) to latch address bits higher than
A15. Any latched addresses are routed to the
PLDs as inputs.
Input Macrocells (IMC) are particularly us eful with
handshaking communication applications where
two processors pass data back and forth through
a common mailbox. Figure 18, page 45 shows a
typical configuration where the Master MCU writ es
to the Port A Data Out Register. This, in turn, can
be read by the Slave MCU via the activation of the
“Slave-READ” output enable product term.
The Slave can also write to the Port A Input Mac-
rocells (IMC) and the Master can then read the In-
put Macrocell s (IMC) direct ly.
Note that the Slave-READ” and “Slave-Wr” sig-
nals are product terms that are derived from the
Slave MCU inputs READ Strobe (RD, CNTL1),
WRITE Strobe (WR/WRL, CNTL0), and
Slave_CS.
Figure 16. Input Macrocell
OUTPUT
MACROCELLS A
AND
MACROCELLS B
PT
PT
FEEDBACK
AND ARRAY
PLD INPUT BUS
PORT
DRIVER
I/O PIN
INTERNAL DATA BUS
DIRECTION
REGISTER
MUX
MUX
ALE/AS
PT
Q
Q
D
D
G
LATCH INPUT MACROCELL
ENABLE (.OE)
D FF
INPUT MACROCELL_ RD
AI04926
45/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
External Chip Se lect
The CPLD also provides eight External Chip Se-
lect (ECS0-ECS7) outputs that can be used to se-
lect external devices. Each External Chip Select
(ECS0-ECS7) consists of one product term that
can be configured active High or Low.
The output enable of t he pin is controlled by either
the output enable product term or the Direction
Register. (See Figure 17.)
Figure 17. External Chip Select Signal
Figure 18. Handshaking Communication Using Input Macrocells
PLD INPUT BUS
POLARITY
BIT
PORT PIN
ECS PT ECS
To Port C or F
ENABLE (.OE) PT DIRECTION
REGISTER
CPLD AND ARRAY
Port C or Port F
AI04927
MASTER
MCU
MCU-RD
MCU-RD
MCU-WR
SLAVEWR
SLAVECS
MCU-WR
D[7:0]
D[7:0]
CPLD DQ
QD
PORT A
DATA OUT
REGISTER
PORT A
INPUT
MACROCELL
PORT A
SLAVEREAD
SLAVE
MCU
RD
WR
AI02877C
PSD
PSD4256G6V
46/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MCU BUS INTERFACE
The “no-glue logic” MCU Bus Interface block can
be directly connected to most popular 8-bit and 16-
bit MCUs and their control signals. Key MCUs,
with their bus t ypes and control signals, are shown
in Table 35 and Table 36, page 47. The MCU in-
terface type is specified us ing the PSDsoft.
Table 35. 16-bit MCUs and Their Cont rol Signals
Not e: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O func-
tions.
2. ALE /A S i nput is optiona l for MC Us with a non-m ul tiplex ed b us.
3. This configuration i s f or MC68H C812A4_EC at 5MHz, 3V onl y.
MCU CNTL0 CNTL1 CNTL2 PD3 PD02ADIO0 PF3-PF0
68302, 68306, MMC2001 R/W LDS UDS (Note 1)AS (Note 1)
68330, 68331, 68332, 68340 R/W DS SIZ0 (Note 1)AS A0 (Note 1)
68LC302, MMC2001 WEL OE —WEHAS (Note 1)
68HC16 R/W DS SIZ0 (Note 1)AS A0 (Note 1)
68HC912 R/W E LSTRB DBE EA0
(Note 1)
68HC812 3 R/W E LSTRB (Note 1) (Note 1)A0 (Note 1)
80196 WR RD BHE (Note 1)ALE A0 (Note 1)
80196SP WRL RD (Note 1)WRH ALE A0 (Note 1)
80186 WR RD BHE (Note 1)ALE A0 (Note 1)
80C161, 80C164-80C167 WR RD BHE (Note 1)ALE A0 (Note 1)
80C51XA WRL RD PSEN WRH ALE A4/D0 A3-A1
H8/300 WRL RD (Note 1)WRH AS A0
47/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 36. 8 -bit MCUs and Their Control Signals
Not e: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O func-
tions.
2. ALE /A S i nput is optiona l for MC Us with a non-m ul tiplex ed b us.
3. This configuration i s f or MC68H C812A4_EC at 5MHz, 3V onl y.
MCU CNTL0 CNTL1 CNTL2 PD7 PD02ADIO0 PF3-PF0
8031/8051 WR RD PSEN (Note 1)ALE A0 (Note 1)
80C51XA WR RD PSEN (Note 1)ALE A4 A3-A0
80C251 WR PSEN (Note 1) (Note 1)ALE A0 (No te 1)
80C251 WR RD PSEN (Note 1)ALE A0 (Note 1)
80198 WR RD (Note 1) (N ote 1)ALE A0 (No te 1)
68HC11 R/W E(Note 1) (Note 1)AS A0 (No te 1)
68HC05C0 WR RD (Note 1) (N ote 1)AS A0 (No te 1)
68HC912 R/W E(Note 1)DBE AS A0 (Note 1)
Z80 WR RD (Note 1) (Note 1) (Not e 1)A0 (No te 1)
Z8 R/W DS (Note 1) (Note 1)AS A0 (Note 1)
68330 R/W DS (Note 1) (Note 1)AS A0 A3-A1
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD Interface to a Multiplexed Bus
Fig ure 1 9 sh o ws an example of a system using an
MCU with a multiplexed bus and a PSD 4256G 6V.
The ADIO port on the PSD is connected direct ly to
the MCU address/data bus. Address Strobe (ALE/
AS, PD0) latches the address signals internally.
Latched addresses can be brought out to Port E, F
or G. The PSD drives the ADIO data bus only
when one of it s internal r esourc es is accessed and
READ Strobe (RD, CNTL1) is active. Should the
system addres s bus exceed s ixteen bits, Ports A,
B, C, or F may be used a s additional address in-
puts.
Figure 19. An Example of a Typical Multiplexed Bus Interface
No te : 1. AD[ 15:8] is for 16-b i t MCU
MCU
WR
RD
BHE
ALE
RESET
AD[7:0]
AD[15:8]1
A[15:8]
A[7:0]
ADIO
PORT
PORT
F
PORT
G
PORT
A
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
(OPTIONAL)
(OPTIONAL)
PSD
AI04928B
A[23:16]
(OPTIONAL)
or A[15:8]
49/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PSD Interface to a Non-Mu ltiplexed, 16-bit Bus
Fig ure 2 0 sh o ws an example of a system using an
MCU with a 16-bit, non-multiplexed bus and a
PSD4256G6V. The address bus is connected to
the ADIO Port, and the data bus is connected to
Ports F and G. Ports F and G are in tri-state mode
when the PSD is not accessed by the MCU.
Should the system address bus exceed sixteen
bit, Ports A, B, or C may be used for additional ad-
dress inputs.
Figure 20. An Example of a Typical Non-Multiplexed Bus Interface
Note: 1. D[15:8] is for 16-bit MCU
MCU
WR
RD
BHE
ALE
RESET
D[15:0]
A[15:0]
D[15:8]1
D[7:0]
ADIO
PORT
PORT
F
PORT
G
PORT
A
WR (CNTRL0)
RD (CNTRL1)
BHE (CNTRL2)
RST
ALE (PD0)
PORT D
PSD
AI04929B
A[23:16]
(OPTIONAL)
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Data Byte Enable Reference for a 16-bi t Bus
MCUs have different data byt e orientations. Table
37 to Table 40 show how the µPS D3200 Family in-
terprets byte/word operations in different bus
WRITE configurations. Even-byte refers to loca-
tions with address A 0 eq ual to 0, and odd by te as
locations wi t h A0 equal to 1.
Table 37. 16-Bit Data Bus with BHE
16-bit MCU Bus Interface Examples
Figure 21, page 51 to Figure 26, page 57 show ex-
amples of the basic connections between the
µPSD32 00 F amily and some popular MCUs. The
µPSD3200 Family Control input pins are labeled
as to the M CU function for which they are conf ig-
ured. The MCU bus interface is specified using
PSDsoft. The Voltage Standby (VSTBY, PE6) line
should be held at Ground if not in use.
Table 38. 16-Bit Data Bus with WRH and WRL
Table 39. 16-Bit Data Bus with SIZ0, A0
(Motorola MCU)
Table 40. 16-Bit Data Bus with LDS, UDS
(Motorola MCU)
BHE A0 D15-D8 D7-D0
0 0 Odd Byte Even Byte
0 1 Odd Byte
1 0 Even Byte
WRH WRL D15-D8 D7-D0
0 0 Odd Byte Even Byte
0 1 Odd Byte
1 0 Even Byte
SIZ0 A0 D15-D8 D7-D0
0 0 Even Byte Odd Byte
1 0 Even Byte
1 1 Odd Byte
WRH WRL D15-D8 D7-D0
0 0 Even Byte Odd Byte
1 0 Even Byte
0 1 Odd Byte
51/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
80C196 and 80C186
In Figure 21, t he Intel 80C196 M CU, which has a
16-bit multiplexed address/data bus, is shown
connected to a µPSD3200 Family. The READ
Strobe (RD, CNTL1), and WRITE Strobe (WR/
WRL, CNTL0) signals are conn ected to the CNTL
pins. When BHE is not used, the PSD c an be con-
figured t o receive WRL and WRITE Enable High-
byte (WRH/DB E, PD3) from the MCU. Higher ad-
dress inputs (A16-A19) can be routed to Ports A,
B, or C as input to the PLD.
The AMD 80186 family has the same bus connec-
tion to t he PSD as the 80C196.
Figure 21. Interfacing the PSD with an 80C196
X1
X2
P1.0/EPA0/T2CLK
P1.1/EPA1
P1.2/EPA2/T2DIR
P1.3/EPA3
P1.4/EPA4
P1.5/EPA5
P1.6/EPA6
P1.7/EPA7
P3.0/AD0
P3.1/AD1
P3.2/AD2
P3.3/AD3
P3.4/AD4
P3.5/AD5
P3.6/AD6
P3.7/AD7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA2
PA1
PA3
PA4
PA5
PA6
PA7
P4.0/AD8
P4.1/AD9
P4.2/AD10
P4.3/AD11
P4.4/AD12
P4.5/AD13
P4.6/AD14
P4.7/AD15
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
RESET
RD/P5.3
WR/WRL/P5.2
BHE/WRH/P5.5
ALE/ADV/P5.0
INST/P5.1
SLPINT/P5.4
RESET
31
32
33
34
35
36
37
38
3
19
18
57
56
55
54
53
52
51
50
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
59
39
60
40
79
80
1
21
22
23
24
25
26
27
28
PSD80C196NT
A19-A16 A[19:16]
7
9
8
4
RD
WR
BHE
ALE
3
1
RESET
51
52
53
54
55
56
57
58
AI04930
AD15-AD0 AD[15:0]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
PD3 (WRH)
2
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
71
72
73
74
75
76
77
78
8 30495070
GNDGNDGNDGNDGND
92969
VCC VCC VCC
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
3
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
EP.0/A16
EP.1/A17
EP.2/A18
EP.3/A19
14
13
12
11
31
BUSWIDTH/P5.7 10
EA 33
RESET
READY/P5.6 2
P2.0/TX/PVR
P2.1/RXD/PALE
P2.2/EXINT/PROG
P2.3/INTB
P2.4/INTINTOUT
P2.5/HLD
P2.6/HLDA/CPVER
P2.7/CLKOUT/PAC
36
37
38
39
40
41
42
43
P6.0/EPA8
P6.1/EPA9
P6.2/T1CLK
P6.3/T1DIR
P6.4/SC0
P6.5/SD0
P6.6/SC1
P6.7/SD1
58
59
60
61
62
63
64
65
NMI
VREF
VPP
ANGND
ACH4/P0.4/PMD.0
ACH5/P0.5/PMD.1
ACH6/P0.6/PMD.2
ACH7/P0.7/PMD.3
32
49
6
48
44
45
46
47 A16
A17
A18
A19
A16
A17
A18
A19
PSD4256G6V
52/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MC683xx and MC68HC16
Figure 22 shows a MC68331 with a 16-bit non-
multiplexed da ta b us and 24-bi t ad dress bus. The
data bus from the MC68331 i s connect ed to Port F
(D0-D7) and Port G (D8-D15). The SIZ0 and A0 in-
puts determine the high/low byt e sele ction. The R/
W, DS and SIZ0 signals are connected to the
CNTL0-CN TL2 pins.
The MC68HC16, and other members of the
MC683x x f am ily, has the s ame bu s connection to
the PSD as the MC68331 shown in Figure 22.
Figure 22. Interfacing the PSD with an MC68331
VCC_BAR
D[15:0]
A16
A5
D1
D13
DS\
AS
A8
D12
A1
A18
A19
A23
D4
D12
D8
A22
D7
D3
A[23:0]
D3
D11
A16
A17
D14
D13
A3 D2
D5
A19
A0
A12
D2
A4
R/W\
D6
D5
RESET\
A7
A2
A13
A14
A15
D7
D9
D10
D15
D4
A17
A6
SIZ0
D10
D15
A18
A21
A11
D0
D1
D6
D11
D14
D9
D0
A20
D8 A9
A10
MC68331
A1 20
A2 21
A3 22
A4 23
A5 24
A6 25
A7 26
A8 27
A9 30
A10 31
A11 32
A12 33
A13 35
A14 36
A15 37
A16 38
A17 41
A18 42
A19_CS6/ 121
A20_CS7/ 122
A21_CS8/ 123
A22_CS9/ 124
A23_CS10/ 125
R_W 79
AS 82
D0
111
D1
110
D2
109
D4
105
D5
104
D6
103
D7
102
D8
100
D9
99
D10
98
D11
97
D13
93
D14
92
D15
91
A0 90
D3
108
D12
94
DS 85
SIZ0 81
SIZ1 80
CSBOOT/ 112
BR_CS0/ 113
BG_CS1/ 114
BGACK_CS2/ 115
FC0_CS3/ 118
FC1_CS4/ 119
FC2_CS5/ 120
RESET 68
DSACK0
89
DSACK1
88
CLKOUT 66
IRQ1
77
IRQ2
76
IRQ3
75
IRQ4
74
IRQ5
73
IRQ6
72
IRQ7
71
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
PA5 56
PA6 57
PA7 58
CNTL0(R/W)
59
CNTL1(DS)
60
CNTL2 (SIZ0)
40
PD0 (AS)
79
RESET
39
ADIO8
13 PG0 21
PA3 54
PA4 55
PA2 53
PA0 51
PA1 52
PB0 61
PB1 62
PB2 63
PB3 64
PB4 65
PB5 66
PB6 67
PB7 68
PC0 41
PC1 42
PC2 43
PC3 44
PC4 45
PC5 46
PC6 47
PC7 48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc 29
Vcc 69
Vcc 9
GND
50 GND
49 GND
30 GND
8
GND
70
PD2 (CSI)
1PD1 (CLKIN)
80
PD3
2
PE6 (VSTBY)
77
RESET\
A[23:0]
D[15:0]
AI04951b
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
80C51XA
The Philips 80C51XA MCU has a 16-bit multi-
ple xed bus with burst cycle s. Address b its (A3-A1 )
are not multiplexed, while (A19-A4) are multi-
plexed with data bits (D15-D0).
The µPSD3200 Family supports the 80C51XA
burst mode. The WRH signal is connected to PD3,
and WHL is connected to CNTL0. The RD and
PSEN signals are connected to the CNTL1 and
CNTL2 pins. Figure 23 shows the schematic dia-
gram.
The 80C51XA improves bus throughput and per-
formance by issui ng burst cycl es to retrie ve codes
fr om memo ry. In burst cycle s, a ddress A19- A4 are
latched internally by the PSD, whil e the 80C51XA
drives the A3-A1 signals to retrieve sequentially up
to 16 byt es of code. The P SD a cc ess t ime is then
measured from address A3-A1 valid to data in val-
id. The P SD bus timing requirement in a burst cy-
cle is identical to the normal bus cycle, except the
address setup and hold time with respect to Ad-
dress Strobe (ALE/AS, PD0) is not required.
Figure 23. Interfacing the PSD with an 80C51XA-G 3
VCC_BAR
VCC_BAR
D[15:0]
WRL\
RD\
PSEN\
ALE
A4D0
A5D1
A6D2
A7D3
A8D4
A9D5
A10D6
A11D7
A12D8
A13D9
A14D10
A15D11
A16D12
A17D13
A18D14
A19D15
RESET\
RESET\
A3
A2
A1
WRH\
A[3:1]
A1
A2
A3
U3
CRYSTAL
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
PA5 56
PA6 57
PA7 58
CNTL0(WR)
59
CNTL1(RD)
60
CNTL2(PSEN)
40
PD0 (ALE)
79
RESET
39
ADIO8
13 PG0 21
PA3 54
PA4 55
PA2 53
PA0 51
PA1 52
PB0 61
PB1 62
PB2 63
PB3 64
PB4 65
PB5 66
PB6 67
PB7 68
PC0 41
PC1 42
PC2 43
PC3 44
PC4 45
PC5 46
PC6 47
PC7 48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc 29
Vcc 69
Vcc 9
GND
50 GND
49 GND
30 GND
8
GND
70
PD2 (CSI)
1PD1 (CLKIN)
80
PD3 (WRH)
2
PE6 (VSTBY)
77
XA-G3
A0/WRH 2
A1 3
A2 4
A3 5
A4D0 43
A5D1 42
A6D2 41
A7D3 40
A8D4 39
A9D5 38
A10D6 37
A11D7 36
A12D8 24
A13D9 25
A14D10 26
A15D11 27
A16D12 28
A17D13 29
A18D14 30
A19D15 31
PSEN 32
RD 19
WRL 18
ALE 33
RST
10
INT0
14
INT1
15
EA/WAIT
35
BUSW
17
XTAL1
21
XTAL2
20
RXD0
11
TXD0
13
RXD1
6
TXD1
7
T2EX
9
T2
8
T0
16
D[15:0]
A[3:1]
AI04952b
PSD4256G6V
54/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
H8/300
Figure 24 shows an Hitachi H8/2350 with a 16-bit
non-multiplexed data bus, and a 24-bit address
bus. The H8 d ata bus i s connect ed t o Port F (D0-
D7) and Port G (D8-D15).
The WRH si gnal is connected to PD3, and WHL is
connected to CNTL0. The RD signal is connect ed
to CNTL1. The connection to the Address Strobe
(AS) signal is optional, and is required if the ad-
dresses are to be latched.
Figure 24. Interfacing the PSD with an H83/2350
VCC_BAR
AS
RESET\
RD\
RESET\
WRL\
A21
A3
A[23:0]
A11
A1
A9
A14
A15
A20
A5
A8
A13
A10
A7
A18
A19
A17
A2
A16
A4
A6
A12
A0
D4
D9
D10
D15
D8
D7
D[15:0]
D2
D5
D0
D11
D13
D3
D14
D1
D6
D12
WRH\
A22
A23
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A16
A17
A18
A19
U3
CRYSTAL
H8S/2655
PC0/A0 2
PC1/A1 3
PC2/A2 4
PC3/A3 5
PC4/A4 7
PC5/A5 8
PC6/A6 9
PC7/A7 10
PB0/A8 11
PB1/A9 12
PB2/A10 13
PB3/A11 14
PB4/A12 16
PB5/A13 17
PB6/A14 18
PB7/A15 19
PA0/A16 20
PA1/A17 21
PA2/A18 22
PA3/A19 23
PA4/A20/IRQ4 25
PA5/A21/IRQ5 26
PA6/A22/IRQ6 27
PA7/A23/IRQ7 28
CS7/IRQ3
29
CS6/IRQ2
30
IRQ1
31
IRQ0
32
RXD0
55
TXD0
53
SCK0
57
RXD1
56
TXD1
54
SCK1
58
RXD2
90
TXD2
89
SCK2
91
PF0/BREQ
88
PF1/BACK
87
PF2/LCAS/WAIT/B
86
NMI
74
PO0/TIOCA3
71
PO1/TIOCB3
70
PO2/TIOCC3/TMRI
69
PO3/TIOCD3/TMCI
68
PO4/TIOCA4/TMRI
67
PO5/TIOCB4/TMRC
66
PO6/TIOCA5/TMRO
65
PO7/TIOCB5/TMRO
64
DREQ/CS4
60
TEND0/CS5
61
DREQ1
62
TEND1
63
PE0/D0
34
PE0/D1
35
PE0/D2
36
PE0/D3
37
PE0/D4
39
PE0/D5
40
PE0/D6
41
PE0/D7
42
PD0/D8
43
PD1/D9
44
PD2/D10
45
PD3/D11
46
PD4/D12
48
PD5/D13
49
PD6/D14
50
PD7/D15
51
RD 83
LWR 85
HWR 84
AS 82
PF0/PHI0
80
RESET 73
WDTOVF 72
MOD0
113
MOD1
114
MOD2
115
STBY 75
EXTAL
78
XTAL
77
PG0/CAS/OE 116
PG1/CS3 117
PG2/CS2 118
PG3/CS1 119
PG4/CS0 120
PO8/TIOCA0/DACK 112
PO9/TIOCB0/DACK 111
PO10/TIOCC0/TCL 110
PO11/TIOCD0/TCL 109
PO12/TIOCA1 108
PO13/TIOCB1/TCL 107
PO14/TIOCA2 106
PO15/TIOCB2/TCL 105
AN0 95
AN1 96
AN2 97
AN3 98
AN4 99
AN5 100
AN6/DA0 101
AN7/DA1 102
ADTRG 92
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
PA5 56
PA6 57
PA7 58
CNTL0(WRL)
59
CNTL1(RD)
60
CNTL2
40
PD0 (AS)
79
RESET
39
ADIO8
13 PG0 21
PA3 54
PA4 55
PA2 53
PA0 51
PA1 52
PB0 61
PB1 62
PB2 63
PB3 64
PB4 65
PB5 66
PB6 67
PB7 68
PC0 41
PC1 42
PC2 43
PC3 44
PC4 45
PC5 46
PC6 47
PC7 48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc 29
Vcc 69
Vcc 9
GND
50 GND
49 GND
30 GND
8
GND
70
PD2 (CSI)
1PD1 (CLKIN)
80
PD3 (WRH)
2
PE6 (VSTBY)
77
A[23:0]
D[15:0]
AI04953b
55/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MMC2001
The Motorola MCORE MMC2001 MCU has a
MOD input pin that selects internal or external boot
ROM. T he PSD can be configured as t he external
flash boot ROM or as extension to the internal
ROM (see Figure 25, page 56).
The MMC2001 has a 16-bit external data bus and
20 addres s lin es with external chip select signal s.
The Chip Select Control Registers allow the user
to customize the bus interface and timin g to fit the
individual system requirement. A typical interface
configuration to the PSD is shown in Figure 25,
page 56. The M MC2001’s R/W s ignal is conn ect-
ed to the CNTL0 p in, while EB 0 and EB 1 (enable
byte-0 and enable byte-1) are connected to the
CNTL1 (UDS) and CNTL2 (LDS) pins. The WEN
bit in the Chip Select Control Register should be
set to 1 to terminate the EB0-EB1 earlier to pro-
vide the write data hold time for the PSD. The
WSC and WWS bits in the Contr ol Register are set
to wait states that meet the PSD access time re-
quirement.
Another option i s to configure the EB 0 and EB1 as
WRL and WRH signals. I n t his case, the PSD con-
trol setting will be: OE, WRL, WRH where OE is
the READ signal for the MMC2001.
C16x Family
The PSD supports Infineon’s C16X family of
MCUs (C161-C167) in both the multiplexed and
non-multiplexed bus configuration. In Figure 26,
page 57, the C167 CR is shown conn ected to the
PSD in a multiplexed bus configuration. Th e con-
trol signals from the MCU are WR, RD, BHE and
ALE, and are routed to the corresponding PSD
pins.
The C167 has an other contro l signal setting (RD ,
WRL, WRH, ALE) which is also supported by the
PSD.
PSD4256G6V
56/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 25. Interfacing the PSD with an MMC200 1
VCC_BAR VCC_BAR
A16
ALE
AD14
AD10
AD6
A17
A19
RD\
AD13
AD9
AD5
AD1
RESET\
A19
BHE\
AD7
A[19:16]
A17
AD[15:0]
AD12
AD4
AD2
A18
WR\
AD15
AD8
A18
AD11
A16
RESET\
AD3
AD0
U3
CRYSTAL
PSD
ADIO0
3
ADIO1
4
ADIO2
5
ADIO3
6
ADIO4
7
ADIO5
10
ADIO6
11
ADIO7
12
ADIO9
14
ADIO10
15
ADIO11
16
ADIO12
17
ADIO13
18
ADIO14
19
ADIO15
20
PF0 31
PF1 32
PF2 33
PF3 34
PF4 35
PF5 36
PF6 37
PF7 38
PG1 22
PG2 23
PG3 24
PG4 25
PG5 26
PG6 27
PG7 28
PA5 56
PA6 57
PA7 58
CNTL0(WR)
59
CNTL1(RD)
60
CNTL2(BHE)
40
PD0 (ALE)
79
RESET
39
ADIO8
13 PG0 21
PA3 54
PA4 55
PA2 53
PA0 51
PA1 52
PB0 61
PB1 62
PB2 63
PB3 64
PB4 65
PB5 66
PB6 67
PB7 68
PC0 41
PC1 42
PC2 43
PC3 44
PC4 45
PC5 46
PC6 47
PC7 48
PE0 (TMS)
71
PE1 (TCK/ST)
72
PE2 (TDI)
73
PE3 (TDO)
74
PE4 (TSTAT/RDY)
75
PE5 (TERR)
76
PE7 (VBATON)
78
Vcc 29
Vcc 69
Vcc 9
GND
50 GND
49 GND
30 GND
8
GND
70
PD2 (CSI)
1PD1 (CLKIN)
80
PD3 (WRH)
2
PE6 (VSTBY)
77
Infineon C167CR
AD0 100
AD1 101
Vcc 109
AD2 102
AD3 103
AD4 104
AD5 105
AD6 106
AD7 107
AD8 108
AD9 111
AD10 112
AD11 113
AD12 114
AD13 115
AD14 116
AD15 117
EA 99
ALE 98
READY
97
WR/WRL 96
RD 95
Vcc 93
XTAL1
138
XTAL2
137
RSTIN 140
RSTOUT 141
NMI 142
P4.0/A16 85
A17 86
A18 87
A19 88
A20 89
A21 90
A22 91
P4.7/A23 92
P3.0/T0IN
65
P3.1/T6OUT
66
P3.2/CAPIN
67
P3.3/T3OUT
68
P3.4/T3EUD
69
P3.5/T4IN
70
P3.6/T3IN
73
P3.7/T2IN
74
P3.8/MRST
75
P3.9/MTSR
76
P3.10/TXD0
77
P3.11/RXD0
78
P3.12/BHE/WRH 79
P3.13/SCLK
80
P3.15/CLKOUT
81
P1L0 118
P1L1 119
P1L2 120
P1L3 121
P1L4 122
P1L5 123
P1L6 124
P1L7 125
P1H0 128
P1H1 129
P1H2 130
P1H3 131
P1H4 132
P1H5 133
P1H6 134
P1H7 135
P2.0/CC0IO 47
P2.1/CC1IO 48
P2.2/CC2IO 49
P2.3/CC3IO 50
P2.4/CC4IO 51
P2.5/CC5IO 52
P2.6/CC6IO 53
P2.7/CC7IO 54
P2.8/CC8IO/EX0IN 57
P2.9/CC9IO/EX1IN 58
P2.10/CC10IO/EX2IN 59
P2.11/CC11IO/EX3IN 60
P2.12/CC12IO/EX4IN 61
P2.13/CC13IO/EX5IN 62
P2.14/CC14IO/EX6IN 63
P2.15/CC15IO/EX7IN 64
P5.0/AN0
27
P5.1/AN1
28
P5.2/AN2
29
P5.3/AN3
30
P5.4/AN4
31
P5.5/AN5
32
P5.6/AN6
33
P5.7/AN7
34
P5.8/AN8
35
P5.9/AN9
36
P5.10/AN10/T6UED
39
P5.11/AN11/T5UED
40
P5.12/AN12/T6IN
41
P5.13/AN13/T5IN
42
P5.14/AN14/T4UED
43
P5.15/AN15/T2UED
44
P6.0/!CS0
1
P6.1/!CS1
2
P6.2/!CS2
3
P6.3/!CS3
4
P6.4/!CS4
5
P6.5/!HOLD
6
P6.6/!HLDA
7
P6.7/!BREQ
8
P7.0/POUT0
19
P7.1/POUT1
20
P7.2/POUT2
21
P7.3/POUT3
22
P7.4/CC28IO
23
P7.5/CC29IO
24
P7.6/CC30IO
25
P7.7/CC31IO
26
P8.0/CC16IO
9
P8.1/CC17IO
10
P8.2/CC18IO
11
P8.3/CC19IO
12
P8.4/CC20IO
13
P8.5/CC21IO
14
P8.6/CC22IO
15
P8.7/CC23IO
16
Vss
143
Vss
139
Vss
127
Vss
110
Vss
94
Vss
83
Vss
71
Vss
55
Vss
45
Vss
18
Agnd
38
Vcc 144
Vcc 136
Vcc 126
Vcc 82
Vcc 72
Vcc 17
Vcc 56
Vcc 46
Vref
37
ADIO[15:0]
A[19:16]
AI04954b
57/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 26. Interfacing the PSD with a C167CR
XTAL1
XTAL2
P8.0/CC16IO
P8.1/CC17IO
P8.2/CC18IO
P8.3/CC19IO
P8.4/CC20IO
P8.5/CC21IO
P8.6/CC22IO
P8.7/CC23IO
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
PF0
PF1
PF2
PF3
PF4
PF5
PF6
PF7
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PA0
PA2
PA1
PA3
PA4
PA5
PA6
PA7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0 (WR)
CNTL1 (RD)
CNTL2 (BHE)
PD0 (ALE)
PD1 (CLKIN)
PD2 (CSI)
RESET
RD
WR/WRL
P312/BHE/WRH
ALE
RESET
31
32
33
34
35
36
37
38
3
138
137
9
10
11
12
13
14
15
16
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
4
5
6
7
10
11
12
13
14
15
16
17
18
19
20
59
39
60
40
79
80
1
21
22
23
24
25
26
27
28
PSD
C167CR
A19-A16 A[19:16]
95
96
79
98
RD
WR
BHE
ALE
RESET
51
52
53
54
55
56
57
58
AI04955
AD15-AD0 AD[15:0]
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
61
62
63
64
65
66
67
68
41
42
43
44
45
46
47
48
PD3 (WRH)
2
PE0 (TMS)
PE1 (TCK/ST)
PE2 (TDI)
PE3 (TDO)
PE4 (TSTAT/RDY)
PE5 (TERR)
PE6 (VSTBY)
PE7 (VBATON)
71
72
73
74
75
76
77
78
8 30495070
GNDGNDGNDGNDGND
92969
VCC VCC VCC
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
100
101
102
103
104
105
106
107
108
111
112
113
114
115
116
117
P4.0/A16
P4.1/A17
P4.2/A18
P4.3/A19
85
86
87
88
140
EA 99
RSTIN
P7.0/POUT0
P7.1/POUT1
P7.2/POUT2
P7.3/POUT3
P7.4/CC28IO
P7.5/CC29IO
P7.6/CC30IO
P7.7/CC31IO
19
20
21
22
23
24
25
26
P6.0/!CS0
P6.1/!CS1
P6.2/!CS2
P6.3/!CS3
P6.4/!CS4
P6.5/!HOLD
P6.6/!HLDA
P6.7/!BREQ
1
2
3
4
5
6
7
8
A16
A17
A18
A19
A16
A17
A18
A19
P5.8/AN8
P5.9/AN9
P5.10/AN10/T6UED
P5.11/AN11/T5UED
P5.12/AN12/T6IN
P5.13/AN13
P5.14/AN14/T4UED
P5.15/AN15/T2UED
35
36
39
40
41
42
43
44
P5.0/AN0
P5.1/AN1
P5.2/AN2
P5.3/AN3
P5.4/AN4
P5.5/AN5
P5.6/AN6
P5.7/AN7
27
28
29
30
31
32
33
34
P3.8/MRST
P3.9/MTSR
P3.10/TXD0
P3.11/RXD0
P3.12
P3.13/SCLK
P3.15/CLKOUT
75
76
77
78
79
80
81
P3.0/T0IN
P3.1/T6OUT
P3.2/CAPIN
P3.3/T3OUT
P3.4/T3UED
P3.5/T4IN
P3.6/T3IN
P3.7/T2IN
65
66
67
68
69
70
73
74
Vref
READY
37
97
P1H7
P1H6
P1H5
P1H4
P1H3
P1H2
P1H1
P1H0
135
134
133
132
131
130
129
128
P1L7
P1L6
P1L5
P1L4
P1L3
P1L2
P1L1
P1L0
125
124
123
122
121
120
119
118
P2.0/CC0IO
P2.1/CC1IO
P2.2/CC2IO
P2.3/CC3IO
P2.4/CC4IO
P2.5/CC5IO
P2.6/CC6IO
P2.7/CC7IO
47
48
49
50
51
52
53
54
P2.8/CC8IO/EX0IN
P2.9/CC9IO/EX1IN
P2.10/CC10IO/EX2IN
P2.11/CC11IO/EX3IN
P2.12/CC12IO/EX4IN
P2.13/CC13IO/EX5IN
P2.14/CC14IO/EX6IN
P2.15/CC15IO/EX7IN
57
58
59
60
61
62
63
64
RSTOUT
NMI
141
142
P4.4/A20
P4.5/A21
P4.6/A22
P4.7/A23
89
90
91
92
143139127110 94 83 71 55 45 18
VssVssVssVssVssVssVssVssVssVss
AGND
38
144136129109 93 82 72 56 46 17
VccVccVccVccVccVccVccVccVccVcc
Vcc
PSD4256G6V
58/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
8-bit MCU Bus Interface Examp les
Figure 21, page 51 to Figure 30 show examples of
the basic connections between the PSD and some
popular MCUs. T he PSD Cont rol input pins are la -
beled as to the MCU function for which they are
configured. The MCU bus interface is specified us-
ing the PSDsoft Express Configuration.
80C31
Figure 21, page 51 shows the bus i nterface for the
80C31 which has an 8-bit, multiplexed address/
data bus. The lower address byte is multiplexed
with the data bus. The MCU control signals Pro-
gram Select Enable (PSEN, CNTL2), READ
Strobe (RD, CNTL1), and WRITE Strobe (WR,
CNTL0) may be used for accessing the internal
memory and I/O Ports blocks. Address Strobe
(ALE/AS, PD0) latches the address.
Figure 27. Interfacing the PSD with an 80C31
EA/VP
X1
X2
RESET
RESET
INT0
INT1
T0
T1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PC0
PC2
PC1
PC3
PC4
PC5
PC6
PC7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
RD
WR
PSEN
ALE/P
TXD
RXD
RESET
29
28
27
25
24
23
22
21
30
39
31
19
18
9
12
13
14
15
1
2
3
4
5
6
7
8
38
37
36
35
34
33
32
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
48
50
49
10
9
8
7
6
5
4
3
2
52
51
PSD
80C31
AD7-AD0 AD[7:0]
21
22
23
24
25
26
27
28
17
16
29
30
A8
A9
A10
A11
A12
A13
A14
A15
RD
WR
PSEN
ALE
11
10
RESET
20
19
18
17
14
13
12
11
AI02880C
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
80C251
The Intel 80C251 MCU features a user-config-
urable bus interface with four possible bus config-
urations, as shown in Table 41. The first
configuration is 80C31-c ompatible, and t he bus in-
terface to the PSD is identi cal to that shown in Fig-
ure 21, page 51. The second and third
configurations have the same bus connection as
shown in Figure 41, page 87. There is only one
READ Strobe (P SEN) connect ed to CNTL1 on the
PSD. The A16 connection to PA0 allows for a larg-
er address input to the PSD. T he fourth configura-
tion is shown in Figure 28, page 60. READ Strobe
(RD) is con nected to CNTL1 a nd Program Select
Enable (PSEN) is connected to CNTL2.
The 80C251 has two major operat ing modes :
Page Mode. Data (D7-D0) is multiplexed wit h ad-
dress (A15-A8). In a bus cycle where there is a
Page hit, Address Strobe (ALE/AS, PD0) is not ac-
tive and only addresses (A7-A0) are changing .
Non-Page Mode. The data is multiplexed with
the lower address byte and Address Strobe (ALE/
AS, PD0) is active in every bus cycle.
The PS D supports both modes. In Page Mode, the
PSD bus timing is identical to Non-Page Mode, ex-
cept the address hold time and setup time with re-
spect to Address Strobe (ALE/AS, PD0) is not
required. The PSD access time is measured from
address (A7-A0) valid to data invalid.
Table 41. 80C251 Configurations
Configuration 80C251 READ/WRITE Pins Connecting to PSD Pins Page Mode
1 WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Non-Page Mode, 80C31
compatible A7-A0 multiplex with
D7-D0
2 WR
PSEN only CNTL0
CNTL1 Non-Page Mode
A7-A0 multiplex with D7-D0
3 WR
PSEN only CNTL0
CNTL1 Page Mode
A15-A8 multiplex with D7-D0
4 WR
RD
PSEN
CNTL0
CNTL1
CNTL2
Page Mode
A15-A8 multiplex with D7-D0
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 28. Interfacing the PSD with the 80C251, with One READ Input
Figure 29. Interfacing the PSD with the 80C251, wi th R D and PSEN Inputs
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
32
26
43
42
41
40
39
38
37
36
24
25
27
28
29
30
31
33
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD14
AD15
AD13
AD11
AD12
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD15
ALE
WR
A16
RD
AD14
AD12
AD13
14
9
2
3
4
5
6
7
8
21
20
11
13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
X2
X1
P3.3/INT1
RST
EA
A161
P0.1
P0.0
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
PSEN
WR
RD/A16
PC0
PC1
PC3
PC4
PC5
PC6
PC7
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
80C251SB PSD
RESET
RESET
35
P3.4/T0
P3.5/T1
16
15
17
10
RESET
PC2
AI02881C
A171
ADIO0
ADIO1
ADIO2
ADIO3
ADIO4
ADIO5
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
ADIO12
ADIO13
ADIO14
ADIO15
CNTL0(WR)
CNTL1(RD)
CNTL2(PSEN)
PD0-ALE
PD1
PD2
RESET
32
26
43
42
41
40
39
38
37
36
24
25
27
28
29
30
31
33
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD14
AD15
AD13
AD11
AD12
A0
A1
A2
A3
A4
A5
A6
A7
AD8
AD9
AD10
AD11
AD15
ALE
WR
PSEN
RD
AD14
AD12
AD13
14
9
2
3
4
5
6
7
8
21
20
11
13
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P3.0/RXD
P3.1/TXD
P3.2/INT0
X2
X1
P3.3/INT1
RST
EA
P0.1
P0.0
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
ALE
PSEN
WR
RD/A16
PC0
PC1
PC3
PC4
PC5
PC6
PC7
19
18
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
7
6
5
4
3
2
52
51
80C251SB PSD
RESET
RESET
35
P3.4/T0
P3.5/T1
16
15
17
10
RESET
PC2
AI02882C
61/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
80C51XA
The Philips 80C51XA MCU family supports an 8-
or 16-bit, multiplexed bus that can have burst cy-
cles. Address bits (A3-A0) are not multiplexed,
while (A19-A4) are multiplexed with data bits
(D15-D0) in 16-bi t mode. In 8-bit mode, (A11-A 4)
are multiplexed wit h data bi ts (D7-D0).
The 80C51XA can be configured to operate in 8-
bit data mode (see Figure 30).
The 80C51XA improves bus throughput and per-
formance be executing burst cycles for code re-
trievals. In Burst Mode, address (A19-A4) are
latched internally by the PSD, whil e the 80C51XA
changes the A3-A0 signals to retrieve up to 16
bytes of code. The PSD access time is them mea-
sured from address A3-A0 valid to data invalid.
The PSD bus timing requireme nt in Burst Mode is
identical to the normal bus cycle, except the ad-
dress setup and hold time wit h respect to Address
Strobe (ALE/AS, PD0) does not apply.
Figure 30. Interfacing the PSD with the 80C51XA, 8-bit Data Bus
9
10
11
12
13
14
15
16
ADIO0
ADIO1
ADIO2
ADIO3
AD104
AD105
ADIO6
ADIO7
ADIO8
ADIO9
ADIO10
ADIO11
AD1012
AD1013
ADIO14
ADIO15
CNTL0(R_W)
CNTL1(E)
CNTL2
PD0AS
PD1
PD2
RESET
20
21
22
23
24
25
3
5
4
6
42
41
40
39
38
37
36
35
AD0
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A14
A15
A13
A11
A12
AD1
AD2
AD3
AD4
AD5
AD6
AD7
E
AS
R/W
XT
EX
RESET
IRQ
XIRQ
PA0
PA1
PA2
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
VRH
VRL
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC0
PC1
PC3
PC4
PC5
PC6
PC7
PD0
PD1
PD2
PD3
PD4
PD5
MODA
E
AS
R/W
31
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
48
8
9
10
49
50
47
8
7
17
19
18
34
33
32
43
44
45
46
47
48
49
50
52
51
30
29
28
27
29
28
27
25
24
23
22
21
20
19
18
17
14
13
12
11
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
7
6
5
4
3
2
52
51
MODB
2
68HC11
PSD
RESET
RESET
AD7-AD0
AD7-AD0
PC2
AI02884C
PSD4256G6V
62/104
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
68HC11
Figure 31 shows a bus interface to a 68HC11
where the PSD is configured in 8-bit, multiplexed
mode with E a nd R/W settings. The DPLD can be
used to generate the READ and WR signals for
external devices.
Figure 31. Interfacing the PSD with a 68HC11
63/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
I/O POR TS
There are seven programmable I/O ports: Ports A,
B, C, D, E, F and G. Each port pin is individually
user configurable, thus allowing multiple funct ions
per port. Th e ports are configured using PSDsoft
or by the MCU writing to on-chip registers in the
CSIOP space.
The topics discussed in this section are:
Gen e ra l Po rt a rch itecture
Port operating modes
Port Configuration Registers (PCR)
Port Data Registers
Individual Port functionality.
General Port Architecture
The general architecture of the I/O Port block is
shown in Figure 32, page 64. Individual Port archi-
tectures ar e shown in Figure 34, page 71 to Figure
36, page 74. In general, once the purpose for a
port pin has been defined, that pin is no longer
available for other purposes. Exceptions are not-
ed.
As shown in Figure 31, page 62, the ports contain
an output multiplexer whose select signals are
driven by t he conf iguration bit s in the Control Reg-
isters (Ports E, F and G only) and PS Ds oft Config-
uration. Inputs to the multiplexer include the
following:
Output data from the Data Out register
Latched address outputs
CPLD M acrocell output
External Chip Select from the CPLD.
The Port Data B uf fer (PDB) is a tri-state buffer t hat
allows only one source at a time to be read. The
Port Data Buffer (PDB) is connec ted to the Internal
Data Bus for feedback and can be read by the
MCU. The Data Out and Macrocel l outputs, Direc-
tion Register and Cont rol Register, and port pin in-
put are all connected to the Port Data Buffer
(PDB).
The Port pin’s tri-state output driver enable is con-
trolled b y a two input OR gate whose inputs come
from the CPLD AND Array enable product term
and the Direction Register. If the enable product
term of any of the Array outputs are not defined
and that port pin is no t defined as a CPLD output
in the PSDabel file, the Direction Register has sole
control of the buffer that drives t he port pin.
The conten ts of these registers can be alt ered by
the MCU. The Port Data Buffer (PDB) feedback
path a llows the M CU to che ck the contents of t he
registers.
Ports A, B, and C have embedded Input Macro-
cells (IMC). The Input Macrocells (IMC) can be
configured as latches, registers, or direct inputs to
the PLDs. The latches and registers are clocked
by Address Strobe (ALE/AS, PD0) or a product
term from the PLD AND Array. The outputs from
the Input Macrocells (IMC) drive the PLD input bus
and can be read by the MCU. See the section en-
titled “Input Macrocells (IMC)”, on page 44.
Port Operating Mode s
The I/O Ports have several modes of operation.
Some modes can be defined using PSDsoft , some
by the MCU writing to the registers in CSIOP
space, and some by both. The modes that can
only be defined using PSDsoft must be pro-
grammed into the device and c annot be c hanged
unless the device is reprogrammed. The modes
that can be changed by the MCU can be done so
dynamically at run-time. The PLD I/O, Data Port,
Address Input, Peripheral I/O and MCU RESET
Modes are the only modes that must be defined
before programming the device. All other modes
can be change d by the MCU at run-tim e. See Ap-
plication Note
AN1171
for mor e detail.
Table 43, page 6 6 summarizes which modes are
available on each port. Table 44, page 66 shows
how and where the different modes are config-
ured. Each of the port operating modes are de-
scribed in the following secti ons.
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figu re 3 2. Ge nera l I/O P ort A rchi tec ture
INTERNAL DATA BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
EXT CS
ALE
READ MUX
P
D
B
CPLD-INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
AI02885
65/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MCU I/O Mode
In the MCU I/O mode, the MCU uses the PSD
Por ts to expand its own I/O ports. By setting up the
CSIOP space, the ports on the PSD are mapped
into the MCU address space. The addresses of
the ports are listed in Table 6, page 17.
A port pin can be put into MCU I/O mode by writing
a 0 to the corresponding bit in the Control Register
(for Ports E, F and G). The MCU I/O direction may
be changed by writing to the corresponding bit in
the Direction Register, or by the output enable
product term. S ee the sec tion en titled “P ort Oper-
ating Modes”, on page 63. When the pin is config-
ured as an output, the content of the Data Out
Register drives the pin. When configured as an in-
put, the MCU can read the port input through the
Data In buf fer. See Fi gure 31, page 62.
Ports A, B and C do not have Control Registers,
and are in MCU I/O mode by default. They can be
used for PLD I/O if they are specified in PSDsoft.
PL D I/ O Mode
The P LD I/O Mode uses a po rt as an input to the
CPLD’s Input M acroc ells (IMC), and/ or as an out-
put from the CPLD’s Output Macrocells (OMC).
The output can be tri-stated wi th a control signal.
This output enable control signal can be defined
by a product ter m from the PLD, or by resett ing the
corresponding bit in the Direction Register to 0.
The corresponding bit in the Direction Register
must not be set to 1 if the pin is define d for a PLD
input signal in PSDsoft. The PLD I/O mode is
specified in PSDsoft by declaring the port pins,
and then specifying an equatio n in PSDsoft.
Address Out Mode
For MCUs with a multiplexed address/data bus,
Address Out mode can be used to drive latched
addresses onto the port pins. These port pins can,
in turn, drive external devices. Either the output
enable or the corresponding bi ts of both t he Direc-
tion Register and Control Register must be set to
a 1 for pins to use Address Out mode. This must
be done by the MCU at run-time. See Table 44,
page 66 for the address output pin assignment s on
Ports E, F and G for various MCUs.
Note: Do not drive address signals with Address
Out M ode t o an external memory device if it is in-
tended for the MCU to B oot from the external de-
vi ce . The M CU mu st firs t Bo ot fro m PS D me mo ry
so the Direction and Control register bits can be
set.
Table 42. Port Operating Modes
No te : 1. Can b e m ul tiplexed wit h other I/O funct i ons.
2. Available to Motorola 16-bit 683xx and HC16 families of MCUs.
Port Mode Port A Port B Port C Port D Port E Port F Port G
MCU I/O Yes Yes Yes Yes Yes Yes Yes
PLD I/O
McellA Outp uts
McellB Outp uts
Additional Ext. CS Outputs
PLD Inputs
Yes
No
No
Yes
Yes
Yes
No
Yes
No
No
Yes
Yes
No
No
No
Yes
No
No
No
No
No
No
Yes
Yes
No
No
No
No
Address Out No No No No
Yes (A7 –
0) Yes (A7 –
0)
Yes (A7 –
0)
or (A15 – 8)
Address In Yes Yes Yes Yes No Yes No
Data Port No No No No No Yes Yes
Peripheral I/O Yes No No Yes No Yes No
JTAG ISP No No No No Yes1 No No
MCU RESET Mode2No No No No No Yes Yes
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 43. Port Op erating Mod e Settings
Not e: 1. N/A = No t Appl ica b le
2. The direction of the Port A,B,C , and F pin s are contr ol l ed by the Direction Register OR ed with the indiv i dual output enable product
term (.oe) from the CPLD AND Ar ray.
3. Any of these three methods enables the JTA G pi ns on Por t E.
4. Con tr ol Regis ter setti ng is not applica ble to Ports A, B a nd C.
Table 44. I/O Port Latch ed Address Ou tput Assignm ents
Not e: 1. N/A = No t Appl ica b le.
Mode Defined in PSDsoft Control
Register
Setting
Direction
Register
Setting
VM Register
Setting JTAG Enable
MCU I/O Declare pins only 0 (Note 4)1 = output,
0 = input
(Note 2)N/A N/A
PLD I/O Declare pins and
Logic equations N/A (Note 2)N/A N/A
Data Port (Port F, G) Selected for MCU
with non-multiplexed
bus N/A N/A N/A N/A
Address Out
(Port E, F, G) Declare pins only 1 1 (Note 2)N/A N/A
Address In
(Port A, B, C, D, F)
Declare pins or Logic
equation for Input
Macrocells N/A N/A N/A N/A
Peripheral I/O
(Port F) Logic equations
(PSEL0 and PSEL1) N/A N/A PIO bit = 1 N/A
JTAG ISP 3Declare pins only N/A N/A N/A JTAG_Enable
MCU RESET Mode Specific pin logic
level N/A N/A N/A N/A
MCU Port E
(PE3-PE0) Port E
(PE7-PE4) Port F
(PF3-PF0) Port F
(PF7-PF4) Port G
(PG3-PG0) Port G
(PG7-PG4)
80C51XA N/A(1) Address
a7-a4 N/A Address
a7-a4 Address
a11-a 8 Address
a15-a12
80C251 N/A N/A N/A N/A Address
a11-a8 Address
a15-a12
All Other
MCUs with Multiplexed Bus Address
a3-a0 Address
a7-a4 Address
a3-a0 Address
a7-a4
Address
a11-a8
(a3-a0 for 8-
bit MCU)
Address
a15-a12
(a7-a4 for 8-
bit MCU)
67/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Address In Mode
For MCUs that have more than 16 address sig-
nals, the higher addresses can be connected to
Port A, B, C, D or F, and are routed as inputs to the
PLDs. The address input can be latched in the In-
put Macrocell (IMC) by Address Strobe (ALE/AS,
PD0). Any input that is included in the DPLD equa-
tions for the primary Flash memory, secondary
Flash memory or SRAM i s considered to be an ad-
dress input.
Data Port Mode
Ports F and G ca n be used as a data bus port for
a MCU with a non-multiplexed addre ss/data bu s.
The Dat a Port is connected to th e dat a bus of t he
MCU. The general I/O functions are disabled in
Ports F and G if the ports ar e configured as a Data
Port. Data Port mode is automatically configured
in PSDsoft when a non-multiplexed bus MCU is
selected.
Peripheral I/O Mode
Peripheral I/O mode can be used to interface with
external 8 -bit perip herals. I n this mode, al l o f Po rt
F serves as a tri -state, bi-directional data buffer for
the MCU. Peripheral I/O mode is enabled by set-
ting bit 7 of the VM Register to a 1. Figure 32
shows how Port A acts as a bi-directional buffer for
the MCU data bus if Peripheral I/O mode is en-
abled. An equation for PSEL0 and/or PSEL1 must
be specified in PSDsoft. The buffer is tri-stated
when PSEL0 or PSEL1 is not active.
Figure 33. Peripheral I/O Mode
RD
PSEL0
PSEL1
PSEL
VM REGISTER BIT 7
WR
PA0-PA7
D0-D7
DATA BUS
AI02886
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
JTAG In-System Program mi ng (ISP)
Port E is J TAG complia nt, and can be used for In-
System Programming (ISP). You can multiplex
JTAG operations with other functions on Port E
because In-System Programming (ISP) is not per-
formed during normal system operation. F or more
information on the JTAG Port, see the section en-
titled “RESET”, on page 33.
MCU RESET Mod e
Ports F and G can be configured to operate in
MCU RESET Mode. This mo de is available when
PSD is configured for the Motorola 16-bit 683xx
and HC16 family and is active only during reset.
At the rising edge of the RESET input, the MCU
reads the logic level on the data bus (D15-D0)
pins. The MCU then configures some of its I/O pin
functions according to the logic level input on the
data bus lines. Tw o dedicated buf fers are u sually
enabled during RESET t o drive the data bus lines
to the des ired logic level.
The PSD ca n repla ce the t wo buf fers by c onfigur-
ing Ports F and G to operate in MCU RESET
Mode. In this mode, the PSD will drive the pre-de-
fined logic level or data pattern on to the MCU data
bus when RE SET is act ive and there is no ongoing
bus cycle. After RESET, Ports F and G return to
the normal Data Port mode.
The MCU RESET Mode is enabled and configured
in PSDs oft. The u ser defines the log ic level (data
pattern) that will be drive out from Ports F and G
during RESET.
Port Configuration Registers (PCR)
Each Port has a set of Port Configuration Regis-
ters (PCR) used for confi guration. The contents of
the registers can be accessed by the MCU through
normal READ/WRITE bus cycles at the addresses
given in Table 6, page 17. The addresses in T able
6 are the offsets in hexad ecimal from the base of
the CSIOP register.
The pins of a port are individually configurabl e and
each bit in the register controls its respective pin.
For example, bit 0 in a register refers to bit 0 of its
port. The three Port Configuration Registers
(PCR), shown in Ta bl e 45, are us ed for setti ng the
Port configurations . The default Power-up state for
each register in Table 45 is 00 h.
Control Register
Any bit reset to '0' in the Control Register sets the
corresponding port pin to MCU I/O mo de, a nd a 1
sets it to Address O ut mode. T he default mode is
MCU I/O. Only Ports E, F and G have an associat -
ed Control Register.
Table 45. Port Configuration Registers (PCR)
No te : 1. See T able 49, page 69 for Drive Regi ster bit definit i on.
Register Name Port MCU Access
Control E, F, G WRITE/READ
Direction A, B, C, D, E, F, G WRITE/READ
Drive Select1A, B, D, E, G WRITE/READ
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Direction Register
The Direction Register controls the direction of
data flow in the I/O Ports. Any bit set t o 1 i n t he Di-
rection Register causes the corresponding pin to
be an output, and any bit set to 0 causes it to be
an input. The default mode for all port pins is input.
Figure 33, page 67 a nd Figure 35 , page 72 show
the Port Architecture diagrams for Ports A /B/C and
E/F/G, respectivel y. The direction of data flow for
Ports A, B , C and F are controlled n ot only by the
direction register, but also by the output enable
product term fr om the PLD A ND Array. If the ou t-
put enable product term is not act ive, the Direction
Register has sole control of a given pi n’s direction.
An example of a configuration for a Port with the
three least significant bit s set to output and the re-
mainder set to input is shown in Table 48. Since
Port D only cont ains four pins, the Di rection Reg-
ister for Port D has only the four least significant
bits active.
Drive Select Register
The Drive Select Register configures the pi n driver
as Open Drain or CMOS. An external pull-up resis-
tor should be used for pins configured as Open
Drain.
A pin can be configured as Open Drai n if its corre-
sponding bit in the Drive Select Register is set to a
1. The default pin drive is CMOS.
Table 49 shows the Drive Regist er for P ort s A , B,
D, E and G. It summarizes which pins can be con-
figured as Open Drain out puts.
Table 46. Port Pin Direction Control, Output
Enable P.T. Not Defin ed
Table 47. Port Pin Direction Control, Output
Enable P.T . Defined
Table 48. Port Direction Assignment Example
Table 49. Drive Register Pin Assignment
Note: 1. NA = Not Applicable.
Direction Register Bit Port Pin Mode
0 Input
1 Output
Direction
Register Bit Output Enable
P.T. Port Pin Mode
0 0 Input
0 1 Output
1 0 Output
1 1 Output
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
0 0 0 0 0 1 1 1
Drive
Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Port A Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port B Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port D NA(1) NA(1) NA(1) NA(1) Open
Drain Open
Drain Open
Drain Open
Drain
Port E Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
Port G Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain Open
Drain
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Port Data Registers
The Port Data Registers, shown in Table 50, are
used by the MCU to write data to or read data f rom
the ports. Table 50 shows the register name, the
ports having each register type, and MCU access
for each register type. The registers are described
next.
Data In
Port pins are connected dir ectly to the Data In buff-
er. In MCU I/O Input mode, the pin input is read
through the Data In buffer.
Data Out Register
Stores output dat a wri tten by t he MCU i n the MCU
I/O Output mode. The contents of the Register are
driven out to the pins if the Direction Register or
the output enable product term is set to 1. The
contents of the regi ster can also be read back by
the MCU.
Outp ut Macroc ell s (O M C )
The CPLD Ou tput Macrocel ls (OMC ) occupy a lo-
cation in the MCU’s address space. The MCU can
read the out put of the Output Macr ocell s (OMC). If
the Mask Mac rocell Reg ister bits are not set, writ-
ing to the Macrocell loads data to the Macrocell
flip-flops. S ee the section entitled “I/O PORTS”, on
page 63.
Mask Macrocell Register
Each M ask Macrocell Reg ister bit corresponds t o
an Output Macrocell (OMC) flip-flop. When the
Mask Macrocell Register bit is set to a 1, loading
data into the Output Macrocell (OMC) flip-flop is
blocked. The default value is 0, or unblock ed.
Input Macro cells (IMC)
The Input Macrocells (IMC) can be used t o latch or
store external inputs. The outputs of the Input
Macrocells (IMC) are routed to the PLD input bus,
and can be read by the MCU. See the section en-
titled “Input Macrocells (IMC)”, on page 44.
Table 50. Port Data Registers
Register Name Port MCU Access
Data In A, B, C, D, E, F,
GREAD – input on pin
Data Out A, B, C, D, E, F,
GWRITE/READ
Output Macrocell A, B READ – outputs of Macrocells
WRITE – loading Macrocells Flip-flop
Mask Macrocell A, B WRITE/READ – prevents loading into a given
Macrocell
Input Macrocell A, B, C READ – outputs of the Input Macrocells
Enable Out A, B, C, F READ – the output enable control of the port driver
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Enable Out
The Enable Out register can be read by the MCU.
It contains the output enable values for a given
port. A 1 indicates the driver is in output mode. A
0 indicates the driver is in tri-state and the pin is in
input mode.
Ports A, B and C – Fu nction ality and Structure
Ports A, B, and C have similar functionality and
s tr u ct ure, as s how n i n Fi g ur e 3 4 . T h e po r t s c a n be
configured to perform one or more of the follo wing
functions:
MCU I/O Mode
CPLD Output – Macrocells McellA7-McellA0
can be connecte d to Port A. Mcell B7 -Mcell B0
can be connecte d to Port B. Ext ernal Chip
Select (ECS7-E CS0) can be connected to Port
C or Port F.
CPLD Input – Via the Input Macro cells (IMC).
Address In – Additional high addre ss inputs
using the Input Mac rocells (IMC).
Open Drain – pins PA7-PA0 can be configured
to Open Drain mode.
Figu re 34. P ort A , B, and C Stru c ture
INTERNAL DATA BUS
DATA OUT
Register
DQ
DQ
WR
WR
MCELLA7-MCELLA0 (Port A)
MCELLB7-MCELLB0 (Port B)
Ext.CS (Port C)
ENABLE PRODUCT TERM (.OE)
READ MUX
P
D
B
CPLD-INPUT
DIR Register
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
MUX
PORT Pin
DATA OUT
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Port D – Function ality and Structure
Port D has four I/O pins. S ee Figure 35. Port D can
be configured t o perform one or more of the f ollow-
ing functions:
MCU I/O mode
CPLD Input – direct input to the CPLD, no Input
Macrocells (I MC )
Port D pins can be configured in PSDsoft as in-
put pins for other dedicated functions:
Address Strobe (ALE/ AS, PD0)
CLKIN (PD1) as input to the Macrocells Fli p-
flops and APD counter
PSD Chip Se lect Input (CSI , PD2 ) . Dr iving th is
signal High disables the Flash memory, SRAM
and CSIOP.
WRITE-Enable High-byt e (WRH, PD3) input, or
as DB E input from a MC68HC912.
Figure 35. Port D Structure
INTERNAL DATA BUS
DATA OUT
Register
DQ
DQ
WR
WR
READ MUX
P
D
B
CPLD-INPUT
DIR Register
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT D PIN
DATA OUT
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Port E – Fun ct i onality an d S truc ture
Port E can be configured to perform one or more
of the following functions (see Figure 36, page 74):
MCU I/O Mode
In-System Programming (ISP) – JTAG port can
be enabled for programming/ erase of the PSD
device. (See the section entitled “RESET”, on
page 33, for more informat ion on JTAG
programming.)
Open Drain – pins can be configured in Open
Drain Mode
Battery Backup features
PE6 can be c onfigured for a battery input sup-
ply, Voltage Standby (VSTBY).
PE7 can be configure d as a Battery-on Indi-
cator (VBATON), indicating when VCC is less
than VBAT.
Latched Ad dress output – Provide latched
address output.
Port F – Fun ctionality an d Structur e
Port F can be configured to perform one or more
of the following func tions:
MCU I/O Mode
CPLD Output – Ext ernal Chip Select (ECS7-
ECS0) can be connected to Port F or Port C.
CPLD Input – direct input to the CPLD, no Input
Macrocells (IMC)
Latched Ad dress output – Provide latched
address output as per Table 44, page 66.
Data Port – connected to D7-D0 when P ort F is
configured as Data Port for a non-multiplex ed
bus
Peripheral Mode
MCU RESET Mode – for 16-bit Mot orola 683xx
and HC16 MCUs
Port G – Functi onality and Structure
Port G can be configured to perform on e or more
of the following func tions:
MCU I/O Mode
Latched Ad dress output – Provide latched
address output as per Table 44, page 66.
Open Drain – pins can be configured in Open
Drain Mode
Data Port – connected t o D15-D8 when Port G
is configured as Data Por t for a non-multiplexed
bus
MCU RESET Mode – for 16-bit Mot orola 683xx
and HC16 MCUs
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figu re 36. P ort E , F, and G S truc ture
INTERNAL DATA BUS
DATA OUT
Register
DQ
D
G
Q
DQ
DQ
WR
WR
WR
ADDRESS
Ext. CS (Port F)
ENABLE PRODUCT TERM (.OE)
ALE
READ MUX
P
D
B
CPLD-INPUT (Port F)
CONTROL Register
DIR Register
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT Pin
DATA OUT
ADDRESS
A[7:0] OR A[15:8]
AI04938
ISP or Battery Back-Up (Port E)
Configuration Bit
75/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
POWER MANAGEMENT
The PSD de vice of fers configurab le power saving
options. These options may be used individually or
in combi nations, as follows:
All memory blocks i n a PSD (primary Flash
memor y, secondary Flash memory, and SRAM)
are built with power management technology. In
addition to using special silicon design
methodology, power management technology
puts the memories into Standby Mode when
address/data i nputs are not changing (zero DC
current). As soon as a tran sition occurs on an
input, the affected memory “wakes up”,
changes and latches its outputs, then goes back
to standby. The designer does
not
have to d o
anything special to achieve m emory Standby
Mode when no inputs are changing—it happens
automatically.
The PLD sections can also achieve Standby
Mode when its inputs are not chan ging, as de-
scribed for the Power Managem ent Mode Reg-
isters (PMMR), later.
The Automatic Power Down (APD) block allows
the PS D to reduce to standby current
automatical l y. The APD Unit als o blocks MCU
address/data signals from reaching t he
memories and PLDs. This feature i s available
on all PSD devices. The APD Unit is described
in more det ail in the section ent itled “Automatic
Power-down (APD) Unit and Power-down
Mode”, on page 76.
Built in logic monitors the Address Strobe of the
MCU for activity. If there is no activity for a cer-
tain period (the MCU is asleep), the APD Unit
initiates Power-down mode (if enabled). Once in
Power-down mode, all address/data signals are
blocked from reaching the PSD memories and
PLDs, and the memories are deselected inter-
nally. This all ows the memories and PLDs to re-
main in Standby Mode even if t he address /data
signals are changing state externally (noise,
other devices on the MCU bus, etc.). Keep in
mind that any unbl oc ked PL D input s igna ls that
are changing states keeps the PLD out of
Standby Mode, but not the memories.
PSD Chi p Se l e ct Input (C SI, PD2) can be used
to disable the i nternal memories, placing them
in Standby Mode even if inputs are changin g.
This feature does not block any i nternal signals
or disable the PLDs. This is a good alternative
to using the APD Unit, especially if your MCU
has a chip select output. There is a slight
penalty in memory access time when PSD Chip
Select Input (CSI, PD2) makes its initial
transition from deselected to selected.
The Power Managem ent Mod e Registers
(PMMR) can be written by the MCU at run-time
to manage power. All PSD devices support
“blocking bit s” in these registers that are set to
block designated signals from reachi ng bot h
PLDs. Current consumption of the PLDs is
directly related to the composite frequenc y of
the changes on their inputs ( see Figure 40,
page 82).
Significant power savings can be achieved by
blocking signals that are not used in DPLD or
CPLD logic equations at run-time. PSDsoft cre-
ates a fuse map that automatically blocks the
low add ress by te (A 7-A0) or the contro l si gnals
(CNTL0-CNTL2, ALE and WRITE-Enable High-
byte (WRH/DBE, PD3)) if none of these signals
are used in PLD logic equations.
PSD devices have a Turbo bit in PM MR0. This
bit can be set to turn the Turbo mode off (the de-
fault is with Turbo mode turned on). Whil e Turbo
mode is off, the PLDs can achieve standby cur-
rent when no PLD inputs are changing (zero DC
current). Even when inputs do change, signifi-
cant power can be saved at lower frequencies
(AC current), compared to when Turbo mode is
on. When the Turbo mode is on, there is a s ig-
nificant DC current component, and the AC
component is higher.
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Automatic Power-down (APD) Unit and Power-down Mode
The A PD Unit, shown in Figure 3 7, puts t he PSD
into Power-down mode by monitoring the activity
of Address Strobe (ALE/A S, PD0). If the APD Unit
is enabled, as s oon as act ivity on A ddres s S trobe
(ALE/AS, PD0) stops, a four bit counter starts
counting. If Address Strobe (ALE/AS, PD0) re-
mains inactive for fifteen clock periods of CLKIN
(PD1), Power-down (PDN) goes High, and the
PSD enters Power-down mode, as discussed
next.
Po we r-down Mode
By default, if you enable the APD Unit, Power-
down mod e is automatically enabled. The device
enters Power-down mode if Address Strobe (ALE/
AS, PD0) remains inactive for fifteen periods of
CLKIN (PD1).
The following should be kept in mind when the
PSD is in Power-down mode:
If Address Strobe (ALE/AS, PD0) starts pul sing
again, the PSD returns to normal operation. The
PSD also returns to normal operat ion if either
PSD Chip Selec t Input (CSI, PD2) is Low or the
Reset ( R ESET ) input is High.
The MCU address/data bus i s blocked from all
memory and PLDs.
Various signal s can be blocked (prior to Power-
down mode) from entering the PLDs by setting
the appropriate bits in the Power Management
Mode Registers (PMMR). The blocked signals
include MCU control signals and the common
CLKIN (PD1). Note that blocking CLKIN (PD1)
from the PLDs does not block CLKIN (PD1)
fr om the APD Unit.
All PSD memories enter St andby Mode and are
drawing standby current. However, the PLDs
and I/ O ports blocks do
not
go into Standby
Mode becaus e you do not want to have to wait
for the logic and I/O to “wake-up” before their
outputs can change. See Table 52, page 76 for
Power-down mode effect s on PSD port s.
Typical Standby current is or the order of µA .
This standby curren t value assum es that there
are no transitions on any PLD input.
Table 51. Effect of Po wer-down Mode on Ports
Figure 37. APD Unit
Table 52. PSD Timing and Standby Current During Power-down Mode
Note: 1. Power-dow n does not a ffect the operation o f the PLD. The PLD oper ation in thi s mo de is based o nl y on th e T urbo bit.
2. Typ i cal current consump tion assu ming no PL D i nputs ar e changi ng st ate and the PL D T urbo bi t is 0.
Port Function Pin Level
MCU I/O No Change
PLD Out No Change
Address Out Undefined
Data Port Tri-State
Peripheral I/O Tri-State
Mode PLD Propagation Delay
Memory Access
Time Access Recovery Time to
Normal Access Typical Standby
Current
Power-down Normal tPD (Note 1)No Access tLVDV 50 µA (Note 2)
APD EN
PMMR0 BIT 1=1
ALE
RESET
CSI
CLKIN
TRANSITION
DETECTION
EDGE
DETECT
APD
COUNTER
POWER DOWN
(PDN) Select
DISABLE BUS
INTERFACE
Secondary Flash
Memory Select
Primary Flash
Memory Select
SRAM Select
PD
CLR
PD
DISABLE Primary and Secondary
FLASH Memory and SRAM
PLD
AI04939
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Othe r Po wer S aving Options
The PSD offers other reduced power saving op-
tions that are independent of the Power-down
mode. Except for the SRAM Standby and PSD
Chip Select Input (CSI, PD2) features, they are en-
abled by setting bits in PMMR0 and PMMR2 (as
summarized in Table 23 and Tabl e 24, page 21).
PL D Power Manage m e nt
The power and spee d of the PLDs are con trolled
by the Turbo bit (bit 3) in PMMR0. By setting the
bit to 1, the Turbo mode is of f and the P LDs con-
sume the specified standby current when the in-
puts are not switching for an extended time of
70 ns. The propagation delay time is increased af-
ter the Turbo bit is s et to 1 (turned off) when the in-
puts change at a composite frequency of less than
15 MHz. When the Turbo bi t is reset t o '0' (turned
on), the PLDs run at full power and speed. The
Turbo bit affects the PLD’s D C power, AC powe r,
and propagation delay. See the AC and DC char-
acteristics tables for PLD timing values (Table 71).
Blocking MCU cont rol signals with the PMMR2 bit s
can further reduce PLD AC power consumption.
SRAM Stand by Mode (Battery Backup)
The PSD supports a battery backup mode in which
the content s of the SRAM are retained in the event
of a power l oss. The SRA M has V oltage Standby
(VSTBY, PE6) that can be connect ed to an exter nal
battery. When VCC becomes lower than VSTBY
then the PSD automatically connects to Voltage
Standby (VSTBY, PE6) as a power source to the
SRAM. The SRAM standby current (ISTBY) is typi-
cally 0.5 µA. The SRAM data retenti on voltage is
2V minimum. The Battery-on Indicator (VBATON)
can be routed to PE7. This signal indi cates when
the VCC has dropped below VSTBY, and that the
SRAM is running on battery power.
PSD Chip Sele ct Input (CSI, PD2 )
PD2 of Port D can be configured in PSDsoft as
PSD Chip Select Input (CSI). When Low, the sig-
nal selects and enables the internal primary Flash
memory, sec ondary F lash m em ory, SRA M , and I/
O blo cks for READ o r WRITE o p er ations involving
the PSD. A High on PSD Chip Select Input (CSI,
PD2) disables the primary Flash memory , second-
ary Flash memory, and SRAM, and reduces the
PSD power consumption. However, the PLD and
I/O signals remain operational when PSD Chip Se-
lect Input (CSI, P D2) is Hi gh.
There may be a timing penalty when using PSD
Chip Select Input (CSI, PD2) depending on the
speed grade of the PSD that you are using. See
the timing parameter tSLQV in Tabl e 71.
Inpu t Cl oc k
The PSD provides the option to turn off CLKIN
(PD1) to the PLD to save AC power consumption.
CLKIN (PD1) is an input to the PLD AND Array and
the Output Macrocells (OMC).
During Power-down mode, or, if CLKIN (PD1) is
not being used a s part of the PLD logic equation,
the clock should be disabled to save AC power.
CLKIN (PD1) is disconnected from the PLD AND
Array or the Macrocel l s block by setting bits 4 or 5
to a 1 in PMMR0.
Figure 38. Enable Power-down Flow Chart
Enable APD
Set PMMR0 Bit 1 = 1
PSD in Power
Down Mode
ALE/AS idle
for 15 CLKIN
clocks?
RESET
Yes
No
OPTIONAL
Disable desired inputs to PLD
by setting PMMR0 bits 4 and 5
and PMMR2 bits 0 to 6.
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Inpu t Control Si gn a l s
The PSD provides the option to turn off the ad-
dress input (A7-A0) and input control signals
(CNTL0, CNTL1, CNTL2, Address Strobe (ALE/
AS, PD0) and WRITE-Enable High-byte (WRH/
DBE, PD3)) to the PLD to save AC power con-
sumption. These signals are inputs to the PLD
AND Arr ay. During Power-down mode, or, if any of
them are not being used as part of the PLD logic
equation, these control signals should be disabled
to save AC power. They are disconnected from the
PLD AND A rray by setting bits 0, 2, 3, 4, 5 and 6
to a 1 in PMMR2.
Table 53. ADP Counter Opera tion
APD Enable Bit ALE PD Polarity ALE Level APD Counter
0 X X Not Counting
1 X Pulsing Not Counting
1 1 1 Counting (Generates PDN after 15 Clocks)
1 0 0 Counting (Generates PDN after 15 Clocks)
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
RESET TIMING AND DEVICE STATUS AT RESET
Power-on RESET
Upon Power-up, the PSD requires a Reset (RE-
SET) pulse of duration tNLNH-PO (minimum 1ms)
after VCC is steady. During this period, the device
loads internal configurations, clears some of the
registers and s ets the F lash mem ory into Opera t-
ing mode. After the ri sing edge of Reset (RESET),
the PSD remains in the RESET Mode for an a ddi-
tional period, tOPR (maximum 120 ns), before the
first memory access is al lowed .
The PSD Flash memory is reset to the READ
Mode upon Power-up. Sector Select (FS0-FS15
and CSBOOT0-CSBOOT3) must all be Low,
WRITE Strobe (WR/WRL, CNTL0) High, during
Power-on RESET for maximum security of the
data content s and to remove the possibility of data
being written on the first edge of WRITE Strobe
(WR/WRL, CNTL0). Any Flash memory WRITE
cycle initiation is prevented automatically when
VCC is below VLKO.
Warm RESET
Once the device is up and running, the device can
be reset with a pulse of a much shorter duration,
tNLNH (minimu m 150ns). T he same tOPR period is
needed before the device is operational after
Warm RESET. Figu re 39, page 80 show s the tim-
ing of the Power-up and Warm RESET.
I/O Pin, Register and PLD Status at RESET
Table 54 shows t he I/O p in, register and PL D sta-
tus during Power-on RESET, Warm RESET and
Power-down mode. PLD outputs are always valid
dur ing Warm RESET , and they are valid in Power-
on RESET once the internal PSD Configuration
bits are lo aded. This loading of PSD is c ompleted
typically lo ng before t he VCC ramps up to ope ra t-
ing level. On ce the P LD is acti ve, the state of t he
outputs are determined by equations specified in
PSDsoft.
RESET of Flash Memo ry Er ase and Program
Cycles
An external Reset (RESET) also resets the inter-
nal Flash memory state machine. During a Flash
memory Program or Erase cycle, Reset (RESET)
terminates the cycle and returns the Flash memo-
ry to the READ Mode within a period of tNLNH-A
(min imum 25µs).
Table 54. Status During Power-on RESET, Warm RESET, and Power-down Mode
No te : 1. The SR_code and Per ipheral M o de bits in the VM Register are al ways cleared to '0' on P ower-on RESET or Warm RESET.
Port Configuration Power-on RESET Warm Reset Power-down Mode
MCU I/O Input mode Input mode Unchanged
PLD Output Valid after internal PSD
configuration bits are
loaded Valid Depends on inputs to PLD
(addresses are blocked in
PD mode)
Address Out Tri-stated Tri-stated Not defined
Data Port Tri-stated Tri-stated Tri-stated
Peripheral I/O Tri-stated Tri-stated Tri-stated
Register Power-On Reset Warm Reset Power-down Mode
PMMR0 and PMMR2 Cleared to 0 Unchanged Unchanged
Macrocells Flip-flop status Cleared to 0 by internal
Power-On Reset Depends on .re and .pr
equations Depends on .re and .pr
equations
VM Register(1) Initialized, based on the
selection in PSDsoft
Configuration menu
Initialized, based on the
selection in PSDsoft
Configur ation menu Unchanged
All other registers Cleared to 0 Cleared to 0 Unchanged
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 39. Reset (RESET) Timin g
PROGRAMMING IN-CIRCUIT USING T HE JTAG SERIAL I NTERFACE
The JTAG Serial Interface on the PSD can be en-
abled on Port E (see Table 55). All memory blocks
(primary Flash memory and secondary Flash
memory), PLD logic, and PSD Configuration bits
may be programmed through the JTAG-ISC Serial
Interface. A blank device can be mounted on a
printed circuit boar d and programmed using J TAG
In-Syst em Programming (IS P).
The standard JTAG signals (IEEE 1149.1) are
TMS, TCK, T DI, and TDO. Two addit i onal signals,
TSTA T an d TERR , are optional JTAG ex tensions
used to speed up Program and Erase cycles.
By default, on a blank PSD (as shipped from the
factory, or after erasure), four pins on Port E are
enabled for the basic JTAG signals TMS, TCK,
TDI, and TDO
.
See Application Note
AN1153
for more details on
JTAG In-System Programming (ISP).
Standard JTAG Sign als
The standard JTAG signa ls (TMS, TCK , TDI, and
TDO) can be enabled by any of three different con-
ditions that are logically ORed. When enabled,
TDI, TDO, TCK, and TMS are inputs, waiting for a
se rial com mand from an ext ernal JTAG cont roller
device (such as FlashLINK or Automated Test
Equipment). When the enabling command is re-
ceived from the external JTAG controller device,
TDO becom es an output and the JTAG channel is
fully functional inside the PSD. The same com-
mand that enables the JTAG channel may option-
ally enable the two additional JTAG pins, T STAT
and TERR.
The following s ymbolic logic equat ion specifies the
conditions enabling the four basic JTAG pins
(TMS, TCK, TDI, and TDO) on their respective
Port E pi ns. F or purposes of di scussion, the logic
label JTAG_ON is used. When JTAG_ON is true,
the four pins are enabled for JTAG. When
JTAG_ON is false, the four pins can be used for
general PSD I/O.
JTAG_ON = PSDsoft_enabled +
/* An NVM configuration bit inside
the PSD is set by the designer in
the PSDsoft Configuration utili-
ty. This dedicates the pins for
JTAG at all times (compliant with
IEEE 1149.1 */
Microcontroller_enabled +
/* The microcontroller can set a
bit at run-time by writing to the
PSD register, JTAG Enable. This
register is located at address
CSIOP + offset C7h. Setting the
JTAG_ENABLE bit in this register
will enable the pins for JTAG use.
This bit is cleared by a PSD reset
or the microcontroller. See Table
21 for bit definition. */
PSD_product_term_enabled;
/* A dedicated product term (PT)
inside the PSD can be used to en-
able the JTAG pins. This PT has
the reserved name JTAGSEL. Once
defined as a node in PSDabel, the
designer can write an equation for
JTAGSEL. This method is used when
the Port E JTAG pins are multi-
plexed with other I/O signals. It
is recommended to tie logically
the node JTAGSEL to the JEN\ sig-
nal on the Flashlink cable when
multiplexing JTAG signals. See Ap-
plication Note 1153 for details.
*/
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
VCC VCC(min)
Power-On Reset Warm Reset
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
The sta te of t he PSD Res et (RE S ET) s ig nal does
not interrupt (or prevent) JTAG operations if the
JTAG pins are dedicated by an NVM c onf iguration
bit (via PSDsoft). However, Reset (RESET) will
prevent or interrupt JTAG operations if the JTAG
Enable R egister (as shown in Table 21, pag e 20)
is used to enable the JTAG pins.
The PSD supports JTAG In-System-Programma-
bility (ISP) commands, but not Boundary Scan.
ST’s PSDsoft software tool and FlashLINK JTAG
programming cable implement the JTAG In-Sys-
tem-Programmability (ISP) commands .
JTAG Extensions
TSTAT and TERR are two JTAG extension signals
enabled by a JTAG command received over the
four standard JTAG pins (TMS, TCK, TDI, and
TDO). They are used to speed Program and Erase
cycles by indicat ing status on PSD pins instead of
having to scan the status out serially using the
standard JTAG channel. See Application Note
AN1153
.
TERR indicates if an error has occurred when
erasing a sec tor or programming in Flash memory .
This signal g oes Low (active) whe n an Error con-
dition occurs, and stays Low until a specific JTA G
command is executed or a Reset (RESET) pulse
is received after an “ISC_DISABLE” command.
TSTAT behaves the same as Ready/Busy (PE4)
described in the section entitled “Ready/Busy
(PE4)”, on page 24. TSTAT is High when the
µPSD3200 Family device is in READ Mode (pri-
mary Flash memory and secondary Fl ash memory
contents can be read). TS TAT is Lo w when F lash
memory Program or Erase cycles are in progress,
and also when data is being written to t he second-
ary Flash mem ory.
TSTAT and TERR can be configured as open-
drain type signals with a JTAG command.
Note: The state of Reset (Reset) does not interrupt
(or prevent) JTAG operations if the JTAG signals
are dedicated by an NVM Configuration bit (via
PSDsoft). However, Reset (Reset) prevents or in-
terrupts JTAG operations if the JTAG Enable Reg-
ister (as shown in Table 21, page 20) is used to
enable the JTAG signal s.
Security and Flash memory Prote ction
When the security bit is set, the device cannot be
read on a Device Programmer or through the
JTAG Port. When using the JTAG Port, only a F ull
Chip Erase command is allowed.
All other Program, Erase and Verify commands
are blocked. Fu ll Chip Erase returns t he device t o
a non-sec ured blank state. The Security Bit can be
set in PSDsoft.
All primary Flash memory and secondary Flash
memory sectors can indi vidually be sector protect -
ed against erasure. The sector protect bits can be
set in PSDsoft.
Table 55. JTAG Port Signals
INITIAL DELIVERY STATE
When delivered from ST, the PSD device has all
bits in the memory and PLDs set to 1. The PSD
Configuration Regist er bits are set to 0. The code,
configuration, and PLD logic are loaded using the
programming procedure. Information for program-
ming the device is available directly from ST.
Please contact you r local sales representative.
Port E Pin JTAG Signals Description
PE0 TMS Mode Select
PE1 TCK Clock
PE2 TDI Serial Data In
PE3 TDO Serial Data Out
PE4 TSTAT Status
PE5 TERR Error Flag
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
AC/DC PARAMETERS
These tables describe the AD and DC parameters
of the µP S D3200 Fam ily:
DC Elect ri cal Specificati on
AC Timing Speci fication
PLD Timing
Combi nato rial Timing
Synchronous Clock Mod e
Async hronous Clock Mode
Input Macrocell Timing
MCU Ti ming
READ Ti ming
–WRITE Timing
Peripheral Mode Timing
Pow e r -d own and RESET Timing
The following are issues concern ing the parame-
ters presented:
In the DC specification the supply current is
given for different modes of oper ation. Before
calculatin g the total power consumpt ion,
determi ne the percentage of ti me that the PSD
is in each mode. Also, the supply power is
considerably different if t he Turbo bit is 0.
The AC power component gives t he PLD, Flash
memory, and S RAM mA/ MHz specification.
Figure 40 shows the PLD mA/MHz as a function
of the number of Product T erms (PT) used.
In the PLD timing parameters, add the required
delay when Turbo bit is 0.
Figure 40. PLD ICC / Fre qu e n c y Co nsumpti on
0
10
20
30
40
50
60 VCC = 3V
010155 20 25
ICC – (mA)
TURBO ON (100%)
TURBO ON (25%)
TURBO OFF
TURBO OFF
HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz)
PT 100%
PT 25%
AI04942
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 56. Examp le of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode On)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory
Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operat ional Mode s
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 54 PT
% of total product terms = 54/217 = 25%
Turbo Mode = ON
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE
+ %SRAM x 0.8 mA/MHz x Freq ALE
+ % PLD x 1.1 mA/MHz x Freq PLD
+ #PT x 200 µA/PT)
= 50 µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz
+ 0.15 x 0.8 mA/MHz x 4 MHz
+ 1.1 mA/MHz x 8 MHz
+ 54 x 0.2 mA/PT)
= 45 µA + 0.1 x (3.84 + 0.48 + 8.8 + 10.8 mA)
= 45 µA + 0.1 x 23.92
= 45 µA + 2.39 mA
= 2.43 mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT
= 0 mA.
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 57. Examp le of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode Off)
Conditions
Highest Composite PLD input frequency
(Freq PLD) = 8 MHz
MCU ALE frequency (Freq ALE) = 4 MHz
% Flash memory
Access = 80%
% SRAM access = 15%
% I/O access = 5% (no additional power above base)
Operat ional Mode s
% Normal = 10%
% Power-down Mode = 90%
Number of product terms used
(from fitter report) = 54 PT
% of total product terms = 54/217 = 25%
Turbo Mode = Off
Calculation (using typical values)
ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc))
= Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE
+ %SRAM x 0.8 mA/MHz x Freq ALE
+ % PLD x (from graph using Freq PLD))
= 50 µA x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz
+ 0.15 x 0.8 mA/MHz x 4 MHz
+ 15 mA)
= 45 µA + 0.1 x (3.84 + 0.48 + 15)
= 45 µA + 0.1 x 18.84
= 45 µA + 1.94 mA
= 1.98 mA
This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT
= 0 mA.
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
MAX I MUM R AT I N G
Stressing the device ab ove t he rati ng l isted in t he
Absolute Maximum Rati ngs” table may cause per-
manent damage to the device. These are stress
ratings only and operation of the device at t hes e or
any other con ditions ab ove those i ndicated i n the
Operating sections of this specification is not im-
plied. Exposure to Absolute Maximum Rating con-
ditions for extended periods may affect device
reliability. Refer also to the STMicroelectronics
SURE Program and other relevant quality docu-
ments.
Table 58. Absolute Maximum Rating s
Not e: 1. I PC/ JEDEC J- STD-02 0A
2. JED EC St d JESD22-A114A (C1=100 pF, R1=1500 , R2=500 )
Symbol Parameter Min. Max. Unit
TSTG Storage Temperature –65 150 °C
TLEAD Lead Temperature during Soldering (20 seconds max.)1235 °C
VIO Input and Output Voltage (Q = VOH or Hi-Z) –0.6 4.0 V
VCC Supply Voltage –0.6 4.0 V
VPP Device Programmer Supply Voltage –0.6 13.5 V
VESD Electrostatic Discharge Voltage (Human Body model) 2–2000 2000 V
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
DC AND AC PARAMETERS
This section summarizes the operating and m ea-
surement conditions, and the DC and AC charac-
teristics of the device. The parameters in the DC
and AC Characteristic tables that follow are de-
rived from tests performed under the Measure-
ment Conditions summarized in the relevant
tables. Des igners shoul d c heck that the operating
conditions i n their circuit match the meas urement
conditions when relying on the quoted parame-
ters.
Table 59. Operating Conditions
Table 60. AC Symbols for PLD Timing
Example : tAVLX Time from Address Valid to ALE Invalid.
Table 61. AC Measurement Conditions
Note: 1. Output Hi-Z i s defined as the poin t w here data o ut is no l onger driven.
Symbol Parameter Min. Max. Unit
VCC Supply Voltage 2.7 3.6 V
TAAmbient Operating Temperature (industrial) –40 85 °C
Ambient Operating Temperature (commercial) 0 70 °C
Signal Letters Signal Behavior
A Address Input t Time
C CEout Output L Logic Level Low or ALE
D Input Data H Logic Level High
E E Input V Valid
I Interrupt Input X No Longer a Valid Logic Level
L ALE Input Z Float
N RESET Input or Output PW Pulse Width
P Port Signal Output
RU
DS, LDS, DS, RD, PSEN Inputs
S Chip Select Input
TR/W
Input
W WR Input
BVSTBY Output
M Output Macrocell
Symbol Parameter Min. Max. Unit
CLLoad Capacitance 30 pF
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 62. Capacitance
Not e: 1. Sampled only, not 100% tested.
2. Typ i cal value s are for TA = 2 C and nomi nal su ppl y volta ges.
Figu re 41 . AC Measurement I/O W aveform Figure 42. AC Measurement Load Cir cui t
Figure 43. Switching Waveforms - Key
Symbol Parameter Test Condition Typ.2Max.Unit
CIN Input Capacitance (for input pins) VIN = 0V 46pF
COUT Output Capacitance (for input/
output pins) VOUT = 0V 812
pF
CVPP Capacitance (for CNTL2/VPP)V
PP = 0V 18 25 pF
0.9VCC
0V
Test Point 1.5V
AI04947
Device
Under Test
2.0 V
400
CL = 30 pF
(Including Scope and
Jig Capacitance) AI04948
WAVEFORMS INPUTS OUTPUTS
STEADY INPUT
MAY CHANGE FROM
HI TO LO
MAY CHANGE FROM
LO TO HI
DON'T CARE
OUTPUTS ONLY
STEADY OUTPUT
WILL BE CHANGING
FROM HI TO LO
WILL BE CHANGING
LO TO HI
CHANGING, STATE
UNKNOWN
CENTER LINE IS
TRI-STATE
AI03102
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 63. DC Characteristics
No te: 1. Reset (RESE T ) has hy s teres i s . V IL1 is valid at or below 0.2VCC –0.1. VIH1 is val i d at or abov e 0.8VCC.
2. CSI desel ected or in ternal PD is activ e.
3. PLD is in non-Turbo mode, and none of the inputs are switching.
4. Please see Fi gure 40, pa ge 82 for th e PLD current calculation.
5. IOUT = 0 mA
Note : 1. Con dit ions (i n add itio n t o thos e in Ta ble 5 9, VCC = 4.5 to 5. 5V) : VSS = 0V; CL fo r Port 0, A LE an d PSEN ou tput i s 100p F; CL fo r
other out puts is 80pF
Symbol Parameter Conditions Min. Typ. Max. Unit
VIH High Level Input Voltage 2.7V < VCC < 3.6V 0.7VCC VCC +0.5 V
VIL Low Level Input Voltage 2.7V < VCC < 3.6V –0.5 0.8 V
VIH1 RESET High Level Input Voltage (Note 1)0.8VCC VCC +0.5 V
VIL1 RESET Low Level Input Voltage (Note 1)–0.5 0.2VCC –0.1 V
VHYS RESET Pin Hysteresis 0.3 V
VLKO VCC (min) for Flash Erase and
Program 1.5 2.3 V
VOL Output Low Voltage IOL = 20 µA, VCC = 2.7V 0.01 0.1 V
IOL = 4 mA, VCC = 2.7V 0.15 0.45 V
VOH Output High Voltage Except
VSTBY On IOH = –20 µA, VCC = 2.7V 2.6 2.69 V
IOH = –1 mA, VCC = 2.7V 2.3 2.4 V
VOH1 Output High Voltage VSTBY On IOH1 = –1 µA VSTBY – 0. 8 V
VSTBY SRAM Standby Voltage 2.0 VCC V
ISTBY SRAM Standby Current VCC = 0V 0.5 1 µA
IIDLE Idle Current (VSTBY input) VCC > VSTBY –0.1 0.1 µA
VDF SRAM Data Retention Voltage Only on VSTBY 2V
I
SB Standby Supply Current
for Power-down Mode CSI >VCC –0.3V (Notes 2,3)50 100 µA
ILI Input Leaka ge Curren t VSS < VIN < VCC –1 ±0.1 1 µA
ILO Output Leakage Current 0.45 < VIN < VCC –10 ±5 10 µA
ICC (DC)
(Note 5)Operating
Supply Current
PLD Only
PLD_TURBO = Off,
f = 0 MHz (Note 3)0µA/
PT
PLD_TURBO = On,
f = 0 MHz 200 400 µA/
PT
Flash memory During Flash memory
WRITE/Erase Only 10 25 mA
Read only, f = 0 MHz 0 0 mA
SRAM f = 0 MHz 0 0 mA
ICC (AC)
(Note 5)
PLD AC Adder note 4
Flash memory AC Adder 1.2 1.8 mA/
MHz
SRAM AC Adder 0.8 1.5 mA/
MHz
89/104
PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 44. Input to Output Disable / Enable
Table 64 . CPLD Comb i natorial Ti m i ng
Table 65. CPLD Macrocell Synchr onous Clock Mode Timing
Note: 1. CL KI N (PD1) tCLCL = tCH + tCL.
Symbol Parameter Conditions -10 PT
Aloc Turbo
Off Unit
Min Max
tPD CPLD Input Pin/Feedback to
CPLD Combinatorial Output 38 + 4 + 20 ns
tEA CPLD Input to CPLD Output
Enable 43 + 20 ns
tER CPLD Input to CPLD Output
Disable 43 + 20 ns
tARP CPLD Register Clear or
Preset Delay 38 + 20 ns
tARPW CPLD Register Clear or
Preset Pulse Width 28 + 20 ns
tARD CPLD Array Delay Any
Macrocell 23 + 4 ns
Symbol Parameter Conditions -10 PT
Aloc Turbo
Off Unit
Min Max
fMAX
Maximum Frequency
External Feedback 1/(tS+tCO)22.7 MHz
Maximum Frequency
Internal Feedback (fCNT)1/(tS+tCO–10) 29.4 MHz
Maximum Frequency
Pipelined Data 1/(tCH+tCL)45.0 MHz
tSInput Setup Time 18 + 4 + 20 ns
tHInput Hold Time 0 ns
tCH Clock High Time Clock Input 11 ns
tCL Clock Low Time Clock Input 11 ns
tCO Clock to Output Delay Clock Input 26 ns
tARD CPLD Array Delay Any Macrocell 23 + 4 ns
tMIN Minimum Clock Period 1 tCH+tCL 22 ns
tER tEA
INPUT
INPUT TO
OUTPUT
ENABLE/DISABLE
AI02863
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 66. CPLD Macrocell Asynchronous Clock Mo de T iming
Figu re 45 . Sy nchronous Cloc k Mode Tim i ng – PLD
Fig ur e 46. As y nchron ou s RESET / Pr eset
Symbol Parameter Conditions -10 PT
Aloc Turbo
Off Unit
Min Max
fMAXA
Maximum Frequency
External Feedback 1/(tSA+tCOA)23.8 MHz
Maximum Frequency
Internal Feedback (fCNTA)1/(tSA+tCOA–10) 31.25 MHz
Maximum Frequency
Pipelined Data 1/(tCHA+tCLA)38.4 MHz
tSA Input Setup Time 8 + 4 + 20 ns
tHA Input Hold Time 10 ns
tCHA Clock High Time 15 + 20 ns
tCLA Clock Low Time 12 + 20 ns
tCOA Clock to Output Delay 34 + 20 ns
tARD CPLD Array Delay Any Macrocell 23 + 4 ns
tMINA Minimum Clock Period 1/fCNTA 32 ns
tCH tCL
tCO
tH
tS
CLKIN
INPUT
REGISTERED
OUTPUT
AI02860
tARP
REGISTER
OUTPUT
tARPW
RESET/PRESET
INPUT
AI02864
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 47. Asynchronous Clock Mode Ti ming (product term clock)
Figure 48. Input Macrocell Timing (Product Term Clock)
Table 67. Input Macroc ell Timin g
Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. AL E latch timings refer to tAVLX and tLXAX.
Symbol Parameter Conditions -10 PT
Aloc Turbo
Off Unit
Min Max
tIS Input Setup Time (Note 1)0ns
t
IH Input Hold Time (Note 1)25 + 20 ns
tINH NIB Input High Time (Note 1 )13 ns
tINL NIB Input Low Time (Note 1)12 ns
tINO NIB Input to Combinatorial
Delay (Note 1)55 + 4 + 20 ns
tCHA tCLA
tCOA
tHAtSA
CLOCK
INPUT
REGISTERED
OUTPUT
AI02859
tINH tINL
tINO
tIH
tIS
PT CLOCK
INPUT
OUTPUT
AI03101
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 68. Program, WRITE and Eras e Times
Not e: 1. Programmed t o all zero before erase.
2. The po l ling sta tus, DQ7, is vali d tQ7V QV tim e units bef ore the data byte, DQ0- DQ7, is valid for reading.
3. DQ7 is DQ15 for M otorola MCU with 16-bit data bus.
Figure 49. Peripheral I/O WRITE Timing Diagram
Symbol Parameter Min. Typ. Max. Unit
Flash Progr am 8.5 s
Flash Bulk Erase1 (pre-programmed) 330s
Flash Bulk Erase (not pre-program med ) 10 s
tWHQV3 Sector Erase (pre-programmed) 1 30 s
tWHQV2 Sector Erase (not pre-programmed) 2.2 s
tWHQV1 Byte Program 14 1200 µs
Program / Erase Cycles (per Sector) 100,000 cycles
tWHWLO Sector Erase Time-Out 100 µs
tQ7VQV DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling)2,3 30 ns
tDVQV (PF)
tWLQV (PF) tWHQZ (PF)
ADDRESS DATA OUT
A/D BUS
WR
PORT F
DATA OUT
ALE/AS
AI05741
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 50. READ T imi ng Diagram
Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode.
tAVLX tLXAX1
tLVLX
tAVQV
tSLQV
tRLQV tRHQX
tRHQZ
tELTL
tEHEL
tRLRH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
RD
(PSEN, DS)
E
R/W
AI02895
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Tabl e 69. RE AD Timing
Note: 1. RD timing has th e sam e timin g as DS, L DS, UDS , an d PSEN signal s.
2. RD an d PSEN have the same timing for 8031.
3. Any input used to sele ct an internal PSD function.
4. In multipl exed mode latched address generated from ADIO delay to address output on any Port.
5. RD timing has th e same tim in g as DS, LDS, and UDS signals.
Symbol Parameter Conditions -10 Turbo
Off Unit
Min Max
tLVLX ALE or AS Pulse Width 22 ns
tAVLX Address Setup Time (Note 3)7ns
t
LXAX Address Hold Time (Note 3)8ns
t
AVQV
Address Valid to Data Valid 2.7 < VCC < 3.6V
(Note 3)100 + 20 ns
Address Valid to Data Valid, 8031,
80251 3.0 < VCC < 3.6V
(Note 3)90 + 20 ns
tSLQV CS Valid to Data Valid 100 ns
tRLQV
RD to Data Valid 8-Bit Bus (Note 5)35 ns
RD or PSEN to Data Valid 8-Bit Bus,
8031, 80251 (Note 2)45 ns
tRHQX RD Data Hold Ti me (Note 1)0ns
t
RLRH RD Pulse Width 36 ns
tRHQZ RD to Data High-Z (Note 1)38 ns
tEHEL E Pulse Width 38 ns
tTHEH R/W Setup Time to Enable 10 ns
tELTL R/W Hold Time After Enable 0 ns
tAVPV Address Input Valid to
Address Output Delay (Note 4)35 ns
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figu re 51. WR I TE Ti m ing D ia gra m
tAVLX tLXAX
tLVLX
tAVWL
tSLWL
tWHDX
tWHAX
tELTL
tEHEL
tWLMV
tWLWH
tDVWH
tTHEH
tAVPV
ADDRESS
VALID
ADDRESS
VALID
DATA
VALID
DATA
VALID
ADDRESS OUT
tWHPV
STANDARD
MCU I/O OUT
ALE/AS
A/D
MULTIPLEXED
BUS
ADDRESS
NON-MULTIPLEXED
BUS
DATA
NON-MULTIPLEXED
BUS
CSI
WR
(DS)
E
R/ W
AI02896
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 70. WRITE Timing
Note: 1. Any input used to select an internal PSD function.
2. In mu l tiplexed m ode, latc hed add ress gen erated f rom A DIO delay to addres s output on any port .
3. WR has the sam e ti m i ng as E, LDS, UDS, WRL, and WRH signals.
4. Assuming data is stable before active WRITE signal.
5. Assuming WRITE is active before data becomes valid.
6. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory.
7. tWHA X is 11 ns when writing to the Output Macrocel l Registers.
Symbol Parameter Conditions -10 Unit
Min Max
tLVLX ALE or AS Pulse Width 22
tAVLX Address Setup Time (Note 1)7ns
t
LXAX Address Hold Time (Note 1)8ns
t
AVWL Address Valid to Leading
Edge of WR (Notes 1,3)15 ns
tSLWL CS Valid to Leading Edge of WR (Note 3)15 ns
tDVWH WR Data Setup Time (Note 3)40 ns
tWHDX WR Data Hold Time (Note 3,7)5ns
t
WLWH WR Pulse Width (Note 3)40 ns
tWHAX1 Trailing Edge of WR to Address Invalid (Note 3)8ns
t
WHAX2 Trailing Edge of WR to DPLD Address
Invalid (Note 3,6)0ns
t
WHPV Trailing Edge of WR to Port Output
Valid Using I/O Port Data Register (Note 3)45 ns
tDVMV Data Valid to Port Output Valid
Using Macrocell Register Preset/Clear (Notes 3,5)65 ns
tAVPV Address Input Valid to Address
Output Delay (Note 2)35 ns
tWLMV WR Valid to Port Output Valid Using
Macrocell Register Preset/Clear (Notes 3,4)65 ns
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figure 52. Peripheral I/O READ Timing Diagram
Table 71. Port F Peripheral Data Mode READ Timing
Symbol Parameter Conditions -10 Turbo
Off Unit
Min Max
tAVQVPF Address Valid to Data Valid (Note 3)50 + 20 ns
tSLQV–PF CSI Valid to Data Valid 50 + 20 ns
tRLQV–PF RD to Data Valid (Notes 1,4)35 ns
RD to Data Valid 8031 Mode 45 ns
tDVQV–PF Data In to Data Out Valid 34 ns
tQXRH–PF RD Data Hold Time 0 ns
tRLRH–PF RD Pulse Width (Note 1)35 ns
tRHQZ–PF RD to Data High-Z (Note 1)38 ns
tQXRH (PF)
tRLQV (PF)
tRLRH (PF)
tDVQV (PF)
tRHQZ (PF)
tSLQV (PF)
tAVQV (PF)
ADDRESS DATA VALID
ALE/AS
A/D BUS
RD
DATA ON PORT F
CSI
AI05740
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 72. Port F Peripheral Data Mo de WRITE Ti ming
Note: 1. RD has the sam e ti m i ng as DS, LDS, UDS , an d PSEN (in 8031 combined mode).
2. WR has the same timing as the E, LDS, UD S, WRL, and WRH signal s.
3. Any input used to se lect Port F Data Peripheral mo de.
4. Data i s al ready st able on Port F.
5. Data sta ble on ADIO pins to data on Port F.
Table 73. Power-down Timing
Table 74. Reset (RESET) Timin g
No te: 1. Reset (RESE T ) d oes not re set Flash memory Pr ogram or Erase cyc l es.
2. Warm RESET aborts Flash memory Program or Era se cy cl es, and put s t he device i n READ M ode.
Figure 53. Reset (RESET) Timing Diagram
Table 75. VSTBYON Timing
Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms.
Symbol Parameter Conditions -10 Unit
Min Max
tWLQV–PF WR to Data Propagation Delay (Note 2)40 ns
tDVQV–PF Data to Port A Data Propagation Delay (Note 5)35 ns
tWHQZ–PF WR Invalid to Port A Tri-state (Note 2)33 ns
Symbol Parameter Conditions -10 Unit
Min Max
tLVDV ALE Access Time from Power-down 128 ns
tCLWH Maximum Delay from APD Enable to
Internal PDN Valid Signal U sing CLKIN
(PD1) 15 * tCLCL1µs
Symbol Parameter Conditions Min Max Unit
tNLNH RESET Active Low Time 1300 ns
tNLNH–PO Power-on RESET Active Low Time 1 ms
tNLNH–A Warm RESET Active Low Time 225 µs
tOPR RESET High to Operational Device 300 ns
Symbol Parameter Conditions Min Typ Max Unit
tBVBH VSTBY Detection to VSTBYON Output High (Note 1)20 µs
tBXBL VSTBY Off Detection to VSTBYON Output
Low (Note 1)20 µs
tNLNH-PO tOPR
AI02866b
RESET
tNLNH
tNLNH-A tOPR
VCC VCC(min)
Power-On Reset Warm Reset
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PSD4256G6V
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Figu re 54. I SC Ti m i ng Di a gra m
Table 76. ISC Timing
No te : 1. For non-PL D P rogramming, Erase or in IS C by-pass mo de.
2. For Program or Erase PLD only.
Symbol Parameter Conditions -10 Unit
Min Max
tISCCF Clock (TCK, PC1) Frequency (except for
PLD) (Note 1)15 MHz
tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1)30 ns
tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1)30 ns
tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2)2 MHz
tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2)240 ns
tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2)240 ns
tISCPSU ISC Port Set Up Time 11 ns
tISCPH ISC Port Hold Up Time 5 ns
tISCPCO ISC Port Clock to Output 26 ns
tISCPZV ISC Port High-Impedance to Valid Output 26 ns
tISCPVZ ISC Port Valid Output to
High-Impedance 26 ns
ISCCH
TCK
TDI/TMS
ISC OUTPUTS/TDO
ISC OUTPUTS/TDO
t
ISCCL
t
ISCPH
t
ISCPSU
t
ISCPVZ
t
ISCPZV
tISCPCO
t
AI02865
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PART NUMBERING
Table 77. Ordering Information Scheme
For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device,
please contact the ST Sales Office nearest to you.
Example: PSD42 5 6 G 6 V 10 U I T
Device Type
PSD42 = Flash PSD with CPLD
SRAM Size
3 = 64Kbit
5 = 256Kbit
Flash Memory Size
5 = 4Mbit
6 = 8Mbit
I/O Count
G = 52 I/O
2nd Non-Volatile Memory
2 = 256Kbit Flash Memory
6 = 512Kbit Flash Memory
Operating Voltage
V = VCC = 2.7 to 3.6V
Speed
90 = 90ns
10 = 100ns
12 = 120ns
Package
U = TQFP80
Tempera ture Rang e
blank = 0 to 70°C (Commercial)
I = –40 to 85°C (Industrial)
Option
T = Tape & Reel Packing
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
PACKAGE MECHANICAL INF O RMATION
Figure 55. TQFP80 – 80-le ad Plastic Qua d Flatpack Packa ge Ou tline
Not e: Drawing is not to scale.
QFP-A
Nd
E1
CP
b
e
A2
A
N
LA1 α
D1
D
1
E
Ne
c
D2
E2
L1
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
Table 78. TQFP80 – 80-lead Plastic Quad Flatpack Package Mechanical Data
Symb mm inches
Typ Min Max Typ Min Max
A 1.60 0.063
A1 0.05 0.15 0.002 0.006
A2 1.40 1.35 1.45 0.055 0.053 0.057
b0.22 0.17 0.27 0.009 0.007 0.011
c 0.09 0.20 0.004 0.008
D 14.00 0.551
D1 12.00 0.472
D2 9.50 0.374
E 14.00 0.473
E1 12.00 0.394
E2 9.50 0.374
e 0.50 0.020
L 0.60 0.45 0.75 0.024 0.018 0.030
L1 1.00 0.039
α3.5 3.5 0°
n80 80
Nd 20 20
Ne 20 20
CP 0.08 0.003
103/104
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
APPENDIX A. PIN ASSIGNMENTS
Table 79. PSD425 6G6V TQFP 80
Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments Pin No. Pin
Assign
ments
1 PD2 21 PG0 41 PC0 61 PB0
2 PD3 22 PG1 42 PC1 62 PB1
3 AD0 23 PG2 43 PC2 63 PB2
4 AD1 24 PG3 44 PC3 64 PB3
5 AD2 25 PG4 45 PC4 65 PB4
6 AD3 26 PG5 46 PC5 66 PB5
7 AD4 27 PG6 47 PC6 67 PB6
8 GND 28 PG7 48 PC7 68 PB7
9VCC 29 VCC 49 GND 69 VCC
10 AD5 30 GND 50 GND 70 GND
11 AD6 31 PF0 51 PA0 71 PE0
12 AD7 32 PF1 52 PA1 72 PE1
13 AD8 33 PF2 53 PA2 73 PE2
14 AD9 34 PF3 54 PA3 74 PE3
15 AD10 35 PF4 55 PA4 75 PE4
16 AD11 36 PF5 56 PA5 76 PE5
17 AD12 37 PF6 57 PA6 77 PE6
18 AD13 38 PF7 58 PA7 78 PE7
19 AD14 39 RESET 59 CNTL0 79 PD0
20 AD15 40 CNTL2 60 CNTL1 80 PD1
PSD4256G6V
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This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
RE VISION HISTORY
Table 80. Document Revisio n History
Date Rev. Description of Revision
06-Aug-2001 1.0 Document written
13-Sep-2001 1.1 Package mechanical data updated
14-Dec-2001 1.2 Added 100ns specification; removed 90 and 120 ns specifications. Updated AC specification
and Port C and F functions
12-Aug-2002 1.3 Added 8-bit MCU Interface
14-Nov-2002 1.4 Update characteristics and features (Table 69, 77)
17-Nov-2003 1.5 Modify Instructions, correct part numbering (Table 29, 77)
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