PSD4256G6V Flash In-System Programmable (ISP) Peripherals for 8-bit or 16-bit MCUs PRELIMINARY DATA FEATURES SUMMARY DUAL BANK FLASH MEMORIES Figure 1. Package - 8Mbits of Primary Flash Memory (16 uniform sectors, 64Kbyte) - 512Kbits of Secondary Flash Memory with 4 sectors - Concurrent operation: READ from one memory while erasing and writing the other 256 KBITS OF SRAM (BATTERY-BACKED) PLD WITH MACROCELLS TQFP80 (U) - Over 3000 Gates of PLD: CPLD and DPLD - CPLD with 16 Output Macrocells (OMCs) and 24 Input Macrocells (IMCs) - DPLD - user defined internal chip select decoding - 100,000 Erase/Write Cycles of Flash Memory - 1,000 Erase/Write Cycles of PLD SEVEN I/O PORTS WITH 52 I/O PINS: - 15 Year Data Retention 52 individually configurable I/O port pins that can be used for the following functions: - MCU I/Os - PLD I/Os SINGLE SUPPLY VOLTAGE - 3V (+20%/-10%) MEMORY SPEED - Special function I/Os - 100ns Flash memory and SRAM access time for VCC = 3V (+20%/-10%) - l/O ports may be configured as open-drain outputs - 90ns Flash memory and SRAM access time for VCC = 3.3V (+/-10%) - Latched MCU address output HIGH ENDURANCE: IN-SYSTEM PROGRAMMING (ISP) WITH JTAG - Built-in JTAG compliant serial port allows fullchip In-System Programmability - Efficient manufacturing allow easy product testing and programming - Use low cost FlashLINK cable with PC PAGE REGISTER - Internal page register that can be used to expand the microcontroller address space by a factor of 256 PROGRAMMABLE POWER MANAGEMENT November 2003 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. Rev. 1.5 1/104 PSD4256G6V TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 In-System Programming (ISP) via JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSDsoft. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 PSD ARCHITECTURAL OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 MCU Bus Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ISP via JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 In-Application Programming (IAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Page Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DEVELOPMENT SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 REGISTER BIT DEFINITION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DETAILED OPERATION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Memory Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . . 24 Ready/Busy (PE4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Memory Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 INSTRUCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power-up Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 READ Memory Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 READ Primary Flash Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 READ Memory Sector Protection Status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Reading the Erase/Program Status Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Data Polling (DQ7) - DQ15 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Toggle Flag (DQ6) - DQ14 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 2/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Error Flag (DQ5) - DQ13 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Erase Time-out Flag (DQ3) - DQ11 for Motorola . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PROGRAMMING FLASH MEMORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Data Toggle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Unlock Bypass. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 ERASING FLASH MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Flash Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Suspend Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Resume Sector Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 SPECIFIC FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Flash Memory Sector Protect. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 RESET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset (RESET) Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 MEMORY SELECT SIGNALS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Configuration Modes for MCUs with Separate Program and Data Spaces . . . . . . . . . . . . . . . 35 Combined Space Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 80C31 Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 PAGE REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 MEMORY ID REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PLDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 The Turbo Bit in PSD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 DECODE PLD (DPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 COMPLEX PLD (CPLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Output Macrocell (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Product Term Allocator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 3/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Loading and Reading the Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 The OMC Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 The Output Enable of the OMC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 External Chip Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 MCU BUS INTERFACE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 PSD Interface to a Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 PSD Interface to a Non-Multiplexed, 16-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Data Byte Enable Reference for a 16-bit Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 16-bit MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 80C196 and 80C186 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 MC683xx and MC68HC16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 H8/300 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 MMC2001 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 C16x Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 8-bit MCU Bus Interface Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 80C31 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 80C251 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 80C51XA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 68HC11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 General Port Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Port Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 MCU I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 PLD I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Address Out Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Address In Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Data Port Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Peripheral I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 JTAG In-System Programming (ISP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 4/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V MCU RESET Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Port Configuration Registers (PCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Drive Select Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Port Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Data In. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Data Out Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Output Macrocells (OMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Mask Macrocell Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Input Macrocells (IMC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Enable Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Ports A, B and C - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Port D - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Port E - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Port F - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Port G - Functionality and Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 POWER MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Automatic Power-down (APD) Unit and Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Power-down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Other Power Saving Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PLD Power Management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 SRAM Standby Mode (Battery Backup). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PSD Chip Select Input (CSI, PD2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Input Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Input Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 RESET TIMING AND DEVICE STATUS AT RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Power-on RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 RESET of Flash Memory Erase and Program Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 5/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . . 80 Standard JTAG Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Security and Flash memory Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 6/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V SUMMARY DESCRIPTION The PSD family of memory systems for microcontrollers (MCUs) brings In-System-Programmability (ISP) to Flash memory and programmable logic. The result is a simple and flexible solution for embedded designs. PSD devices combine many of the peripheral functions found in MCU-based applications (8-bit or 16-bit), such as configurable memories, PLD logic, and I/O. PSD devices integrate an optimized Macrocell logic architecture. The Macrocell was created to address the unique requirements of embedded system designs. It allows direct connection between the system address/data bus, and the internal PSD registers, to simplify communication between the MCU and other supporting devices. The PSD family offers two methods to program the PSD Flash memory while the PSD is soldered to the circuit board: In-System Programming (ISP) via JTAG, and In-Application Programming (IAP). In-System Programming (ISP) via JTAG An IEEE 1149.1 compliant JTAG In-System Programming (ISP) interface is included on the PSD enabling the entire device (Flash memories, PLD, configuration) to be rapidly programmed while soldered to the circuit board. This requires no MCU participation, which means the PSD can be programmed anytime, even when completely blank. The innovative JTAG interface to Flash memories is an industry first, solving key problems faced by designers and manufacturing houses, such as: First time programming. How do I get firmware into the Flash memory the very first time? JTAG is the answer. Program the blank PSD with no MCU involvement. Inventory build-up of pre-programmed devices. How do I maintain an accurate count of preprogrammed Flash memory and PLD devices based on customer demand? How many and what version? JTAG is the answer. Build your hardware with blank PSDs soldered directly to the board and then custom program just before they are shipped to the customer. No more labels on chips, and no more wasted inventory. Expensive sockets. How do I eliminate the need for expensive and unreliable sockets? JTAG is the answer. Solder the PSD directly to the circuit board. Program first time and subsequent times with JTAG. No need to handle devices and bend the fragile leads. In-Application Programming (IAP) Two independent Flash memory arrays are included so that the MCU can execute code from one while erasing and programming the other. Robust product firmware updates in the filed are possible over any communication channel (e.g., CAN, Ethernet, UART, J1850) using this unique architecture. Designers are relieved of these problems: Simultaneous READ and WRITE to Flash memory. How can the MCU program the same memory from which it executing code? It cannot. The PSD allows the MCU to operate the two Flash memory blocks concurrently, reading code from one while erasing and programming the other during IAP. Complex memory mapping. How can I map these two memories efficiently? A programmable Decode PLD (DPLD) is embedded in the PSD MODULE. The concurrent PSD memories can be mapped anywhere in MCU address space, segment by segment with extremely high address resolution. As an option, the secondary Flash memory can be swapped out of the system memory map when IAP is complete. A built-in page register breaks the MCU address limit. Separate Program and Data space. How can I write to Flash memory while it resides in Program space during field firmware updates? My 80C51XA will not allow it. The PSD provides means to reclassify Flash memory as Data space during IAP, then back to Program space when complete. PSDsoft PSDsoft, a software development tool from ST, guides you through the design process step-bystep making it possible to complete an embedded MCU design capable of ISP/IAP in just hours. Select your MCU and PSDsoft takes you through the remainder of the design with point and click entry, covering PSD selection, pin definitions, programmable logic inputs and outputs, MCU memory map definition, ANSI-C code generation for your MCU, and merging your MCU firmware with the PSD design. When complete, two different device programmers are supported directly from PSDsoft: FlashLINK (JTAG) and PSDpro. 7/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 2. Logic Diagram Table 1. Pin Names VCC 8 PA0-PA7 8 PB0-PB7 3 8 CNTL0CNTL2 PC0-PC7 4 PD0-PD3 PSD4xxxGx 8 16 PE0-PE7 AD0-AD15 PA0-PA7 Port-A PB0-PB7 Port-B PC0-PC7 Port-C PD0-PD3 Port-D PE0-PE7 Port-E PF0-PF7 Port-F PG0-PG7 Port-G AD0-AD15 Address/Data CNTL0-CNTL2 Control RESET Reset VCC Supply Voltage VSS Ground 8 PF0-PF7 RESET 8 PG0-PG7 VSS AI04916 8/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V 61 PB0 62 PB1 63 PB2 64 PB3 65 PB4 66 PB5 67 PB6 69 VCC 68 PB7 70 GND 71 PE0 72 PE1 73 PE2 74 PE3 75 PE4 76 PE5 77 PE6 78 PE7 79 PD0 80 PD1 Figure 3. TQFP80 Connections 43 PC2 AD14 19 42 PC1 AD15 20 41 PC0 CNTL2 40 44 PC3 AD13 18 RESET 39 45 PC4 AD12 17 PF7 38 46 PC5 AD11 16 PF6 37 47 PC6 AD10 15 PF5 36 48 PC7 AD9 14 PF4 35 49 GND AD8 13 PF3 34 50 GND AD7 12 PF2 33 51 PA0 AD6 11 PF1 32 52 PA1 AD5 10 PF0 31 53 PA2 VCC 9 VCC 29 GND 30 54 PA3 GND 8 PG7 28 AD4 7 PG6 27 55 PA4 PG5 26 56 PA5 AD3 6 PG4 25 57 PA6 AD2 5 PG3 24 58 PA7 AD1 4 PG2 23 59 CNTL0 AD0 3 PG1 22 60 CNTL1 PD3 2 PG0 21 PD2 1 AI04943 9/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 2. TQFP80 Pin Description Pin Name ADIO0ADIO7 ADIO8ADIO15 CNTL0 CNTL1 Pin 3-7 10-12 13-20 59 60 Type Description I/O This is the lower Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the lower address bits, connect AD0-AD7 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A0-A7 to this port. 3. If you are using an 80C51XA in burst mode, connect A4/D0 through A11/D7 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. I/O This is the upper Address/Data port. Connect your MCU address or address/data bus according to the following rules: 1. If your MCU has a multiplexed address/data bus where the data is multiplexed with the address bits, connect A8-A15 or AD8-AD15 to this port. 2. If your MCU does not have a multiplexed address/data bus, connect A8-A15 to this port. 3. If you are using an 80C51XA in burst mode, connect A12/D8 through A19/D15 to this port. ALE or AS latches the address. The PSD drives data out only if the READ signal is active and one of the PSD functional blocks has been selected. The addresses on this port are passed to the PLDs. I The following control signals can be connected to this pin, based on your MCU: 1. WR - active Low, WRITE Strobe input. 2. R_W - active High, READ/active Low WRITE input. 3. WRL - active Low, WRITE to Low-byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. I The following control signals can be connected to this pin, based on your MCU: 1. 1RD - active Low, READ Strobe input. 2. E - E clock input. 3. DS - active Low, Data Strobe input. 4. LDS - active Low, Strobe for low data byte. This pin is connected to the PLDs. Therefore, these signals can be used in decode and other logic equations. CNTL2 40 I READ or other Control input pin, with multiple configurations. Depending on the MCU interface selected, this pin can be: 1. PSEN - Program Select Enable, active Low in code retrieve bus cycle (80C51XA mode). 2. BHE - High-byte enable, 16-bit data bus. 3. UDS - active Low, Strobe for high data byte, 16-bit data bus mode. 4. SIZ0 - Byte enable input. 5. LSTRB - Low Strobe input. This pin is also connected to the PLDs. RESET 39 I Active Low input. Resets I/O Ports, PLD Macrocells and some of the Configuration Registers and JTAG registers. Must be Low at Power-up. RESET also aborts any Flash memory Program or Erase cycle that is currently in progress. 51-58 I/O CMOS or Open Drain These pins make up Port A. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. CPLD Macrocell (McellA0-McellA7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). PA0-PA7 10/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Pin Name PB0-PB7 PC0-PC7 PD0 PD1 PD2 PD3 PE0 PE1 PE2 PE3 Pin Type Description 61-68 I/O CMOS or Open Drain These pins make up Port B. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. CPLD Macrocell (McellB0-McellB7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). 41-48 I/O CMOS These pins make up Port C. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs. 3. Latched, transparent or registered PLD inputs (can also be PLD input for address A16 and above). 79 I/O CMOS or Open Drain PD0 pin of Port D. This port pin can be configured to have the following functions: 1. ALE/AS input - latches address on ADIO0-ADIO15. 2. AS input - latches address on ADIO0-ADIO15 on the rising edge. 3. MCU I/O - standard output or input port. 4. Transparent PLD input (can also be PLD input for address A16 and above). 80 I/O CMOS or Open Drain PD1 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. CLKIN - clock input to the CPLD Macrocells, the APD Unit's Power-down counter, and the CPLD AND Array. 1 I/O CMOS or Open Drain PD2 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. PSD Chip Select Input (CSI). When Low, the MCU can access the PSD memory and I/O. When High, the PSD memory blocks are disabled to conserve power. The falling edge of this signal can be used to get the device out of Power-down mode. 2 I/O CMOS or Open Drain PD3 pin of Port D. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Transparent PLD input (can also be PLD input for address A16 and above). 3. WRH - for 16-bit data bus, WRITE to high byte, active low. 71 I/O CMOS or Open Drain PE0 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TMS Input for the JTAG Serial Interface. 72 I/O CMOS or Open Drain PE1 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TCK Input for the JTAG Serial Interface. 73 I/O CMOS or Open Drain PE2 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TDI input for the JTAG Serial Interface. 74 I/O CMOS or Open Drain PE3 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TDO output for the JTAG Serial Interface. 11/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Pin Name Pin Type Description 75 I/O CMOS or Open Drain PE4 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TSTAT output for the JTAG Serial Interface. 4. Ready/Busy output for parallel In-System Programming (ISP). 76 I/O CMOS or Open Drain PE5 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. TERR active Low output for the JTAG Serial Interface. 77 I/O CMOS or Open Drain PE6 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. VSTBY - SRAM standby voltage input for SRAM battery backup. 78 I/O CMOS or Open Drain PE7 pin of Port E. This port pin can be configured to have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address output. 3. Battery-on Indicator (VBATON). Goes High when power is being drawn from the external battery. 31-38 I/O CMOS or Open Drain These pins make up Port F. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. External Chip Select (ECS0-ECS7) outputs, or inputs to CPLD. 3. Latched address outputs. 4. Address A1-A3 inputs in 80C51XA mode (PF0 is grounded) 5. Data bus port (D0-D7) in a non-multiplexed bus configuration. 6. Peripheral I/O mode. 7. MCU RESET Mode. PG0-PG7 21-28 I/O CMOS or Open Drain These pins make up Port G. These port pins are configurable and can have the following functions: 1. MCU I/O - standard output or input port. 2. Latched address outputs. 3. Data bus port (D8-D15) in a non-multiplexed, 16-bit bus configuration. 4. MCU RESET Mode. VCC 9, 29, 69 Supply Voltage GND 8, 30, 49, 50, 70 Ground pins PE4 PE5 PE6 PE7 PF0-PF7 Note: Signal names that have multiple names or functions are defined using PSDsoft. 12/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PG0 - PG7 PF0 - PF7 AD0 - AD15 CNTL0, CNTL1, CNTL2 CLKIN PORT G PROG. PORT PORT F PROG. PORT ADIO PORT PROG. MCU BUS INTRF. PLD INPUT BUS CLKIN 82 8 CSIOP GLOBAL CONFIG. & SECURITY CLKIN PLD, CONFIGURATION & FLASH MEMORY LOADER JTAG SERIAL CHANNEL PORT A ,B & C 24 INPUT MACROCELLS PORT A & B 16 OUTPUT MACROCELLS 8 EXT CS TO PORT C or F PORT F 256 KBIT BATTERY BACKUP SRAM 512 KBIT SECONDARY FLASH MEMORY (BOOT OR DATA) 4 SECTORS 16 SECTORS 8 MBIT PRIMARY FLASH MEMORY RUNTIME CONTROL AND I/O REGISTERS PERIP I/O MODE SELECTS SRAM SELECT SECTOR SELECTS SECTOR SELECTS FLASH ISP CPLD (CPLD) FLASH DECODE PLD (DPLD) EMBEDDED ALGORITHM MACROCELL FEEDBACK OR PORT INPUT 82 PAGE REGISTER ADDRESS/DATA/CONTROL BUS PORT E PROG. PORT PORT D PROG. PORT PORT C PROG. PORT PORT B PROG. PORT PORT A PROG. PORT POWER MANGMT UNIT PE0 - PE7 PD0 - PD3 PC0 - PC7 PB0 - PB7 PA0 - PA7 VSTDBY (PE6 ) PSD4256G6V Figure 4. PSD Block Diagram AI04917 Note: Additional address lines can be brought in to the device via Port A, B, C, D, or F. This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 13/104 PSD4256G6V PSD ARCHITECTURAL OVERVIEW PSD devices contain several major functional blocks. Figure 4, page 13 shows the architecture of the PSD device family. The functions of each block are described briefly in the following sections. Many of the blocks perform multiple functions and are user configurable. Memory Each of the memory blocks is briefly discussed in the following paragraphs. A more detailed discussion can be found in the section entitled "Memory Blocks" on page 23. The 8Mbit primary Flash memory is the main memory of the PSD. It is divided into 16 equallysized sectors that are individually selectable. The 512Kbit secondary Flash memory is divided into 4 sectors. Each sector is individually selectable. The 256Kbit SRAM is intended for use as a scratch-pad memory or as an extension to the MCU SRAM. If an external battery is connected to the PSD's Voltage Standby (VSTBY, PE6) signal, data is retained in the event of power failure. Each memory block can be located in a different address space as defined by the user. The access times for all memory types includes the address latching and DPLD decoding time. PLDs The device contains two PLD blocks, the Decode PLD (DPLD) and the Complex PLD (CPLD), as shown in Table 2, page 10, each optimized for a different function. The functional partitioning of the PLDs reduces power consumption, optimizes cost/performance, and eases design entry. The DPLD is used to decode addresses and to generate Sector Select signals for the PSD internal memory and registers. The DPLD has combinatorial outputs, while the CPLD can implement more general user-defined logic functions. The CPLD has 16 Output Macrocells (OMC) and 8 combinatorial outputs. The PSD also has 24 Input Macrocells (IMC) that can be configured as inputs to the PLDs. The PLDs receive their inputs from the PLD Input Bus and are differentiated by their output destinations, number of product terms, and Macrocells. The PLDs consume minimal power. The speed and power consumption of the PLD is controlled by the Turbo Bit in PMMR0 and other bits in PMMR2. These registers are set by the MCU at run-time. There is a slight penalty to PLD propagation time when not in the Turbo mode. I/O Ports The PSD has 52 I/O pins divided among seven ports (Port A, B, C, D, E, F, and G). Each I/O pin can be individually configured for different functions. Ports can be configured as standard MCU I/ O ports, PLD I/O, or latched address outputs for MCUs using multiplexed address/data buses. The JTAG pins can be enabled on Port E for InSystem Programming (ISP). MCU Bus Interface The PSD easily interfaces with most 8-bit or 16-bit MCUs, either with multiplexed or non-multiplexed address/data buses. The device is configured to respond to the MCU's control pins, which are also used as inputs to the PLDs. ISP via JTAG Port In-System Programming (ISP) can be performed through the JTAG signals on Port E. This serial interface allows complete programming of the entire PSD MODULE device. A blank device can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO) can be multiplexed with other functions on Port E. Table 3 indicates the JTAG pin assignments. Table 3. PLD I/O Inputs Outputs Product Terms Decode PLD (DPLD) 82 17 43 Complex PLD (CPLD) 82 24 150 Name Table 4. JTAG Signals on Port E Port E Pins JTAG Signal PE0 TMS PE1 TCK PE2 TDI PE3 TDO PE4 TSTAT PE5 TERR 14/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V In-System Programming (ISP) Using the JTAG signals on Port E, the entire PSD device (memory, logic, configuration) can be programmed or erased without the use of the MCU. In-Application Programming (IAP) The primary Flash memory can also be programmed, or re-programmed, in-system by the MCU executing the programming algorithms out of the secondary Flash memory, or SRAM. The secondary Flash memory can be programmed the same way by executing out of the primary Flash memory. Table 5, page 15 indicates which programming methods can program different functional blocks of the PSD. Page Register The 8-bit Page Register expands the address range of the MCU by up to 256 times. The paged address can be used as part of the address space to access external memory and peripherals, or internal memory and I/O. The Page Register can also be used to change the address mapping of the Flash memory blocks into different memory spaces for IAP. Power Management Unit (PMU) The Power Management Unit (PMU) gives the user control of the power consumption on selected functional blocks based on system requirements. The PMU includes an Automatic Power-down (APD) Unit that turns off device functions during MCU inactivity. The APD Unit has a Power-down mode that helps reduce power consumption. The PSDalso has some bits that are configured at run-time by the MCU to reduce power consumption of the CPLD. The Turbo Bit in PMMR0 can be reset to '0' and the CPLD latches its outputs and goes to Standby Mode until the next transition on its inputs. Additionally, bits in PMMR2 can be set by the MCU to block signals from entering the CPLD to reduce power consumption. See the section entitled "POWER MANAGEMENT" on page 75 for more details. Table 5. Methods of Programming Different Functional Blocks of the PSD Functional Block JTAG-ISP Device Programmer IAP Primary Flash Memory Yes Yes Yes Secondary Flash memory Yes Yes Yes PLD Array (DPLD and CPLD) Yes Yes No PSD Configuration Yes Yes No 15/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V DEVELOPMENT SYSTEM The PSD family is supported by PSDsoft, a Windows-based software development tool (Windows-95, Windows-98, Windows-NT). A PSD design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD pin functions and memory map information. The general design flow is shown in Figure 5. PSDsoft is available from our web site (the address is given on the back page of this data sheet) or other distribution channels. PSDsoft directly supports two low cost device programmers form ST: PSDpro and FlashLINK (JTAG). Both of these programmers may be purchased through your local distributor/representative, or directly from our web site using a credit card. The PSD is also supported by third party device programmers. See our web site for the current list. Figure 5. PSDsoft Development Tool Choose MCU and PSD Automatically configures MCU bus interface and other PSD attributes Define PSD Pin and Node Functions Point and click definition of PSD pin functions, internal nodes, and MCU system memory map Define General Purpose Logic in CPLD C Code Generation Point and click definition of combinatorial and registered logic in CPLD. Access HDL is available if needed GENERATE C CODE SPECIFIC TO PSD FUNCTIONS Merge MCU Firmware with PSD Configuration A composite object file is created containing MCU firmware and PSD configuration MCU FIRMWARE HEX OR S-RECORD FORMAT USER'S CHOICE OF MICROCONTROLLER COMPILER/LINKER *.OBJ FILE PSD Programmer PSDPro, or FlashLINK (JTAG) *.OBJ FILE AVAILABLE FOR 3rd PARTY PROGRAMMERS (CONVENTIONAL or JTAG-ISC) AI04919 16/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PSD REGISTER DESCRIPTION AND ADDRESS OFFSETS Table 6 shows the offset addresses to the PSD Table 6 provides brief descriptions of the registers registers relative to the CSIOP base address. The in CSIOP space. The following sections give a CSIOP space is the 256 bytes of address that is almore detailed description. located by the user to the internal PSD registers. Table 6. Register Address Offset Register Name Data In Port Port Port Port Port Port Port Other(1) A B C D E F G 00 01 10 11 Control Description 30 40 41 Reads Port pin as input, MCU I/O input mode 32 42 43 Selects mode between MCU I/O or Address Out Data Out 04 05 14 15 34 44 45 Stores data for output to Port pins, MCU I/O output mode Direction 06 07 16 17 36 46 47 Configures Port pin as input or output Drive Select 08 09 19 38 49 Configures Port pins as either CMOS or Open Drain Input Macrocell 0A 0B 1A Enable Out 0C 0D Output Macrocells A 20 Output Macrocells B Mask Macrocells A Mask Macrocells B 1C Reads Input Macrocells Reads the status of the output enable to the I/ O Port driver 4C READ - reads output of Macrocells A WRITE - loads Macrocell Flip-flops READ - reads output of Macrocells B WRITE - loads Macrocell Flip-flops 21 22 Blocks writing to the Output Macrocells A 23 Blocks writing to the Output Macrocells B Flash Memory Protection 1 C0 Read only - Primary Flash Sector Protection Flash Memory Protection 2 C1 Read only - Primary Flash Sector Protection Flash Boot Protection C2 Read only - PSD Security and Secondary Flash memory Sector Protection JTAG Enable C7 Enables JTAG Port PMMR0 B0 Power Management Register 0 PMMR2 B4 Power Management Register 2 Page E0 Page Register VM E2 Places PSD memory areas in Program and/ or Data space on an individual basis. Memory_ID0 F0 Read only - SRAM and Primary memory size Memory_ID1 F1 Read only - Secondary memory type and size Note: 1. Other registers that are not part of the I/O ports. 17/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V REGISTER BIT DEFINITION All the registers of the PSD are included here, for reference. Detailed descriptions of these registers can be found in the following sections. Table 7. Data-In Registers - Ports A, B, C, D, E, F, and G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definitions (Read only registers): READ Port pin status when Port is in MCU I/O input mode. Table 8. Data-Out Registers - Ports A, B, C, D, E, F, and G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definitions: Latched data for output to Port pin when pin is configured in MCU I/O output mode. Table 9. Direction Registers - Ports A, B, C, D, E, F, and G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definitions: Portpin <i> 0 = Port pin <i> is configured in Input mode (default). Portpin <i> 1 = Port pin <i> is configured in Output mode. Table 10. Control Registers - Ports E, F, and G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definitions: Portpin <i> 0 = Port pin <i> is configured in MCU I/O mode (default). Portpin <i> 1 = Port pin <i> is configured in Latched Address Out mode. Table 11. Drive Registers - Ports A, B, D, E, and G Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definitions: Portpin <i> 0 = Port pin <i> is configured for CMOS Output driver (default). Portpin <i> 1 = Port pin <i> is configured for Open Drain output driver. Table 12. Enable-Out Registers - Ports A, B, C, and F Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port pin 7 Port pin 6 Port pin 5 Port pin 4 Port pin 3 Port pin 2 Port pin 1 Port pin 0 Note: Bit Definitions (Read only registers): Portpin <i> 0 = Port pin <i> is in tri-state driver (default). Portpin <i> 1 = Port pin <i> is enabled. 18/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 13. Input Macrocells - Ports A, B, and C Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IMcell 7 IMcell 6 IMcell 5 IMcell 4 IMcell 3 IMcell 2 IMcell 1 IMcell 0 Note: Bit Definitions (Read only registers): READ Input Macrocell (IMC7-IMC0) status on Ports A, B, and C. Table 14. Output Macrocells A Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0 Note: Bit Definitions: WRITE Register: Load MCellA7-MCellA0 with '0' or '1.' READ Register: Read MCellA7-MCellA0 output status. Table 15. Out Macrocells B Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0 Note: Bit Definitions: WRITE Register: Load MCellB7-MCellB0 with '0' or '1.' READ Register: Read MCellB7-MCellB0 output status. Table 16. Mask Macrocells A Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcella 7 Mcella 6 Mcella 5 Mcella 4 Mcella 3 Mcella 2 Mcella 1 Mcella 0 Note: Bit Definitions: McellA<i>_Prot 0 = Allow MCellA<i> flip-flop to be loaded by MCU (default). McellA<i>_Prot 1 = Prevent MCellA<i> flip-flop from being loaded by MCU. Table 17. Mask Macrocells B Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mcellb 7 Mcellb 6 Mcellb 5 Mcellb 4 Mcellb 3 Mcellb 2 Mcellb 1 Mcellb 0 Note: Bit Definitions: McellB<i>_Prot 0 = Allow MCellB<i> flip-flop to be loaded by MCU (default). McellB<i>_Prot 1 = Prevent MCellB<i> flip-flop from being loaded by MCU. Table 18. Flash Memory Protection Register 1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec7_Prot Sec6_Prot Sec5_Prot Sec4_Prot Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Note: Bit Definitions (Read only register): Sec<i>_Prot 1 = Primary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Primary Flash memory Sector <i> is not write protected. Table 19. Flash Memory Protections Register 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Sec15_Prot Sec14_Prot Sec13_Prot Sec12_Prot Sec11_Prot Sec10_Prot Sec9_Prot Sec8_Prot Note: Bit Definitions (Read only register): Sec<i>_Prot 1 = Primary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Primary Flash memory Sector <i> is not write protected. 19/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 20. Flash Boot Protection Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Security_Bit not used not used not used Sec3_Prot Sec2_Prot Sec1_Prot Sec0_Prot Note: Bit Definitions: Sec<i>_Prot 1 = Secondary Flash memory Sector <i> is write protected. Sec<i>_Prot 0 = Secondary Flash memory Sector <i> is not write protected. Security_Bit 0 = Security Bit in device has not been set. Security_Bit 1 = Security Bit in device has been set. Table 21. JTAG Enable Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used not used not used not used not used not used not used JTAGEnable Note: Bit Definitions: JTAGEnable 1 = JTAG Port is enabled. JTAGEnable 0 = JTAG Port is disabled. Table 22. Page Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PGR 7 PGR 6 PGR 5 PGR 4 PGR 3 PGR 2 PGR 1 PGR 0 Note: Bit Definitions: Configure Page input to PLD. Default is PGR7-PGR0 = '0.' 20/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 23. PMMR0 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used (set to 0) not used (set to 0) PLD MCells CLK PLD Array CLK PLD Turbo not used (set to 0) APD Enable not used (set to 0) Note: The bits of this register are cleared to zero following power-up. Subsequent Reset (RESET) pulses do not clear the registers. Bit Definitions: APD Enable 0 = Automatic Power-down (APD) is disabled. 1 = Automatic Power-down (APD) is enabled. PLD Turbo 0 = PLD Turbo is on. 1 = PLD Turbo is off, saving power. PLD Array CLK 0 = CLKIN to the PLD AND array is connected. Every CLKIN change powers up the PLD when Turbo Bit is off. 1 = CLKIN to the PLD AND array is disconnected, saving power. PLD MCells CLK 0 = CLKIN to the PLD Macrocells is connected. 1 = CLKIN to the PLD Macrocells is disconnected, saving power. Table 24. PMMR2 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used (set to 0) PLD Array WRH PLD Array ALE PLD Array CNTL2 PLD Array CNTL1 PLD Array CNTL0 not used (set to 0) PLD Array Addr Note: For Bit 4, Bit 3, Bit 2: See Table 35, page 46 for the signals that are blocked on pins CNTL0-CNTL2. Bit Definitions: PLD Array Addr 0 = Address A7-A0 are connected to the PLD array. 1 = Address A7-A0 are blocked from the PLD array, saving power. Note: In X A Mode, A3-A0 come from PF3-PF0, and A7-A4 come from ADIO7-ADIO4. PLD Array CNTL2 0 = CNTL2 input to the PLD AND array is connected. 1 = CNTL2 input to the PLD AND array is disconnected, saving power. PLD Array CNTL1 0 = CNTL1 input to the PLD AND array is connected. 1 = CNTL1 input to the PLD AND array is disconnected, saving power. PLD Array CNTL0 0 = CNTL0 input to the PLD AND array is connected. 1 = CNTL0 input to the PLD AND array is disconnected, saving power. PLD Array ALE 0 = ALE input to the PLD AND array is connected. 1 = ALE input to the PLD AND array is disconnected, saving power. PLD Array WRH 0 = WRH/DBE input to the PLD AND array is connected. 1 = WRH/DBE input to the PLD AND array is disconnected, saving power. Table 25. VM Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Peripheral mode not used (set to 0) not used (set to 0) FL_data Boot_data FL_code Boot_code SR_code Note: On RESET, Bits 1-4 are loaded to configurations that are selected by the user in PSDsoft. Bit 0 and Bit 7 are always cleared on RESET. Bit 0-4 are active only when the device is configured in 8051 Mode. Bit Definitions: SR_code 0 = PSEN cannot access SRAM in 80C51XA modes. 1 = PSEN can access SRAM in 80C51XA modes. Boot_Code 0 = PSEN cannot access Secondary NVM in 80C51XA modes. 1 = PSEN can access Secondary NVM in 80C51XA modes. FL_Code 0 = PSEN cannot access Primary Flash memory in 80C51XA modes. 1 = PSEN can access Primary Flash memory in 80C51XA modes. Boot_data 0 = RD cannot access Secondary NVM in 80C51XA modes. 1 = RD can access Secondary NVM in 80C51XA modes. FL_data 0 = RD cannot access Primary Flash memory in 80C51XA modes. 1 = RD can access Primary Flash memory in 80C51XA modes. Peripheral mode 0 = Peripheral mode of Port F is disabled. 1 = Peripheral mode of Port F is enabled. 21/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 26. Memory_ID0 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 S_size 3 S_size 2 S_size 1 S_size 0 F_size 3 F_size 2 F_size 1 F_size 0 Note: Bit Definitions: F_size[3:0] S_size[3:0] 0h = There is no Primary Flash memory 1h = Primary Flash memory size is 256Kbit 2h = Primary Flash memory size is 512Kbit 3h = Primary Flash memory size is 1Mbit 4h = Primary Flash memory size is 2Mbit 5h = Primary Flash memory size is 4Mbit 6h = Primary Flash memory size is 8Mbit 0h = There is no SRAM 1h = SRAM size is 16Kbit 2h = SRAM size is 32Kbit 3h = SRAM size is 64Kbit 4h = SRAM size is 128Kbit 5h = SRAM size is 256Kbit Table 27. Memory_ID1 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 not used (set to 0) not used (set to 0) B_type 1 B_type 0 B_size 3 B_size 2 B_size 1 B_size 0 Note: Bit Definitions: F_size[3:0] S_size[3:0] 0h = There is no Secondary NVM 1h = Secondary NVM size is 128Kbit 2h = Secondary NVM size is 256Kbit 3h = Secondary NVM size is 512Kbit 0h = Secondary NVM is Flash memory 1h = Secondary NVM is EEPROM 22/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V DETAILED OPERATION As shown in Figure 4, page 13, the PSD consists of six major types of functional blocks: Memory Blocks MCU Bus Interface I/O Ports Power Management Unit (PMU) JTAG-ISP Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable. Memory Blocks The PSD has the following memory blocks: - Primary Flash memory - Secondary Flash memory - SRAM The Memory Select signals for these blocks originate from the Decode PLD (DPLD) and are userdefined in PSDsoft. Table 28 summarizes the sizes and organizations of the memory blocks. Table 28. Memory Block Size and Organization Primary Flash Memory Secondary Flash Memory SRAM Sector Number Sector Size (Bytes) Sector Select Signal Sector Size (Bytes) Sector Select Signal SRAM Size (Bytes) SRAM Select Signal 0 64K FS0 16K CSBOOT0 32K RS0 1 64K FS1 8K CSBOOT1 2 64K FS2 8K CSBOOT2 3 64K FS3 32K CSBOOT3 4 64K FS4 5 64K FS5 6 64K FS6 7 64K FS7 8 64K FS8 9 64K FS9 10 64K FS10 11 64K FS11 12 64K FS12 13 64K FS13 14 64K FS14 15 64K FS15 Total 1024K 16 Sectors 64K 4 Sectors 32K 23/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Primary Flash Memory and Secondary Flash memory Description a Flash memory block is being written to, or when The primary Flash memory is divided evenly into 8 a Flash memory block is being erased. The output sectors. The secondary Flash memory is divided is a '1' (Ready) when no WRITE or Erase cycle is into 4 sectors of different size. Each sector of eiin progress. ther memory block can be separately protected from Program and Erase cycles. Memory Operation Flash memory may be erased on a sector-by-secThe primary Flash memory and secondary Flash tor basis, and programmed word-by-word. Flash memory are addressed through the MCU Bus Insector erasure may be suspended while data is terface. The MCU can access these memories in read from other sectors of the block and then reone of two ways: sumed after reading. The MCU can execute a typical bus WRITE or During a Program or Erase cycle in Flash memory, READ operation just as it would if accessing a the status can be output on the Ready/Busy pin RAM or ROM device using standard bus cycles. (PE4). This pin is set up using PSDsoft. The MCU can execute a specific instruction that Memory Block Select Signals consists of several WRITE and READ operations. This involves writing specific data The DPLD generates the Select signals for all the patterns to special addresses within the Flash internal memory blocks (see the section entitled memory to invoke an embedded algorithm. "PLDs", on page 37). Each of the sectors of the priThese instructions are summarized in Table 29, mary Flash memory has a Select signal (FS0page 25. FS15) which can contain up to three product terms. Each of the sectors of the secondary Flash Typically, the MCU can read Flash memory using memory has a Select signal (CSBOOT0READ operations, just as it would read a ROM deCSBOOT3) which can contain up to three product vice. However, Flash memory can only be erased terms. Having three product terms for each Select and programmed using specific instructions. For signal allows a given sector to be mapped in differexample, the MCU cannot write a single byte dient areas of system memory. When using a MCU rectly to Flash memory as one would write a byte with separate Program and Data space to RAM. To program a word into Flash memory, (80C51XA), these flexible Select signals allow dythe MCU must execute a Program instruction, then namic re-mapping of sectors from one memory test the status of the Programming event. This staspace to the other before and after IAP. The tus test is achieved by a READ operation or polling SRAM block has a single Select signal (RS0). Ready/Busy (PE4). Ready/Busy (PE4) Flash memory can also be read by using special This signal can be used to output the Ready/Busy instructions to retrieve particular Flash device instatus of the PSD. The output is a '0' (Busy) when formation (sector protect status and ID). 24/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 29. 16-bit Instructions FS0-FS15 or CSBOOT0CSBOOT3 Cycle 1 READ(5) 1 "Read" RD @ RA READ Main Flash ID(6, 13) 1 READ Sector Protection(6,8,13) Instruction(14) Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 AAh@ XAAAh 55h@ X554h 90h@ XAAAh Read ID @ XX02h 1 AAh@ XAAAh 55h@ X554h 90h@ XAAAh Read 00h or 01h @ XX04h Program a Flash Word(13) 1 AAh@ XAAAh 55h@ X554h A0h@ XAAAh PD@ PA Flash Sector Erase(7,13) 1 AAh@ XAAAh 55h@ X554h 80h@ XAAAh AAh@ XAAAh 55h@ X554h 30h@ SA 30h(7)@ next SA Flash Bulk Erase(13) 1 AAh@ XAAAh 55h@ X554h 80h@ XAAAh AAh@ XAAAh 55h@ X554h 10h@ XAAAh Suspend Sector Erase(11) 1 B0h@ XXXXh Resume Sector Erase(12) 1 30h@ XXXXh RESET(6) 1 F0h@ XXXXh Unlock Bypass 1 AAh@ XAAAh 55h@ X554h 20h@ XAAAh Unlock Bypass Program(9) 1 A0h@ XXXXh PD@ PA Unlock Bypass Reset(10) 1 90h@ XXXXh 00h@ XXXXh Note: 1. All bus cycles are WRITE bus cycles, except the ones with the "Read" label 2. All values are in hexadecimal: X = "Don't care." Addresses of the form XXXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data read from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR , CNTL0). PA is an even address for PSD in word programming mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS15 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High). 3. Sector Select (FS0 to FS15 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft. 4. Only address bits A11-A0 are used in instruction decoding. 5. No Unlock or instruction cycles are required when the device is in the READ Mode 6. The RESET instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High. 7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80s. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0) = (1,0). 9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 14. All WRITE bus cycles in an instruction are byte-WRITE to an even address (XAAAh or X554h). A Flash memory Program bus cycle writes a word to an even address. 25/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 30. 8-bit Instructions FS0-FS7 or CSBOOT0CSBOOT3 Cycle 1 READ(5) 1 "Read" RD @ RA READ Main Flash ID(6, 13) 1 READ Sector Protection(6,8,13) Instruction(14) Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 AAh@ 555h 55h@ AAAh 90h@ 555h READ ID@ 01h 1 AAh@ 555h 55h@ AAAh 90h@ 555h Read 00h or 01h @ 02h Program a Flash Word(13) 1 AAh@ 555h 55h@ AAAh A0h@ 555h PD@ PA Flash Sector Erase(7,13) 1 AAh@ 555h 55h@ AAAh 80h@ 555h AAh@ 555h 55h@ AAAh 30h@ SA 30h(7)@ next SA Flash Bulk Erase(13) 1 AAh@ 555h 55h@ AAAh 80h@ 555h AAh@ 555h 55h@ AAAh 10h@ 555h Suspend Sector Erase(11) 1 B0h@ XXXh Resume Sector Erase(12) 1 30h@ XXXh RESET(6) 1 F0h@ XXXh Unlock Bypass 1 AAh@ 555h 55h@ AAAh 20h@ 555h Unlock Bypass Program(9) 1 A0h@ XXXh PD@ PA Unlock Bypass Reset(10) 1 90h@ XXXh 00h@ XXXh Note: 1. All bus cycles are WRITE bus cycles, except the ones with the "Read" label 2. All values are in hexadecimal: X = "Don't care." Addresses of the form XXXh, in this table, must be even addresses RA = Address of the memory location to be read RD = Data read from location RA during the READ cycle PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of WRITE Strobe (WR , CNTL0). PA is an even address for PSD in word programming mode. PD = Data word to be programmed at location PA. Data is latched on the rising edge of WRITE Strobe (WR, CNTL0) SA = Address of the sector to be erased or verified. The Sector Select (FS0-FS7 or CSBOOT0-CSBOOT3) of the sector to be erased, or verified, must be Active (High). 3. Sector Select (FS0 to FS7 or CSBOOT0 to CSBOOT3) signals are active High, and are defined in PSDsoft. 4. Only address bits A11-A0 are used in instruction decoding. 5. No Unlock or instruction cycles are required when the device is in the READ Mode 6. The RESET instruction is required to return to the READ Mode after reading the Flash ID, or after reading the Sector Protection Status, or if the Error Flag Bit (DQ5/DQ13) goes High. 7. Additional sectors to be erased must be written at the end of the Sector Erase instruction within 80s. 8. The data is 00h for an unprotected sector, and 01h for a protected sector. In the fourth cycle, the Sector Select is active, and (A1,A0) = (1,0). 9. The Unlock Bypass instruction is required prior to the Unlock Bypass Program instruction. 10. The Unlock Bypass Reset Flash instruction is required to return to reading memory data when the device is in the Unlock Bypass mode. 11. The system may perform READ and Program cycles in non-erasing sectors, read the Flash ID or read the Sector Protection Status when in the Suspend Sector Erase mode. The Suspend Sector Erase instruction is valid only during a Sector Erase cycle. 12. The Resume Sector Erase instruction is valid only during the Suspend Sector Erase mode. 13. The MCU cannot invoke these instructions while executing code from the same Flash memory as that for which the instruction is intended. The MCU must retrieve, for example, the code from the secondary Flash memory when reading the Sector Protection Status of the primary Flash memory. 14. All WRITE bus cycles in an instruction are byte-WRITE to an even address (555h or AAAh). A Flash memory Program bus cycle writes a word to an even address. 26/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V INSTRUCTIONS An instruction consists of a sequence of specific operations. Each received byte is sequentially decoded by the PSD and not executed as a standard WRITE operation. The instruction is executed when the correct number of bytes are properly received and the time between two consecutive bytes is shorter than the time-out period. Some instructions are structured to include READ operations after the initial WRITE operations. The instruction must be followed exactly. Any invalid combination of instruction bytes or time-out between two consecutive bytes while addressing Flash memory resets the device logic into READ Mode (Flash memory is read like a ROM device). The PSD supports the instructions summarized in Table 29, page 25: Erase memory by chip or sector Suspend or resume sector erase Program a Word RESET to READ Mode READ Primary Flash Identifier value READ Sector Protection Status Bypass These instructions are detailed in Table 29, page 25. For efficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and are followed by an instruction byte or confirmation byte. The coded cycles consist of writing the data AAh to address XAAAh during the first cycle and data 55h to address X554h during the second cycle (unless the Bypass instruction feature is used, as described later). Address signals A15A12 are "Don't care" during the instruction WRITE cycles. However, the appropriate Sector Select signal (FS0-FS15, or CSBOOT0-CSBOOT3) must be selected. The primary and secondary Flash memories have the same instruction set (except for READ Primary Flash Identifier). The Sector Select signals determine which Flash memory is to receive and execute the instruction. The primary Flash memory is selected if any one of its Sector Select signals (FS0-FS15) is High, and the secondary Flash memory is selected if any one of its Sector Select signals (CSBOOT0-CSBOOT3) is High. Power-up Condition The PSD internal logic is reset upon Power-up to the READ Mode. Sector Select (FS0-FS15 and CSBOOT0-CSBOOT3) must be held Low, and WRITE Strobe (WR/WRL, CNTL0) High, during Power-up for maximum security of the data contents and to remove the possibility of data being written on the first edge of WRITE Strobe (WR/ WRL, CNTL0). Any WRITE cycle initiation is locked when VCC is below VLKO. READ Under typical conditions, the MCU may read the primary Flash memory, or secondary Flash memory, using READ operations just as it would a ROM or RAM device. Alternately, the MCU may use READ operations to obtain status information about a Program or Erase cycle that is currently in progress. Lastly, the MCU may use instructions to read special data from these memory blocks. The following sections describe these READ functions. READ Memory Contents Primary Flash memory and secondary Flash memory are placed in the READ Mode after Power-up, chip reset, or a Reset Flash instruction (see Table 29, page 25). The MCU can read the memory contents of the primary Flash memory, or the secondary Flash memory by using READ operations any time the READ operation is not part of an instruction. READ Primary Flash Identifier The primary Flash memory identifier is read with an instruction composed of 4 operations: 3 specific WRITE operations and a READ operation (see Table 29, page 25). The identifier for the primary Flash memory is E7h. The secondary Flash memory does not support this instruction. READ Memory Sector Protection Status The Flash memory Sector Protection Status is read with an instruction composed of four operations: three specific WRITE operations and a READ operation (see Table 29, page 25). The READ operation produces 01h if the Flash memory sector is protected, or 00h if the sector is not protected. The sector protection status for all NVM blocks (primary Flash memory, or secondary Flash memory) can be read by the MCU accessing the Flash Protection and Flash Boot Protection registers in PSD I/O space. See the section entitled "Flash Memory Sector Protect", on page 33, for register definitions. 27/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Reading the Erase/Program Status Bits The PSD provides several status bits to be used by the MCU to confirm the completion of an Erase or Program cycle of Flash memory. These status bits minimize the time that the MCU spends performing these tasks and are defined in Table 31. The status byte resides in an even location, and can be read as many times as needed. Also note that DQ15-DQ8 is an even byte for Motorola MCUs with a 16-bit data bus. For Flash memory, the MCU can perform a READ operation to obtain these status bits while an Erase or Program instruction is being executed by the embedded algorithm. See the section entitled "PROGRAMMING FLASH MEMORY", on page 30, for details. Table 31. Status Bits DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Data Polling Toggle Flag Error Flag X Erase Timeout X X X Table 32. Status Bits for Motorola 16-bit MCU DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 Data Polling Toggle Flag Error Flag X Erase Timeout X X X Notes:X = Not guaranteed value, can be read either '1' or '0.' DQ15-DQ0 represent the Data Bus bits, D15-D0. FS0-FS15/CSBOOT0-CSBOOT3 are active High. 28/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Data Polling (DQ7) - DQ15 for Motorola When erasing or programming in Flash memory, the Data Polling Bit (DQ7/DQ15) outputs the complement of the bit being entered for programming/ writing on the DQ7/DQ15 Bit. Once the Program instruction or the WRITE operation is completed, the true logic value is read on the Data Polling Bit (DQ7/DQ15) (in a READ operation). Data Polling is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). It must be performed at the address being programmed or at an address within the Flash memory sector being erased. During an Erase cycle, the Data Polling Bit (DQ7/DQ15) outputs a '0.' After completion of the cycle, the Data Polling Bit (DQ7/DQ15) outputs the last bit programmed (it is a '1' after erasing). If the location to be programmed is in a protected Flash memory sector, the instruction is ignored. If all the Flash memory sectors to be erased are protected, the Data Polling Bit (DQ7/DQ15) is reset to '0' for about 100s, and then returns to the value from the previously addressed location. No erasure is performed. Toggle Flag (DQ6) - DQ14 for Motorola The PSD offers another way for determining when the Flash memory Program cycle is completed. During the internal WRITE operation and when either FS0-FS15 or CSBOOT0-CSBOOT3 is true, the Toggle Flag Bit (DQ6/DQ14) toggles from 0 to '1' and '1' to '0' on subsequent attempts to read any word of the memory. When the internal cycle is complete, the toggling stops and the data read on the Data Bus D0-D7 is the value from the addressed memory location. The device is now accessible for a new READ or WRITE operation. The cycle is finished when two successive READs yield the same output data. The Toggle Flag Bit (DQ6/DQ14) is effective after the fourth WRITE pulse (for a Program instruction) or after the sixth WRITE pulse (for an Erase instruction). If the location to be programmed belongs to a protected Flash memory sector, the instruction is ignored. If all the Flash memory sectors selected for erasure are protected, the Toggle Flag Bit (DQ6/DQ14) toggles to '0' for about 100s and then returns to the value from the previously addressed location. Error Flag (DQ5) - DQ13 for Motorola During a normal Program or Erase cycle, the Error Flag Bit (DQ5/DQ13) is reset to '0.' This bit is set to '1' when there is a failure during a Flash memory Program, Sector Erase, or Bulk Erase cycle. In the case of Flash memory programming, the Error Flag Bit (DQ5/DQ13) indicates the attempt to program a Flash memory bit, or bits, from the programmed state, 0, to the erased state, '1,' which is not a valid operation. The Error Flag Bit (DQ5/ DQ13) may also indicate a Time-out condition while attempting to program a word. In case of an error in a Flash memory Sector Erase or Word Program cycle, the Flash memory sector in which the error occurred or to which the programmed location belongs must no longer be used. Other Flash memory sectors may still be used. The Error Flag Bit (DQ5/DQ13) is reset after a RESET instruction. A RESET instruction is required after detecting an error on the Error Flag Bit (DQ5/DQ13). Erase Time-out Flag (DQ3) - DQ11 for Motorola The Erase Time-out Flag Bit (DQ3/DQ11) reflects the time-out period allowed between two consecutive Sector Erase instructions. The Erase Time-out Flag Bit (DQ3/DQ11) is reset to '0' after a Sector Erase cycle for a period of 100s + 20% unless an additional Sector Erase instruction is decoded. After this period, or when the additional Sector Erase instruction is decoded, the Erase Time-out Flag Bit (DQ3/DQ11) is set to '1.' 29/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PROGRAMMING FLASH MEMORY Flash memory must be erased prior to being programmed. The MCU may erase Flash memory all at once or by-sector. Although erasing Flash memory occurs on a sector or device basis, programming Flash memory occurs on a word basis. The primary and secondary Flash memories require the MCU to send an instruction to program a word or to erase sectors (see Table 29, page 25). Once the MCU issues a Flash memory Program or Erase instruction, it must check the status bits for completion. The embedded algorithms that are invoked inside the PSD support several means to provide status to the MCU. Status may be checked using any of three methods: Data Polling, Data Toggle, or Ready/Busy (PE4) signal. Data Polling Polling on the Data Polling Bit (DQ7/DQ15) is a method of checking whether a Program or Erase cycle is in progress or has completed. Figure 6 shows the Data Polling algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location of the word to be programmed in Flash memory to check the status. The Data Polling Bit (DQ7/DQ15) becomes the complement of the corresponding bit of the original data word to be programmed. The MCU continues to poll this location, comparing data and monitoring the Error Flag Bit (DQ5/DQ13). When the Data Polling Bit (DQ7/DQ15) matches the corresponding bit of the original data, and the Error Flag Bit (DQ5/DQ13) remains '0,' the embedded algorithm is complete. If the Error Flag Bit (DQ5/DQ13) is '1,' the MCU should test the Data Polling Bit (DQ7/ DQ15) again since the Data Polling Bit (DQ7/ DQ15) may have changed simultaneously with the Error Flag Bit (DQ5/DQ13) (see Figure 6). The Error Flag Bit (DQ5/DQ13) is set if either an internal time-out occurred while the embedded algorithm attempted to program the location or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the word that was written to the Flash memory with the word that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 6 still applies. However, the Data Polling Bit (DQ7/DQ15) is '0' until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5/ DQ13) indicates a time-out condition on the Erase cycle, a 0 indicates no error. The MCU can read any even location within the sector being erased to get the Data Polling Bit (DQ7/DQ15) and the Error Flag Bit (DQ5/DQ13). PSDsoft generates ANSI C code functions that implement these Data Polling algorithms. Figure 6. Data Polling Flowchart START READ DQ5 and DQ7 (DQ13 and DQ15) at Valid Even Address DQ7 (DQ15) = Data7 (Data15) Yes No No DQ5 (DQ13) =1 Yes READ DQ7 (DQ15) DQ7 (DQ15) = Data7 (Data15) Yes No Program or Erase Cycle failed Program or Erase Cycle is complete Issue RESET instruction AI04920 30/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Data Toggle Checking the Toggle Flag Bit (DQ6/DQ14) is another method of determining whether a Program or Erase cycle is in progress or has completed. Figure 7 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm within the PSD begins. The MCU then reads the location to be programmed in Flash memory to check the status. The Toggle Flag Bit (DQ6/DQ14) toggles each time the MCU reads this location until the embedded algorithm is complete. The MCU continues to read this location, checking the Toggle Flag Bit (DQ6/DQ14) and monitoring the Error Flag Bit (DQ5/DQ13). When the Toggle Flag Bit (DQ6/DQ14) stops toggling (two consecutive READs yield the same value), and the Error Flag Bit (DQ5/DQ13) remains '0,' the embedded algorithm is complete. If the Error Flag Bit (DQ5/DQ13) is '1,' the MCU should test the Toggle Flag Bit (DQ6/DQ14) again, since the Toggle Flag Bit (DQ6/DQ14) may have changed simultaneously with the Error Flag Bit (DQ5/DQ13) (see Figure 7). The Error Flag Bit (DQ5/DQ13) is set if either an internal time-out occurred while the embedded algorithm attempted to program, or if the MCU attempted to program a '1' to a bit that was not erased (not erased is logic '0'). It is suggested (as with all Flash memories) to read the location again after the embedded programming algorithm has completed, to compare the word that was written to Flash memory with the word that was intended to be written. When using the Data Toggle method after an Erase cycle, Figure 7 still applies. the Toggle Flag Bit (DQ6/DQ14) toggles until the Erase cycle is complete. A '1' on the Error Flag Bit (DQ5/DQ13) indicates a time-out condition on the Erase cycle, a '0' indicates no error. The MCU can read any even location within the sector being erased to get the Toggle Flag Bit (DQ6/DQ14) and the Error Flag Bit (DQ5/DQ13). PSDsoft generates ANSI C code functions which implement these Data Toggling algorithms. Unlock Bypass The Unlock Bypass instruction allows the system to program words to the Flash memories faster than using the standard Program instruction. The Unlock Bypass mode is entered by first initiating two Unlock cycles. This is followed by a third WRITE cycle containing the Unlock Bypass command, 20h (as shown in Table 29, page 25). The Flash memory then enters the Unlock Bypass mode. A two-cycle Unlock Bypass Program instruction is all that is required to program in this mode. The first cycle in this instruction contains the Unlock Bypass Program command, A0h. The second cycle contains the program address and data. Additional data is programmed in the same manner. This mode dispense with the initial two Unlock cycles required in the standard Program instruction, resulting in faster total programming time. During the unlock bypass mode, only the Unlock Bypass Program and Unlock Bypass Reset instructions are valid. To exit the Unlock Bypass mode, the system must issue the two-cycle Unlock Bypass Reset instruction. The first cycle must contain the data 90h; the second cycle the data 00h. Addresses are "Don't care" for both cycles. The Flash memory then returns to READ Mode. Figure 7. Data Toggle Flowchart START READ DQ5 and DQ6 (DQ13 and DQ14) at Valid Even Address DQ6 (DQ14) = Toggle No Yes No DQ5 (DQ13) =1 Yes READ DQ6 (DQ14) DQ6 (DQ14) = Toggle No Yes Program or Erase Cycle failed Program or Erase Cycle is complete Issue RESET instruction AI04921 31/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V ERASING FLASH MEMORY Flash Bulk Erase The Flash Bulk Erase instruction uses six WRITE operations followed by a READ operation of the status register, as described in Table 29, page 25. If any byte of the Bulk Erase instruction is wrong, the Bulk Erase instruction aborts and the device is reset to the READ Memory mode. During a Bulk Erase, the memory status may be checked by reading the Error Flag Bit (DQ5/ DQ13), the Toggle Flag Bit (DQ6/DQ14), and the Data Polling Bit (DQ7/DQ15), as detailed in the section entitled "PROGRAMMING FLASH MEMORY", on page 30. The Error Flag Bit (DQ5/DQ13) returns a '1' if there has been an Erase Failure (maximum number of Erase cycles have been executed). It is not necessary to program the memory with 00h because the PSD automatically does this before erasing to 0FFh. During execution of the Bulk Erase instruction, the Flash memory does not accept any instructions. Flash Sector Erase The Sector Erase instruction uses six WRITE operations, as described in Table 29, page 25. Additional Flash Sector Erase confirm commands and Flash memory sector addresses can be written subsequently to erase other Flash memory sectors in parallel, without further coded cycles, if the additional commands are transmitted in a shorter time than the time-out period of about 100s. The input of a new Sector Erase command restarts the time-out period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3/DQ11). If the Erase Time-out Flag Bit (DQ3/ DQ11) is '0,' the Sector Erase instruction has been received and the time-out period is counting. If the Erase Time-out Flag Bit (DQ3/DQ11) is '1,' the time-out period has expired and the PSD is busy erasing the Flash memory sector(s). Before and during Erase time-out, any instruction other than Suspend Sector Erase and Resume Sector Erase, abort the cycle that is currently in progress, and reset the device to READ Mode. It is not necessary to program the Flash memory sector with 00h as the PSD does this automatically before erasing. During a Sector Erase, the memory status may be checked by reading the Error Flag Bit (DQ5/ DQ13), the Toggle Flag Bit (DQ6/DQ14), and the Data Polling Bit (DQ7/DQ15), as detailed in the section entitled "PROGRAMMING FLASH MEMORY", on page 30. During execution of the Erase cycle, the Flash memory accepts only RESET and Suspend Sector Erase instructions. Erasure of one Flash memory sector may be suspended, in order to read data from another Flash memory sector, and then resumed. Suspend Sector Erase When a Sector Erase cycle is in progress, the Suspend Sector Erase instruction can be used to suspend the cycle by writing 0B0h to any even address when an appropriate Sector Select (FS0FS15 or CSBOOT0-CSBOOT3) is High. (See Table 29, page 25). This allows reading of data from another Flash memory sector after the Erase cycle has been suspended. Suspend Sector Erase is accepted only during the Flash Sector Erase instruction execution and defaults to READ Mode. A Suspend Sector Erase instruction executed during an Erase time-out period, in addition to suspending the Erase cycle, terminates the time out period. The Toggle Flag Bit (DQ6/DQ14) stops toggling when the PSD internal logic is suspended. The status of this bit must be monitored at an address within the Flash memory sector being erased. The Toggle Flag Bit (DQ6/DQ14) stops toggling between 0.1s and 15s after the Suspend Sector Erase instruction has been executed. The PSD is then automatically set to READ Mode. If an Suspend Sector Erase instruction was executed, the following rules apply: - Attempting to read from a Flash memory sector that was being erased outputs invalid data. - Reading from a Flash memory sector that was not being erased is valid. - The Flash memory cannot be programmed, and only responds to Resume Sector Erase and RESET instructions (READ is an operation and is allowed). - If a RESET instruction is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase If a Suspend Sector Erase instruction was previously executed, the Erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of writing 030h to any even address while an appropriate Sector Select (FS0FS15 or CSBOOT0-CSBOOT3) is High. (See Table 29, page 25.) 32/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V SPECIFIC FEATURES Flash Memory Sector Protect Each sector of Primary or Secondary Flash memory can be separately protected against Program and Erase cycles. Sector Protection provides additional data security because it disables all Program or Erase cycles. This mode can be activated (or deactivated) through the JTAG-ISP Port or a Device Programmer. Sector protection can be selected for each sector using the PSDsoft program. This automatically protects selected sectors when the device is programmed through the JTAG Port or a Device Programmer. Flash memory sectors can be unprotected to allow updating of their contents using the JTAG Port or a Device Programmer. The MCU can read (but cannot change) the sector protection bits. Any attempt to program or erase a protected Flash memory sector is ignored by the device. The Verify operation results in a READ of the protected data. This allows a guarantee of the retention of the Protection status. The sector protection status can be read by the MCU through the Flash memory protection and Secondary Flash memory protection registers (in the CSIOP block) or use the READ Sector Protection instruction. See Table 18, page 19 to Table 20, page 20. RESET The RESET instruction consists of one WRITE cycle (see Table 29, page 25). It can also be optionally preceded by the standard two WRITE SRAM The SRAM is enabled when SRAM Select (RS0) from the DPLD is High. SRAM Select (RS0) can contain up to three product terms, allowing flexible memory mapping. The SRAM can be backed up using an external battery. The external battery should be connected to the Voltage Standby (VSTBY, PE6) line. If you have an external battery connected to the PSD, the contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are retained so long as the battery voltage remains at 2V or greater. If the supply voltage falls below the bat- decoding cycles (writing AAh to AAAh, and 55h to 554h). The RESET instruction must be executed after: - Reading the Flash Protection Status or Flash ID - An Error condition has occurred (and the device has set the Error Flag Bit (DQ5/DQ13) to '1') during a Flash memory Program or Erase cycle. The RESET instruction immediately puts the Flash memory back into normal READ Mode. However, if there is an error condition (with the Error Flag Bit (DQ5/DQ13) set to '1') the Flash memory will return to the READ Mode in 25s after the RESET instruction is issued. The RESET instruction is ignored when it is issued during a Program or Bulk Erase cycle of the Flash memory. The RESET instruction aborts any ongoing Sector Erase cycle, and returns the Flash memory to the normal READ Mode in 25s. Reset (RESET) Pin A pulse on the Reset (RESET) pin aborts any cycle that is in progress, and resets the Flash memory to the READ Mode. When the reset occurs during a Program or Erase cycle, the Flash memory takes up to 25 s to return to the READ Mode. It is recommended that the Reset (RESET) pulse (except for Power On Reset, as described on page 79) be at least 25s so that the Flash memory is always ready for the MCU to retrieve the bootstrap instructions after the RESET cycle is complete. tery voltage, an internal power switch-over to the battery occurs. PE7 can be configured as an output that indicates when power is being drawn from the external battery. This Battery-on Indicator (VBATON, PE7) signal is High when the supply voltage falls below the battery voltage and the battery on Voltage Standby (VSTBY, PE6) is supplying power to the internal SRAM. SRAM Select (RS0), Voltage Standby (VSTBY, PE6) and Battery-on Indicator (VBATON, PE7) are all configured using PSDsoft. 33/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V MEMORY SELECT SIGNALS The Primary Flash Memory Sector Select (FS0FS15), Secondary Flash Memory Sector Select (CSBOOT0-CSBOOT3) and SRAM Select (RS0) signals are all outputs of the DPLD. They are defined using PSDsoft. The following rules apply to the equations for these signals: 1. Primary Flash memory and secondary Flash memory Sector Select signals must not be larger than the physical sector size. 2. Any primary Flash memory sector must not be mapped in the same memory space as another Flash memory sector. 3. A secondary Flash memory sector must not be mapped in the same memory space as another secondary Flash memory sector. 4. SRAM, I/O, and Peripheral I/O spaces must not overlap. 5. A secondary Flash memory sector may overlap a primary Flash memory sector. In case of overlap, priority is given to the secondary Flash memory sector. 6. SRAM, I/O, and Peripheral I/O spaces may overlap any other memory sector. Priority is given to the SRAM, I/O, or Peripheral I/O. Example FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0. Any address greater than 9FFFh accesses the primary Flash memory segment 0. You can see that half of the primary Flash memory segment 0 and one-fourth of secondary Flash memory segment 0 cannot be accessed in this example. Also note that an equation that defined FS1 to anywhere in the range of 8000h to BFFFh would not be valid. Figure 8 shows the priority levels for all memory components. Any component on a higher level can overlap and has priority over any component on a lower level. Components on the same level must not overlap. Level 1 has the highest priority and level 3 has the lowest. Memory Select Configuration for MCUs with Separate Program and Data Spaces The 80C31 and compatible family of MCUs can be configured to have separate address spaces for Program memory (selected using Program Select Enable (PSEN, CNTL2)) and Data memory (selected using READ Strobe (RD, CNTL1)). Any of the memories within the PSD can reside in either space or both spaces. This is controlled through manipulation of the VM register that resides in the CSIOP space. The VM register is set using PSDsoft to have an initial value. It can subsequently be changed by the MCU so that memory mapping can be changed on-the-fly. For example, you may wish to have SRAM and primary Flash memory in the Data space at Boot-up, and secondary Flash memory in the Program space at Boot-up, and later swap the secondary Flash memory and primary Flash memory. This is easily done with the VM register by using PSDsoft to configure it for Boot-up and having the MCU change it when desired. Table 25, page 21 describes the VM Register. Figure 8. Priority Level of Memory and I/O Components Highest Priority Level 1 SRAM, I /O, or Peripheral I /O Level 2 Secondary Non-Volatile Memory Level 3 Primary Flash Memory Lowest Priority 34/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. AI02867D PSD4256G6V Configuration Modes for MCUs with Separate Program and Data Spaces Combined Space Modes Separate Space Modes. Program space is separated from Data space. For example, Program The Program and Data spaces are combined into Select Enable (PSEN, CNTL2) is used to access one memory space that allows the primary Flash the program code from the primary Flash memory, memory, secondary Flash memory, and SRAM to while READ Strobe (RD, CNTL1) is used to acbe accessed by either Program Select Enable cess data from the secondary Flash memory, (PSEN, CNTL2) or READ Strobe (RD, CNTL1). SRAM and I/O Port blocks. This configuration reFor example, to configure the primary Flash memquires the VM register to be set to 0Ch (see Figure ory in Combined space, Bits 2 and 4 of the VM reg9). ister are set to 1 (see Figure 10). 80C31 Memory Map Example See the Application Notes for examples. Figure 9. 8031 Memory Modules - Separate Space DPLD SRAM Secondary Flash Memory Primary Flash Memory RS0 CSBOOT0-3 FS0-FS15 CS CS OE CS OE OE PSEN RD AI04922 Figure 10. 8031 Memory Modules - Combined Space DPLD RD RS0 Secondary Flash Memory Primary Flash Memory SRAM CSBOOT0-3 FS0-FS15 CS CS OE CS OE OE VM REG BIT 3 VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 RD VM REG BIT 0 AI04923 35/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PAGE REGISTER The 8-bit Page Register increases the addressing capability of the MCU by a factor of up to 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0-FS15, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations. If memory paging is not needed, or if not all eight page register bits are needed for memory paging, these bits may be used in the CPLD for general logic. See Application Note AN1154. Table 22, page 20 and Figure 11 show the Page Register. The eight flip-flops in the register are connected to the internal data bus (D0-D7). The MCU can write to or read from the Page Register. The Page Register can be accessed at address location CSIOP + E0h. Figure 11. Page Register RESET D0 - D7 D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 PGR0 INTERNAL SELECTS AND LOGIC PGR1 PGR2 PGR3 PGR4 DPLD AND CPLD PGR5 PGR6 PGR7 R/ W PAGE REGISTER MEMORY ID REGISTERS The 8-bit "Read only" Memory Status Registers are included in the CSIOP space. The user can determine the memory configuration of the PSD device by reading the Memory ID0 and Memory PLD AI02871B ID1 registers. The content of the registers is defined as shown in Table 26, page 22 and Table 27, page 22. 36/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PLDS The PLDs bring programmable logic functionality to the PSD. After specifying the logic for the PLDs using PSDsoft, the logic is programmed into the device and available upon Power-up. The PSD contains two PLDs: the Decode PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in the following sections. Figure 12, page 38 shows the configuration of the PLDs. The DPLD performs address decoding for internal components, such as memory, registers, and I/O ports Select signals. The CPLD can be used for logic functions, such as loadable counters and shift registers, state machines, and encoding and decoding logic. These logic functions can be constructed using the 16 Output Macrocells (OMC), 24 Input Macrocells (IMC), and the AND Array. The CPLD can also be used to generate External Chip Select (ECS0ECS2) signals. The AND Array is used to form product terms. These product terms are specified using PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are shown in Table 33. The Turbo Bit in PSD The PLDs in the PSD3200 Family can minimize power consumption by switching to standby when inputs remain unchanged for an extended time of about 70ns. Resetting the Turbo Bit to '0' (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if no inputs are changing. Turning the Turbo mode off increases propagation delays while reducing power consumption. See the section entitled "POWER MANAGEMENT", on page 75, on how to set the Turbo Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals from entering the PLDs. This reduces power consumption and can be used only when these MCU control signals are not used in PLD logic equations. Each of the two PLDs has unique characteristics suited for its applications. They are described in the following sections. Table 33. DPLD and CPLD Inputs Input Source Input Name Number of Signals MCU Address Bus(1) A15-A0 16 MCU Control Signals CNTL0-CNTL2 3 Reset RST 1 Power-down PDN 1 Port A Input Macrocells PA7-PA0 8 Port B Input Macrocells PB7-PB0 8 Port C Input Macrocells PC7-PC0 8 Port D Inputs PD3-PD0 4 Port F Inputs PF7-PF0 8 Page Register PGR7-PGR0 8 Macrocell A Feedback MCELLA.FB7-FB0 8 Macrocell B Feedback MCELLB.FB7-FB0 8 Flash memory Program Status Bit Ready/Busy 1 Note: 1. The address inputs are A19-A4 in 80C51XA mode. 37/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 12. PLD Diagram 8 PAGE REGISTER DATA BUS DECODE PLD 82 16 PRIMARY FLASH MEMORY SELECTS 4 SECONDARY NON-VOLATILE MEMORY SELECTS 3 SRAM SELECT 1 CSIOP SELECT 2 PERIPHERAL SELECTS 16 JTAG SELECT DIRECT MACROCELL ACCESS FROM MCU DATA BUS OUTPUT MACROCELL FEEDBACK CPLD 16 OUTPUT MACROCELL PT ALLOC. 82 24 INPUT MACROCELL (PORT A,B,C) I/O PORTS PLD INPUT BUS 1 MCELLA TO PORT A 8 MCELLB TO PORT B 8 8 EXTERNAL CHIP SELECTS TO PORT C or PORT F DIRECT MACROCELL INPUT TO MCU DATA BUS 24 INPUT MACROCELL and INPUT PORTS 12 PORT D and PORT F INPUTS AI04924B 38/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V DECODE PLD (DPLD) The DPLD, shown in Figure 13, is used for decoding the address for internal and external components. The DPLD can be used to generate the following decode signals: 8 Sector Select (FS0-FS15) signals for the primary Flash memory (three product terms each) 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) 1 internal SRAM Select (RS0) signal (three product terms) 1 internal CSIOP Select (PSD Configuration Register) signal 1 JTAG Select signal (enables JTAG-ISP on Port E) 2 internal Peripheral Select signals (Peripheral I/O mode). Figure 13. DPLD Logic Array (INPUTS) I /O PORTS (PORT A,B,C,F) 3 CSBOOT 0 3 CSBOOT 1 3 CSBOOT 2 3 CSBOOT 3 3 FS0 (32) 3 MCELLA.FB [7:0] (FEEDBACKS) (8) MCELLB.FB [7:0] (FEEDBACKS) (8) 3 3 PGR0 -PGR7 (8) 3 A[15:0] * (16) 3 PD[3:0] (ALE,CLKIN,CSI) (4) PDN (APD OUTPUT) CNTRL[2:0] (READ/WRITE CONTROL SIGNALS) (1) (3) RESET (1) RD_BSY (1) 4 SECONDARY FLASH MEMORY SECTOR SELECTS 16 PRIMARY FLASH MEMORY SECTOR SELECTS 3 3 FS15 3 RS0 1 CSIOP 1 PSEL0 1 PSEL1 1 JTAGSEL SRAM SELECT I/O DECODER SELECT PERIPHERAL I/O MODE SELECT AI04925B Note: 1. The address inputs are A19-A4 when in 80C51XA mode 2. Additional address lines can be brought in the PSD via Port A, B, C, D, or F. 39/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V COMPLEX PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift registers, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate eight External Chip Select (ECS0-ECS7), routed to Port C or Port F. Although External Chip Select (ECS0-ECS7) can be produced by any Output Macrocell (OMC), these eight External Chip Select (ECS0-ECS7) on Port C or Port F do not consume any Output Macrocells (OMC). As shown in Figure 14, the CPLD has the following blocks: 24 Input Macrocells (IMC) 16 Output Macrocells (OMC) Product Term Allocator AND Array capable of generating up to 196 product terms Four I/O Ports. Each of the blocks are described in the sections that follow. The Input Macrocells (IMC) and Output Macrocells (OMC) are connected to the PSD internal data bus and can be directly accessed by the MCU. This enables the MCU software to load data into the Output Macrocells (OMC) or read data from both the Input and Output Macrocells (IMC and OMC). This feature allows efficient implementation of system logic and eliminates the need to connect the data bus to the AND Array as required in most standard PLD macrocell architectures. Figure 14. Macrocell and I/O Port PLD INPUT BUS PRODUCT TERMS FROM OTHER MACROCELLS MCU ADDRESS / DATA BUS CPLD MACROCELLS PT PRESET MCU DATA IN PRODUCT TERM ALLOCATOR DATA LOAD CONTROL MCU LOAD I/O PORTS LATCHED ADDRESS OUT DATA I/O PIN D Q POLARITY SELECT MACROCELL OUT TO MCU CPLD OUTPUT PR DI LD D/T MUX PT CLOCK PLD INPUT BUS MUX AND ARRAY MUX WR UP TO 10 PRODUCT TERMS GLOBAL CLOCK SELECT Q D/T/JK FF SELECT CK COMB. /REG SELECT PDR CL CLOCK SELECT INPUT D WR PT CLEAR Q DIR REG. PT OUTPUT ENABLE (OE) MUX INPUT MACROCELLS I/O PORT INPUT PT INPUT LATCH GATE/CLOCK ALE/AS MUX MACROCELL FEEDBACK Q D Q D G AI04945 40/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Output Macrocell (OMC) Eight of the Output Macrocells (OMC) are connected to Ports A pins and are named as McellA0McellA7. The other eight Macrocells are connected to Ports B pins and are named as McellB0McellB7. The Output Macrocell (OMC) architecture is shown in Figure 15, page 43. As shown in the figure, there are native product terms available from the AND Array, and borrowed product terms available (if unused) from other Output Macrocells (OMC). The polarity of the product term is controlled by the XOR gate. The Output Macrocell (OMC) can implement either sequential logic, using the flip-flop element, or combinatorial logic. The multiplexer selects between the sequential or combinatorial logic outputs. The multiplexer output can drive a port pin and has a feedback path to the AND Array inputs. The flip-flop in the Output Macrocell (OMC) block can be configured as a D, T, JK, or SR type in the PSDsoft program. The flip-flop's clock, preset, and clear inputs may be driven from a product term of the AND Array. Alternatively, the external CLKIN (PD1) signal can be used for the clock input to the flip-flop. The flip-flop is clocked on the rising edge of CLKIN (PD1). The preset and clear are active High inputs. Each clear input can use up to two product terms. Table 34. Output Macrocell Port and Data Bit Assignments Output Macrocell Port Assignment Native Product Terms Maximum Borrowed Product Terms 16-bit MCU Loading or Reading(1) Motorola 16-bit MCU for Loading or Reading McellA0 Port A0 3 6 D0 D8 McellA1 Port A1 3 6 D1 D9 McellA2 Port A2 3 6 D2 D10 McellA3 Port A3 3 6 D3 D11 McellA4 Port A4 3 6 D4 D12 McellA5 Port A5 3 6 D5 D13 McellA6 Port A6 3 6 D6 D14 McellA7 Port A7 3 6 D7 D15 McellB0 Port B0 4 5 D8 D0 McellB1 Port B1 4 5 D9 D1 McellB2 Port B2 4 5 D10 D2 McellB3 Port B3 4 5 D11 D3 McellB4 Port B4 4 6 D12 D4 McellB5 Port B5 4 6 D13 D5 McellB6 Port B6 4 6 D14 D6 McellB7 Port B7 4 6 D15 D7 Note: 1. D7-D0 are used for loading or reading in 8-bit mode. 41/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Product Term Allocator The CPLD has a Product Term Allocator. PSDsoft, uses the Product Term Allocator to borrow and place product terms from one Macrocell to another. The following list summarizes how product terms are allocated: McellA0-McellA7 all have three native product terms and may borrow up to six more McellB0-McellB3 all have four native product terms and may borrow up to five more McellB4-McellB7 all have four native product terms and may borrow up to six more. Each Macrocell may only borrow product terms from certain other Macrocells. Product terms already in use by one Macrocell are not available for another Macrocell. If an equation requires more product terms than are available to it, then "external" product terms are required, which consume other Output Macrocells (OMC). If external product terms are used, extra delay is added for the equation that required the extra product terms. This is called product term expansion. PSDsoft performs this expansion as needed. Loading and Reading the Output Macrocells (OMC) The Output Macrocells (OMC) block occupies a memory location in the MCU address space, as defined by the CSIOP (see Figure 21 to Figure 30 for examples of the basic connections between the PSD and some popular MCUs). The PSD Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using the PSDsoft Express Configuration. The flip-flops in each of the 16 Output Macrocells (OMC) can be loaded from the data bus by a MCU. Loading the Output Macrocells (OMC) with data from the MCU takes priority over internal functions. As such, the preset, clear, and clock in- puts to the flip-flop can be overridden by the MCU. The ability to load the flip-flops and read them back is useful in such applications as loadable counters and shift registers, mailboxes, and handshaking protocols. Data is loaded to the Output Macrocells (OMC) on the trailing edge of WRITE Strobe (WR/WRL, CNTL0). The OMC Mask Register There is one Mask Register for each of the two groups of eight Output Macrocells (OMC). The Mask Registers can be used to block the loading of data to individual Output Macrocells (OMC). The default value for the Mask Registers is 00h, which allows loading of the Output Macrocells (OMC). When a given bit in a Mask Register is set to a 1, the MCU is blocked from writing to the associated Output Macrocells (OMC). For example, suppose McellA0-McellA3 are being used for a state machine. You would not want a MCU WRITE to McellA to overwrite the state machine registers. Therefore, you would want to load the Mask Register for McellA (Mask Macrocell A) with the value 0Fh. The Output Enable of the OMC The Output Macrocells (OMC) can be connected to an I/O port pin as a PLD output. The output enable of each port pin driver is controlled by a single product term from the AND Array, ORed with the Direction Register output. The pin is enabled upon Power-up if no output enable equation is defined and if the pin is declared as a PLD output in PSDsoft. If the Output Macrocell (OMC) output is declared as an internal node and not as a port pin output in the PSDabel file, then the port pin can be used for other I/O functions. The internal node feedback can be routed as an input to the AND Array. 42/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 15. CPLD Output Macrocell MASK REG. MACROCELL CS INTERNAL DATA BUS RD PT ALLOCATOR WR DIRECTION REGISTER ENABLE (.OE) AND ARRAY PLD INPUT BUS PRESET(.PR) COMB/REG SELECT PT PT DIN PR MUX PT LD POLARITY SELECT IN CLEAR (.RE) CLR PORT DRIVER PROGRAMMABLE FF (D / T/JK /SR) PT CLK CLKIN I/O PIN Q MUX FEEDBACK (.FB) PORT INPUT INPUT MACROCELL AI04946 43/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Input Macrocells (IMC) The CPLD has 24 Input Macrocells (IMC), one for each pin on Ports A, B, and C. The architecture of the Input Macrocells (IMC) is shown in Figure 16. The Input Macrocells (IMC) are individually configurable, and can be used as a latch, register, or to pass incoming Port signals prior to driving them onto the PLD input bus. The outputs of the Input Macrocells (IMC) can be read by the MCU through the internal data bus. The enable for the latch and clock for the register are driven by a multiplexer whose inputs are a product term from the CPLD AND Array or the MCU Address Strobe (ALE/AS). Each product term output is used to latch or clock four Input Macrocells (IMC). Port inputs 3-0 can be controlled by one product term and 7-4 by another. Configurations for the Input Macrocells (IMC) are specified by PSDsoft (see Application Note AN1171). Outputs of the Input Macrocells (IMC) can be read by the MCU via the IMC buffer. See Figure 21, page 51 to Figure 30, page 61 for examples of the basic connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using the "I/O Ports", on page 14. Input Macrocells (IMC) can use Address Strobe (ALE/AS, PD0) to latch address bits higher than A15. Any latched addresses are routed to the PLDs as inputs. Input Macrocells (IMC) are particularly useful with handshaking communication applications where two processors pass data back and forth through a common mailbox. Figure 18, page 45 shows a typical configuration where the Master MCU writes to the Port A Data Out Register. This, in turn, can be read by the Slave MCU via the activation of the "Slave-READ" output enable product term. The Slave can also write to the Port A Input Macrocells (IMC) and the Master can then read the Input Macrocells (IMC) directly. Note that the "Slave-READ" and "Slave-Wr" signals are product terms that are derived from the Slave MCU inputs READ Strobe (RD, CNTL1), WRITE Strobe (WR/WRL, CNTL0), and Slave_CS. Figure 16. Input Macrocell INTERNAL DATA BUS INPUT MACROCELL _ RD DIRECTION REGISTER ENABLE ( .OE ) AND ARRAY PLD INPUT BUS PT OUTPUT MACROCELLS A AND MACROCELLS B I/O PIN PT PORT DRIVER MUX Q D PT MUX ALE/AS D FF FEEDBACK Q D G LATCH INPUT MACROCELL AI04926 44/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V External Chip Select The CPLD also provides eight External Chip Select (ECS0-ECS7) outputs that can be used to select external devices. Each External Chip Select (ECS0-ECS7) consists of one product term that can be configured active High or Low. The output enable of the pin is controlled by either the output enable product term or the Direction Register. (See Figure 17.) Figure 17. External Chip Select Signal CPLD AND ARRAY PLD INPUT BUS Port C or Port F ENABLE (.OE) PT DIRECTION REGISTER ECS To Port C or F ECS PT PORT PIN POLARITY BIT AI04927 Figure 18. Handshaking Communication Using Input Macrocells PSD SLAVE - CS RD WR SLAVE - READ PORT A DATA OUT REGISTER MCU- RD D [ 7:0] CPLD D Q SLAVE MCU PORT A MCU - WR MCU- WR MASTER MCU SLAVE - WR D [ 7:0] PORT A INPUT MACROCELL Q D MCU - RD AI02877C 45/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V MCU BUS INTERFACE The "no-glue logic" MCU Bus Interface block can be directly connected to most popular 8-bit and 16bit MCUs and their control signals. Key MCUs, with their bus types and control signals, are shown in Table 35 and Table 36, page 47. The MCU interface type is specified using the PSDsoft. Table 35. 16-bit MCUs and Their Control Signals MCU CNTL0 CNTL1 CNTL2 PD02 PD3 ADIO0 PF3-PF0 68302, 68306, MMC2001 R/W LDS UDS (Note 1) AS -- (Note 1) 68330, 68331, 68332, 68340 R/W DS SIZ0 (Note 1) AS A0 (Note 1) 68LC302, MMC2001 WEL OE -- WEH AS -- (Note 1) 68HC16 R/W DS SIZ0 (Note 1) AS A0 (Note 1) 68HC912 R/W E LSTRB DBE E A0 (Note 1) 68HC812 3 R/W E LSTRB (Note 1) (Note 1) A0 (Note 1) 80196 WR RD BHE (Note 1) ALE A0 (Note 1) 80196SP WRL RD (Note 1) WRH ALE A0 (Note 1) 80186 WR RD BHE (Note 1) ALE A0 (Note 1) 80C161, 80C164-80C167 WR RD BHE (Note 1) ALE A0 (Note 1) 80C51XA WRL RD PSEN WRH ALE A4/D0 A3-A1 WRH AS A0 -- H8/300 WRL RD (Note 1) Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O functions. 2. ALE/AS input is optional for MCUs with a non-multiplexed bus. 3. This configuration is for MC68HC812A4_EC at 5MHz, 3V only. 46/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 36. 8-bit MCUs and Their Control Signals MCU CNTL0 CNTL1 CNTL2 PD7 PD02 ADIO0 PF3-PF0 8031/8051 WR RD PSEN (Note 1) ALE A0 (Note 1) 80C51XA WR RD PSEN (Note 1) ALE A4 A3-A0 80C251 WR PSEN (Note 1) (Note 1) ALE A0 (Note 1) 80C251 WR RD PSEN (Note 1) ALE A0 (Note 1) 80198 WR RD (Note 1) (Note 1) ALE A0 (Note 1) 68HC11 R/W E (Note 1) (Note 1) AS A0 (Note 1) 68HC05C0 WR RD (Note 1) (Note 1) AS A0 (Note 1) 68HC912 R/W E (Note 1) DBE AS A0 (Note 1) Z80 WR RD (Note 1) (Note 1) (Note 1) A0 (Note 1) Z8 R/W DS (Note 1) (Note 1) AS A0 (Note 1) 68330 R/W DS (Note 1) (Note 1) AS A0 A3-A1 Note: 1. Unused CNTL2 pin can be configured as CPLD input. Other unused pins (PD3-PD0, PF3-PF0) can be configured for other I/O functions. 2. ALE/AS input is optional for MCUs with a non-multiplexed bus. 3. This configuration is for MC68HC812A4_EC at 5MHz, 3V only. 47/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PSD Interface to a Multiplexed Bus Figure 19 shows an example of a system using an MCU with a multiplexed bus and a PSD4256G6V. The ADIO port on the PSD is connected directly to the MCU address/data bus. Address Strobe (ALE/ AS, PD0) latches the address signals internally. Latched addresses can be brought out to Port E, F or G. The PSD drives the ADIO data bus only when one of its internal resources is accessed and READ Strobe (RD, CNTL1) is active. Should the system address bus exceed sixteen bits, Ports A, B, C, or F may be used as additional address inputs. Figure 19. An Example of a Typical Multiplexed Bus Interface PSD MCU AD [ 7:0] AD[15:8]1 or A[15:8] ADIO PORT WR WR (CNTRL0) RD RD (CNTRL1) BHE (CNTRL2) BHE RST ALE A [ 7: 0] PORT F (OPTIONAL) PORT G (OPTIONAL) PORT A A [ 15: 8] A [ 23:16] (OPTIONAL) ALE (PD0) PORT D RESET AI04928B Note: 1. AD[15:8] is for 16-bit MCU 48/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PSD Interface to a Non-Multiplexed, 16-bit Bus Figure 20 shows an example of a system using an MCU with a 16-bit, non-multiplexed bus and a PSD4256G6V. The address bus is connected to the ADIO Port, and the data bus is connected to Ports F and G. Ports F and G are in tri-state mode when the PSD is not accessed by the MCU. Should the system address bus exceed sixteen bit, Ports A, B, or C may be used for additional address inputs. Figure 20. An Example of a Typical Non-Multiplexed Bus Interface PSD MCU D [ 15:0] ADIO PORT PORT F D [ 7:0] A [ 15:0] PORT G WR WR (CNTRL0) RD RD (CNTRL1) BHE (CNTRL2) BHE RST ALE PORT A D[15:8]1 A [ 23:16] (OPTIONAL) ALE (PD0) PORT D RESET AI04929B Note: 1. D[15:8] is for 16-bit MCU 49/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Data Byte Enable Reference for a 16-bit Bus MCUs have different data byte orientations. Table 37 to Table 40 show how the PSD3200 Family interprets byte/word operations in different bus WRITE configurations. Even-byte refers to locations with address A0 equal to 0, and odd byte as locations with A0 equal to 1. Table 37. 16-Bit Data Bus with BHE BHE A0 D15-D8 D7-D0 0 0 Odd Byte Even Byte 0 1 Odd Byte -- 1 0 -- Even Byte 16-bit MCU Bus Interface Examples Figure 21, page 51 to Figure 26, page 57 show examples of the basic connections between the PSD3200 Family and some popular MCUs. The PSD3200 Family Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using PSDsoft. The Voltage Standby (VSTBY, PE6) line should be held at Ground if not in use. Table 38. 16-Bit Data Bus with WRH and WRL WRH WRL D15-D8 D7-D0 0 0 Odd Byte Even Byte 0 1 Odd Byte -- 1 0 -- Even Byte Table 39. 16-Bit Data Bus with SIZ0, A0 (Motorola MCU) SIZ0 A0 D15-D8 D7-D0 0 0 Even Byte Odd Byte 1 0 Even Byte -- 1 1 -- Odd Byte Table 40. 16-Bit Data Bus with LDS, UDS (Motorola MCU) WRH WRL D15-D8 D7-D0 0 0 Even Byte Odd Byte 1 0 Even Byte -- 0 1 -- Odd Byte 50/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V 80C196 and 80C186 In Figure 21, the Intel 80C196 MCU, which has a 16-bit multiplexed address/data bus, is shown connected to a PSD3200 Family. The READ Strobe (RD, CNTL1), and WRITE Strobe (WR/ WRL, CNTL0) signals are connected to the CNTL pins. When BHE is not used, the PSD can be configured to receive WRL and WRITE Enable High- byte (WRH/DBE, PD3) from the MCU. Higher address inputs (A16-A19) can be routed to Ports A, B, or C as input to the PLD. The AMD 80186 family has the same bus connection to the PSD as the 80C196. Figure 21. Interfacing the PSD with an 80C196 A19-A16 A[ 19:16] AD15-AD0 AD[ 15:0 ] VCC 80C196NT 19 18 32 49 6 48 44 45 46 47 58 59 60 61 62 63 64 65 36 37 38 39 40 41 42 43 57 56 55 54 53 52 51 50 PSD X1 X2 P3.0/AD0 P3.1/AD1 P3.2/AD2 P3.3/AD3 P3.4/AD4 P3.5/AD5 P3.6/AD6 P3.7/AD7 3 4 5 6 7 10 11 12 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 5 6 7 10 11 12 P4.0/AD8 P4.1/AD9 P4.2/AD10 P4.3/AD11 P4.4/AD12 P4.5/AD13 P4.6/AD14 P4.7/AD15 13 14 15 16 17 18 19 20 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 13 14 15 16 17 18 19 20 EP.0/A16 EP.1/A17 EP.2/A18 EP.3/A19 14 13 12 11 9 WR 59 7 RD 60 8 BHE 40 4 ALE 79 80 1 2 NMI VREF VPP ANGND ACH4/P0.4/PMD.0 ACH5/P0.5/PMD.1 ACH6/P0.6/PMD.2 ACH7/P0.7/PMD.3 P6.0/EPA8 P6.1/EPA9 P6.2/T1CLK P6.3/T1DIR P6.4/SC0 P6.5/SD0 P6.6/SC1 P6.7/SD1 WR/WRL/P5.2 RD/P5.3 BHE/WRH/P5.5 P2.0/TX/PVR P2.1/RXD/PALE P2.2/EXINT/PROG P2.3/INTB P2.4/INTINTOUT P2.5/HLD P2.6/HLDA/CPVER P2.7/CLKOUT/PAC ALE/ADV/P5.0 EA 31 READY/P5.6 P1.0/EPA0/T2CLK P1.1/EPA1 P1.2/EPA2/T2DIR P1.3/EPA3 BUSWIDTH/P5.7 P1.4/EPA4 P1.5/EPA5 INST/P5.1 P1.6/EPA6 SLPINT/P5.4 P1.7/EPA7 2 10 3 1 29 69 VCC VCC ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 A16 A17 A18 A19 33 RESET 9 VCC RESET 39 71 72 73 74 75 76 77 78 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CNTL0 (WR) CNTL1 (RD) CNTL2 (BHE) PD0 (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 RESET PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) GND GND GND GND GND 8 30 49 50 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19 70 RESET AI04930 51/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V MC683xx and MC68HC16 Figure 22 shows a MC68331 with a 16-bit nonmultiplexed data bus and 24-bit address bus. The data bus from the MC68331 is connected to Port F (D0-D7) and Port G (D8-D15). The SIZ0 and A0 inputs determine the high/low byte selection. The R/ W, DS and SIZ0 signals are connected to the CNTL0-CNTL2 pins. The MC68HC16, and other members of the MC683xx family, has the same bus connection to the PSD as the MC68331 shown in Figure 22. Figure 22. Interfacing the PSD with an MC68331 D[15:0] D[15:0] A[23:0] A[23:0] 69 9 PSD 29 VCC_BAR D8 100 D9 99 D10 98 D11 97 D12 94 D13 93 D14 92 D15 91 89 88 77 76 75 74 73 72 71 D8 D9 D10 D11 D12 D13 D14 D15 DSACK0 DSACK1 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19_CS6/ A20_CS7/ A21_CS8/ A22_CS9/ A23_CS10/ 90 20 21 22 23 24 25 26 A0 A1 A2 A3 A4 A5 A6 A7 3 4 5 6 7 10 11 12 27 30 31 32 33 35 36 37 38 41 42 121 122 123 124 125 A8 A9 A10 A11 A12 A13 A14 A15 13 14 15 16 17 18 19 20 79 R_W 85 DS 81 SIZ0 AS RESET SIZ1 CLKOUT CSBOOT/ BR_CS0/ BG_CS1/ BGACK_CS2/ FC0_CS3/ FC1_CS4/ FC2_CS5/ A16 A17 A18 A19 A20 A21 A22 A23 R/W\ DS\ 59 60 SIZ0 40 AS 79 80 1 2 RESET\ 39 82 68 80 66 112 113 114 115 118 119 120 71 72 73 74 75 76 77 78 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 Vcc A0 A1 A2 A3 A4 A5 A6 A7 Vcc D0 D1 D2 D3 D4 D5 D6 D7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 CNTL0(R/W) CNTL1(DS) CNTL2 (SIZ0) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 RESET PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 (AS) PD1 (CLKIN) PD2 (CSI) PD3 31 32 33 34 35 36 37 38 D0 D1 D2 D3 D4 D5 D6 D7 21 22 23 24 25 26 27 28 D8 D9 D10 D11 D12 D13 D14 D15 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19 GND GND GND GND GND 111 110 109 108 105 104 103 102 8 30 49 50 70 D0 D1 D2 D3 D4 D5 D6 D7 Vcc MC68331 RESET\ AI04951b 52/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V 80C51XA The Philips 80C51XA MCU has a 16-bit multiplexed bus with burst cycles. Address bits (A3-A1) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0). The PSD3200 Family supports the 80C51XA burst mode. The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD and PSEN signals are connected to the CNTL1 and CNTL2 pins. Figure 23 shows the schematic diagram. The 80C51XA improves bus throughput and performance by issuing burst cycles to retrieve codes from memory. In burst cycles, address A19-A4 are latched internally by the PSD, while the 80C51XA drives the A3-A1 signals to retrieve sequentially up to 16 bytes of code. The PSD access time is then measured from address A3-A1 valid to data in valid. The PSD bus timing requirement in a burst cycle is identical to the normal bus cycle, except the address setup and hold time with respect to Address Strobe (ALE/AS, PD0) is not required. Figure 23. Interfacing the PSD with an 80C51XA-G3 D[15:0] D[15:0] A[3:1] VCC_BAR CRYSTAL 20 11 13 6 7 9 8 16 RESET\ 10 14 15 35 17 VCC_BAR XTAL1 XTAL2 RXD0 TXD0 RXD1 TXD1 T2EX T2 T0 RST INT0 INT1 A4D0 A5D1 A6D2 A7D3 A8D4 A9D5 A10D6 A11D7 A12D8 A13D9 A14D10 A15D11 A16D12 A17D13 A18D14 A19D15 A3 A2 A1 A0/WRH WRL RD PSEN EA/WAIT ALE BUSW 43 42 41 40 39 38 37 36 3 A4D0 4 A5D1 A6D2 5 6 A7D3 A8D4 7 A9D5 10 A10D6 11 A11D7 12 24 25 26 27 28 29 30 31 A12D8 13 A13D9 14 A14D10 15 A15D11 16 A16D12 17 A17D13 18 A18D14 19 A19D15 20 5 4 3 2 18 19 A3 A2 A1 WRH\ WRL\ RD\ 59 60 32 PSEN\ 40 33 ALE 79 80 1 2 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 69 Vcc 21 U3 Vcc 9 XA-G3 Vcc PSD 29 A[3:1] ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 CNTL0(WR) CNTL1(RD) CNTL2(PSEN) RESET PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 31 32 33 34 35 36 37 38 A1 A2 A3 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 8 30 49 50 70 GND GND GND GND GND 71 72 73 74 75 76 77 78 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD0 (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) RESET\ 39 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 AI04952b 53/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V H8/300 Figure 24 shows an Hitachi H8/2350 with a 16-bit non-multiplexed data bus, and a 24-bit address bus. The H8 data bus is connected to Port F (D0D7) and Port G (D8-D15). The WRH signal is connected to PD3, and WHL is connected to CNTL0. The RD signal is connected to CNTL1. The connection to the Address Strobe (AS) signal is optional, and is required if the addresses are to be latched. Figure 24. Interfacing the PSD with an H83/2350 D[15:0] D[15:0] A[23:0] A[23:0] 78 PD0/D8 PD1/D9 PD2/D10 PD3/D11 PD4/D12 PD5/D13 PD6/D14 PD7/D15 EXTAL U3 CRYSTAL 77 29 30 31 32 55 53 57 56 54 58 90 89 91 88 87 86 74 71 70 69 68 67 66 65 64 60 61 62 63 113 114 115 80 RESET\ XTAL CS7/IRQ3 CS6/IRQ2 IRQ1 IRQ0 RXD0 TXD0 SCK0 RXD1 TXD1 SCK1 RXD2 TXD2 SCK2 PF0/BREQ PF1/BACK PF2/LCAS/WAIT/B NMI PO0/TIOCA3 PO1/TIOCB3 PO2/TIOCC3/TMRI PO3/TIOCD3/TMCI PO4/TIOCA4/TMRI PO5/TIOCB4/TMRC PO6/TIOCA5/TMRO PO7/TIOCB5/TMRO DREQ/CS4 TEND0/CS5 DREQ1 TEND1 MOD0 MOD1 MOD2 PF0/PHI0 PB0/A8 PB1/A9 PB2/A10 PB3/A11 PB4/A12 PB5/A13 PB6/A14 PB7/A15 PA0/A16 PA1/A17 PA2/A18 PA3/A19 PA4/A20/IRQ4 PA5/A21/IRQ5 PA6/A22/IRQ6 PA7/A23/IRQ7 LWR RD AS HWR RESET WDTOVF STBY PO8/TIOCA0/DACK PO9/TIOCB0/DACK PO10/TIOCC0/TCL PO11/TIOCD0/TCL PO12/TIOCA1 PO13/TIOCB1/TCL PO14/TIOCA2 PO15/TIOCB2/TCL AN0 AN1 AN2 AN3 AN4 AN5 AN6/DA0 AN7/DA1 ADTRG PG0/CAS/OE PG1/CS3 PG2/CS2 PG3/CS1 PG4/CS0 2 3 4 5 7 8 9 10 A0 A1 A2 A3 A4 A5 A6 A7 3 4 5 6 7 10 11 12 11 12 13 14 16 17 18 19 20 21 22 23 25 26 27 28 85 83 A8 A9 A10 A11 A12 A13 A14 A15 13 14 15 16 17 18 19 20 A16 A17 A18 A19 A20 A21 A22 A23 WRL\ RD\ 40 82 AS 84 WRH\ 73 72 75 112 111 110 109 108 107 106 105 59 60 RESET\ 79 80 1 2 39 71 72 73 74 75 76 77 78 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 9 69 Vcc 43 44 45 46 48 49 50 51 PC0/A0 PC1/A1 PC2/A2 PC3/A3 PC4/A4 PC5/A5 PC6/A6 PC7/A7 Vcc D8 D9 D10 D11 D12 D13 D14 D15 PE0/D0 PE0/D1 PE0/D2 PE0/D3 PE0/D4 PE0/D5 PE0/D6 PE0/D7 Vcc 34 35 36 37 39 40 41 42 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 CNTL0(WRL) CNTL1(RD) CNTL2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 RESET PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 (AS) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) 31 32 33 34 35 36 37 38 D0 D1 D2 D3 D4 D5 D6 D7 21 22 23 24 25 26 27 28 D8 D9 D10 D11 D12 D13 D14 D15 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19 GND GND GND GND GND D0 D1 D2 D3 D4 D5 D6 D7 PSD 8 30 49 50 70 H8S/2655 29 VCC_BAR 95 96 97 98 99 100 101 102 92 116 117 118 119 120 AI04953b 54/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V MMC2001 The Motorola MCORE MMC2001 MCU has a MOD input pin that selects internal or external boot ROM. The PSD can be configured as the external flash boot ROM or as extension to the internal ROM (see Figure 25, page 56). The MMC2001 has a 16-bit external data bus and 20 address lines with external chip select signals. The Chip Select Control Registers allow the user to customize the bus interface and timing to fit the individual system requirement. A typical interface configuration to the PSD is shown in Figure 25, page 56. The MMC2001's R/W signal is connected to the CNTL0 pin, while EB0 and EB1 (enable byte-0 and enable byte-1) are connected to the CNTL1 (UDS) and CNTL2 (LDS) pins. The WEN bit in the Chip Select Control Register should be set to 1 to terminate the EB0-EB1 earlier to provide the write data hold time for the PSD. The WSC and WWS bits in the Control Register are set to wait states that meet the PSD access time requirement. Another option is to configure the EB0 and EB1 as WRL and WRH signals. In this case, the PSD control setting will be: OE, WRL, WRH where OE is the READ signal for the MMC2001. C16x Family The PSD supports Infineon's C16X family of MCUs (C161-C167) in both the multiplexed and non-multiplexed bus configuration. In Figure 26, page 57, the C167CR is shown connected to the PSD in a multiplexed bus configuration. The control signals from the MCU are WR, RD, BHE and ALE, and are routed to the corresponding PSD pins. The C167 has another control signal setting (RD, WRL, WRH, ALE) which is also supported by the PSD. 55/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 25. Interfacing the PSD with an MMC2001 A[19:16] A[19:16] AD[15:0] VCC_BAR 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 P5.0/AN0 P5.1/AN1 P5.2/AN2 P5.3/AN3 P5.4/AN4 P5.5/AN5 P5.6/AN6 P5.7/AN7 P5.8/AN8 P5.9/AN9 P5.10/AN10/T6UED P5.11/AN11/T5UED P5.12/AN12/T6IN P5.13/AN13/T5IN P5.14/AN14/T4UED P5.15/AN15/T2UED P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO EA P1H7 P1H6 P1H5 P1H4 P1H3 P1H2 P1H1 P1H0 P1L7 P1L6 P1L5 P1L4 P1L3 P1L2 P1L1 P1L0 P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IO/EX2IN P2.11/CC11IO/EX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN Vref READY 143 139 127 110 94 RESET\ P4.0/A16 A17 A18 A19 A20 A21 A22 P4.7/A23 WR/WRL RD P3.12/BHE/WRH ALE P6.0/!CS0 P6.1/!CS1 P6.2/!CS2 P6.3/!CS3 P6.4/!CS4 P6.5/!HOLD P6.6/!HLDA P6.7/!BREQ Vss Vss Vss Vss Vss 37 97 P3.13/SCLK P3.15/CLKOUT RSTIN RSTOUT NMI 108 111 112 113 114 115 116 117 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 13 14 15 16 17 18 19 20 85 86 87 88 89 90 91 92 96 95 79 98 69 9 29 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 WR\ RD\ BHE\ ALE RESET\ 59 60 40 79 80 1 2 39 71 72 73 74 75 76 77 78 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 A16 A17 A18 A19 99 135 134 133 132 131 130 129 128 125 124 123 122 121 120 119 118 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 Vcc 3 4 5 6 7 10 11 12 Vcc AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CNTL0(WR) CNTL1(RD) CNTL2(BHE) RESET PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 (ALE) PD1 (CLKIN) PD2 (CSI) PD3 (WRH) 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19 GND GND GND GND GND 1 2 3 4 5 6 7 8 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 Agnd 27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44 P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3EUD P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TXD0 P3.11/RXD0 100 101 102 103 104 105 106 107 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 140 141 142 38 80 81 XTAL2 Vss Vss Vss Vss Vss 65 66 67 68 69 70 73 74 75 76 77 78 83 71 55 45 18 137 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 Vcc 82 72 56 46 17 U3 CRYSTAL ADIO[15:0] 8 30 49 50 70 XTAL1 PSD Vcc Vcc Vcc Vcc Vcc 138 Vcc Vcc Vcc Vcc Vcc Infineon C167CR 144 136 126 109 93 VCC_BAR AI04954b 56/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 26. Interfacing the PSD with a C167CR A19-A16 A[ 19:16] AD15-AD0 Vcc 144136129109 93 82 72 56 46 17 VccVccVccVccVccVccVccVccVccVcc 138 65 66 67 68 69 70 73 74 75 76 77 78 79 80 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 3 4 5 6 7 10 11 12 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 108 111 112 113 114 115 116 117 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 13 14 15 16 17 18 19 20 XTAL1 81 27 28 29 30 31 32 33 34 35 36 39 40 41 42 43 44 1 2 3 4 5 6 7 8 19 20 21 22 23 24 25 26 9 10 11 12 13 14 15 16 37 97 XTAL2 P3.0/T0IN P3.1/T6OUT P3.2/CAPIN P3.3/T3OUT P3.4/T3UED P3.5/T4IN P3.6/T3IN P3.7/T2IN P3.8/MRST P3.9/MTSR P3.10/TXD0 P3.11/RXD0 P3.12 P3.13/SCLK PSD 100 101 102 103 104 105 106 107 C167CR 137 85 86 87 88 89 90 91 92 P5.0/AN0 WR/WRL P5.1/AN1 P5.2/AN2 RD P5.3/AN3 P312/BHE/WRH P5.4/AN4 P5.5/AN5 ALE P5.6/AN6 P5.7/AN7 EA P5.8/AN8 P5.9/AN9 P1H7 P5.10/AN10/T6UED P1H6 P5.11/AN11/T5UED P1H5 P5.12/AN12/T6IN P1H4 P5.13/AN13 P1H3 P5.14/AN14/T4UED P1H2 P5.15/AN15/T2UED P1H1 P1H0 P6.0/!CS0 P1L7 P6.1/!CS1 P1L6 P6.2/!CS2 P1L5 P6.3/!CS3 P1L4 P6.4/!CS4 P1L3 P6.5/!HOLD P1L2 P1L1 P6.6/!HLDA P1L0 P6.7/!BREQ 96 WR 59 95 RD 60 79 BHE 40 98 ALE 79 80 P7.0/POUT0 P7.1/POUT1 P7.2/POUT2 P7.3/POUT3 P7.4/CC28IO P7.5/CC29IO P7.6/CC30IO P7.7/CC31IO P8.0/CC16IO P8.1/CC17IO P8.2/CC18IO P8.3/CC19IO P8.4/CC20IO P8.5/CC21IO P8.6/CC22IO P8.7/CC23IO Vref 99 135 134 133 132 131 130 129 128 125 124 123 122 121 120 119 118 9 VCC 29 69 VCC VCC ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PF0 PF1 PF2 PF3 PF4 PF5 PF6 PF7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7 A16 A17 A18 A19 P4.0/A16 P4.1/A17 P4.2/A18 P4.3/A19 P4.4/A20 P4.5/A21 P4.6/A22 P4.7/A23 P3.15/CLKOUT AD[ 15:0 ] VCC 1 2 RESET 39 71 72 73 74 75 76 77 78 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 CNTL0 (WR) CNTL1 (RD) CNTL2 (BHE) PD0 (ALE) PD1 (CLKIN) PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PD2 (CSI) PD3 (WRH) RESET PE0 (TMS) PE1 (TCK/ST) PE2 (TDI) PE3 (TDO) PE4 (TSTAT/RDY) PE5 (TERR) PE6 (VSTBY) PE7 (VBATON) GND GND GND GND GND 8 30 49 50 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 31 32 33 34 35 36 37 38 21 22 23 24 25 26 27 28 51 52 53 54 55 56 57 58 61 62 63 64 65 66 67 68 41 42 43 44 45 46 47 48 A16 A17 A18 A19 70 47 48 49 50 51 52 53 54 57 58 59 60 61 62 63 64 P2.0/CC0IO P2.1/CC1IO P2.2/CC2IO P2.3/CC3IO P2.4/CC4IO P2.5/CC5IO P2.6/CC6IO P2.7/CC7IO P2.8/CC8IO/EX0IN P2.9/CC9IO/EX1IN P2.10/CC10IO/EX2IN P2.11/CC11IO/EX3IN P2.12/CC12IO/EX4IN P2.13/CC13IO/EX5IN P2.14/CC14IO/EX6IN P2.15/CC15IO/EX7IN 140 RSTIN RSTOUT 141 NMI AGND VssVssVssVssVssVssVssVssVssVss READY 143139127110 94 83 71 55 45 18 142 38 RESET AI04955 57/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V 8-bit MCU Bus Interface Examples Figure 21, page 51 to Figure 30 show examples of the basic connections between the PSD and some popular MCUs. The PSD Control input pins are labeled as to the MCU function for which they are configured. The MCU bus interface is specified using the PSDsoft Express Configuration. 80C31 Figure 21, page 51 shows the bus interface for the 80C31 which has an 8-bit, multiplexed address/ data bus. The lower address byte is multiplexed with the data bus. The MCU control signals Program Select Enable (PSEN, CNTL2), READ Strobe (RD, CNTL1), and WRITE Strobe (WR, CNTL0) may be used for accessing the internal memory and I/O Ports blocks. Address Strobe (ALE/AS, PD0) latches the address. Figure 27. Interfacing the PSD with an 80C31 AD7-AD0 PSD 80C31 31 19 18 9 RESET 12 13 14 15 EA/VP X1 X2 RESET INT0 INT1 T0 T1 1 2 3 4 5 6 7 8 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE/P TXD RXD AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 30 31 32 33 34 35 36 37 39 38 37 36 35 34 33 32 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 21 22 23 24 25 26 27 28 A8 A9 A10 A11 A12 A13 A14 A15 39 40 41 42 43 44 45 46 17 RD WR 47 16 29 30 11 10 RESET RESET AD[ 7:0 ] PSEN ALE 50 49 10 9 8 48 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CNTL0 (WR) PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 CNTL1(RD) CNTL2 (PSEN) PD0-ALE PD1 PD2 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 RESET AI02880C 58/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V 80C251 The Intel 80C251 MCU features a user-configurable bus interface with four possible bus configurations, as shown in Table 41. The first configuration is 80C31-compatible, and the bus interface to the PSD is identical to that shown in Figure 21, page 51. The second and third configurations have the same bus connection as shown in Figure 41, page 87. There is only one READ Strobe (PSEN) connected to CNTL1 on the PSD. The A16 connection to PA0 allows for a larger address input to the PSD. The fourth configuration is shown in Figure 28, page 60. READ Strobe (RD) is connected to CNTL1 and Program Select Enable (PSEN) is connected to CNTL2. The 80C251 has two major operating modes: Page Mode. Data (D7-D0) is multiplexed with address (A15-A8). In a bus cycle where there is a Page hit, Address Strobe (ALE/AS, PD0) is not active and only addresses (A7-A0) are changing. Non-Page Mode. The data is multiplexed with the lower address byte and Address Strobe (ALE/ AS, PD0) is active in every bus cycle. The PSD supports both modes. In Page Mode, the PSD bus timing is identical to Non-Page Mode, except the address hold time and setup time with respect to Address Strobe (ALE/AS, PD0) is not required. The PSD access time is measured from address (A7-A0) valid to data invalid. Table 41. 80C251 Configurations Configuration 80C251 READ/WRITE Pins Connecting to PSD Pins Page Mode 1 WR RD PSEN CNTL0 CNTL1 CNTL2 Non-Page Mode, 80C31 compatible A7-A0 multiplex with D7-D0 2 WR PSEN only CNTL0 CNTL1 Non-Page Mode A7-A0 multiplex with D7-D0 3 WR PSEN only CNTL0 CNTL1 Page Mode A15-A8 multiplex with D7-D0 4 WR RD PSEN CNTL0 CNTL1 CNTL2 Page Mode A15-A8 multiplex with D7-D0 59/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 28. Interfacing the PSD with the 80C251, with One READ Input PSD 80C251SB 2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17 RESET 10 35 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 X1 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 X2 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 ALE PSEN RST WR RD/A16 EA A0 A1 A2 A3 A4 A5 A6 A7 30 31 32 33 34 35 36 37 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 39 40 41 42 43 44 45 46 43 42 41 40 39 38 37 36 A0 A1 A2 A3 A4 A5 A6 A7 24 25 26 27 28 29 30 31 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 33 ALE 47 32 RD 50 18 WR 19 A16 49 10 9 8 RESET RESET 48 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 CNTL0 ( WR) CNTL1( RD) CNTL 2(PSEN) PD0- ALE PD1 PD2 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 A161 29 28 27 25 24 23 22 21 A171 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 RESET AI02881C Figure 29. Interfacing the PSD with the 80C251, with RD and PSEN Inputs 80C251SB 2 3 4 5 6 7 8 9 21 20 11 13 14 15 16 17 RESET 10 35 PSD P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 X1 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 X2 P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 RST EA ALE PSEN WR RD/A16 43 42 41 40 39 38 37 36 A0 A1 A2 A3 A4 A5 A6 A7 24 25 26 27 28 29 30 31 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 A0 A1 A2 A3 A4 A5 A6 A7 30 31 32 33 34 35 36 37 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 39 40 41 42 43 44 45 46 33 ALE 47 32 RD 50 18 WR 19 PSEN 49 10 9 8 RESET RESET 48 ADIO0 ADIO1 ADIO2 ADIO3 ADIO4 ADIO5 ADIO6 ADIO7 ADIO8 ADIO9 ADIO10 ADIO11 ADIO12 ADIO13 ADIO14 ADIO15 CNTL0 ( WR) CNTL1( RD) CNTL 2(PSEN) PD0- ALE PD1 PD2 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 RESET AI02882C 60/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V 80C51XA The Philips 80C51XA MCU family supports an 8or 16-bit, multiplexed bus that can have burst cycles. Address bits (A3-A0) are not multiplexed, while (A19-A4) are multiplexed with data bits (D15-D0) in 16-bit mode. In 8-bit mode, (A11-A4) are multiplexed with data bits (D7-D0). The 80C51XA can be configured to operate in 8bit data mode (see Figure 30). The 80C51XA improves bus throughput and performance be executing burst cycles for code re- trievals. In Burst Mode, address (A19-A4) are latched internally by the PSD, while the 80C51XA changes the A3-A0 signals to retrieve up to 16 bytes of code. The PSD access time is them measured from address A3-A0 valid to data invalid. The PSD bus timing requirement in Burst Mode is identical to the normal bus cycle, except the address setup and hold time with respect to Address Strobe (ALE/AS, PD0) does not apply. Figure 30. Interfacing the PSD with the 80C51XA, 8-bit Data Bus AD7-AD0 AD7-AD0 PSD 31 30 29 28 27 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 30 31 32 33 34 35 36 37 42 41 40 39 38 37 36 35 A8 A9 A10 A11 A12 A13 A14 A15 39 40 41 42 43 44 45 46 68HC11 8 7 RESET 17 19 18 2 34 33 32 43 44 45 46 47 48 49 50 52 51 XT EX RESET IRQ XIRQ MODB PA0 PA1 PA2 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 VRH VRL PA3 PA4 PA5 PA6 PA7 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 PD0 PD1 PD2 PD3 PD4 PD5 MODA E AS R/W 9 10 11 12 13 14 15 16 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 20 21 22 23 24 25 47 50 49 10 9 8 48 ADIO0 ADIO1 ADIO2 ADIO3 AD104 AD105 ADIO6 ADIO7 PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 ADIO8 ADIO9 ADIO10 ADIO11 AD1012 AD1013 ADIO14 ADIO15 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 CNTL0 (R _W) CNTL1(E) CNTL 2 PD0 - AS PD1 PD2 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 29 28 27 25 24 23 22 21 7 6 5 4 3 2 52 51 20 19 18 17 14 13 12 11 RESET 3 5 E 4 AS 6 R/ W RESET AI02884C 61/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V 68HC11 Figure 31 shows a bus interface to a 68HC11 where the PSD is configured in 8-bit, multiplexed mode with E and R/W settings. The DPLD can be used to generate the READ and WR signals for external devices. Figure 31. Interfacing the PSD with a 68HC11 62/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V I/O PORTS There are seven programmable I/O ports: Ports A, B, C, D, E, F and G. Each port pin is individually user configurable, thus allowing multiple functions per port. The ports are configured using PSDsoft or by the MCU writing to on-chip registers in the CSIOP space. The topics discussed in this section are: General Port architecture Port operating modes Port Configuration Registers (PCR) Port Data Registers Individual Port functionality. General Port Architecture The general architecture of the I/O Port block is shown in Figure 32, page 64. Individual Port architectures are shown in Figure 34, page 71 to Figure 36, page 74. In general, once the purpose for a port pin has been defined, that pin is no longer available for other purposes. Exceptions are noted. As shown in Figure 31, page 62, the ports contain an output multiplexer whose select signals are driven by the configuration bits in the Control Registers (Ports E, F and G only) and PSDsoft Configuration. Inputs to the multiplexer include the following: Output data from the Data Out register Latched address outputs CPLD Macrocell output External Chip Select from the CPLD. The Port Data Buffer (PDB) is a tri-state buffer that allows only one source at a time to be read. The Port Data Buffer (PDB) is connected to the Internal Data Bus for feedback and can be read by the MCU. The Data Out and Macrocell outputs, Direction Register and Control Register, and port pin input are all connected to the Port Data Buffer (PDB). The Port pin's tri-state output driver enable is controlled by a two input OR gate whose inputs come from the CPLD AND Array enable product term and the Direction Register. If the enable product term of any of the Array outputs are not defined and that port pin is not defined as a CPLD output in the PSDabel file, the Direction Register has sole control of the buffer that drives the port pin. The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB) feedback path allows the MCU to check the contents of the registers. Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can be configured as latches, registers, or direct inputs to the PLDs. The latches and registers are clocked by Address Strobe (ALE/AS, PD0) or a product term from the PLD AND Array. The outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the MCU. See the section entitled "Input Macrocells (IMC)", on page 44. Port Operating Modes The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft, some by the MCU writing to the registers in CSIOP space, and some by both. The modes that can only be defined using PSDsoft must be programmed into the device and cannot be changed unless the device is reprogrammed. The modes that can be changed by the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input, Peripheral I/O and MCU RESET Modes are the only modes that must be defined before programming the device. All other modes can be changed by the MCU at run-time. See Application Note AN1171 for more detail. Table 43, page 66 summarizes which modes are available on each port. Table 44, page 66 shows how and where the different modes are configured. Each of the port operating modes are described in the following sections. 63/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 32. General I/O Port Architecture DATA OUT REG. D Q D Q DATA OUT WR ADDRESS ALE ADDRESS PORT PIN OUTPUT MUX G MACROCELL OUTPUTS EXT CS INTERNAL DATA BUS READ MUX P OUTPUT SELECT D DATA IN B CONTROL REG. D Q ENABLE OUT WR DIR REG. D Q WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD - INPUT AI02885 64/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V MCU I/O Mode In the MCU I/O mode, the MCU uses the PSD Ports to expand its own I/O ports. By setting up the CSIOP space, the ports on the PSD are mapped into the MCU address space. The addresses of the ports are listed in Table 6, page 17. A port pin can be put into MCU I/O mode by writing a 0 to the corresponding bit in the Control Register (for Ports E, F and G). The MCU I/O direction may be changed by writing to the corresponding bit in the Direction Register, or by the output enable product term. See the section entitled "Port Operating Modes", on page 63. When the pin is configured as an output, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer. See Figure 31, page 62. Ports A, B and C do not have Control Registers, and are in MCU I/O mode by default. They can be used for PLD I/O if they are specified in PSDsoft. PLD I/O Mode The PLD I/O Mode uses a port as an input to the CPLD's Input Macrocells (IMC), and/or as an output from the CPLD's Output Macrocells (OMC). The output can be tri-stated with a control signal. This output enable control signal can be defined by a product term from the PLD, or by resetting the corresponding bit in the Direction Register to 0. The corresponding bit in the Direction Register must not be set to 1 if the pin is defined for a PLD input signal in PSDsoft. The PLD I/O mode is specified in PSDsoft by declaring the port pins, and then specifying an equation in PSDsoft. Address Out Mode For MCUs with a multiplexed address/data bus, Address Out mode can be used to drive latched addresses onto the port pins. These port pins can, in turn, drive external devices. Either the output enable or the corresponding bits of both the Direction Register and Control Register must be set to a 1 for pins to use Address Out mode. This must be done by the MCU at run-time. See Table 44, page 66 for the address output pin assignments on Ports E, F and G for various MCUs. Note: Do not drive address signals with Address Out Mode to an external memory device if it is intended for the MCU to Boot from the external device. The MCU must first Boot from PSD memory so the Direction and Control register bits can be set. Table 42. Port Operating Modes Port Mode Port A Port B Port C Port D Port E Port F Port G MCU I/O Yes Yes Yes Yes Yes Yes Yes PLD I/O McellA Outputs McellB Outputs Additional Ext. CS Outputs PLD Inputs Yes No No Yes Yes Yes No Yes No No Yes Yes No No No Yes No No No No No No Yes Yes No No No No Address Out No No No No Yes (A7 - 0) Yes (A7 - 0) Yes (A7 - 0) or (A15 - 8) Address In Yes Yes Yes Yes No Yes No Data Port No No No No No Yes Yes Peripheral I/O Yes No No Yes No Yes No JTAG ISP No No No No Yes1 No No MCU RESET Mode2 No No No No No Yes Yes Note: 1. Can be multiplexed with other I/O functions. 2. Available to Motorola 16-bit 683xx and HC16 families of MCUs. 65/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 43. Port Operating Mode Settings Mode Control Register Setting Defined in PSDsoft Direction Register Setting VM Register Setting JTAG Enable MCU I/O Declare pins only 0 (Note 4) 1 = output, 0 = input (Note 2) N/A N/A PLD I/O Declare pins and Logic equations N/A (Note 2) N/A N/A Data Port (Port F, G) Selected for MCU with non-multiplexed bus N/A N/A N/A N/A Address Out (Port E, F, G) Declare pins only 1 1 (Note 2) N/A N/A Address In (Port A, B, C, D, F) Declare pins or Logic equation for Input Macrocells N/A N/A N/A N/A Peripheral I/O (Port F) Logic equations (PSEL0 and PSEL1) N/A N/A PIO bit = 1 N/A JTAG ISP 3 Declare pins only N/A N/A N/A JTAG_Enable MCU RESET Mode Specific pin logic level N/A N/A N/A N/A Note: 1. N/A = Not Applicable 2. The direction of the Port A,B,C, and F pins are controlled by the Direction Register ORed with the individual output enable product term (.oe) from the CPLD AND Array. 3. Any of these three methods enables the JTAG pins on Port E. 4. Control Register setting is not applicable to Ports A, B and C. Table 44. I/O Port Latched Address Output Assignments MCU 80C51XA 80C251 All Other MCUs with Multiplexed Bus Port E (PE3-PE0) Port E (PE7-PE4) Port F (PF3-PF0) Port F (PF7-PF4) Port G (PG3-PG0) Port G (PG7-PG4) N/A(1) Address a7-a4 N/A Address a7-a4 Address a11-a8 Address a15-a12 N/A N/A N/A N/A Address a11-a8 Address a15-a12 Address a3-a0 Address a7-a4 Address a3-a0 Address a7-a4 Address a11-a8 (a3-a0 for 8bit MCU) Address a15-a12 (a7-a4 for 8bit MCU) Note: 1. N/A = Not Applicable. 66/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Address In Mode For MCUs that have more than 16 address signals, the higher addresses can be connected to Port A, B, C, D or F, and are routed as inputs to the PLDs. The address input can be latched in the Input Macrocell (IMC) by Address Strobe (ALE/AS, PD0). Any input that is included in the DPLD equations for the primary Flash memory, secondary Flash memory or SRAM is considered to be an address input. Data Port Mode Ports F and G can be used as a data bus port for a MCU with a non-multiplexed address/data bus. The Data Port is connected to the data bus of the MCU. The general I/O functions are disabled in Ports F and G if the ports are configured as a Data Port. Data Port mode is automatically configured in PSDsoft when a non-multiplexed bus MCU is selected. Peripheral I/O Mode Peripheral I/O mode can be used to interface with external 8-bit peripherals. In this mode, all of Port F serves as a tri-state, bi-directional data buffer for the MCU. Peripheral I/O mode is enabled by setting bit 7 of the VM Register to a 1. Figure 32 shows how Port A acts as a bi-directional buffer for the MCU data bus if Peripheral I/O mode is enabled. An equation for PSEL0 and/or PSEL1 must be specified in PSDsoft. The buffer is tri-stated when PSEL0 or PSEL1 is not active. Figure 33. Peripheral I/O Mode RD PSEL0 PSEL PSEL1 VM REGISTER BIT 7 D0 - D7 DATA BUS PA0 - PA7 WR AI02886 67/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V JTAG In-System Programming (ISP) Port E is JTAG compliant, and can be used for InSystem Programming (ISP). You can multiplex JTAG operations with other functions on Port E because In-System Programming (ISP) is not performed during normal system operation. For more information on the JTAG Port, see the section entitled "RESET", on page 33. MCU RESET Mode Ports F and G can be configured to operate in MCU RESET Mode. This mode is available when PSD is configured for the Motorola 16-bit 683xx and HC16 family and is active only during reset. At the rising edge of the RESET input, the MCU reads the logic level on the data bus (D15-D0) pins. The MCU then configures some of its I/O pin functions according to the logic level input on the data bus lines. Two dedicated buffers are usually enabled during RESET to drive the data bus lines to the desired logic level. The PSD can replace the two buffers by configuring Ports F and G to operate in MCU RESET Mode. In this mode, the PSD will drive the pre-defined logic level or data pattern on to the MCU data bus when RESET is active and there is no ongoing bus cycle. After RESET, Ports F and G return to the normal Data Port mode. The MCU RESET Mode is enabled and configured in PSDsoft. The user defines the logic level (data pattern) that will be drive out from Ports F and G during RESET. Port Configuration Registers (PCR) Each Port has a set of Port Configuration Registers (PCR) used for configuration. The contents of the registers can be accessed by the MCU through normal READ/WRITE bus cycles at the addresses given in Table 6, page 17. The addresses in Table 6 are the offsets in hexadecimal from the base of the CSIOP register. The pins of a port are individually configurable and each bit in the register controls its respective pin. For example, bit 0 in a register refers to bit 0 of its port. The three Port Configuration Registers (PCR), shown in Table 45, are used for setting the Port configurations. The default Power-up state for each register in Table 45 is 00h. Control Register Any bit reset to '0' in the Control Register sets the corresponding port pin to MCU I/O mode, and a 1 sets it to Address Out mode. The default mode is MCU I/O. Only Ports E, F and G have an associated Control Register. Table 45. Port Configuration Registers (PCR) Register Name Port MCU Access Control E, F, G WRITE/READ Direction A, B, C, D, E, F, G WRITE/READ Drive Select1 A, B, D, E, G WRITE/READ Note: 1. See Table 49, page 69 for Drive Register bit definition. 68/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Direction Register The Direction Register controls the direction of data flow in the I/O Ports. Any bit set to 1 in the Direction Register causes the corresponding pin to be an output, and any bit set to 0 causes it to be an input. The default mode for all port pins is input. Figure 33, page 67 and Figure 35, page 72 show the Port Architecture diagrams for Ports A/B/C and E/F/G, respectively. The direction of data flow for Ports A, B, C and F are controlled not only by the direction register, but also by the output enable product term from the PLD AND Array. If the output enable product term is not active, the Direction Register has sole control of a given pin's direction. An example of a configuration for a Port with the three least significant bits set to output and the remainder set to input is shown in Table 48. Since Port D only contains four pins, the Direction Register for Port D has only the four least significant bits active. Drive Select Register The Drive Select Register configures the pin driver as Open Drain or CMOS. An external pull-up resistor should be used for pins configured as Open Drain. A pin can be configured as Open Drain if its corresponding bit in the Drive Select Register is set to a 1. The default pin drive is CMOS. Table 49 shows the Drive Register for Ports A, B, D, E and G. It summarizes which pins can be configured as Open Drain outputs. Table 46. Port Pin Direction Control, Output Enable P.T. Not Defined Direction Register Bit Port Pin Mode 0 Input 1 Output Table 47. Port Pin Direction Control, Output Enable P.T. Defined Direction Register Bit Output Enable P.T. Port Pin Mode 0 0 Input 0 1 Output 1 0 Output 1 1 Output Table 48. Port Direction Assignment Example Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 1 1 1 Table 49. Drive Register Pin Assignment Drive Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Port A Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port B Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port D NA(1) NA(1) NA(1) NA(1) Open Drain Open Drain Open Drain Open Drain Port E Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Port G Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Open Drain Note: 1. NA = Not Applicable. 69/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Port Data Registers The Port Data Registers, shown in Table 50, are used by the MCU to write data to or read data from the ports. Table 50 shows the register name, the ports having each register type, and MCU access for each register type. The registers are described next. Data In Port pins are connected directly to the Data In buffer. In MCU I/O Input mode, the pin input is read through the Data In buffer. Data Out Register Stores output data written by the MCU in the MCU I/O Output mode. The contents of the Register are driven out to the pins if the Direction Register or the output enable product term is set to 1. The contents of the register can also be read back by the MCU. Output Macrocells (OMC) The CPLD Output Macrocells (OMC) occupy a location in the MCU's address space. The MCU can read the output of the Output Macrocells (OMC). If the Mask Macrocell Register bits are not set, writing to the Macrocell loads data to the Macrocell flip-flops. See the section entitled "I/O PORTS", on page 63. Mask Macrocell Register Each Mask Macrocell Register bit corresponds to an Output Macrocell (OMC) flip-flop. When the Mask Macrocell Register bit is set to a 1, loading data into the Output Macrocell (OMC) flip-flop is blocked. The default value is 0, or unblocked. Input Macrocells (IMC) The Input Macrocells (IMC) can be used to latch or store external inputs. The outputs of the Input Macrocells (IMC) are routed to the PLD input bus, and can be read by the MCU. See the section entitled "Input Macrocells (IMC)", on page 44. Table 50. Port Data Registers Register Name Port MCU Access Data In A, B, C, D, E, F, G READ - input on pin Data Out A, B, C, D, E, F, G WRITE/READ Output Macrocell A, B READ - outputs of Macrocells WRITE - loading Macrocells Flip-flop Mask Macrocell A, B WRITE/READ - prevents loading into a given Macrocell Input Macrocell A, B, C READ - outputs of the Input Macrocells Enable Out A, B, C, F READ - the output enable control of the port driver 70/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Enable Out The Enable Out register can be read by the MCU. It contains the output enable values for a given port. A 1 indicates the driver is in output mode. A 0 indicates the driver is in tri-state and the pin is in input mode. Ports A, B and C - Functionality and Structure Ports A, B, and C have similar functionality and structure, as shown in Figure 34. The ports can be configured to perform one or more of the following functions: MCU I/O Mode CPLD Output - Macrocells McellA7-McellA0 can be connected to Port A. McellB7-McellB0 can be connected to Port B. External Chip Select (ECS7-ECS0) can be connected to Port C or Port F. CPLD Input - Via the Input Macrocells (IMC). Address In - Additional high address inputs using the Input Macrocells (IMC). Open Drain - pins PA7-PA0 can be configured to Open Drain mode. Figure 34. Port A, B, and C Structure DATA OUT Register D DATA OUT Q WR PORT Pin OUTPUT MUX MCELLA7-MCELLA0 (Port A) MCELLB7-MCELLB0 (Port B) Ext.CS (Port C) INTERNAL DATA BUS READ MUX P D DATA IN B ENABLE OUT DIR Register D Q WR ENABLE PRODUCT TERM (.OE) INPUT MACROCELL CPLD - INPUT AI04936B 71/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Port D - Functionality and Structure Port D has four I/O pins. See Figure 35. Port D can be configured to perform one or more of the following functions: MCU I/O mode CPLD Input - direct input to the CPLD, no Input Macrocells (IMC) Port D pins can be configured in PSDsoft as input pins for other dedicated functions: Address Strobe (ALE/AS, PD0) CLKIN (PD1) as input to the Macrocells Flipflops and APD counter PSD Chip Select Input (CSI, PD2). Driving this signal High disables the Flash memory, SRAM and CSIOP. WRITE-Enable High-byte (WRH, PD3) input, or as DBE input from a MC68HC912. Figure 35. Port D Structure DATA OUT Register DATA OUT D Q WR PORT D PIN OUTPUT MUX INTERNAL DATA BUS READ MUX OUTPUT SELECT P D DATA IN B DIR Register D WR Q CPLD - INPUT AI04937 72/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Port E - Functionality and Structure Port E can be configured to perform one or more of the following functions (see Figure 36, page 74): MCU I/O Mode In-System Programming (ISP) - JTAG port can be enabled for programming/erase of the PSD device. (See the section entitled "RESET", on page 33, for more information on JTAG programming.) Open Drain - pins can be configured in Open Drain Mode Battery Backup features - PE6 can be configured for a battery input supply, Voltage Standby (VSTBY). - PE7 can be configured as a Battery-on Indicator (VBATON), indicating when VCC is less than VBAT. Latched Address output - Provide latched address output. Port F - Functionality and Structure Port F can be configured to perform one or more of the following functions: MCU I/O Mode CPLD Output - External Chip Select (ECS7ECS0) can be connected to Port F or Port C. CPLD Input - direct input to the CPLD, no Input Macrocells (IMC) Latched Address output - Provide latched address output as per Table 44, page 66. Data Port - connected to D7-D0 when Port F is configured as Data Port for a non-multiplexed bus Peripheral Mode MCU RESET Mode - for 16-bit Motorola 683xx and HC16 MCUs Port G - Functionality and Structure Port G can be configured to perform one or more of the following functions: MCU I/O Mode Latched Address output - Provide latched address output as per Table 44, page 66. Open Drain - pins can be configured in Open Drain Mode Data Port - connected to D15-D8 when Port G is configured as Data Port for a non-multiplexed bus MCU RESET Mode - for 16-bit Motorola 683xx and HC16 MCUs 73/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 36. Port E, F, and G Structure DATA OUT Register D Q D Q DATA OUT WR ADDRESS ALE ADDRESS A[ 7:0] OR A[15:8] G PORT Pin OUTPUT MUX Ext. CS (Port F) INTERNAL DATA BUS READ MUX P OUTPUT SELECT D DATA IN B CONTROL Register D ENABLE OUT Q WR DIR Register D Q WR ENABLE PRODUCT TERM (.OE) CPLD - INPUT (Port F) ISP or Battery Back-Up (Port E) Configuration Bit AI04938 74/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V POWER MANAGEMENT The PSD device offers configurable power saving options. These options may be used individually or in combinations, as follows: All memory blocks in a PSD (primary Flash memory, secondary Flash memory, and SRAM) are built with power management technology. In addition to using special silicon design methodology, power management technology puts the memories into Standby Mode when address/data inputs are not changing (zero DC current). As soon as a transition occurs on an input, the affected memory "wakes up", changes and latches its outputs, then goes back to standby. The designer does not have to do anything special to achieve memory Standby Mode when no inputs are changing--it happens automatically. The PLD sections can also achieve Standby Mode when its inputs are not changing, as described for the Power Management Mode Registers (PMMR), later. The Automatic Power Down (APD) block allows the PSD to reduce to standby current automatically. The APD Unit also blocks MCU address/data signals from reaching the memories and PLDs. This feature is available on all PSD devices. The APD Unit is described in more detail in the section entitled "Automatic Power-down (APD) Unit and Power-down Mode", on page 76. Built in logic monitors the Address Strobe of the MCU for activity. If there is no activity for a certain period (the MCU is asleep), the APD Unit initiates Power-down mode (if enabled). Once in Power-down mode, all address/data signals are blocked from reaching the PSD memories and PLDs, and the memories are deselected internally. This allows the memories and PLDs to remain in Standby Mode even if the address/data signals are changing state externally (noise, other devices on the MCU bus, etc.). Keep in mind that any unblocked PLD input signals that are changing states keeps the PLD out of Standby Mode, but not the memories. PSD Chip Select Input (CSI, PD2) can be used to disable the internal memories, placing them in Standby Mode even if inputs are changing. This feature does not block any internal signals or disable the PLDs. This is a good alternative to using the APD Unit, especially if your MCU has a chip select output. There is a slight penalty in memory access time when PSD Chip Select Input (CSI, PD2) makes its initial transition from deselected to selected. The Power Management Mode Registers (PMMR) can be written by the MCU at run-time to manage power. All PSD devices support "blocking bits" in these registers that are set to block designated signals from reaching both PLDs. Current consumption of the PLDs is directly related to the composite frequency of the changes on their inputs (see Figure 40, page 82). Significant power savings can be achieved by blocking signals that are not used in DPLD or CPLD logic equations at run-time. PSDsoft creates a fuse map that automatically blocks the low address byte (A7-A0) or the control signals (CNTL0-CNTL2, ALE and WRITE-Enable Highbyte (WRH/DBE, PD3)) if none of these signals are used in PLD logic equations. PSD devices have a Turbo bit in PMMR0. This bit can be set to turn the Turbo mode off (the default is with Turbo mode turned on). While Turbo mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC current). Even when inputs do change, significant power can be saved at lower frequencies (AC current), compared to when Turbo mode is on. When the Turbo mode is on, there is a significant DC current component, and the AC component is higher. 75/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Automatic Power-down (APD) Unit and Power-down Mode the appropriate bits in the Power Management The APD Unit, shown in Figure 37, puts the PSD Mode Registers (PMMR). The blocked signals into Power-down mode by monitoring the activity include MCU control signals and the common of Address Strobe (ALE/AS, PD0). If the APD Unit CLKIN (PD1). Note that blocking CLKIN (PD1) is enabled, as soon as activity on Address Strobe from the PLDs does not block CLKIN (PD1) (ALE/AS, PD0) stops, a four bit counter starts from the APD Unit. counting. If Address Strobe (ALE/AS, PD0) remains inactive for fifteen clock periods of CLKIN All PSD memories enter Standby Mode and are (PD1), Power-down (PDN) goes High, and the drawing standby current. However, the PLDs PSD enters Power-down mode, as discussed and I/O ports blocks do not go into Standby next. Mode because you do not want to have to wait for the logic and I/O to "wake-up" before their Power-down Mode outputs can change. See Table 52, page 76 for By default, if you enable the APD Unit, PowerPower-down mode effects on PSD ports. down mode is automatically enabled. The device Typical Standby current is or the order of A. enters Power-down mode if Address Strobe (ALE/ This standby current value assumes that there AS, PD0) remains inactive for fifteen periods of are no transitions on any PLD input. CLKIN (PD1). The following should be kept in mind when the PSD is in Power-down mode: Table 51. Effect of Power-down Mode on Ports If Address Strobe (ALE/AS, PD0) starts pulsing Port Function Pin Level again, the PSD returns to normal operation. The MCU I/O No Change PSD also returns to normal operation if either PSD Chip Select Input (CSI, PD2) is Low or the PLD Out No Change Reset (RESET) input is High. Address Out Undefined The MCU address/data bus is blocked from all memory and PLDs. Data Port Tri-State Various signals can be blocked (prior to PowerPeripheral I/O Tri-State down mode) from entering the PLDs by setting Figure 37. APD Unit APD EN PMMR0 BIT 1=1 TRANSITION DETECTION DISABLE BUS INTERFACE ALE CLR RESET CSI PD Secondary Flash Memory Select Primary Flash Memory Select APD COUNTER EDGE DETECT PD PLD CLKIN SRAM Select POWER DOWN (PDN) Select DISABLE Primary and Secondary FLASH Memory and SRAM AI04939 Table 52. PSD Timing and Standby Current During Power-down Mode Mode Power-down PLD Propagation Delay Normal tPD (Note 1) Memory Access Time Access Recovery Time to Normal Access Typical Standby Current No Access tLVDV 50 A (Note 2) Note: 1. Power-down does not affect the operation of the PLD. The PLD operation in this mode is based only on the Turbo bit. 2. Typical current consumption assuming no PLD inputs are changing state and the PLD Turbo bit is 0. 76/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Other Power Saving Options The PSD offers other reduced power saving options that are independent of the Power-down mode. Except for the SRAM Standby and PSD Chip Select Input (CSI, PD2) features, they are enabled by setting bits in PMMR0 and PMMR2 (as summarized in Table 23 and Table 24, page 21). PLD Power Management The power and speed of the PLDs are controlled by the Turbo bit (bit 3) in PMMR0. By setting the bit to 1, the Turbo mode is off and the PLDs consume the specified standby current when the inputs are not switching for an extended time of 70 ns. The propagation delay time is increased after the Turbo bit is set to 1 (turned off) when the inputs change at a composite frequency of less than 15 MHz. When the Turbo bit is reset to '0' (turned on), the PLDs run at full power and speed. The Turbo bit affects the PLD's DC power, AC power, and propagation delay. See the AC and DC characteristics tables for PLD timing values (Table 71). Blocking MCU control signals with the PMMR2 bits can further reduce PLD AC power consumption. SRAM Standby Mode (Battery Backup) The PSD supports a battery backup mode in which the contents of the SRAM are retained in the event of a power loss. The SRAM has Voltage Standby (VSTBY, PE6) that can be connected to an external battery. When VCC becomes lower than VSTBY then the PSD automatically connects to Voltage Standby (VSTBY, PE6) as a power source to the SRAM. The SRAM standby current (ISTBY) is typically 0.5 A. The SRAM data retention voltage is 2V minimum. The Battery-on Indicator (VBATON) can be routed to PE7. This signal indicates when the VCC has dropped below VSTBY, and that the SRAM is running on battery power. PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft as PSD Chip Select Input (CSI). When Low, the signal selects and enables the internal primary Flash memory, secondary Flash memory, SRAM, and I/ O blocks for READ or WRITE operations involving the PSD. A High on PSD Chip Select Input (CSI, PD2) disables the primary Flash memory, secondary Flash memory, and SRAM, and reduces the PSD power consumption. However, the PLD and I/O signals remain operational when PSD Chip Select Input (CSI, PD2) is High. There may be a timing penalty when using PSD Chip Select Input (CSI, PD2) depending on the speed grade of the PSD that you are using. See the timing parameter tSLQV in Table 71. Input Clock The PSD provides the option to turn off CLKIN (PD1) to the PLD to save AC power consumption. CLKIN (PD1) is an input to the PLD AND Array and the Output Macrocells (OMC). During Power-down mode, or, if CLKIN (PD1) is not being used as part of the PLD logic equation, the clock should be disabled to save AC power. CLKIN (PD1) is disconnected from the PLD AND Array or the Macrocells block by setting bits 4 or 5 to a 1 in PMMR0. Figure 38. Enable Power-down Flow Chart RESET Enable APD Set PMMR0 Bit 1 = 1 OPTIONAL Disable desired inputs to PLD by setting PMMR0 bits 4 and 5 and PMMR2 bits 0 to 6. No ALE/AS idle for 15 CLKIN clocks? Yes PSD in Power Down Mode AI04940 77/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Input Control Signals The PSD provides the option to turn off the address input (A7-A0) and input control signals (CNTL0, CNTL1, CNTL2, Address Strobe (ALE/ AS, PD0) and WRITE-Enable High-byte (WRH/ DBE, PD3)) to the PLD to save AC power consumption. These signals are inputs to the PLD AND Array. During Power-down mode, or, if any of them are not being used as part of the PLD logic equation, these control signals should be disabled to save AC power. They are disconnected from the PLD AND Array by setting bits 0, 2, 3, 4, 5 and 6 to a 1 in PMMR2. Table 53. ADP Counter Operation APD Enable Bit ALE PD Polarity ALE Level APD Counter 0 X X Not Counting 1 X Pulsing Not Counting 1 1 1 Counting (Generates PDN after 15 Clocks) 1 0 0 Counting (Generates PDN after 15 Clocks) 78/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V RESET TIMING AND DEVICE STATUS AT RESET Power-on RESET Upon Power-up, the PSD requires a Reset (RESET) pulse of duration tNLNH-PO (minimum 1ms) after VCC is steady. During this period, the device loads internal configurations, clears some of the registers and sets the Flash memory into Operating mode. After the rising edge of Reset (RESET), the PSD remains in the RESET Mode for an additional period, tOPR (maximum 120 ns), before the first memory access is allowed. The PSD Flash memory is reset to the READ Mode upon Power-up. Sector Select (FS0-FS15 and CSBOOT0-CSBOOT3) must all be Low, WRITE Strobe (WR/WRL, CNTL0) High, during Power-on RESET for maximum security of the data contents and to remove the possibility of data being written on the first edge of WRITE Strobe (WR/WRL, CNTL0). Any Flash memory WRITE cycle initiation is prevented automatically when VCC is below VLKO. Warm RESET Once the device is up and running, the device can be reset with a pulse of a much shorter duration, tNLNH (minimum 150ns). The same tOPR period is needed before the device is operational after Warm RESET. Figure 39, page 80 shows the timing of the Power-up and Warm RESET. I/O Pin, Register and PLD Status at RESET Table 54 shows the I/O pin, register and PLD status during Power-on RESET, Warm RESET and Power-down mode. PLD outputs are always valid during Warm RESET, and they are valid in Poweron RESET once the internal PSD Configuration bits are loaded. This loading of PSD is completed typically long before the VCC ramps up to operating level. Once the PLD is active, the state of the outputs are determined by equations specified in PSDsoft. RESET of Flash Memory Erase and Program Cycles An external Reset (RESET) also resets the internal Flash memory state machine. During a Flash memory Program or Erase cycle, Reset (RESET) terminates the cycle and returns the Flash memory to the READ Mode within a period of tNLNH-A (minimum 25s). Table 54. Status During Power-on RESET, Warm RESET, and Power-down Mode Port Configuration Power-on RESET Warm Reset Power-down Mode MCU I/O Input mode Input mode Unchanged PLD Output Valid after internal PSD configuration bits are loaded Valid Depends on inputs to PLD (addresses are blocked in PD mode) Address Out Tri-stated Tri-stated Not defined Data Port Tri-stated Tri-stated Tri-stated Peripheral I/O Tri-stated Tri-stated Tri-stated Register Power-On Reset Warm Reset Power-down Mode PMMR0 and PMMR2 Cleared to 0 Unchanged Unchanged Macrocells Flip-flop status Cleared to 0 by internal Power-On Reset Depends on .re and .pr equations Depends on .re and .pr equations VM Register (1) Initialized, based on the selection in PSDsoft Configuration menu Initialized, based on the selection in PSDsoft Configuration menu Unchanged All other registers Cleared to 0 Cleared to 0 Unchanged Note: 1. The SR_code and Peripheral Mode bits in the VM Register are always cleared to '0' on Power-on RESET or Warm RESET. 79/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 39. Reset (RESET) Timing VCC VCC(min) tNLNH-PO Power-On Reset tOPR tNLNH tNLNH-A tOPR Warm Reset RESET AI02866b PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE The JTAG Serial Interface on the PSD can be enJTAG_ON = PSDsoft_enabled + abled on Port E (see Table 55). All memory blocks /* An NVM configuration bit inside (primary Flash memory and secondary Flash the PSD is set by the designer in memory), PLD logic, and PSD Configuration bits the PSDsoft Configuration utilimay be programmed through the JTAG-ISC Serial ty. This dedicates the pins for Interface. A blank device can be mounted on a JTAG at all times (compliant with printed circuit board and programmed using JTAG In-System Programming (ISP). IEEE 1149.1 */ The standard JTAG signals (IEEE 1149.1) are Microcontroller_enabled + TMS, TCK, TDI, and TDO. Two additional signals, /* The microcontroller can set a TSTAT and TERR, are optional JTAG extensions bit at run-time by writing to the used to speed up Program and Erase cycles. PSD register, JTAG Enable. This By default, on a blank PSD (as shipped from the register is located at address factory, or after erasure), four pins on Port E are enabled for the basic JTAG signals TMS, TCK, CSIOP + offset C7h. Setting the TDI, and TDO. JTAG_ENABLE bit in this register See Application Note AN1153 for more details on will enable the pins for JTAG use. JTAG In-System Programming (ISP). This bit is cleared by a PSD reset Standard JTAG Signals or the microcontroller. See Table The standard JTAG signals (TMS, TCK, TDI, and 21 for bit definition. */ TDO) can be enabled by any of three different conPSD_product_term_enabled; ditions that are logically ORed. When enabled, /* A dedicated product term (PT) TDI, TDO, TCK, and TMS are inputs, waiting for a inside the PSD can be used to enserial command from an external JTAG controller device (such as FlashLINK or Automated Test able the JTAG pins. This PT has Equipment). When the enabling command is rethe reserved name JTAGSEL. Once ceived from the external JTAG controller device, defined as a node in PSDabel, the TDO becomes an output and the JTAG channel is designer can write an equation for fully functional inside the PSD. The same comJTAGSEL. This method is used when mand that enables the JTAG channel may optionally enable the two additional JTAG pins, TSTAT the Port E JTAG pins are multiand TERR. plexed with other I/O signals. It The following symbolic logic equation specifies the is recommended to tie logically conditions enabling the four basic JTAG pins the node JTAGSEL to the JEN\ sig(TMS, TCK, TDI, and TDO) on their respective nal on the Flashlink cable when Port E pins. For purposes of discussion, the logic multiplexing JTAG signals. See Aplabel JTAG_ON is used. When JTAG_ON is true, plication Note 1153 for details. the four pins are enabled for JTAG. When JTAG_ON is false, the four pins can be used for */ general PSD I/O. 80/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V The state of the PSD Reset (RESET) signal does not interrupt (or prevent) JTAG operations if the JTAG pins are dedicated by an NVM configuration bit (via PSDsoft). However, Reset (RESET) will prevent or interrupt JTAG operations if the JTAG Enable Register (as shown in Table 21, page 20) is used to enable the JTAG pins. The PSD supports JTAG In-System-Programmability (ISP) commands, but not Boundary Scan. ST's PSDsoft software tool and FlashLINK JTAG programming cable implement the JTAG In-System-Programmability (ISP) commands. JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by a JTAG command received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to speed Program and Erase cycles by indicating status on PSD pins instead of having to scan the status out serially using the standard JTAG channel. See Application Note AN1153. TERR indicates if an error has occurred when erasing a sector or programming in Flash memory. This signal goes Low (active) when an Error condition occurs, and stays Low until a specific JTAG command is executed or a Reset (RESET) pulse is received after an "ISC_DISABLE" command. TSTAT behaves the same as Ready/Busy (PE4) described in the section entitled "Ready/Busy (PE4)", on page 24. TSTAT is High when the PSD3200 Family device is in READ Mode (primary Flash memory and secondary Flash memory contents can be read). TSTAT is Low when Flash memory Program or Erase cycles are in progress, and also when data is being written to the secondary Flash memory. INITIAL DELIVERY STATE When delivered from ST, the PSD device has all bits in the memory and PLDs set to 1. The PSD Configuration Register bits are set to 0. The code, configuration, and PLD logic are loaded using the TSTAT and TERR can be configured as opendrain type signals with a JTAG command. Note: The state of Reset (Reset) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Configuration bit (via PSDsoft). However, Reset (Reset) prevents or interrupts JTAG operations if the JTAG Enable Register (as shown in Table 21, page 20) is used to enable the JTAG signals. Security and Flash memory Protection When the security bit is set, the device cannot be read on a Device Programmer or through the JTAG Port. When using the JTAG Port, only a Full Chip Erase command is allowed. All other Program, Erase and Verify commands are blocked. Full Chip Erase returns the device to a non-secured blank state. The Security Bit can be set in PSDsoft. All primary Flash memory and secondary Flash memory sectors can individually be sector protected against erasure. The sector protect bits can be set in PSDsoft. Table 55. JTAG Port Signals Port E Pin JTAG Signals Description PE0 TMS Mode Select PE1 TCK Clock PE2 TDI Serial Data In PE3 TDO Serial Data Out PE4 TSTAT Status PE5 TERR Error Flag programming procedure. Information for programming the device is available directly from ST. Please contact your local sales representative. 81/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V AC/DC PARAMETERS These tables describe the AD and DC parameters of the PSD3200 Family: DC Electrical Specification - Power-down and RESET Timing The following are issues concerning the parameters presented: In the DC specification the supply current is given for different modes of operation. Before calculating the total power consumption, determine the percentage of time that the PSD is in each mode. Also, the supply power is considerably different if the Turbo bit is 0. The AC power component gives the PLD, Flash memory, and SRAM mA/MHz specification. Figure 40 shows the PLD mA/MHz as a function of the number of Product Terms (PT) used. In the PLD timing parameters, add the required delay when Turbo bit is 0. AC Timing Specification PLD Timing - Combinatorial Timing - Synchronous Clock Mode - Asynchronous Clock Mode - Input Macrocell Timing MCU Timing - READ Timing - WRITE Timing - Peripheral Mode Timing Figure 40. PLD ICC / Frequency Consumption 60 VCC = 3V O URB T 50 RB O O FF 40 30 TU ICC - (mA) ) 100% ON ( O TURB 5%) ON (2 20 10 PT 100% PT 25% F O RB TU OF 0 0 5 10 15 20 HIGHEST COMPOSITE FREQUENCY AT PLD INPUTS (MHz) 25 AI04942 82/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 56. Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode On) Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) = 8 MHz = 4 MHz % Flash memory Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 10% % Power-down Mode = 90% Number of product terms used Turbo Mode (from fitter report) = 54 PT % of total product terms = 54/217 = 25% = ON Calculation (using typical values) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE + %SRAM x 0.8 mA/MHz x Freq ALE + % PLD x 1.1 mA/MHz x Freq PLD + #PT x 200 A/PT) = 50 A x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz + 0.15 x 0.8 mA/MHz x 4 MHz + 1.1 mA/MHz x 8 MHz + 54 x 0.2 mA/PT) = 45 A + 0.1 x (3.84 + 0.48 + 8.8 + 10.8 mA) = 45 A + 0.1 x 23.92 = 45 A + 2.39 mA = 2.43 mA This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT = 0 mA. 83/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 57. Example of PSD Typical Power Calculation at VCC = 3.0V (with Turbo Mode Off) Conditions Highest Composite PLD input frequency (Freq PLD) MCU ALE frequency (Freq ALE) = 8 MHz = 4 MHz % Flash memory Access = 80% % SRAM access = 15% % I/O access = 5% (no additional power above base) Operational Modes % Normal = 10% % Power-down Mode = 90% Number of product terms used Turbo Mode (from fitter report) = 54 PT % of total product terms = 54/217 = 25% = Off Calculation (using typical values) ICC total = Ipwrdown x %pwrdown + %normal x (ICC (ac) + ICC (dc)) = Ipwrdown x %pwrdown + % normal x (%flash x 1.2 mA/MHz x Freq ALE + %SRAM x 0.8 mA/MHz x Freq ALE + % PLD x (from graph using Freq PLD)) = 50 A x 0.90 + 0.1 x (0.8 x 1.2 mA/MHz x 4 MHz + 0.15 x 0.8 mA/MHz x 4 MHz + 15 mA) = 45 A + 0.1 x (3.84 + 0.48 + 15) = 45 A + 0.1 x 18.84 = 45 A + 1.94 mA = 1.98 mA This is the operating power with no Flash memory Program or Erase cycles in progress. Calculation is based on IOUT = 0 mA. 84/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 58. Absolute Maximum Ratings Symbol Parameter TSTG Storage Temperature TLEAD Lead Temperature during Soldering (20 seconds max.)1 Min. Max. Unit -65 150 C 235 C VIO Input and Output Voltage (Q = VOH or Hi-Z) -0.6 4.0 V VCC Supply Voltage -0.6 4.0 V VPP Device Programmer Supply Voltage -0.6 13.5 V VESD Electrostatic Discharge Voltage (Human Body model) 2 -2000 2000 V Note: 1. IPC/JEDEC J-STD-020A 2. JEDEC Std JESD22-A114A (C1=100 pF, R1=1500 , R2=500 ) 85/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 59. Operating Conditions Symbol VCC Parameter Min. Max. Unit Supply Voltage 2.7 3.6 V Ambient Operating Temperature (industrial) -40 85 C 0 70 C TA Ambient Operating Temperature (commercial) Table 60. AC Symbols for PLD Timing Signal Letters Signal Behavior A Address Input t Time C CEout Output L Logic Level Low or ALE D Input Data H Logic Level High E E Input V Valid I Interrupt Input X No Longer a Valid Logic Level L ALE Input Z Float N RESET Input or Output PW Pulse Width P Port Signal Output R UDS, LDS, DS, RD, PSEN Inputs S Chip Select Input T R/W Input W WR Input B VSTBY Output M Output Macrocell Example: tAVLX - Time from Address Valid to ALE Invalid. Table 61. AC Measurement Conditions Symbol CL Parameter Load Capacitance Min. Max. Unit 30 Note: 1. Output Hi-Z is defined as the point where data out is no longer driven. 86/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. pF PSD4256G6V Table 62. Capacitance Symbol Parameter Test Condition Typ.2 Max. Unit CIN Input Capacitance (for input pins) VIN = 0V 4 6 pF COUT Output Capacitance (for input/ output pins) VOUT = 0V 8 12 CVPP Capacitance (for CNTL2/VPP) VPP = 0V 18 25 pF pF Note: 1. Sampled only, not 100% tested. 2. Typical values are for TA = 25C and nominal supply voltages. Figure 41. AC Measurement I/O Waveform Figure 42. AC Measurement Load Circuit 2.0 V 0.9VCC 400 Test Point 1.5V Device Under Test 0V CL = 30 pF (Including Scope and Jig Capacitance) AI04947 AI04948 Figure 43. Switching Waveforms - Key WAVEFORMS INPUTS OUTPUTS STEADY INPUT STEADY OUTPUT MAY CHANGE FROM HI TO LO WILL BE CHANGING FROM HI TO LO MAY CHANGE FROM LO TO HI WILL BE CHANGING LO TO HI DON'T CARE CHANGING, STATE UNKNOWN OUTPUTS ONLY CENTER LINE IS TRI-STATE AI03102 87/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 63. DC Characteristics Symbol Parameter Conditions Min. Typ. Max. Unit VIH High Level Input Voltage 2.7V < VCC < 3.6V 0.7VCC VCC +0.5 V VIL Low Level Input Voltage 2.7V < VCC < 3.6V -0.5 0.8 V VIH1 RESET High Level Input Voltage (Note 1) 0.8VCC VCC +0.5 V VIL1 RESET Low Level Input Voltage -0.5 0.2VCC -0.1 V VHYS RESET Pin Hysteresis 0.3 VLKO VCC (min) for Flash Erase and Program 1.5 VOL Output Low Voltage (Note 1) V 2.3 V IOL = 20 A, VCC = 2.7V 0.01 0.1 V IOL = 4 mA, VCC = 2.7V 0.15 0.45 V Output High Voltage Except VSTBY On IOH = -20 A, VCC = 2.7V 2.6 2.69 V IOH = -1 mA, VCC = 2.7V 2.3 2.4 V VOH1 Output High Voltage VSTBY On IOH1 = -1 A VSTBY - 0.8 VSTBY SRAM Standby Voltage ISTBY SRAM Standby Current VCC = 0V IIDLE Idle Current (VSTBY input) VCC > VSTBY -0.1 VDF SRAM Data Retention Voltage Only on VSTBY 2 ISB Standby Supply Current for Power-down Mode CSI >VCC -0.3V (Notes 2,3) ILI Input Leakage Current VSS < VIN < VCC ILO Output Leakage Current 0.45 < VIN < VCC VOH PLD Only ICC (DC) Operating (Note 5) Supply Current Flash memory SRAM ICC (AC) (Note Note: 1. 2. 3. 4. 5. V 2.0 0.5 VCC V 1 A 0.1 A V 50 100 A -1 0.1 1 A -10 5 10 A PLD_TURBO = Off, f = 0 MHz (Note 3) 0 PLD_TURBO = On, f = 0 MHz 200 400 A/ PT During Flash memory WRITE/Erase Only 10 25 mA Read only, f = 0 MHz 0 0 mA f = 0 MHz 0 0 mA A/ PT PLD AC Adder note 4 Flash memory AC Adder 1.2 1.8 mA/ MHz SRAM AC Adder 0.8 1.5 mA/ MHz 5) Reset (RESET) has hysteresis. VIL1 is valid at or below 0.2VCC -0.1. VIH1 is valid at or above 0.8VCC. CSI deselected or internal PD is active. PLD is in non-Turbo mode, and none of the inputs are switching. Please see Figure 40, page 82 for the PLD current calculation. IOUT = 0 mA Note: 1. Conditions (in addition to those in Table 59, VCC = 4.5 to 5.5V): VSS = 0V; CL for Port 0, ALE and PSEN output is 100pF; CL for other outputs is 80pF 88/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 44. Input to Output Disable / Enable INPUT tER tEA INPUT TO OUTPUT ENABLE/DISABLE AI02863 Table 64. CPLD Combinatorial Timing -10 Symbol Parameter Turbo Off Unit Max PT Aloc +4 + 20 ns Conditions Min tPD CPLD Input Pin/Feedback to CPLD Combinatorial Output 38 tEA CPLD Input to CPLD Output Enable 43 + 20 ns tER CPLD Input to CPLD Output Disable 43 + 20 ns tARP CPLD Register Clear or Preset Delay 38 + 20 ns tARPW CPLD Register Clear or Preset Pulse Width + 20 ns tARD CPLD Array Delay 28 Any Macrocell 23 +4 Max PT Aloc ns Table 65. CPLD Macrocell Synchronous Clock Mode Timing -10 Symbol Parameter Conditions Min Maximum Frequency External Feedback fMAX Maximum Frequency Internal Feedback (fCNT) Maximum Frequency Pipelined Data Turbo Off Unit 1/(tS+tCO) 22.7 MHz 1/(tS+tCO-10) 29.4 MHz 1/(tCH+tCL) 45.0 MHz tS Input Setup Time 18 tH Input Hold Time 0 ns tCH Clock High Time Clock Input 11 ns tCL Clock Low Time Clock Input 11 ns tCO Clock to Output Delay Clock Input 26 tARD CPLD Array Delay Any Macrocell 23 tMIN Minimum Clock Period 1 tCH+tCL +4 + 20 ns ns +4 22 ns ns Note: 1. CLKIN (PD1) tCLCL = tCH + tCL. 89/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 66. CPLD Macrocell Asynchronous Clock Mode Timing -10 Symbol Parameter Min Maximum Frequency External Feedback fMAXA Maximum Frequency Internal Feedback (fCNTA) Maximum Frequency Pipelined Data PT Aloc Conditions Max Turbo Off Unit 1/(tSA+tCOA) 23.8 MHz 1/(tSA+tCOA-10) 31.25 MHz 1/(tCHA+tCLA) 38.4 MHz tSA Input Setup Time 8 tHA Input Hold Time 10 tCHA Clock High Time 15 + 20 ns tCLA Clock Low Time 12 + 20 ns tCOA Clock to Output Delay + 20 ns tARD CPLD Array Delay tMINA Minimum Clock Period +4 Any Macrocell 23 +4 32 tCL CLKIN tS ns ns Figure 45. Synchronous Clock Mode Timing - PLD tCH ns ns 34 1/fCNTA + 20 tH INPUT tCO REGISTERED OUTPUT AI02860 Figure 46. Asynchronous RESET / Preset tARPW RESET/PRESET INPUT tARP REGISTER OUTPUT AI02864 90/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 47. Asynchronous Clock Mode Timing (product term clock) tCHA tCLA CLOCK tSA tHA INPUT tCOA REGISTERED OUTPUT AI02859 Figure 48. Input Macrocell Timing (Product Term Clock) t INH t INL PT CLOCK t IS t IH INPUT OUTPUT t INO AI03101 Table 67. Input Macrocell Timing -10 Symbol Parameter Conditions Min Max PT Aloc Turbo Off Unit tIS Input Setup Time (Note 1) 0 tIH Input Hold Time (Note 1) 25 tINH NIB Input High Time (Note 1) 13 ns tINL NIB Input Low Time (Note 1) 12 ns tINO NIB Input to Combinatorial Delay (Note 1) ns + 20 55 +4 + 20 ns ns Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to tAVLX and tLXAX. 91/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 68. Program, WRITE and Erase Times Symbol Parameter Min. Flash Program Typ. 3 Flash Bulk Erase (not pre-programmed) 10 tWHQV3 Sector Erase (pre-programmed) 1 tWHQV2 Sector Erase (not pre-programmed) 2.2 Byte Program 14 Program / Erase Cycles (per Sector) tWHWLO tQ7VQV Unit 8.5 Flash Bulk Erase1 (pre-programmed) tWHQV1 Max. s 30 s s 30 s s 1200 s 100,000 Sector Erase Time-Out cycles 100 s 2,3 30 DQ7 Valid to Output (DQ7-DQ0) Valid (Data Polling) ns Note: 1. Programmed to all zero before erase. 2. The polling status, DQ7, is valid tQ7VQV time units before the data byte, DQ0-DQ7, is valid for reading. 3. DQ7 is DQ15 for Motorola MCU with 16-bit data bus. Figure 49. Peripheral I/O WRITE Timing Diagram ALE /AS A / D BUS ADDRESS DATA OUT tWLQV tWHQZ (PF) (PF) WR tDVQV (PF) PORT F DATA OUT AI05741 92/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 50. READ Timing Diagram tAVLX 1 tLXAX ALE /AS tLVLX A/D MULTIPLEXED BUS ADDRESS VALID DATA VALID tAVQV ADDRESS NON-MULTIPLEXED BUS ADDRESS VALID DATA NON-MULTIPLEXED BUS DATA VALID tSLQV CSI tRLQV tRHQX tRLRH RD (PSEN, DS) tRHQZ tEHEL E tTHEH tELTL R/ W tAVPV ADDRESS OUT AI02895 Note: 1. tAVLX and tLXAX are not required for 80C251 in Page Mode or 80C51XA in Burst Mode. 93/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 69. READ Timing -10 Symbol Parameter Conditions Min tLVLX ALE or AS Pulse Width tAVLX Address Setup Time tLXAX Address Hold Time Address Valid to Data Valid tAVQV Address Valid to Data Valid, 8031, 80251 tSLQV Max Turbo Off Unit 22 ns (Note 3) 7 ns (Note 3) 8 ns 2.7 < VCC < 3.6V (Note 3) 3.0 < VCC < 3.6V (Note 3) CS Valid to Data Valid 100 + 20 ns 90 + 20 ns 100 ns RD to Data Valid 8-Bit Bus (Note 5) 35 ns RD or PSEN to Data Valid 8-Bit Bus, 8031, 80251 (Note 2) 45 ns tRHQX RD Data Hold Time (Note 1) tRLRH RD Pulse Width tRHQZ RD to Data High-Z tEHEL E Pulse Width 38 ns tTHEH R/W Setup Time to Enable 10 ns tELTL R/W Hold Time After Enable 0 ns tAVPV Address Input Valid to Address Output Delay tRLQV Note: 1. 2. 3. 4. 5. 0 ns 36 ns (Note 1) 38 (Note 4) 35 RD timing has the same timing as DS, LDS, UDS, and PSEN signals. RD and PSEN have the same timing for 8031. Any input used to select an internal PSD function. In multiplexed mode latched address generated from ADIO delay to address output on any Port. RD timing has the same timing as DS, LDS, and UDS signals. 94/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. ns ns PSD4256G6V Figure 51. WRITE Timing Diagram tAVLX t LXAX ALE / AS t LVLX A/D MULTIPLEXED BUS ADDRESS VALID DATA VALID tAVWL ADDRESS NON-MULTIPLEXED BUS ADDRESS VALID DATA NON-MULTIPLEXED BUS DATA VALID tSLWL CSI tDVWH t WLWH WR (DS) t WHDX t WHAX t EHEL E t THEH t ELTL R/ W t WLMV tAVPV t WHPV ADDRESS OUT STANDARD MCU I/O OUT AI02896 95/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 70. WRITE Timing -10 Symbol Parameter Conditions Unit Min Max tLVLX ALE or AS Pulse Width tAVLX Address Setup Time (Note 1) 7 ns tLXAX Address Hold Time (Note 1) 8 ns tAVWL Address Valid to Leading Edge of WR (Notes 1,3) 15 ns tSLWL CS Valid to Leading Edge of WR (Note 3) 15 ns tDVWH WR Data Setup Time (Note 3) 40 ns tWHDX WR Data Hold Time (Note 3,7) 5 ns tWLWH WR Pulse Width (Note 3) 40 ns tWHAX1 Trailing Edge of WR to Address Invalid (Note 3) 8 ns tWHAX2 Trailing Edge of WR to DPLD Address Invalid (Note 3,6) 0 ns tWHPV Trailing Edge of WR to Port Output Valid Using I/O Port Data Register tDVMV Data Valid to Port Output Valid Using Macrocell Register Preset/Clear tAVPV Address Input Valid to Address Output Delay tWLMV WR Valid to Port Output Valid Using Macrocell Register Preset/Clear Note: 1. 2. 3. 4. 5. 6. 7. 22 (Note 3) 45 ns (Notes 3,5) 65 ns (Note 2) 35 ns (Notes 3,4) 65 ns Any input used to select an internal PSD function. In multiplexed mode, latched address generated from ADIO delay to address output on any port. WR has the same timing as E, LDS, UDS, WRL, and WRH signals. Assuming data is stable before active WRITE signal. Assuming WRITE is active before data becomes valid. tWHAX2 is the address hold time for DPLD inputs that are used to generate Sector Select signals for internal PSD memory. tWHAX is 11 ns when writing to the Output Macrocell Registers. 96/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 52. Peripheral I/O READ Timing Diagram ALE /AS ADDRESS A/D BUS DATA VALID tAVQV (PF) tSLQV (PF) CSI tRLQV (PF) tQXRH (PF) tRHQZ (PF) tRLRH (PF) RD tDVQV (PF) DATA ON PORT F AI05740 Table 71. Port F Peripheral Data Mode READ Timing -10 Symbol Parameter Min tAVQV-PF Address Valid to Data Valid tSLQV-PF CSI Valid to Data Valid Turbo Off Unit Max 50 + 20 ns 50 + 20 ns Conditions (Note 3) (Notes 1,4) 35 ns RD to Data Valid 8031 Mode 45 ns tDVQV-PF Data In to Data Out Valid 34 ns tQXRH-PF RD Data Hold Time tRLRH-PF RD Pulse Width (Note 1) tRHQZ-PF RD to Data High-Z (Note 1) RD to Data Valid tRLQV-PF 0 ns 35 ns 38 ns 97/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 72. Port F Peripheral Data Mode WRITE Timing -10 Symbol Parameter Conditions Unit Min Max tWLQV-PF WR to Data Propagation Delay (Note 2) 40 ns tDVQV-PF Data to Port A Data Propagation Delay (Note 5) 35 ns tWHQZ-PF WR Invalid to Port A Tri-state (Note 2) 33 ns Note: 1. 2. 3. 4. 5. RD has the same timing as DS, LDS, UDS, and PSEN (in 8031 combined mode). WR has the same timing as the E, LDS, UDS, WRL, and WRH signals. Any input used to select Port F Data Peripheral mode. Data is already stable on Port F. Data stable on ADIO pins to data on Port F. Table 73. Power-down Timing -10 Symbol Parameter Conditions Unit Min tLVDV ALE Access Time from Power-down tCLWH Maximum Delay from APD Enable to Internal PDN Valid Signal Max 128 Using CLKIN (PD1) ns 15 * tCLCL1 s Table 74. Reset (RESET) Timing Symbol tNLNH tNLNH-PO tNLNH-A tOPR Parameter Conditions RESET Active Low Time 1 Min Max Unit 300 ns Power-on RESET Active Low Time 1 ms Warm RESET Active Low Time 2 25 s RESET High to Operational Device 300 ns Note: 1. Reset (RESET) does not reset Flash memory Program or Erase cycles. 2. Warm RESET aborts Flash memory Program or Erase cycles, and puts the device in READ Mode. Figure 53. Reset (RESET) Timing Diagram VCC VCC(min) tNLNH-PO tNLNH tNLNH-A tOPR Power-On Reset tOPR Warm Reset RESET AI02866b Table 75. VSTBYON Timing Symbol Parameter Conditions Min Typ Max Unit tBVBH VSTBY Detection to VSTBYON Output High (Note 1) 20 s tBXBL VSTBY Off Detection to VSTBYON Output Low (Note 1) 20 s Note: 1. VSTBYON timing is measured at VCC ramp rate of 2ms. 98/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Figure 54. ISC Timing Diagram t ISCCH TCK t ISCCL t ISCPSU t ISCPH TDI/TMS t ISCPZV t ISCPCO ISC OUTPUTS/TDO t ISCPVZ ISC OUTPUTS/TDO AI02865 Table 76. ISC Timing -10 Symbol Parameter Conditions Unit Min Max tISCCF Clock (TCK, PC1) Frequency (except for PLD) (Note 1) tISCCH Clock (TCK, PC1) High Time (except for PLD) (Note 1) 30 ns tISCCL Clock (TCK, PC1) Low Time (except for PLD) (Note 1) 30 ns tISCCFP Clock (TCK, PC1) Frequency (PLD only) (Note 2) tISCCHP Clock (TCK, PC1) High Time (PLD only) (Note 2) 240 ns tISCCLP Clock (TCK, PC1) Low Time (PLD only) (Note 2) 240 ns tISCPSU ISC Port Set Up Time 11 ns tISCPH ISC Port Hold Up Time 5 ns 15 2 MHz MHz tISCPCO ISC Port Clock to Output 26 ns tISCPZV ISC Port High-Impedance to Valid Output 26 ns tISCPVZ ISC Port Valid Output to High-Impedance 26 ns Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode. 2. For Program or Erase PLD only. 99/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PART NUMBERING Table 77. Ordering Information Scheme Example: PSD42 5 6 G 6 V - 10 U I T Device Type PSD42 = Flash PSD with CPLD SRAM Size 3 = 64Kbit 5 = 256Kbit Flash Memory Size 5 = 4Mbit 6 = 8Mbit I/O Count G = 52 I/O 2nd Non-Volatile Memory 2 = 256Kbit Flash Memory 6 = 512Kbit Flash Memory Operating Voltage V = VCC = 2.7 to 3.6V Speed 90 = 90ns 10 = 100ns 12 = 120ns Package U = TQFP80 Temperature Range blank = 0 to 70C (Commercial) I = -40 to 85C (Industrial) Option T = Tape & Reel Packing For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 100/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V PACKAGE MECHANICAL INFORMATION Figure 55. TQFP80 - 80-lead Plastic Quad Flatpack Package Outline D D1 D2 A2 e E2 E1 E Ne b N 1 A Nd CP L1 c QFP-A A1 L Note: Drawing is not to scale. 101/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V Table 78. TQFP80 - 80-lead Plastic Quad Flatpack Package Mechanical Data mm inches Symb Typ Min Max Typ Min Max A - - 1.60 - - 0.063 A1 - 0.05 0.15 - 0.002 0.006 A2 1.40 1.35 1.45 0.055 0.053 0.057 b 0.22 0.17 0.27 0.009 0.007 0.011 c - 0.09 0.20 - 0.004 0.008 D 14.00 - - 0.551 - - D1 12.00 - - 0.472 - - D2 9.50 - - 0.374 - - E 14.00 - - 0.473 - - E1 12.00 - - 0.394 - - E2 9.50 - - 0.374 - - e 0.50 - - 0.020 - - L 0.60 0.45 0.75 0.024 0.018 0.030 L1 1.00 - - 0.039 - - 3.5 0 7 3.5 0 7 n 80 80 Nd 20 20 Ne 20 20 CP - - 0.08 - - 0.003 102/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V APPENDIX A. PIN ASSIGNMENTS Table 79. PSD4256G6V TQFP80 Pin No. Pin Assign ments Pin No. Pin Assign ments Pin No. Pin Assign ments Pin No. Pin Assign ments 1 PD2 21 PG0 41 PC0 61 PB0 2 PD3 22 PG1 42 PC1 62 PB1 3 AD0 23 PG2 43 PC2 63 PB2 4 AD1 24 PG3 44 PC3 64 PB3 5 AD2 25 PG4 45 PC4 65 PB4 6 AD3 26 PG5 46 PC5 66 PB5 7 AD4 27 PG6 47 PC6 67 PB6 8 GND 28 PG7 48 PC7 68 PB7 9 VCC 29 VCC 49 GND 69 VCC 10 AD5 30 GND 50 GND 70 GND 11 AD6 31 PF0 51 PA0 71 PE0 12 AD7 32 PF1 52 PA1 72 PE1 13 AD8 33 PF2 53 PA2 73 PE2 14 AD9 34 PF3 54 PA3 74 PE3 15 AD10 35 PF4 55 PA4 75 PE4 16 AD11 36 PF5 56 PA5 76 PE5 17 AD12 37 PF6 57 PA6 77 PE6 18 AD13 38 PF7 58 PA7 78 PE7 19 AD14 39 RESET 59 CNTL0 79 PD0 20 AD15 40 CNTL2 60 CNTL1 80 PD1 103/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. PSD4256G6V REVISION HISTORY Table 80. Document Revision History Date Rev. Description of Revision 06-Aug-2001 1.0 Document written 13-Sep-2001 1.1 Package mechanical data updated 14-Dec-2001 1.2 Added 100ns specification; removed 90 and 120 ns specifications. Updated AC specification and Port C and F functions 12-Aug-2002 1.3 Added 8-bit MCU Interface 14-Nov-2002 1.4 Update characteristics and features (Table 69, 77) 17-Nov-2003 1.5 Modify Instructions, correct part numbering (Table 29, 77) Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners (c) 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 104/104 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.