REVISIONS LTR DESCRIPTION DATE APPROVED J Add device types 05, 06, 07, 08, 13 July jy and 09. Delete two vendors, CAGE 1987 01295 and 27014. Add margin test. Change to military format. Make parameter changes through drawing. K Delete one vendor from device 01, 1988 CAGE 34335. Add a footnote to MAY 24 V LA table I. Make editorial changes throughout. CURRENT CAGE CODE 67268 REV PAGE REVsTaTus [ REV KExixixde PKdd Jobo de pepo po fd fo po ok OF PAGES PAGES 41 [2/3]4 175 [6 97 | 879 J10} 11f 12913 14 $15916 J 17 Defense Electronics Le ( MILIT RY DRAWING Supply Center : This drawing is available for use by Dayton, Ohio CHECKED BY all Departments and Agencies of the . Department of Defense A MICROCIRCUITS, DIGITAL,NMOS, 2KX8 Original date APRRO TITLE: yy ERASEABLE PROM, MONOLITHIC of drawing: Wi a SILICON 02 February 1979 Size | CODE IDENT. NO. | DWa NO. 7QQD92 A 14933 AMSC N/A REV K PAGE 1 OF 17 7 5962-E793 DISTRIBUTION STATEMENT A. Approved for public release; distribution is unlimited. DESC FORM 193 MAY 861. SCOPE 1.1 Scope. This drawing describes device requirements for class B microcircuits in accordance with 1.2.1 of MIL-STD-883, "Provisions for the use of MIL-STD-883 in conjunction with compliant non-JAN devices". 1.2 Part number. The complete part number shall be as shown in the following example: 78022 01 J xX ~T TT T | | | | | | I I Drawing number Device type Case outline Lead finish per (1.2.1) (1.2.2) MIL-M-38510 1.2.1 Device types. The device types shall identify the circuit function as follows: Device type Generic number Circuit function Access time 01 (see 6.4) 2Kx8-Bit UV EPROM 450 ns 02 (see 6.4) 2Kx8-Bit UV EPROM 450 ns 03 (see 6.4) 2Kx8-Bit UV EPROM 350 ns 04 (see 6.4) 2Kx8-Bit UY EPROM 350 ns 05 (see 6.4) 2Kx8-Bit UV EPROM 150 ns 06 (see 6.4) 2Kx8-Bit UY EPROM 200 ns 07 (see 6.4) 2Kx8-Bit UV EPROM 250 ns 08 (see 6.4) 2Kx8-Bit UV EPROM 300 ns 09 (see 6.4) 2Kx8-Bit UV EPROM 450 ns 1.2.2 Case outline. The case outline shall be as designated in appendix C of MIL-M-38510, and as follows: Outline Tetter Case outline J D-3 (24-pin, 1.290" x .610" x .225"), dual-in-line package 1/ 1.3 Absolute maximum ratings. Supply voltage, Vee -- et ee te eee eee -0.3 V de to t6 Vide 2/ Temperature under bias- - - ---------- -65 C to +135 C Storage temperature range - - --------- -65C to *150C Maximum power dissipation, Pp - - ----- - - 635 mW Lead temperature (soldering, 10 seconds)- - - - +300 C Thermal resistance, junction-to-case (8c) (See MIL-M-38510, appendix C) Junction temperature (Ty) - - --------- +160 C All input or output voltages with respect to ground - -----+------+ +--+ -- -0.3 V de to +6 V dc Yop supply voltage with respect to ground during program (device types 01, 02, 03, 04)- round 6, 07, 08, -0.3 V de to +26.5 V dc Vp supply voltage with respect to Bu -0.3 V de to +13.5 V de ring program (device types 05, and 09) 17 Lid shall be transparent to permit ultraviolet light erasure. 2/ All voltages referenced to Yss. STANDARDIZED SIZE 78022 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 K 2 DESC FORM 193A SEP 87 +X U.S. GOVERNMENT PRINTING OFFICE: 1987549-0961.4 Recommended operating conditions. Case operating temperature range- - - - - - - - -55C to +125C Input low voltage, Vyp- - ------ 7-7 re ~0.1 V de to +0.8 V dc Input high voltage, $ Hoc ccc tots 2.0 V dc to 6.5 V de High level program input voltage, Vyy(ppr)> Udevice types 01, 02, 03, and 04) - - - - - - 24 V dc to 26 V dc (program method A) High level program input voltage, V Pdevice types 05, 06, 07, 08, and HOS? --- 12.0 de to 13.3 V de (program method B) 2. APPLICABLE DOCUMENTS 2.1 Government specification and standard. Unless otherwise specified, the following specification and standard, of the Tssue T{sted in that issue of the Department of Defense Index of Specifications and Standards specified in the solicitation, form a part of this drawing to the extent specified herein. SPECIFICATION MILITARY MIL-M-38510 - Microcircuits, General Specification for. STANDARD MILITARY MIL-STD-883 - Test Methods and Procedures for Microelectronics. (Copies of the specification and standard required by contractors in connection with specific acquisition functions should be obtained from the contracting activity or as directed by the contracting activity.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing shall take precedence. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with 1.2.1 of MIL-STD-883, "provi stons for the use of MIL-STD-883 in conjunction with compliant non-JAN devices" and as specified herein. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimenstons shall be as specified tn MIL-N-38510 and herein. 3.2.1 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.2 Truth table. The truth table shall be as specified on figure 2. 3.2.2.1 Unprogrammed or erased devices. The truth table for unprogrammed devices shall be as specified on figure 2. 3.2.2.2 Programmed devices. The requirements for supplying programmed devices are not part of this drawing. . 3.2.3 Block diagram. The block diagram shall be as specified on figure 3. 3.2.4 Case outline. The case outline shall be in accordance with 1.2.2 herein. STANDARDIZED SIZE 78022 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL K SHEET 3 DAYTON, OHIO 45444 DESC FORM 193A SEP 87 YX U.S. GOVERNMENT PRINTING OFFICE: 1987-549-0963.3 Electrical performance characteristics. Unless otherwise specified, the electrical performance charactertstics ar as specified in table I and apply over the full case operating temperature range. 3.4 Marking. Marking shall be in accordance with MIL-STD-883 (see 3.1 herein). The part shall be marked w the part number listed in 1.2 herein. In addition, the manufacturer's part number ay also be marked as listed in 6.4 herein. 3.5 Processing EPROMS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.5.1 Erasure of EPROMS. When specified, devices shall be erased in accordance with the {procedures and characterTstics speciffed in 4.4. : 3.5.2 Programmability of EPROMS. When specified, devices shall be programmed to the specified jpattern ustng_the- procevures-and cWaracteristics specified in 4.5, 4.6, tables IIIA and IIIB. 3.5.3 Verification of erasure or programmability of EPROMS. When specified, devices shall be verified as elther programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in proper state. Any bit that does not verify to be in the proper state shall constitute a device faflure and shall be removed from the lot. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be Tisted as an approved source of supply in 6.4. The certificate of compliance submitted to DESC-ECS prior to listing as an approved source of supply shall state that the jmanufacturer's product meets the requirements of MIL-STD-883 (see 3.1 herein) and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-STD-883 (see 3.1 herein) shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DESC-ECS shall be required in accordance with MIC-STD-883 (see JI herein). 3.9 Verification and review. DESC, DESC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. 4, QUALITY ASSURANCE PROVIS IONS 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with section of MIC RC3ESTO to the extent specified in MIL-STD-883 (see 3.1 herein). 4.2 Screening: Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D using the circuit submitted with the certificate of compliance (see 3.6 herein). (2) Ta = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. STANDARDIZED SIZE . 78022 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL. =k SHEET 4 DAYTON, OHIO 45444 DESC FORM 193A SEP 87 tf U.S. GOVERNMENT PRINTING OFFICE: 1987549-096.TABLE 1. Electrical performance characteristics. Test | [Symbol | | [ Conditions Unless otherwise specified, I T Group A Limits | Device |subgroups F in |Max uni | Tr = -55C to *125C, GND = 0 V, type | i | Voc = 5 , Vpp = Yec tot | 4 High level output |Voy Igy = -400 yA All (1, 2,3 (2.4 | v voltage | iVr_ = 0.8 V, Vy = 2.0 | | | | . Low level output I VoL Ig_ = 2.1 mA | All 1, 2,3 | [0.45] V voltage ! IVIL = 0.8 V, Vyy = 2.0 V ! ! |! I I I I I | Output leakage {Ito lVouT = 5.5 V ; Ald |1, 2,3 =| 110 | vA current | I l i | { | | | | | { i i I | ; : [ if | I | Vpp read lIppy |Vpp = 5.5V Te = *25C, +125C 01,03 | 1,2 | [5 | ma current I I | | Ve 2/ | Vpp = 5.5V. ce =-55C 3 | 10 [Ippo 1Vpp = 5.5 V 05,06, 11, 2% 3 | 15 | | 07,08, | | | | - | Vec current {I |CE = V OE = V 01,03 |1, 2, 3 130 | mA Cfstandty) 27 (CP - 05:06, TI | | 07,08, | | (40 | | i | 09 | | | | I I __ I I | I Vcc current lec2 (OE = CE = Vit | 01,03 11, 2,3 | {115 | mA factive) 2/ | | [ 05,06, | I I I | | | 07,08, | I {100 | | | | 09 i | I I I T [ Vpp read, lIppi* |Vpp = 5.5 V | 02,04 {1, 2,3 | 125 | mA Vcc current | | | | | fot combined Ice ! ! | [Tpp2* | | | | 1 05,06, | | {105 | IIec | | 07,08, | \ | | | | | 09 i | | | i I [ | | | | Input capacitance ICI Vin = OY | | | | i 3/ | [Te = *25C f = 1 MHz [Ald | 4 | (7 | pF | | | | | I | i I i T I i I Address to output Itacc ICE Lc O4/ 01,02,09/9, 10, 11 | 450 | ns delay | |See = oe re | 03,04 { 350 | | 05 1 | 150 ! | | 06 200 [ | | 07 250 | | 03 300 See footnotes at end of table. STANDARDIZED rr 78022 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL K SHEET 5 DAYTON, OHIO 45444 DESC FORM 193A SEP 87 + U.S. GOVERNMENT PRINTING OFFICE: 1988549-904and 2.0 . TABLE I. Electrical performance characteristics - Continued. T [ Conditions T | Group A [_ Limits | Test [Symbol | eee otherwise specified, | Device isubgroups {Min (Max [Unit | | = -55C to *125C, GND = OV > | type ! | Voc = 5 , Vpp = Yec I I I | | I | { i | | | i CE to output ltce (OE = Vy, 4/ 101,02,09/9, 10, 11 | 450 | ns delay I iSee figure 4 03,04 T [350 | | | 05 150 | | i 06 | | T_07 250 l | [oss 300 { I Output enable itog (CE = Vr_ 4/ 01,02,0919, 10, 11 150 | ns to output delay | [See figure 4 05,04 120 T | l 05,06 | i 75 | | T 07 T 100 | | To 110 i if Output enable ltor [TE = Vy, 4/ 5/ (01,02, 19, 10, 11 | O {130 | ns high to output | iSee figure 4 {03,04 | | | | float | | s i 0 I 60 I l | {07,08 | I l | | pee | I I i i { | Address to output [toy CE = OE = Vy 4/ | AlT 19, 10, 11 | 0 | | ns hold | |See figure [ | | I i | I | | | | | 1/ Vcc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2/ Vpp may be connected directly to Voc except during programming. The supply current would . hen be the sum of Icc and Ipp}. 3/ See 4.3.1c. 4/ Output Toad: 1 TTL gate and C, = 100 pF ty and tg <20 ns; input pulse levels: 0.45 V 0 2.4 ; input timing reference level: 1.0 " and 5 DV; output timing reference level: 0.8 V | 5/ If not tested, shall be guaranteed to the limits specified in table I. STANDARDIZED SIZE 78022 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 DESC FORM 193A SEP 87 # U. S. GOVERNMENT PRINTING OFFICE: 1968-549-904Device types 01 through 09 Case J a7 Li 24] Vec Ae [2 Z3]Ag PIN NAMES As [3 22] A9 Ag Aig Addresses Ag [4] 21] Yep 43 [5 20] O CE Chip enable A2 [6] 13] 410 Ay [7] 18] CE /PGM OE Output enable Ao [8 i207 Oo 0 (a 16] Og oV'7 Outputs % fio) 15] Os 02 [11] 14} 04 GND [I2 13] 03 FIGURE 1. Terminal connections (top view). TRUTH TABLE (UNPROGRAMMED)_1/ Input Mode CE OE |+v +V, Outputs pp cc 2/ Read L L 5 5 Doto Out Standby H x 5 5 High Z Pulsed | y 25 5 Program LteH Data in Program Verify L L 25 5 Dota Out Program Inhibit} Lo | H | 25 5 |High z _l/ Positive togic H * High logic level L = Low logic level X = Irrelevant High Z = High-impedance state _2/ Outputs have internal active pullups. FIGURE 2. Truth table. STANDARDIZED A 78022 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL J SHEET 7 DAYTON, OHIO 45444 DESC FORM 193A SY U.S. GOVERNMENT PRINTING OFFICE: 1987549-096 SEP 87DATA OUTPUTS O9- 07 coo oE- OUTPUT ENABLE -_ == | CHIP ENABLE > ce tocic OUTPUT BUFFERS y Y GATING * DECODER - Ao0-Aio ADDRESS ; INPUTS x ; 16,384 BIT CELL MATRIX PECOGER : .-+p e NOTES: 1. Ag = least significant address bit; Ayo = most significant address bit. 2. O9 = least significant data output bit; 07 = most significant data output bit. FIGURE 3. Block diagram. STANDARDIZED SIZE MILITARY DRAWING A 7e02e DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 d 8 DESC FORM 193A SEP 87 YY U.S. GOVERNMENT PRINTING OFFICE: 1987--549-006ro Vin 22.4 Np TEST ViL=0.45 0.8V4" POINTS o.8v Yjp-@$-_ <n ee => ADDRESSES ob oo. xX c J _ ouTPUT LZ NOTE: _ 1. OE may be delayed up to tacc-tog after falling edge of CE without impact on ace: 2. tpr is specified from OE or CE whichever occurs first. FIGURE 4. Timing diagram. STANDARDIZED oe MILITARY DRAWING 78022 DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL SHEET DAYTON, OHIO 45444 J 9 ep an vt U.S. GOVERNMENT PRINTING OFFICE: 1987-549-096 SEP 87PROGRAM ADDRESSES x ADDRESS N ADDRESS Nem 7 je tas o je tay o (2 (2) . DATA IN DATA IN DATA STABLE ROD N Spb hm tor or (0.200 MAX) (0.200 MA (0,200: MAX ) OE t onl osigtew ,, | (2) (2)]](45ms ey Ne ea SJ CE /PGM _ x. CORT o| het PFT NOTES: . Input timing reference levels are 1.0 V and 2.0 V. . Output timing reference levels are 0.8 V and 2.0 V. Input pulse rise and fall times (10% to 90%) are 20 ns. Input pulse levels are 0.8 V to 2.2 . All times shown in parentheses are minimum times in us unless otherwise specified. Newnes . . / FIGURE 5. Programming waveforms for method A. STANDARDIZED SIZE MILITARY DRAWING A 78022 OFFENSE EEO aes REVISION LEVEL K SHEET 10 DESC FORM 193A SEP 87 3 U.S. GOVERNMENT PRINTING OPFICE: 1967--540-096q poyyew 40} SWudjarem HuLumesboug *uauueuboud ayy 9 4undI4 Aq pazepouwosoze aq 7SnW 4Nq SadLA@p ay JO SILZSLuazoeuRYD Bue did, pue 304 ayy <2 HI, AO} A 2 pue Wy 4OJ A QO SL [aAa, aduavayau Buri qyndut ayy, *T *SILON con NE {sw -G6'1) lf | MdO 4 La wa 30 ($10) sw S60 jag 30 4 e} jf 18304 ( dy } HI, (2) " Wn wod/39 < 4304 (2) me ; je S9Aq Hin 29 NOK (2) dda evn (e101 4 Zz Hon (2) HOq +> ae djq4 - (2) - Ota ino vive ; { aavis NI viva w1lva = ie) wal | Sv4 Wh sassaudav AsINBA ale wvud0ud wyus0ud Hi, 78022 SHEET 1 REVISION LEVEL SIZE A STANDARDIZED MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER DAYTON, OHIO 45444 DESC FORM 193A SEP 87 1987549-096 1 U.S. GOVERNMENT PRINTING OFFICE:TABLE II. Electrical test requirements. 1/ 2/ 3/ 4/ T MIC-STD-883 test requirements [ Subgroups ' | (per method 5005, table 1) [Interim electrical parameters --~ | (method 5004) |Final electrical test parameters | 1*,2,3,/,8,9, | (method 5004) 10,11 {Group A test requirements 1,2,3,4,7,8,9, | (method 5005) 10,11 | |Groups C and D end-point T | electrical parameters | 1,2 or 2, | | (method 5005) | 8{+125C),10 | 1/ * PDA applies to subgroup 1. 2/ Any or all subgroup may be combined when using a high speed tester. 3/ Subgroup 7 shall consist of verifying the pattern specified. 4/ For all electrical tests, the device shall be programmed to the pattern specified. c. A data retention stress test shall be included as part of the screening procedure and shall consist of the following steps. Margin test method A 1. Program greater than 95 percent of the bit locations, including the slowest programming cell (see 3.5.2). 2. Bake, unbiased, for 12 hours at +200C. 3. Perform a margin test using Ym = Vcc = 6.0 V at #25C using loose timing. f . Erase device, then program 45 to 50 percent of the bits to a worst case speed pattern. . 5. Perform dynamic burn-in (see 4.2a). 6. Perform a margin test using Vm = Vcc = 6.0 V at +25C. 7. Perform 100 percent electrical testing at +125C and -55C. Perform 100 percent ac and de electricals at +25 C. 8. Erase device (see 3.5.1), except devices submitted for groups A, B, C, and D. 9. Verify erasure (see 3.5.3). STANDARDIZED SIZE 1202? MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL J SHEET 19 DAYTON, OHIO 46444 DESC FORM 193A SE P 87 1X U.S. GOVERNMENT PRINTING OFFICE: 1987548-096Margin test method B 1. Program greater than 95 percent of the bit locations, including the slowest programming cell (see 3.5.2). The remaining cells shall provide a worst case speed pattern. 2. Bake, unbiased, for 72 hours at +140C to screen for data retention lifetime. 3. Perform a margin test using Vm = *6.0 V at +25C using loose timing (i.e., tacc = lus). 4. Perform dynamic burn-in (see 4.2a). 5. Margin at Vm = 6.0 V. 6. Perform electrical tests (see 4.2). 7. Erase (see 3.5.1}, except devices submitted for groups A, B, C, and D testing. 8. Verify erasure (see 3.5.3). 4.3 Quality conformance inspection. Quality conformance inspection shal] be in accordance with ethod 5005 ct MIL-STD-883 including groups A, B, C, and D inspections. The following additional riteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table 1, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (Czy measurement) shall be measured only for the initial test and after process or design changes which may affect input capacitance. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition C or D using the circuit submitted with the certificate of compliance (see 3.6 herein). (2) Ta = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4 Erasing procedure. The device is erased by exposure to high intensity shortwave ultraviolet light at a wavelength of 253.7 nm. The recommended integrated dose (i.e., UV intensity X exposure time) is 15 W-s/cm. An example of an ultraviolet source which can erase the device in 30 minutes is the model $52 shortwave ultraviolet lamp. The lamp should be used without short wave filters and the EPROM should be placed about one inch from the lamp tubes. After erasure, all bits are in the high state. STANDARDIZED Size 78022 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL J SHEET 13 DAYTON, OHIO 45444 DESC FORM 193A SEP 87 3 U8. GOVERNMENT PRINTING OFFICE: 1967549.0964.5 Programming procedures for method A. The programming characteristics in table IIIA and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The waveforms of figure 5 and programming characteristics of table IIIA shall apply. b. Initially and after each erasure, all bits are in the high "H" state. Information is introduced by selectively programming "L" into the desired bit locations. A programmed "L" can be changed to an H" by ultraviolet light erasure (see 4.4). c. Programming occurs when Yop is 25.0 #1.0 V and CE/PGM is brought to Vyq, also OF is at VIH- 4.6 Programming procedures for method B. The programming characteristics in table IIIB and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming. The waveforms of figure 6 and programming characteristics of table IIIB shall apply. b. Initially and after each erasure, all bits are in the high "H" state. Information is introduced by selectively programming "L" into the desired bit locations. A programmed "L can be changed to an "H" by ultraviolet light erasure (see 4.4). c. Programming occurs when Yop fs 12.0 to 13.3 V and CE/PGM is brought to Vyy. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-M-38510. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use when military specifications do not exist and qualified military devices that will perform the required function are not available for OEM application. When a military specification exists and the product covered by this drawing has been qualified for listing on QPL-38510, the device specified herein will be inactivated and wil? not be used for new design. The QPL-38510 product shall be the preferred item for all applications. 6.2 Replaceability. Replaceability is determined as follows: a. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. b. When a QPL source is established, the part numbered device specified in this drawing will be replaced by the microcircuit identified as part number M38510/2210XBXX. 6.3 Comments. Comments on this drawing should be directed to DESC-ECS, Dayton, Ohio 45444, or telephone 513-296-5375. STANDARDIZED SIE v022 MILITARY DRAWING A DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL J SHEET 14 DAYTON, OHIO 45444 DESC FORM 193A SEP 37 Yr U.S. GOVERNMENT PRINTING OFFICE: 1967549-006TABLE IIIA. Programming characteristics for method A, { I | Limits | Parameters | Symbol | Test conditions [Min | Max |Unit 3 | | Voc supply current 1 lec ITc = +25C, Voc = 5.0 V, | 100 | mA | IViy = 2.0 minimum, | | | | [Vt = 0.80 maximum, | | | | IViq = OF = 5.0 V #10% | | | | | 1 Vpp read current | Ippz \Vpp = 5.5 V, CE/PGM = Vy, | 5 mA | | [1 Vpp program current | Ippo |CE/PGM = Viy, Vpp = 25 V #1.0 V ! | 30 ! mA | | , | | | | | | | ] I | i Address setup time | tas |See figure 5 2 ! us | [ I | UE setup time | toes ! 2 ! us | | [ [ Data setup time | tps | i 2 | | us | ! | | | I Address hold time | tay i t 2 | | us | i | | | I I | DE hold time | tocen | ! 2 ! | us | I | Data hold time | ton 2 ! j us [ Chip deselect to | tor i 0 { 200] ns output float delay | |! ! | | [ [ Output enable to | tog | i 1 200 | ns output delay | | | | | | | | | | I | I I Program pulse width | tpy | | 45 ! 55 | ms | { | | I T | I Program pulse rise time | tprt { 1 5 [ 100 | ns | ! | | | I l I l Program pulse fall time tprt ! ! 5 100 ! ns STANDARDIZED ~ 79022 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL J SHEET 15 DAYTON, OHIO 45444 DESC FORM 193A SEP 87 wr U. S. GOVERNMENT PRINTING OFFICE: 1988-549-904TABLE IIIB. Programming characteristics for method B. [ I T_ limits | Parameters ! Symbol ! Test conditions Min Max unit T I [ | | Vcc supply current | Icc ITc = +25C, Voc = 5.0 Y, | {100 | mA | \Vry = 2.0 minimum, i | | | \r_ = 0.80 maximum, | | | i Vin = OF = 5.0 *#10% | | | | | | | | I I [ I ] Vpp read current | Ippi Vpp = 5.5 V, CE/PGM = Vy, | i 5 | mA ! | | | " I I | Vpp program current Ippe2 TE/PGM = Vry, Vpp = 25 V #1.0 V ! 30 ! mA | | | | I | I I Address setup time | tas See figure 6 | 2 | { us ! ! | | | T FF TT DE setup time tors 2 | us st Data setup time | tps | | 2 ! |! us tT Address hold time taH 2 | } us | | | T Tf TC OE hoid time | toeH | 2 | us | | TT Data hold time ton | ! 2 | 1 us I TT Chip deselect to | tore 1 0 130 ns output float delay | | | |! I | Output enable to | toe | 150 | ns output delay ! | | i [ T TT Program pulse width | tpy i .95 [1.05 [ ms ! | | | TTT Over program pulse width | topw ! {1.95 | 55 | ms | | i | I T I I Voc setup time | tycs ! ! 2 ! ! us I I | | I Vpp setup time 1 typs | j 2 | | us | | | i | STANDARDIZED sze 12022 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL J SHEET i DAYTON, OHIO 45444 DESC FORM 193A SEP 87 #r U. 8. GOVERNMENT PRINTING OFFICE: 1988-540-9046.4 Approved sources of supply. will be added as they become available. certificate of compliance {see 3.6 herein) has been submitted to DESC-ECS. Approved sources of supply are listed herein. |AM27168-450/BJA| | | | Military | Vendor | Vendor ] RepTacement TProgramming | | drawing | CAGE [similar part 1/|military specification] method i | part number | number | number | part number | | T 7802201JX ~T 27 TAM2716/BJA | MS85TO722101BIX | I | | 34649 |MD2716M/B | M38510/22101BUX =| A { | i | | | | 78022025X 2/7) TMM27160M/7883B | | A | | 7802203UX . 2/ AM2716-1DLB | | 2/ SMJ2516-35JM | i 2/ 1PMJ2516-35dM ! A ! | | [ T 78022040X [2/7 [MM2716-19M/8838 | I -- ] | | | 7802205JX [34335 TAM2716B-150/BJA B | 7802206JX | 34335 |AM2716B-200/BJA B | 78022073X | 34335 |AM2716B-250/BJA| | B | | 78022083X | 34335 |AM2716B-300/BUJA| | B | | 7802209JX | 34335 ! B ! | 1/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 2/ Not available from an approved source of supply. Additional sources The vendors listed herein have agreed to this drawing and a DAYTON, OHIO 45444 Vendor CAGE Vendor name Margin test number and address method 34335 Advanced Micro Devices A 901 Thompson Place Sunnyvale, CA 94086 34649 Intel Corporation B 3065 Bowers Avenue Santa Clara, CA 95051 STANDARDIZED A 78022 MILITARY DRAWING DEFENSE ELECTRONICS SUPPLY CENTER REVISION LEVEL kx SHEET 17 DESC FORM 193A SEP 87 + U.S. GOVERNMENT PRINTING OFFICE: 1987-549-096