MIC7400
Configurable PMIC, Five-Channel Buck
Regulator Plus One-Boost with
HyperLight Load® and I2C Control
HyperLight Load is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
March
3, 2015
Revision 2.0
General Description
The MIC7400 is a powerful, highly integrated,
configurable, power-management IC (PMIC) featuring five
synchronous buck regulators, one boost regulator and
high-speed I2C interface with an int ernal EEPROM.
The device offers two distinct modes of operation “stand-
by mode” and “normal mode” intended to provide an
energy optimized solution suitable for portable handheld,
and infotainment applications.
In normal mode, the programmable switching converters
can be configured to support a variety of features,
including start-up sequencing, timing, soft-start ramp,
output voltage levels, current limit levels and output
discharge for each channel.
In stand-b y mode the PMI C can configured in a lo w power
state by either disabling an output or by changing the
output voltage to a lower level. Independent exit from
stand-by mode can be achieved either by I2C
communication or the external ST B Y pin.
The device has five synchronous buck regulators with
high-speed adaptive on-time control supporting even the
challenging ultra-fast transient requirement for Core
supplies. One boost regulator provides a flash-memory
programming supply that delivers up to 200mA of output
current. The boost is equipped with an output disconnect
switch that opens if a short-to-ground fault is detected.
An internal E EP RO M e nab l es a s in gle-chip so lutio n acros s
many platforms by allowing the designer to customize the
PMIC for their design. Modifications can be made without
the need to re-approve a new PMIC, saving valuable
design resources and time.
All switchers provide light-load efficiency with HyperLight
Load® mode for buck and PFM mode for boost. An
additiona l ben ef it of this propr ietary architec tur e is very-low
output ripple voltage throughout the entire load range with
the use of small output capacitors. The MIC7400 is
designed for use with a small inductors (down to 0.47µH
for buck, 1.5µH for boost), and an output capacitor as
small as 10µF for buck, enabling a total solution size of
15mm × 15mm and less than 1mm height.
The datasheet and other support documentation can be
found on Micrel’s website at: www.micrel.com.
Features
• Input voltage: 2.4V to 5.5V
• Five independent synchronous bucks up to 3A
• One independent non-synchronous boost 200mA
• 200µA q u iescent current (all re g u lators on)
• 93% peak buck efficiency, 85% typical efficiency at 1mA
• Dual power mode: stand-by and normal mode
• I²C interface up to 3.4MHz
• I²C on-the-fly EEPROM programmability, featuring:
− Buck and boost output voltage scaling
− Power-on-reset threshold and delay
− Power-up sequencing/sequencing delay
− Buck and boost c u r re nt limit
− Buck and boost pull-down w hen disa ble d
− Individual ON, OFF, and standby modes
− Soft-start and global power-good masking
• 23µA buck typical quiescent current
• 70µA boost typical quiescent current
• 1.5% output accuracy over temperature/line/load
• 2.0MHz boost switching frequency
• 1.3MHz buck operation in continuous mode
• Ultra-fast buck transient response
• 15mm × 15mm × 1.25mm solution size
• Thermal-shutdown and current-limit protection
• 36-pin 4.5mm × 4.5mm × 0.85mm FQFN package
(0.4mm pitch)
• −40°C to +125°C junction temperature range
Applications
• Client and enterprise solid state drives (SSD)
• Consumer and in-vehicle infotainment devices
• Multimedia devices
• Portable handheld devices
• Security camera
• Gaming machines
• Service provider gateways
Micrel, Inc.
MIC7400
March
3, 2015 2 Revision 2.0
Typical Application
Ordering Information
Part Number Marking Output Voltages Features Package(1) Lead
Finish
MIC7400YFL 7400
YWWS 1.8V, 1.1V, 1.8V
1.05V, 1.25V, 12V STBY – Active Low
Falling Edge (DEFAULT) 36-Pin
4.5mm × 4.5mm FQFN Pb-
Free
MIC7400-XXXXYFL (2)
X
X 7400
X YYWW
X
Configurable Configurable 36-Pin
4.5mm × 4.5mm FQFN Pb-
Free
Notes:
1. GREE N, RoHS-compliant package. Lead finish is Matte Ti n. Mold compound is Halogen Free.
2. Configurable options available upon request. Contact Marketi ng.
Micrel, Inc.
MIC7400
March
3, 2015 3 Revision 2.0
Table of Contents
List of Figures .......................................................................................................................................................................... 5
List of Tables ........................................................................................................................................................................... 6
Pin Configuration ..................................................................................................................................................................... 7
Pin Description ........................................................................................................................................................................ 7
Absolute Maximum Ratings .................................................................................................................................................. 10
Operating Ratings ................................................................................................................................................................. 10
Electrical Characteristics ....................................................................................................................................................... 10
Typical Characteristics .......................................................................................................................................................... 15
Functional Characteristics ..................................................................................................................................................... 17
MIC7400 Block Diagram ....................................................................................................................................................... 24
Functional Description ........................................................................................................................................................... 25
Programmable Buck Soft-Start Control ............................................................................................................................. 25
Buck Digital Voltage Control (DVC) ................................................................................................................................... 26
Programmable Boost Soft-Start Control ............................................................................................................................ 27
Boost Digital Voltage Control (DVC) ................................................................................................................................. 28
Buck Current Limit ............................................................................................................................................................. 28
Boost Current Limit ............................................................................................................................................................ 29
Global Pow er Good P in ..................................................................................................................................................... 29
Standard Del a y .................................................................................................................................................................. 29
Power-Up Sequencing ....................................................................................................................................................... 29
Programmable Power-on-Reset (POR) Delay .................................................................................................................. 30
Power-Down Seque nc ing .................................................................................................................................................. 30
Stand-By Mode .................................................................................................................................................................. 31
Resistive Discharge ........................................................................................................................................................... 31
STBY Pin ........................................................................................................................................................................... 31
Safe Start-Up into a Pre-Biased Output ............................................................................................................................ 32
Buck Regulator Po wer Dis sipat io n .................................................................................................................................... 32
Total Power Dissipation ..................................................................................................................................................... 32
Power Derat ing .................................................................................................................................................................. 33
Overtemperature Fault ...................................................................................................................................................... 33
Thermal Measurements ..................................................................................................................................................... 34
Timing Diagrams ................................................................................................................................................................... 35
Normal Power-Up Sequence for Outputs .......................................................................................................................... 35
Standby (STBY) Pin (Wake-Up)............................................................................................................................................ 36
Evaluation Board Schematic ................................................................................................................................................. 37
Bill of Materials ...................................................................................................................................................................... 38
Micrel, Inc.
MIC7400
March
3, 2015 4 Revision 2.0
Table of Contents (Continued)
PCB Layout Guidelines
General .............................................................................................................................................................................. 39
IC ....................................................................................................................................................................................... 39
Input Capacitor .................................................................................................................................................................. 39
Inductor .............................................................................................................................................................................. 39
Output Capac itor ............................................................................................................................................................... 39
Proper Termination of Unused Pins ...................................................................................................................................... 40
PCB Layout Recommendations ............................................................................................................................................ 41
Package Information and Recommended Landing Pattern .................................................................................................. 45
Appendix A ............................................................................................................................................................................ 46
I2C Control Register ........................................................................................................................................................... 47
Serial Port Operation ......................................................................................................................................................... 47
External Host Interface .................................................................................................................................................. 47
Special Host I2C Commands ......................................................................................................................................... 48
Special Ke ys .................................................................................................................................................................. 48
Appendix B ............................................................................................................................................................................ 49
Register Settings Descriptions .......................................................................................................................................... 49
Power Good Register (00’h) .......................................................................................................................................... 49
EEPROM-Ready Register (01’h) ................................................................................................................................... 50
Fault Registers (02’h) ..................................................................................................................................................... 51
Standby Register (03’h) ..................................................................................................................................................... 52
Enable/Disable Register (04’h) .......................................................................................................................................... 53
Regulator Output Voltage Setting NORMAL Mode (05’h − 09’h) ...................................................................................... 54
Boost Regulator Output Voltage Setting NORMAL Mode (0A’h) ...................................................................................... 55
Regulator Voltage Setting STBY Mode (0B’h – 0F’h) ....................................................................................................... 56
Boost Regulator Output Voltage Setting STBY Mode (10’h) ............................................................................................. 57
Sequence Register (11’h) .................................................................................................................................................. 58
Delay Register (17’h) ......................................................................................................................................................... 61
Soft-Start Registers (18’h − 1A’h) ...................................................................................................................................... 62
Current-Limit (Normal Mode) Registers (1B’h − 1D’h) ...................................................................................................... 63
Current-Limit (STBY Mode) Registers (1E − 20’h) ............................................................................................................ 65
Power-on-Reset (POR) Threshold Voltage Setting Register (21’h and 22’h) ................................................................... 66
Pull-Down when Disable d Regis t er (23’h) ......................................................................................................................... 67
Micrel, Inc.
MIC7400
March
3, 2015 5 Revision 2.0
List of Figures
Figure 1. Buck Soft-Start ..................................................................................................................................................... 25
Figure 2. Buck Soft-Start ..................................................................................................................................................... 26
Figure 3. Buck DVC Control Ramp ..................................................................................................................................... 26
Figure 4. Buck DVC Control Ramp ..................................................................................................................................... 27
Figure 5. Boost Soft-Start Ram p ......................................................................................................................................... 27
Figure 6. Boost Soft-Start .................................................................................................................................................... 27
Figure 7. Boost DVC Control Ramp .................................................................................................................................... 28
Figure 8. Standard Delay Time ........................................................................................................................................... 29
Figure 9. Hot Plug − VIN Rising ........................................................................................................................................... 30
Figure 10. POR ..................................................................................................................................................................... 30
Figure 11. Hot Un-Plug − VIN Falling ..................................................................................................................................... 30
Figure 12. I2C Stan d -By Mode .............................................................................................................................................. 31
Figure 13. Output Pull-Down Resistance .............................................................................................................................. 31
Figure 14. STB Y-to-NORMAL Transition (DEFAULT) .......................................................................................................... 32
Figure 15. Pre-Biased Output Voltage .................................................................................................................................. 32
Figure 16. Power Dissi pat io n ................................................................................................................................................ 33
Figure 17. Power Dera ting C urve .......................................................................................................................................... 33
Figure 18. Hot Pl ug Inpu t Volta ge Sp ike ............................................................................................................................... 34
Figure 19. MIC7400 Power -Up/Down ................................................................................................................................... 35
Figure 20. MIC7400 STBY Func tio n (DEF AULT) ................................................................................................................. 36
Figure 21. Connections for Unused Pins .............................................................................................................................. 40
Figure 22. Read/Write Prot ocol ............................................................................................................................................. 47
Micrel, Inc.
MIC7400
March
3, 2015 6 Revision 2.0
List of Tables
Table 1. Buck Outputs Default Soft-Start Time (DEFAULT) ................................................................................................. 26
Table 2. Boost Output Default Soft-Start Time ..................................................................................................................... 28
Table 3. Buck Current Limit Register Settings ...................................................................................................................... 28
Table 4. Summarization of Unused Pin Connections ........................................................................................................... 40
Table 5. Power Good Status Register .................................................................................................................................. 49
Table 6. EEPROM Status Register ....................................................................................................................................... 50
Table 7. Overcurrent Status Fault Register .......................................................................................................................... 51
Table 8. Standby Register ..................................................................................................................................................... 52
Table 9. Enable Register ....................................................................................................................................................... 53
Table 10. DVC Registers for OUT[1 − 5] .............................................................................................................................. 54
Table 11. DVC Registers for OUT6....................................................................................................................................... 55
Table 12. Standby Registers ................................................................................................................................................. 56
Table 13. Standby DVC Register for OUT6 .......................................................................................................................... 57
Table 14. Sequence State 1 Register ................................................................................................................................... 59
Table 15. Sequenc e Stat e 2 Regis ter ................................................................................................................................... 59
Table 16. Sequence State 3 Register ................................................................................................................................... 59
Table 17. Sequence State 4 Register ................................................................................................................................... 60
Table 18. Sequence State 5 Register ................................................................................................................................... 60
Table 19. Sequence State 6 Register ................................................................................................................................... 61
Table 20. Delay Register ....................................................................................................................................................... 61
Table 21. Soft-Start Register Speed Settings ....................................................................................................................... 62
Table 22. Soft-Start Register OUT1 and OUT2 .................................................................................................................... 62
Table 23. Soft-Start Register OUT3 and OUT4 .................................................................................................................... 62
Table 24. Soft-Start Register OUT5 and OUT6 .................................................................................................................... 63
Table 25. Current-Limit Register IOUT1 and IOUT2 ................................................................................................................... 63
Table 26. Current-Limit Register IOUT3 and IOUT4 ................................................................................................................... 64
Table 27. Current-Limit Register IOUT 5 and IOUT6 ................................................................................................................... 64
Table 28. Standby Current-Limit Register IOUT1 and IOUT2 ..................................................................................................... 65
Table 29. Standby Current-Limit Register IOUT3 and IOUT4 ..................................................................................................... 65
Table 30. Standby Current-Limit Register IOUT5 and IOUT6 ..................................................................................................... 66
Table 31. Rising and Falling Power-on-Reset Threshold Voltage Settings .......................................................................... 66
Table 32. Power-on-Reset Rising Threshold Voltage Setting Register (21’h) ...................................................................... 67
Table 33. Power-on-Reset Falling Threshold Voltage Setting Register (22’h) ..................................................................... 67
Table 34. Pull-Do wn whe n Disab led Reg is ter ....................................................................................................................... 67
Micrel, Inc.
MIC7400
March
3, 2015 7 Revision 2.0
Pin Configuration
36-Pin 4.5mm × 4.5mm FQFN (FL)
(Top View)
Pin Description
Pin Number Pin Name Description
1 SW2 Switch Pin 2 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor betw een the ou tput c apac itor and the SW2 pin.
2 PVIN2 Power Supply Voltage 2 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN2 and the power ground PGND2 pin is required and to be
placed as cl ose as possible to the IC.
3 OUT2
Output Voltage Sense 2 (Input): This pin is used to sense the output voltage. Connect OUT2 as close
to the output capacitor as possible to sense output voltage. Also provides the path to discharge the
output through an internal 90Ω resistor when disabled. This pull-down feature is program me d through
the PULLD[x] register.
4 PVIN3 Power Supply Voltage 3 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN3 and the power ground PGND3 pin is required and to be
placed as cl ose as possible to the IC.
5 SW3 Switch Pin 3 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor betw een the ou tput c apac itor and the SW3 pin.
6 PGND3 Power Ground 3: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the sources of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative termina ls of outpu t capa citor s.
7 OUT3
Output Voltage Sense 3 (Input): This pin is used to sense the output voltage. Connect OUT3 as close
to the output capacitor as possible to sense output voltage. Also provides the path to discharge the
output through an internal 90Ω resistor when disabled. This pull-down feature is programme d throu gh
the PULLD[x] register.
8 PVIN4 Power Supply Voltage 4 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN4 and the power ground PGND4 pin is required and to be
placed as cl ose as possible to the IC.
Micrel, Inc.
MIC7400
March
3, 2015 8 Revision 2.0
Pin Description (Continued)
Pin Number Pin Name Description
9 SW4 Switch Pin 4 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor betw een the ou tput c apac itor and the SW4 pin.
10 PGND4 Power Ground 4: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative termina ls of outpu t capa citor s.
11 OUT4
Output Voltage Sense 4 (Input): Th i s pin is used to sense the output voltage. Connect the OUT4 as
close to the output capacitor as possible to sense output voltage. Also provides the path to discharge
the output through an int ern al 90Ω resistor when disabled. This pull-down feature is programmed
through the PULLD[x] register.
12 STBY
Standby Reset (Input): Standby mode allows the total power consumption to be reduced by either
lowering a supply voltage or turning it off. The IC can be placed in standby mode while operating in
normal mode by a high-to-low transition (DEFAULT) on the STBY input. When this occurs, the
STBY_MODEB bit will be set to l ogic “0”. Either a low-to-high transition on the STBY pin or an I²C
write command to the STBY_MODEB bit sets all of the regulators to their normal mode default
settings. This pin can be driven with either a digital signal or open collector output. Do not let this pin
float. Connect to ground or VIN. A pull-down resistor of 100kΩ or less can also be used. There are
both a high-to-lo w (DEFAULT) and low-to-high nor mal to standby trigger options available.
13 SDA High-Speed Mode 3.4MHz I²C Data (Input/Output): This is an open drain, bidirectional data pin. Data
is read on the rising edge of the SCL and data is clocked out on the fall ing edge of the SCL. External
pull-up resistors are required.
14 AGND Analog Ground: Internal signal ground for all low power circuits. Connect to ground plane for best
operation.
15 SCL High-Speed Mode 3.4MHz I²C Clock (Input): I²C serial cl oc k line open dr ai n input. E xternal pull-up
resistors are required.
16 POR
Power-on-Reset (O utput): This is an open drain output that goes high after the POR delay time
elapses. The POR delay time starts as soon as the AVIN pin voltage rises above the upper threshold
set by the PORUP register. The POR output goes low without delay when AVIN falls below the lower
threshold set by the PORDN register.
17 OUT5
Output Voltage Sense 5 (Input): This pin is used to sense the output voltage. Connect OUT5 as close
to the output capacitor as possible to sense output voltage. Also provides the path to discharge the
output through an internal 90Ω resistor when disabled. This pull-down feature is programme d throu gh
the PULLD[x] register.
18 PGND5 Power Ground 5: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negati ve terminals of input
capacitors, and the negative termina ls of outpu t capa citor s.
19 SW5 Switch Pin 5 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor betw een the ou tput c apac itor and the SW5 pin.
20 PVIN5 Power Supply Voltage 5 (Input): Input supply to the source of the internal high-side P-channel
MOSFET. An input capacitor between PVIN5 and the power ground PGND5 pin is required and to be
placed as cl ose as possible to the IC.
21 OUT6
Output Voltage 6 Sense (Input): This pin is used to sense the output voltage. Connect OUT6 as close
to the output capacitor as possible to sense output voltage. Also provides the path to discharge the
output through an internal programmable current source when disabled. This pull-dow n featur e is
programmed through the PULLD[x] register.
22 PGND6 Power Ground 6: The power ground for the boost converter power stage. The P GN D pin conne cts to
the source of the internal low-side N-Channel MOSFET, the negative terminals of input capacitors,
and the negative terminals of output capacitors.
23 SW6 Switch Pin 6 (Input): Inductor connection for the boost regulator. Connect the inductor between the
PVIN6O and SW6 pin.
Micrel, Inc.
MIC7400
March
3, 2015 9 Revision 2.0
Pin Description (Continued)
Pin Number Pin Name Description
24 PVIN6O
Power Supply Voltage 6 (Output): This pin is the output of the power disconnect switch for the boost
regulator. When the boost regulator is on, an internal switch provides a current path for the boost
inductor. In shutdown, an internal P-channel MOSFET i s turned off and disconnects the boost output
from the input supply. This feature eliminates current draw from the input sup ply dur ing shut dow n. An
input capacitor between PVIN6O and the power ground PGND6 pin is required and place as close as
possible to the IC.
25 PVIN6 Power Supply Voltage 6 (Input): Input supply to the internal disconnect switch.
26 PVIN1 Power Supply Voltage 1 (Input): Input supply to the source of the internal hig h-side P-channel
MOSFET. An input capacitor between PVIN1 and the power ground PGND1 pin is required and to be
placed as cl ose as possible to the IC.
27 SW1 Switch Pin 1 (Output): Inductor connection for the synchronous step-down regulator. Connect the
inductor betw een the ou tput c apac itor and the SW1 pin.
28 PGND1 Power Ground 1: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negati ve terminals of input
capacitors, and the negative termina ls of outpu t capa citor s.
29 OUT1
Output Voltage Sense 1(Input): This pin is used to sense the output voltage remotely. Connect OUT1
as close to output capacitor as possible to sense output voltage. T his feat ur e also provides the path to
discharge the output t hrou gh a n inter nal 90Ω resistor when disabled. The pull-dow n featur e is
programmed through the PULLD[x] register.
30 VSLT POR Selection Threshold (Input): A high on this pin sets the PORUP and PORDN registers to their
upper threshold limits and a low to their lower threshold limits. Do not leave floating.
31 AVIN
Analog Voltage Supply (Input): The start-up sequence begins as soon as the AVIN pin voltage rises
above the IC’s UVLO upper threshold. The outputs do not turn off until AVIN pin voltage falls below
the lower threshold limit. A 2.2µF ceramic capacitor from the AVIN pin to AGND pin must be placed
next to the IC.
32 AGND Analog Ground: Internal signal ground for all low power circuits. Connect directly to the layer 2 ground
plane. Layer 2 is the point where all the PGNDs and AGND are connected. Do not connect PGND
and AGND together on the top layer.
33 NC No Connect. Must be left floating.
34 NC No Connect. Must be left floating.
35 PG
Global Power Good (Output): This is an open drain output that is pulled high when all the regulator
power good flags are high. If an output falls below the power good threshold or a thermal fault occurs,
the global power good flag is pulled low. There is a fall ing ed ge de-glitch time of 50µs to prev ent false
triggering on output voltage transients. A power good mask feature programmed through the
PGOOD_MASK[x] registers can be used to ignore a power good fault. When masked an individual
power good fault will not cause the global power good output to de-assert. Do not connect the power
good pull-up resistor to a voltage higher than AVIN.
36 PGND2 Power Ground 2: The power ground for the synchronous buck converter power stage. The PGND pin
connects to the source of the internal low-side N-Channel MOSFET, the negative terminals of input
capacitors, and the negative termina ls of outpu t capa citor s.
EP ePad Exposed Pad: Must be connected to the GND plane for full output power to be realized.
Micrel, Inc.
MIC7400
March
3, 2015 10 Revision 2.0
Absolute Maximum Ratings(3)
Suppl y Voltages (PVIN[1-6]) .................................. -0.3V to 6V
Analog Supply Voltage (AVIN) ............................ -0.3V to 6V
Buck Output Voltages (VOUT[1-5]) ......................... -0.3V to 6V
Boost Output Voltage (VOUT6) ........................... -0.3V to 20V
Buck Switch Voltag es (VSW[1-5]). ......................... -0.3V to 6V
Boost Switch Voltage (VSW6). ........................... -0.3V to 20V
Power Good Voltage (VPG) .............................. -0.3V to AVIN
Power-On Reset Output (VPOR) .......................... -0.3V to 6V
POR Threshold Voltage (VVSLT) ......................... -0.3V to 6V
Standby Voltage (VSTBY) ..................................... -0.3V to 6V
I²C IO (VSDA, VSCL) ........................................... -0.3V to AVIN
AGND to PGND[1-6] ....................................... -0.3V to 0.3V
Ambient Storage Temperature (Ts) ........... -40°C to +150°C
ESD HBM Rating(6) ........................................................ 2kV
ESD MM Rating............................................................ 200V
Operating Ratings(4)
Input Voltage (PVIN[1-6]) ..................................... 2.4V to 5.5V
Analog Input Voltage (AVIN) ............................. 2.4V to 5.5V
Buck Output Voltage Range (VOUT[1-5]) ............. 0.8V to 3.3V
Boost Output Voltage Range (VOUT6) ................... 7V to 14V
Power Good Voltage (VPG) ................................... 0V to AVIN
Power-On Reset Output (VPOR) ............................ 0V to AVIN
POR Threshold Voltage (VVSLT) ........................... 0V to AVIN
Standby Voltage (VSTBY) ....................................... 0V to AVIN
I²C IO (VSDA, VSCL) ................................................ 0V to AVIN
Junction Temperature (TJ)(5) ...................... -40°C to +125°C
Junction Thermal Resistance
4.5mm × 4.5mm FQFN-36 (θJA) ........................ 30°C/W
Electrical Characteristics(7)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter Conditions Min. Typ. Max. Unit
Input Supply (VIN)
Input Voltage Range (AVIN, PVIN[1-6]) 2.4
5.5 V
Operating Quiescent Current
into AVIN(8, 9) VIN = 5.0V; IOUT = 0A
200 240 μA
Operating Quiescent Current
into PVIN(8) VIN = 5.0V; IOUT = 0A
0.3 1 μA
Undervoltage Lockout Threshold AVIN Rising 2.15 2.25 2.35 V
Undervoltage Lockout Hysteresis
150
mV
Standby Input (STBY)
Logic Level High 1.2
V
Logic Level Low
0.4 V
Bias Current into Pin VSTBY = VIN
200 nA
Bias Current out of Pin VSTBY = 0V
200 nA
Rising/Falling Edge Reset Degli tch
100
μs
Notes:
3. Absol ute maximum rati ngs indicate limits beyond which damage to the component may occur.
4. The device is not guarant eed to function outside its operat i ng rating.
5. The maxim um allowable power dissi pation is a function of the maximum junction temperature, TJ(Max), the junction-to-ambient thermal resistance, θJA,
and the ambient temperature, TA. The maximum allowable power dissipat i on will result in excessi ve di e temperature, and the regulator will go into
thermal shutdown.
6. Devices are ESD sensitive. Handling prec autions recommended. Human body model, 1.5kΩ in series with 100pF.
7. Specific at i on for packaged product only.
8. Test ed in a non-switching configuration.
9. When all outputs are configured to the minimum programmable voltage.
Micrel, Inc.
MIC7400
March
3, 2015 11 Revision 2.0
Electrical Characteristics(7) (Continued)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter Conditions Min. Typ. Max. Unit
POR Threshold Input (VSLT)
Logic Level High
1.2
V
Logic Level Low
0.4 V
Bias Current Into Pin VVSLT = VIN
200 nA
Bias Current Out of Pin VVSLT = 0V
200 nA
Power-On-Reset (POR) Comparator
POR Upper Comparator Range
AVIN Rising, VVSLT = 0V
2.646
2.7
2.754
V
POR Lower Comparator Range
AVIN Falling, VVSLT = 0V
2.548
2.6
2.652
V
POR Upper Comparator Range
AVIN Rising, VVSLT = VIN
3.626
3.7
3.774
V
POR Lower Comparator Range
AVIN Falling, VVSLT = VIN
3.528
3.6
3.672
V
Power Reset Output (POR) and Timer
POR Delay
18 20 22 ms
POR Deglitch Delay AVIN Falling
50
μs
POR Output Low Voltage IPOR = 10mA (sinking)
75 400 mV
POR Leakage Current VPOR = 5.5V
200 nA
Global Power Good Output (PG)
Buck Power Good Threshold Voltage VOUT[1-5] Rising 87 91 95 %VOUT
Buck Hysteresis
(10)
VOUT[1-5] Falling
4
%VOUT
Boost Power Good Threshold Voltage VOUT[6] Rising 87 91 95 %VOUT
Boost Hysteresis(10) VOUT[6] Falling
380
mV
Power Good Output Low Voltage IPG = 10mA (sinking)
75 400 mV
Power Good Leakage Current VPG = 5.5V
0.01 200 nA
Power Good De-Glitch Delay VOUT[1-6] Falling
100
μs
Output Sequencing Delay(10)
0.96 1 1.04 ms
Thermal Protection
Thermal Shutdown TJ Rising
160
°C
Thermal Hysteresis
20
°C
Note:
10. Guaranteed by desi gn.
Micrel, Inc.
MIC7400
March
3, 2015 12 Revision 2.0
Electrical Characteristics(7) (Continued)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter Conditions Min. Typ. Max. Unit
Synchronous Buck (VOUT1 - VOUT5)
Buck Output Voltage Accuracy (OUT[1-5])
Typical Output Voltage 1 Accuracy(11) Include s Load, Line , and Reference
−
1.5% 1.5% %
Typical Output Voltage 2 Accuracy(11) Include s Load, Line , and Reference
−
1.5% 1.5% %
Typical Output Voltage 3 Accuracy(11) Include s Load, Line , and Reference
−
1.5% 1.5% %
Typical Output Voltage 4 Accuracy(11) Include s Load, Line , and Reference
−
1.5% 1.5% %
Typical Output Voltage 5 Accuracy(11) Include s Load, Line , and Reference
−
1.5% 1.5% %
Output Voltage 1 Accuracy(11)
−
1% 1% %
Output Voltage 2 Accuracy(11)
−
1% 1% %
Output Voltage 3 Accuracy(11)
−
1% 1% %
Output Voltage 4 Accuracy(11)
−
1% 1% %
Output Voltage 5 Accuracy(11)
−
1% 1% %
Load Regulation IOUT = 10mA to IOUT(MAX)
0.1
%
Line Regulation VIN = 3.3V to 5.0V
0.05
%
Buck Soft-Start
Soft-Start (1-5) LSB(10, 12) 3.84 4 4.16 µs/step
Buck Internal MOSFETs
High-S ide On-Resistance VIN = 3.3V; ISW[1-5] = 200mA 54 mΩ
High-S ide On-Resistance VIN = 5.0V; ISW[1-5] = 200mA 40 mΩ
Low-Side On-Resistance VIN = 3.3V; ISW[1-5] = -200mA 37 mΩ
Low-Side On-Resistance VIN = 5.0V; ISW[1-5] = -200mA 30 mΩ
Output Pull-Down Resistance VSW[1-5] = 0V 75 90 200 Ω
Buck Controller Timing
Fixed On-Time(13) VIN = 3.3; VOUT = 1.0V; IOUT = 1.0 A 220 ns
Minimum OFF-Time 80 ns
Note:
11. Not test ed in a closed loop configuration.
12. The soft-start t ime is calcul ated using t he foll owing equati on: tsoftstart = [(VOUT_PROGRAM – 0.15)/0.05 +1) × tRAMP.
13. Buck frequency is calcul at ed usi ng the following equati on fSW = (VOUT/VIN) × (1/tON).
Micrel, Inc.
MIC7400
March
3, 2015 13 Revision 2.0
Electrical Characteristics(7) (Continued)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter Conditions Min. Typ. Max. Unit
Buck Current Limit (OUT1-OUT5)
Buck 1 Current Limit Threshold See Table 3 for IPROG Settings 3.075 4.1 5.125 A
Buck 2 Current Limit Threshold See Table 3 for IPROG Settings 3.075 4.1 5.125 A
Buck 3 Current Limit Threshold See Table 3 for IPROG Settings 3.075 4.1 5.125 A
Buck 4 Current Limit Threshold See Table 3 for IPROG Settings 4.88 6.1 7.32 A
Buck 5 Current Limit Threshold See Table 3 for IPROG Settings 3.075 4.1 5.125 A
Gross High-Side Curren t Limit [1-5] With Respect to Buck [x] Current Limit
150
%
Zero Cross Threshold Zero crossing detec tor
0
mV
Boost (VOUT6)
Boost Output Voltage (V
OUT6
)
Typical Output Voltage Accuracy(11) Include s Load, Line , and Reference -1.5% 1.5% %
Output Voltage Accuracy(11)
-1%
1% %
Load Regulation IOUT6 = 1.0mA to 200mA
0.2
%
Line Regulation VIN = 2.4V to 5.5V; IOUT6 = 10mA
0.2
%
VOUT6 Discharge Current VIN = 3.3V; VOUT6 = 12V 111 148 185 mA
Boost Soft-Start Step Duration
Soft-Start 6 LSB(10, 12) 3.84 4 4.16 µs/step
Boost Internal MOSFETs
Low-Side On-Resistance VIN = 3.3V; ISW1 = −100mA 160 mΩ
Low-Side On-Resistance VIN = 5.0V; ISW1 = −100mA 140 mΩ
Boost Disconnect MOSFETs
Disconnect Switch On-Resistance IPVIN6O = 100mA; VIN = 3.3V 90 mΩ
Disconnect Switch Current Limit 5 A
Boost Switching Frequency
Switching Frequency (PWM Mode) 1.92 2 2.08 MHz
Minimum Duty Cycle 35 40 45 %
Maximum Duty Cycle 80 85 90 %
Boost Current Limit
NMOS Current-Limit Threshold 2.24 A
Micrel, Inc.
MIC7400
March
3, 2015 14 Revision 2.0
Electrical Characteristics(7) (Continued)
VIN = AVIN = PVIN(1-6) = 5.0V; VOUT1 = 1.8V; VOUT2 = 1.1V; VOUT3 = 1.8V; VOUT4 = 1.05V; VOUT5 = 1.25V; VOUT6 = 12V (refer to the
Evaluation Board Schematic for component values). TA = 25°C, unless otherwise noted. Bold values indicate −40°C ≤ TJ ≤ +125°C.
Parameter Conditions Min. Typ. Max. Unit
I²C Interface
I²C Interface (SCL, SDA)
Low Level Input Voltage
0.4 V
High Level Input Voltage
1.2
V
High Level Input Current −200 0.01 200 nA
Low Level Input Current −200 0.01 200 nA
SDA Pull-Down Resistance 20 Ω
SDA Logic 0 Output Voltage ISDA = 3mA
0.4 V
CLK, DATA Pin Capacitance
0.7
pF
I²C Interface Timing
(10)
SCL Clock Frequency
Standard Mode
100 kHz
Fast Mode
400
High-Speed Mode(10)
3.4 MHz
Micrel, Inc.
MIC7400
March
3, 2015 15 Revision 2.0
Typical Characteris tics
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Buck Efficiency (LDCR = 0mΩ)
vs. Output Current
0.8V
1.0V
1.2V
1.5V
1.8V
V
IN
= 3.3V
L = 2.2µH
T
A
= 25°C
3
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Buck Efficiency (LDCR = 0mΩ)
vs. Output Current
0.8V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
3
V
IN
= 5.0V
L = 2.2µH
T
A
= 25°C
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Boost Efficiency (12V)
vs. Output Current
3.3V
5.0V
L = 2.2µH
DCR = 116mΩ
SAMSUNG
CIG22H2R2MNE
T
A
= 25°C
0.2
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Buck Efficiency (LDCR = 40mΩ)
vs. Output Current
0.8V
1.0V
1.2V
1.5V
1.8V
V
IN
= 5.0V
L = 1.0µH
DCR = 40mΩ
SAMSUNG
CIGW252010GM1R0MNE
T
A
= 25°C
3
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Buck Efficiency (LDCR = 40mΩ)
vs. Output Current
0.8V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
V
IN
= 5.0V
L = 1.0µH
DCR = 40mΩ
SAMSUNG
CIGW252010GM1R0MNE
T
A
= 25⁰C
3
-2.0%
-1.5%
-1.0%
-0.5%
0.0%
0.5%
1.0%
1.5%
2.0%
0.0001 0.001 0.01 0.1 110
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Output Voltage
vs. Output Current
-40
25
85
125
V
IN
= 3.3V
VOUT4 = 1.05V
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Buck Efficiency (LDCR = 116mΩ)
vs. Output Current
0.8V
1.0V
1.2V
1.5V
1.8V
V
IN
= 3.3VL = 2.2µH
DCR = 116mΩ
SAMSUNG
CIG22H2R2MNE
T
A
= 25°C
30
40
50
60
70
80
90
100
0.0001 0.001 0.01 0.1 1
EFFICIENCY (%)
OUTPUT CURRENT (A)
Buck Efficiency (LDCR = 116mΩ)
vs. Output Current
0.8V
1.0V
1.2V
1.5V
1.8V
2.5V
3.3V
V
IN
= 5.0V
L = 2.2µH
DCR = 116mΩ
SAMSUNG
CIG22H2R2MNE
T
A
= 25°C
-1.0%
-0.5%
0.0%
0.5%
1.0%
-50 -25 025 50 75 100 125
OUTPUT VOLTAGE (%)
TEMPERATURE (°C)
Output Voltage
vs. Tem pera ture
V
IN
= 3.3V
VOUT4 = 1.05V
IOUT4 = 2.5A
Micrel, Inc.
MIC7400
March
3, 2015 16 Revision 2.0
Typical Characteristics (Continued)
0.998
0.999
0.999
1.000
1.000
1.001
0.0001 0.001 0.01 0.1 1
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Buck Output Voltage (1.0V)
vs. Output Current
3.3V
5V
T
A
= 25°C
-0.20%
-0.15%
-0.10%
-0.05%
0.00%
0.05%
0.10%
0.15%
0.20%
0.0001 0.001 0.01 0.1 1
OUTPUT VOLTAGE ERROR (%)
OUTPUT CURRENT (A)
Buck Output Voltage Regulation
vs. Output Current
3.3V
5V
T
A
= 25°C
0.000%
0.005%
0.010%
0.015%
0.020%
0.025%
0.030%
0.035%
23456
OUTPUT VOLTAGE ERROR (%)
INPUT VOLTAGE (V)
Buck Line Regulation
vs. Input Voltage
IOUT = 1A
TA= 25°C
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
0 1 2 3
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
Dropout Output Voltage
vs. Output Current
V
IN
= 3.3V
V
OUT
= 3.3V
L = 2.2µH
DCR = 116mΩ
SAMSUNG
CIG22H2R2MNE
T
A
= 25⁰C
0
50
100
150
200
250
300
0.0 1.0 2.0 3.0 4.0 5.0
SUPPLY CURRENT (µA)
INPUT VOLTAGE (V)
V
IN
Operating Supply Current
vs. Input Voltage
I
OUT
= 0A SWITCHING
R
PG
= OPEN
R
POR
= OPEN
T
A
= 25⁰C
0.8
0.9
1.0
1.1
1.2
1.3
1.4
1.5
0.0 1.0 2.0 3.0 4.0 5.0 6.0
SWITCHNG FREQUENCY (MHz)
INPUT VOLTAGE (V)
Buck 2 Switching Frequency
vs. Input Voltage
V
OUT2
= 1.1V
I
OUT2
= 0.5A
T
A
= 25°C
0
1
2
3
4
5
6
0123456
CURRENT LIMIT (A)
OUTPUT VOLTAGE (V)
Current-Limit Threshold
vs. Output Voltage
5.1A
4.6A
4.1A
3.6A
3.1A
2.6A
2.1A
1.6A
1.1A
0
1
2
3
4
5
6
0 1 2 3 4 5 6
CURRENT LIMIT (A)
OUTPUT VOLTAGE (V)
Output Current Limit
vs. Output Voltage
5.1A
4.6A
4.1A
3.6A
3.1A
2.6A
2.1A
1.6A
1.1A
0
1
2
3
4
5
6
0 1 2 3 4 5 6
MEASURED CURRENT LIMI T (A)
PROGRAMMED CURRENT LI MI T (A)
Programmed Current Limit
vs. Measured Current Limit
V
IN
= 5.0V
V
OUT
= 1.05V
Micrel, Inc.
MIC7400
March
3, 2015 17 Revision 2.0
Functional Characteristics
Micrel, Inc.
MIC7400
March
3, 2015 18 Revision 2.0
Functional Characteristics (Continued)
Micrel, Inc.
MIC7400
March
3, 2015 19 Revision 2.0
Functional Characteristics (Continued)
Micrel, Inc.
MIC7400
March
3, 2015 20 Revision 2.0
Functional Characteristics (Continued)
Micrel, Inc.
MIC7400
March
3, 2015 21 Revision 2.0
Functional Characteristics (Continued)
Micrel, Inc.
MIC7400
March
3, 2015 22 Revision 2.0
Functional Characteristics (Continued)
Micrel, Inc.
MIC7400
March
3, 2015 23 Revision 2.0
Functional Characteristics (Continued)
Micrel, Inc.
MIC7400
March
3, 2015 24 Revision 2.0
MIC7400 Block Diagram
Micrel, Inc.
MIC7400
March
3, 2015 25 Revision 2.0
Functional Description
The MIC7400 is one of the industry’s most-advanced
PMIC desig ned for solid st ate drives ( SSD) on the mark et
today. It is a multi-channel solution which offers software
configurable soft-start, sequencing, and digital voltage
control (DVC) that minimizes PC board area. These
features usually require a pin for program ming. However,
this approach makes the IC larger by increasing pin
count, and also increases BOM cost due to the external
components.
The following is a complete list of programmable
features:
• Buck output voltage (0.8V – 3.3V/50mV steps)
• Boost output vo lta ge (7.0V – 14V/ 200mV steps)
• Power-on-reset (2.25V – 4.25V/50mV steps)
• Power-on-reset delay (5ms – 160ms/5ms steps)
• Power-up sequencing (6 time slots)
• Power-u p seq uenc ing delay (0m s – 7ms/1ms steps)
• Soft-start (4µs – 1024µs per step)
• Buck current limit threshold
− (1.1A to 6.1A/0.5A steps)
• Boost current limit threshold
− (1.76A to 2.6A/0.12A steps)
• Boost pull-down (37mA to 148mA/37mA steps)
• Buck pull-down (90Ω)
• Buck standby output volta g e program mable
• Boost sta ndby output volta ge progr am mable
• Global power good masking
These features give the system designer the flexibility to
customize the MIC7400 for their application. For
example, VOUT1 current limit can be programmed to 4.1A
and VOUT2 can be set to 1.1A. These outputs can be
programmed to come up at the same time or 2.0ms
apart. In addition, in power-saving standby mode, the
outputs can either be turned off or programmed to a
lower voltage. With this programmability the MIC7400
can be used in multiple platforms.
The MIC7400 buck regulators are adaptive on-time
synchronous step-down DC-to-DC regulators. They are
designed to o perate over a wide input vo ltage range fr om
2.4V to 5.5V a nd pro vide a r egulate d output vo ltage at up
to 3.0A of output current. An adaptive on-time control
scheme is employed to obtain a constant switching
frequency and to simplify the control compensation. The
device includes an internal soft-start function which
reduces the power supply input surge current at start-up
by controlling the output voltage rise time.
The MIC7400 has a current-mode boost regulator that
can deliver up to 200mA of output current and only
consumes 70µA of quiescent current. The 2.0MHz
switching frequency allows small chip inductors to be
used. Programmable overcurrent sensing protects the
boost from overloads and an output disconnect switch
opens to protect against a short-circuit condition. Soft-
start is also programmable and controls both the rising
and falling output.
Programma b le Buck Soft-Start Control
The MIC7400 soft-start feature forces the output voltage
to rise gradually, which limits the inrush current during
start-up. A slower output rise tim e will draw a lower input
surge current. The soft-start time is based on the least
significant bit (LSB) of an internal DAC and the speed of
the ramp rate, as shown in Figure 1. This illustrates the
soft-start waveform for all five synchronous buck
converters. The initial step starts at 150mV and each
subsequent step is 50mV.
Figure 1. Buck Soft-Start
The output ramp rate (tRAMP) is set by the soft-start
registers. Each output ramp rate can be individually set
from 4µs to 1024µs, see Table 1 for details.
Micrel, Inc.
MIC7400
March
3, 2015 26 Revision 2.0
The soft-start time tSS can be calculated by Equati on 1:
RAMP
OUT
SS
t
mV50 V
15.
0
V
t×
−
=
Eq. 1
Where:
tSS = Output rise time
VOUT = Output voltage
tRAMP = Output dwell time
For example:
s264t
s8
mV50 V15.0V8.1
t
SS
SS
m=
m×
−
=
Where:
VOUT = 1.8V
tRAMP = 8.0µs
Table 1. Buck Outputs Default Soft-Start Time (DEFAULT)
VOUT
(V) tRAMP
(µs) tSS
(µs)
VOUT1 1.8 8 264
VOUT2 1.1 8 152
VOUT3 1.8 8 264
VOUT4 1.05 8 144
VOUT5 1.25 8 176
Figure 2 shows the output of Buck 1 ramping up cleanly,
starting from 0.15V to its final 1.1V value.
Figure 2. Buck Soft-Start
Buck Digital Voltage Control (DVC)
The output voltage has a 6-bit control DAC that can be
programmed from 0.8V to 3.3V in 50mV increments. If
the output is programmed to a higher voltage, then the
output ramps up, as shown in Figure 3.
Figure 3. Buck DVC Control Ramp
Micrel, Inc.
MIC7400
March
3, 2015 27 Revision 2.0
The ramp time is determined by Equation 2:
RAMP
INIT_OUTOUT
t
mV50
VV
t×
−
=∆
Eq. 2
Where:
VOUT_INIT = Initial output voltage
VOUT = Final output voltage
tRAMP = Output dwell time
When the regulator is set in stand-by mode or
programmed to a lower voltage, then the output voltage
ram ps down at a rat e deter m ined by the outp ut ram p rate
(tRAMP), the output capacitance and the external load.
Small loads result in slow output voltage decay and
heavy loads cause the decay to be contr olled b y the DAC
ramp rate.
In Figure 4, VOUT1 is switched to stand-by mode with an
I²C command and then switched back to normal mode
either by an I²C command or a low-to-high transition of
the STBY pin. In this case, the rise and fall tim es are the
same due to a 1A load on VOUT1.
Figure 4. Buck DVC Control Ramp
Programma b le Boost Soft-Start Control
The boost soft-start time is divided into two parts as
shown in Figur e 5. T1 is a fixed 367µ s dela y starti ng from
when the internal enable goes high. This delay gives
enough time for the disconnect switch to turn on and
bring the inductor voltage to VIN before the boost is turned
on. There is a 50µs delay which is controlled by the
parasitic capacitance (Cgd) of the disconnect switch
before the output starts to rise.
After the T1 period, the DAC output ramp starts, T 2. The
total sof t-start tim e, tSS, is the sum of both peri ods. Figure
6 displays th e actu al boos t soft-start waveform.
Figure 5. Boost Soft-Start Ramp
Figure 6. Boost Soft-Start
Micrel, Inc.
MIC7400
March
3, 2015 28 Revision 2.0
( )
( )
s16
V2.0 V4.1V12
2T
t
V2.0 V4.1V
2T
2T1Tt
RAMP
OUT
SS
m×
−
=
×
−
=
+=
Eq. 2
Where:
T1 = 367µs
T2 = 848µs
tSS = 367µs + 848µs = 1.215ms
VOUT = Output voltage
tRAMP = Output dwell time = 16µs
Boost Digital Voltage Control (DVC)
The boost output control works the same way as the
buck, except that the voltage steps are 200mV, see
Figure 7. When the boost is programmed to a lower
voltage the output ramps down at a rate determined by
the output ramp rate (tRAMP), the output capacitance and
the external load. During both the ramp up and down
time, the power good output is blanked and if the power
good mask bit is set to “1”.
Figure 7. Boost DVC Control Ram p
The ramp time can be computed using Equation 3:
RAMP
INIT_OUTOUT
t
V2.0VV
t×
−
=∆
Eq. 3
Where:
VOUT_INIT = Initial output voltage
Table 2. Boost Output Default Soft-Start Time
VOUT
(V) tRAMP
(µs) tSS
(ms)
VOUT6 12 16 1.215
Buck Current Limit
The MIC7400 buck regulators have high-side current
limiting t hat can be v aried b y a 4-bit code. If the regu lator
remains in current limit for more than seven consecutive
PWM cycles, the output is latched off, the over-current
status register bit is set to 1, the power-good status
register bit is set to 0 and the global power good (PG)
output pin is pulled low. An overcurrent fault on one
output will not disable the remaining outputs. Table 3
shows the current limit register settings verses output
current. The current limit register setting is set at twice
the maximum output current.
Table 3. Buck Current Limit Register Settings
IOUT(MAX) IPROG BINARY HEX
0.5A 1.1A 1111 F’h
1.0A 2.1A 1101 D’h
1.5A 3.1A 1011 B'h
2.0A 4.1A 1001 9'h
2.5A 5.1A 0111 7'h
3.0A 6.1A 0101 5'h
The output can be turned back on by recycling the input
power or by software control. To clear the overcurrent
fault by software control, set the enable register bit to “0”
then clear the overcurrent fault by setting the fault
register bit to “0”. This will clear the over-current and
power good status registers. Now the output can be re-
enabled by setting the enable register bit to “1”.
Micrel, Inc.
MIC7400
March
3, 2015 29 Revision 2.0
During start-up sequencing if Output 1 is still shorted,
Outputs 2 through 4 will come up normally. Once an
overcurrent condition is sensed, then the fault register is
set to “1” and the start-up sequence will stop and no
further outputs will be enabled. See Figure 9 for default
start-up sequence.
Boost Current L imit
The boost current lim it features cycle-by-c ycle protect ion.
The dut y cycle is cut imm ediatel y once the cur rent lim it is
hit. W hen the boost curr ent lim it is hit for five consecutive
cycles, the FAULT signal is asserted and remains
asserted with the boost converter keeping on running
until the boost is powered off.
This pr otects the boos t in nor m al overload c ondit ions, but
not in a short-to-ground case. For a short circuit to
ground, the boost current lim it will not be able to limit the
inductor current. This short-circuit condition is sensed by
the current in t he dis con ne c t s witch. When the dis c on nect
switch cur r ent lim it is h it f or f our c onsec uti ve master cloc k
cycles (2MH z), regar dless i f the boost is switch ing or not,
both the disconnect switch and boost are latched off
automatically and the FAULT signal is asserted.
The output can be turned back on by recycling the input
power or by software control. To clear the overcurrent
fault by software control, set the enable register bit to “0”
then clear the overcurrent fault by setting the fault
register bit to “0”.
Global Po wer Goo d Pin
The global power-good output indicates that all the
outputs are above the 91% limit after the power-up
sequence is completed. Once the power-up sequence is
complete, the gl oba l po wer good out put s t a ys high u nle s s
an output falls below its power-good limit, a thermal fault
occurs, the input voltage drops below the lower UVLO
threshold or an output is turned OFF by setting the
enable r egist er bi t to “0” unless the PGO OD_MASK [x] bit
is set to “1” (Default).
A power-good mask bit can be used to control the global
power good output. The power-good mask feature is
programmed thr ough t he P GO O D_MA SK[x] r e gister s and
is used to ignore an individual power-good fault. When
masked, PGOOD_MASK[x] bit is set to “1”, an individual
power good fault will not cause the global power good
output to de-assert.
If all the PGOOD_MASK[x] bits are set to “1”, then the
power good output de-asserts as soon as the first output
starts to ris e. The PGOOD_MASK[x ] bit of the last output
must be s et to “ 0” to ha ve t he PG ou tput s tay low unti l the
last output reaches 91% of its final value.
The global power-good output is an open-drain output. A
pull-up resistor can be connected to VIN or VOUT. Do not
connect the pull-up resistor to a voltage higher than AVIN.
Standard Delay
There is a programmable timer that is used to set the
standard delay time between each time slot. The timer
starts as soon as the previous time slot’s output power
good goes high. When the delay completes, the
regulators assigned to that time slot are enabled, see
Figure 8.
Figure 8. Standard Delay T ime
Power-Up Sequen cing
When power is first applied to the MIC7400, all I²C
registers are loaded with their default values from the
EEPROM. There is about a 1.5ms delay before the first
regulator is enabled while the MIC740 0 goes through the
initialization process. The DELAY register’s STDEL bits
set the delay between powering up each regulator at
initial power up.
The sequenc ing registers allow the ou tputs to com e up in
any order. There are six time slots that an output can be
configured to power up in. Each time slot can be
programmed for up to six regulators to be turned on at
once or none at all.
Figure 9 shows an example of this feature. VOUT4 is
enabled in tim e slot 1. Af ter a 1m s delay, VOUT2 and VOUT3
are enab le a t th e s ame time in time slot 2 . The 1m s is the
standard delay for all of the outputs and can be
programmed from 0ms to 7ms in 1ms. Next, VOUT1 is
powered up in tim e slot 3 and VOUT5 in time slot 4. There
are no regulators programmed for time slot 5. Finally,
VOUT6 is powered up in time slot 6. The globa l po wer good
output, V PG, goes hi gh as s oon as th e las t output r eac hes
91% of its final value.
Micrel, Inc.
MIC7400
March
3, 2015 30 Revision 2.0
Figure 9. Hot Plug
−
VIN Rising
VSLT Pin
The power-on reset threshold toggles between two
different ranges by driving the VSLT pin hig h or low. The
lower range of 2.2 5V to 3. 25V is s elected whe n the VSLT
pin is tied to groun d. The u pper range , 3.25V t o 4.25 V, is
selected when the VSLT pin is tied to VIN.
Programmable Power-on-Reset (POR) Delay
The POR output pin provides the user with a way to let
the SOC know that the input power is failing. If the input
voltage falls below the power-on reset lower threshold
level, the POR output immediately goes low. The lower
threshold is set in the PORDN register and the upper
threshold uses PORUP register.
The low-to-high POR tra nsition can b e delayed fr om 5ms
to 160m s in 5m s increm ents. This f eature can be used to
signal the SOC that the power supplies are stable. The
PORDEL register sets the delay of the POR pin. The
POR delay starts as soon as the AVIN pin voltage rises
above the po wer-on r eset u pper thresh old lim it. Figur e 10
shows the POR operation.
Figure 10. POR
Power-Down Sequencin g
W hen power is rem oved from VIN, all the regulators try to
maintain the output voltage until the input voltage falls
below the UVLO limit of 2.35V as shown in Figure 11.
Figure 11. Hot Un-Plug
−
VIN Falling
Micrel, Inc.
MIC7400
March
3, 2015 31 Revision 2.0
Stand-By Mode
In stand-b y mode, eff iciency can be im proved by lower ing
the output voltage to the standby mode value or turning
an output off com pletely. Ther e are t wo regis ters us ed for
setting the output voltage, normal-mode register and
stand-by mode register. The default power-up voltages
are set in the normal-mode registers.
An I²C write command to the STBY_CTRL_REG register
or the STBY pin can be used to set the MIC7400 into
stand-by mode. Figure 12 shows an I²C write command
implementation. In stand-by mode, the output can be
programmed to a lower voltage or turned completely off.
When disabled, the output will be soft-discharged to zero
if the PULLD[1-6] register are set to 1. If PULLD[x] = 0
the output drifts to PGND at a rate determined by the
load current and output capacitance.
In stand-by, if an output is disabled, the global power
good output is not affected when the PGOOD_MASK[x]
is set to log ic 1. If the PGO OD_MASK[x] is s et to logic 0,
then the global power good flag is pulled low. In Figure
12, all the PGOOD_MASK[x] bits are set to logic 1.
Figure 12. I2C Stand-By Mode
Resistive Discharge
To ensure a known output condition in stand-by mode,
the output is activel y discharged to ground if the output is
disabled. Setting the buck pull down register field
PULLD[1-5] = 1 connects a 90Ω pull down resistor from
OUT[x] to PGND[x] when the MIC7400 is disabled. If
PULLD[x] = 0 the output drifts to PGND at a rate
determined by the load current and the output
capacitance value. The boost has a programmable pull-
down current level from 37mA to 148mA. In Figure 13,
the top trac e shows the norm al pull down and the bott om
trace is with the 90Ω pull-down.
Figure 13. Output Pull-Down Resistance
STBY Pin
A pin-selectable STBY input allows the MIC7400 to be
placed into standby or normal mode. In standby mode,
the individual regulator can be turned on or off or the
output voltage can be set to a different value. If the
regulators are turned off, standby mode cuts the
quiescent current by 23µA for each buck regulator and
70µA for the boost.
Figure 14 illustrates the STBY pin operation. A low-to-
high transition on the STBY pin switches the output from
standby mode to normal mode. There is a 100µs STBY
deglitch time to eliminate nuisance tripping then all the
regulators are enabled at the same time and ramp up
with their programmed ramp rates. A high-to-low
transition on the STBY pin switches the output from
normal mode to standby mode.
Micrel, Inc.
MIC7400
March
3, 2015 32 Revision 2.0
Figure 14. STBY-to-NORMAL Transition (DEFAULT)
Safe Start -Up into a Pre-Biased Output
The MIC7400 is designed for safe start-up into a pre-
biased output. This prevents large negative inductor
currents which can cause the output voltage to dip and
excessive output voltage oscillations. A zero crossing
comparator is used to detect a negative inductor current.
If a negative inductor current is detected, the low-side
synchronous MOSFET functions as a diode and is
immediately turned off.
Figure 15 s hows a 1V output pr e-bias at 0.5V at start-up,
see VOUT4 trace. The inductor current, Trace IL4, is not
allowed to go n egati ve b y m ore than 0. 5A bef ore t he l ow-
side switch is turned off. This feature prevents high
negative inductor current flow in a pre-bias condition
which can damage the IC.
Figure 15. Pre-Biased Output Voltage
Buck Reg u lator Power Dissipation
The total power dissipation in a MIC7400 is a
combination of the five buck regulators and the boost
dissipation. The buck regulators (OUT1 to OUT5)
dissipation is approximately the switcher’s input power
minus the switcher’s output power and minus the power
loss in the inductor:
PD_BUCK ≈ VIN × IIN – VOUT × IOUT – PL_LOSS Eq. 4
While the boost power dissipation is estimated by
Equation 5:
PD_BOOST ≈ VIN × IIN – VOUT x IOUT – PL_LOSS – Vf ×
IOUT
Eq. 5
Although the maximum output current for a single buck
regulator can be as much as 3A, the MIC7400 will
thermal limit and will not support this high output current
on all outputs at the same time.
Total Power Dissipation
The total power dissipation in the MIC7400 package is
equal to the sum of the power loss of each regulator:
PD_TOTAL ≈ SUM (PD_SWITCHERS) Eq. 6
Micrel, Inc.
MIC7400
March
3, 2015 33 Revision 2.0
Once the total power dissipation is calculated, the IC
junction temperature can be estimated using Equation 7:
TJ(MAX) ≈ TA + PD_TOTAL × θJA Eq. 7
Where:
TJ(MAX) = The maximum junction temperature
TA = The ambient temperature
θJA = The junction-to-ambient thermal resistance of the
package (30°C/W)
Figure 16 shows the measured junction temperature
versus power dissipation of the MIC7400 evaluation
board. T he actua l ju nction t em peratur e of the IC dep ends
upon man y factors . The signif icant factors inf luencing the
die temper ature rise ar e co pper thick ness in the PCB, the
surface area available for convection heat transfer, air
flow and power dissipation from other components,
including inductors, SOCs and processor ICs. It is good
engineering practice to measure all power components
temperature during the final design review using a
thermal couple or IR thermometer, see the “Thermal
Measurements” sub-section for details.
Figure 16. Power Dissipation
Power Derating
The MIC7400 package has a 2W power dissipation limit.
To keep the IC junction temperature below a 125°C
design lim it, the output power has to be lim ited above an
ambient tem per ature of 65°C. Figure 17 s hows the po wer
dissipation derating curve.
Figure 17. Powe r Derating Curve
The maximum power dissipation of the package can be
calculated b y Equation 8:
−
≈
JA
AJ(MAX)
MAX)(D
θ
TT
P
Eq. 8
Where:
TJ(MAX) = Maximum junction temperature (125°C)
TA = Ambient temperature
θJA = Junction-to-ambient thermal resistance of the
package (30°C/W).
Overtemperature Fault
An overtemperature fault is triggered when the IC
junction temperature reaches 160°C. When this occurs,
both t h e o vert emperatur e f ault f lag is set to “1”, the g l oba l
power good output is pulled low and all the outputs are
turned off. During the fault condition the I²C interface
remains active and all registers values are maintained.
When the die temperature decreases by 20°C the
overtemperature fault bit can be cleared. To clear the
fault, either recycle power or write a logic “0” to the over
temperature fault register. Once the fault bit is cleared,
the outputs power up to their default values and are
sequenced according to the time slot settings.
Micrel, Inc.
MIC7400
March
3, 2015 34 Revision 2.0
Input Voltage “Hot Plug”
High-voltage spikes twice the input voltage can appear
on the MIC7401 PVIN pins if a battery pack is hot-
plugged to the input supply voltage co nnection as shown
in Figure 18 (Trace 1). These spikes are due to the
inductance of the wires to the battery and the very low
inductanc e and ESR of the ceram ic input capacitors . This
problem can be solved by placing a 150µF POS capacitor
across the input terminals. Figure 18 (Trace 2) shows
that the high-voltage spike is greatly reduced to a value
below the maximum allowable input voltage rating.
Figure 18. Hot Plug Input Voltage Spike
Thermal Measurements
Measuring th e IC’s case te mperature is recommended to
ensure it is within its opera ting lim its. Although this m ight
seem like a very elementary task, it is easy to get
erroneous results. The most common mistake is to use
the standard thermal couple that comes with a thermal
meter. This thermal couple wire gauge is large (typically
22 gauge) and behaves like a heatsink, resulting in a
lower case measurement.
Two reliable m ethods of tem perature meas urement are a
smaller th er mal coupl e wire or an inf rar ed ther mometer . If
a thermal couple wire is used, it must be constructed of
36 gauge wire or higher (smaller wire size) to minimize
the wire heat-sinking effect. In addition, the thermal
couple tip must be covered in either thermal grease or
thermal glue to make sure that the thermal couple
junction is making good contact with the case of the IC.
Omega brand thermal couple (5SC-TT-K-36-36) is
adequate for most applications.
Whenever possible, an infrared thermometer is
recommended. The measurement spot size of most
infrared thermometers is too large for an accurate
reading on a small form factor ICs. However, an IR
thermometer from Optris has a 1mm spot size, which
mak es it a g ood c ho ice f or measur ing the h ottes t po int on
the case. An optional stand makes it easy to hold the
beam on the IC for long periods of time.
Micrel, Inc.
MIC7400
March
3, 2015 35 Revision 2.0
Timing Diagrams
Normal Po wer-Up Sequence for Outputs
The STDEL register sets the delay between powering up
of each regulator at initial power-up (see power-up
sequencing in Figure 19). Once all the internal power
good registers PGOOD[1-6] are all “1”, then the global
PG pin goes high without delay if the PGOOD_MASK[6]
bit is set to “0”.
The PORD EL regis t er s ets the delay for the POR f lag pin.
The POR delay time starts as soon as the AVIN pin
voltage rises above the system UVLO upper threshold
set by the PORUP register. The POR output goes low
without delay if AVIN falls below the lower UVLO
threshold set by the PORDN register.
Figure 19. MIC7400 Power-Up/Down
Micrel, Inc.
MIC7400
March
3, 2015 36 Revision 2.0
Standby (STBY) Pin (Wake-Up)
An I²C write command to the STBY_CTRL_REG register
or the STBY pin can be used to set the MIC7400 into
stand-by mode. The standby (STBY) pin provides a
hardware-specific manner in which to wake-up from
stand-by mode and go into normal mode. Figure 20
shows the STBY pin operation. A low-to-high transition
on the STBY pin switches the output from stand-by mode
to normal mode.
There is a 100µs STBY deglitch time to eliminate
nuisance tripping, then all the regulators are enabled at
the same time and ramp up with their programmed ramp
rates.
Figure 20. MIC7400 STBY Function (DEFAULT)
Micrel, Inc.
MIC7400
March
3, 2015 37 Revision 2.0
Evaluation Board Schematic
SW4
OUT4
MIC7400
C1
2.2µF
PVIN1
L4
1.0µH
PGND4
C14
22µF
PVIN4
C13
10µF
SW3
OUT3
L3
2.2µH
PGND3
C12
22µF
PVIN3
C11
10µF
SW2
OUT2
L2
2.2µH
PGND2
C10
22µF
PVIN2 26
C9
10µF L1
2.2µH
SW1
OUT1
PGND1
C3
22µF
C2
10µF
PVIN6 L6
2.2µH
PVIN6O
SW6
PGND6
C6
10µF
PVIN5 L5
2.2µH
SW5
OUT5
PGND5
C8
22µF
C7
10µF
31
30
AVIN
VSLT
15
14
13
POR
SCL
AGND
SDA
35
34
33
32
PG
NC
NC
AGND
12 STBY
16
R1
100kΩ
OUT6
C5
22µF
R6
499kΩ
D1
PMEG4002
27
29
28
25
24
23
22
21
20
19
17
18
2
1
3
36
4
5
7
6
8
9
11
10
R5
2kΩ
R3
2kΩ
R2
100kΩ
VIN
CLK
SDA
NC
4
3
2
R8
NF
VIN
VIN
VIN
VIN
VIN
VIN
V
OUT1
1.8V/0.8A
V
OUT6
12V/0.2A
V
OUT5
1.25V/1.0A
V
OUT4
1.05V/3.0A
V
OUT3
1.8V/0.5A
V
OUT2
1.1V/0.5A
R7
0Ω
C4
10µF
PGND
PGND
PGND
GND 1
PGND
VIN
VIN
PGND
PGND
PGND
R4
499kΩ
VIN
VSLT
VIN
STAND-BY
STAND-BY
POR
PG
VSLT
TP14
VIN
PG
VSLT
VIN
PGND
C15
150µF +
Micrel, Inc.
MIC7400
March
3, 2015 38 Revision 2.0
Bill of Materials
Item Part Number Manufacturer Description Qty.
C1 CL05A225KO5NQNC Samsung
(14)
2.2µF/16V, Ceramic, X5R, 0402, 0.8mm, ±10% 1
C2, C7, C9, C11,
C13 CL10A106MO8NQNC Samsung 10µF/16V, Ceramic, X5R, 0603, 0.8mm, ±20% 5
C4, C6 CL21A106KAYNNNE Samsung 10µF/25V, Ceramic, X5R, 0805, 1.25mm, ±20% 2
C3, C5, C8, C10,
C12, C14 CL10A226MQ8NUNE Samsung 22µF/6.3V, Ceramic, X5R, 0603, 0.8mm, ±20% 6
C15
EEF-CX0J151XR
Panasonic
150µF/6.3V, POS Capacitor, SP, ±20%
1
D1 PMEG4002EL NXP
(15)
0.2A/40V, Schottky, SOD-882 1
R1, R2 RC1005F104CS
Samsung
100kΩ, Resistor, 0402, 1% 3
R3, R5 RC1005F202CS
Samsung
2.0kΩ, Resistor, 0402, 1% 2
R4, R6 RC1005F4993CS
Samsung
499kΩ, Resistor, 0402, 1% 1
R7 RC1005J000CS
Samsung
0.00Ω, Resistor, 0402, Jumper 1
L1, L2, L3, L5, L6 CIG22H2R2MNE Samsung 2.2µH, 1.6A Inductor, 116mΩ, 2520 × 1.2mm (max) 5
L4 CIGW252010GM1R0MNE Samsung 1.0µH, 3.3A Indu ctor
,
40mΩ, 2520 × 1.0mm (max) 1
U1 MIC7400YFL Micrel(16) Five-Channel Buck Regulator Plus One Boost
with HyperLight Load® and I 2C Control 1
Notes:
14. Samsung: www.samsung.com.
15. NXP: www.nxp.com.
16. Micrel, Inc.: www.micrel.com.
Micrel, Inc.
MIC7400
March
3, 2015 39 Revision 2.0
PCB Layout Guidelines
Warning!!! To minimize EMI and output noise, follow
these layou t recommendations .
PCB layout is critical to achieve reliable, stable, and
efficient performance. A ground plane is required to
control EMI an d minimize the inductanc e in po wer , sig nal ,
and return paths.
The following guidelines should be followed to ensure
proper operation:
General
• Most of the heat removed from the IC is due to the
exposed pad (EP) on the bottom of the IC conducting
heat into the internal ground planes and the ground
plane on the bottom side of the board. Use at least 1 6
vias for the EP to ground plane connection.
• Do not connect the PGND and AGND traces together
on the top layer. The single point connection is made
on the layer 2 ground plane.
• Do not put a via directly in front of a high current pin,
SW, PGND, or PVIN. This will increase the trace
resistance and parasitic inductance.
• Do not place a via in between the input and output
capacitor ground connection. Put it to the inside of the
output capacitor and in the way of the high di/dt
current path.
• Route all power traces on the top layer, as shown in
the example layout.
• Place the input capacitors first and put them as close
as possible to the IC.
IC
• The 2.2µF ceramic capacitor, which is connected to the
AVIN pin, must be loc ate d right at the IC. The AVIN pin
is very noise sensitive and placement of the capacitor
is very critical. Use wide traces to connect to the AVIN
and AGND pins.
• The analog ground pin (AGND) must be connected
directly to the ground planes. Do not route the SGND
pin to the PGND Pad on the top layer.
• Use fat traces to route the input and output power
lines.
• Use Layer 5 as an input voltage power plane.
• Layer 2 and the bottom layer (Layer 6) are ground
planes.
Input Capacitor
• A 10µF X5R or X7R dielectrics ceramic capacitor is
recommended on each of the PVIN pins for bypassing.
• Place the input capacitors on the same side of the
board and as close to the IC as possible.
• Keep both the PVIN pin and PGND connections short.
• If possible, place vias to the ground plane close to the
each input capacitor ground terminal, but not in the
way of the high di/dit current path.
• Use either X7R or X5R dielectric input capacitors. Do
not use Y5V or Z5U type capacitors.
• Do not replace the ceramic input capacitor with any
other type of capacitor. Any type of capacitor can be
placed in parallel with the input capacitor.
• In “Hot-Plug” applications, a Tantalum or Electrolytic
bypass c apac itor must be u sed to l imit the o ver-voltage
spike seen on the input supply with power is suddenly
applied.
Inductor
• Keep the inductor connection to the switch node (SW)
short.
• Do not route any digital lines underneath or close to
the inductor.
• To minimize noise, place a ground plane underneath
the inductor.
Output Capacitor
• Use a wide trace to connect the output capacitor
ground term inal to the input capacitor ground terminal.
In the example layout, all input and output capacitor
ground connections are place back-to-back.
• The OUT [1-6] trace s hould be separat e fr om the power
trace an d connecte d as c lose as p ossible t o the outp ut
capacitor. Sensing a long high-current load trace can
degrade the DC load regulation.
Micrel, Inc.
MIC7400
March
3, 2015 40 Revision 2.0
Proper Termination of Unused Pins
Many designs will not require all six DC-to-DC output
voltages. In these cases, the unused pin must be
connecte d to either VIN or G ND.
The sc hematic in Fig ure 21 sho ws wh ere to ti e the unus ed
pins and Table 4 summarizes the connections.
Figure 21. Connections for Unused Pins
Table 4. Summarization of Unused Pin Connections
Unused VIN PGND
Boost PVIN6, PGIN6O, VOUT6 PGND6, SW6
Buck PVIN[x], VOUT[x} PGND[6], SW[x]
POR POR
SW4
OUT4
MIC7400
C1
2.2µF
PVIN1
L4
1.0µH
PGND4
C14
22µF
PVIN4
C13
10µF
SW3
OUT3
L3
2.2µH
PGND3
C12
22µF
PVIN3
C11
10µF
SW2
OUT2
L2
2.2µH
PGND2
C10
22µF
PVIN2 26
C9
10µF
SW1
OUT1
PGND1
PVIN6
PVIN6O
SW6
PGND6
PVIN5 L5
2.2µH
SW5
OUT5
PGND5
C8
22µF
C7
10µF
31
30
AVIN
VSLT
15
14
13
POR
SCL
AGND
SDA
35
34
33
32
PG
NC
NC
AGND
12 STBY
16
R1
100kΩ
OUT6
R6
499kΩ
27
29
28
25
24
23
22
21
20
19
17
18
2
1
3
36
4
5
7
6
8
9
11
10
R5
2kΩ
R3
2kΩ
VIN
CLK
SDA
NC
4
3
2
R8
NF
VIN
VIN
VIN
VIN
VIN
VIN
V
OUT5
1.25V/1.0A
V
OUT4
1.05V/2.5A
V
OUT3
1.8V/0.5A
V
OUT2
1.1V/0.5A
R7
0Ω
PGND
GND 1
PGND
VIN
VIN
PGND
PGND
PGND
R4
100kΩ
VIN
VSLT
VIN
STAND-BY
STAND-BY
POR
PG
VSLT
TP14
VIN
PG
VSLT
VIN
PGND
C15
150µF +
Micrel, Inc.
MIC7400
March
3, 2015 41 Revision 2.0
PCB Layout Recommendations
Evaluation Board Top Layer
−
Power Component Placement
Evaluation Board Top Layer
−
Layer 1 (Power Routing Layer)
Micrel, Inc.
MIC7400
March
3, 2015 42 Revision 2.0
PCB Layout Recommendations (Continued)
Evaluation Board Top Layer
−
Layer 1 (Power Routing Layer)
Evaluation Board Layer 2 (Ground Plane)
Micrel, Inc.
MIC7400
March
3, 2015 43 Revision 2.0
PCB Layout Recommendations (Continued)
Evaluation Board Top Layer
−
Layer 3 (Signal Routing Layer)
Evaluation Board Layer 4 (Ground Plane)
Micrel, Inc.
MIC7400
March
3, 2015 44 Revision 2.0
PCB Layout Recommendations (Continued)
Evaluation Board Layer
−
Layer 5 (VIN Plane)
Evaluation Board Bottom Later
−
Layer 6 (Ground Plane)
Micrel, Inc.
MIC7400
March
3, 2015 46 Revision 2.0
Via Layout Design and Layout Constraints
Via Layout Design
Notes:
Dimensions in millimeters (mm).
This package is designed to be soldered to a thermal pad on the board. Connect all ground planes together
Customers should contact thei r board fabrication site for recommended solder mask tolerance and via tenting recommendat i ons for vias placed i n the
thermal pad.
16x, dia. 0.2
0.48
1.80
1.80
0.48
Micrel, Inc.
MIC7400
March
3, 2015 47 Revision 2.0
Appendix A
I2C Control Register
The MIC7400 I²C Read/Write registers are detailed here. During normal operation, the configuration data can be saved
into non-volatile registers in EEPROM by addressing the chip and writing to SAVECONFIG key = 66’h. Saving CONFIG
data to EEPROM takes time so the external host should poll the MIC7400 and read the CONFIG bit[1] of EEPROM Ready
register 01’h to determine the end of programming.
All transac tions s tart with a control byte sen t f rom the I ²C m as ter device. T he cont rol b yte begins with a ST ART condi tion,
followed b y a 7-bit slave addres s. The s lave addres s is seven bits long f ollowed b y an eight h bit whic h is a data dir ection
bit (R/W ), a “0” indicates a transm ission (WR ITE) and a “1” ind icates a requ est f or data (READ) . A d ata tr ansf er is al wa ys
terminated by a STOP condition that is g enera ted by the mast er.
Serial Port Operation
External Host Interface
Bidirectional I2C port capable of Standard (up to 100kbits/s), Fast (up to 400kbits/s), Fast Plus (up to 1Mbit/s) and High
Speed (up to 3.4Mbit/s) as defined in the I2C-Bus Specification.
The MIC7400 acts as an I2C slave when addressed by the external host. The MIC7400 slave address uses a fixed 7-bit
code and is f ollowed b y an R/W bit which is part of the cont rol word t hat is ri ght after the s tart bi t as sho wn in Figure 2 2 in
the Device Address column.
The MIC7400 can receive m ultiple data bytes after a single address byte and autom aticall y increments its regis ter pointer
to block fill internal volatile memory. Byte data is latched after individual bytes are received so multi-byte transfers could
be corrupted if interrupted mid-stream.
No system clock is required by the digital core for I2C access from the external host (only the host SCL clock is assumed).
In order to prevent spurious operat ion of the I2C, if a start bit is s een, then any partial com munication is abo rted and new
I2C data is a llo wed. Start bit is when SD A goes lo w when SCL is hig h. Stop bit is when SDA go es hi gh when SCL is high.
Normal I2C exchange is shown in Fi gure 22.
Figure 22. Read/Write Protocol
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Special Host I2C Commands
The following commands are all 2 byte communications:
Byte1 = device address with write bit set, LSB = 0
Byte2 = special key
Special Keys
• SAVECONFIG Key = 66’h. Saves the shadow register configuration data into EEPROM registers 03’h thru 23’h.
• RESET Key = 6A’h. Reloads only NORMAL mode voltage and current limit settings then enables the regulator to
NORMAL m ode with no soft-start, no s equencing, and no de lays. Then c lears the STANDBY register bit 6 in register
03’h.
• RELOAD Key = 6B’h. Reloads all data from EEPROM into the shadow registers. No other actions are performed,
including soft-start, sequencing, and de lay.
• REBOOT Key = 6C ’h . Turns al l r eg ulat ors OFF, r el oa ds EE PRO M da ta into s had o w reg ister s , th en r e-seq ue nc es the
regulators with the programmed soft-start and sequence delays.
• SEQUENCE Key = 6D’h. Turns all regulators OFF, restarts the sequencer including soft-start and sequence delays.
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Appendix B
Register Settings Descriptions
Power Good Register (00’h)
This r egister in dicat es whe n the r e gul ator s 1 − 6 o utput volt age is abo ve 91% of the targ et val ue. T he MI C 7 400 deglitches
the input signal for 50µs in order to prevent false events. The global PG pin indicator is functional ‘AND’ of all the power
good indicators during sequencing. Once the power-up sequence is complete, the global power good output stays high
unless an output falls below its power-good limit, a thermal fault occurs, the input voltage drops below the lower UVLO
threshold or an output is turned OFF by setting the enable register bit to “0” if the PGOOD_MASK[x] bit is set to “0”.
Table 5. Power Good Status Register
Register Name PGOOD1-6_REG Power Good Status Register
Address 0x00’h
Field bit R/W Default Description
PGOOD1 0 R 0 Power Good indicator for Regulator 1
0 = Buck Not Valid 1 = B uck Valid
PGOOD2 1 R 0 Power Good indicator for Regulator 2
0 = Buck Not Valid 1 = B uck Valid
PGOOD3 2 R 0 Power Good indicator for regulator 3
0 = Buck Not Valid 1 = B uck Valid
PGOOD4 3 R 0 Power Good indicator for Regulator 4
0 = Buck Not Valid 1 = Buck Valid
PGOOD5 4 R 0 Power Good indicator for Regulator 5
0 = Buck Not Valid 1 = B uck Valid
PGOOD6 5 R 0 Power Good indicator for Regulator 6
0 = Boost Not Valid 1 = Boost Valid
Reserved 6 R/W 0 Not Used
Reserved 7 R/W 0 Not Used
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EEPROM-Ready Register (01’h)
This register indicates the status of EEPROM to external I²C host.
The READ Y bit = 1 when the Trim and Configuration data have be en loaded into core from EEPROM after reset, reboot
or reload and the chip is ready for operation. [If the SAVE1 bit in register 04’h is read in as logic 1, the configuration
registers will not be loaded from the EEPROM memory and the READY bit will still get set indicating that any startup
procedure involv ing the EEPROM m em or y is com plete. ] The READY bit w ill be s et to 1 after l oadin g or atte m pting to load
Trim and Configuration da ta f rom EEPROM into vo latile mem ory. The T rim data wil l alwa ys be lo aded a nd if SAVE1 b it in
register 04’h is set to logic 0, Configuration data is also loaded. Regardless of the SAVE1 bit being set or not, after the
loading operation the READY bit is set to 1.
The CONFIG bit = 1 when the Configuration data have been saved to EEPROM after the SAVECONFIG Code is issue d
from the Host. If CONF IG=1 before the SAV ECONFIG c ode is issue d, CONFIG wil l be cleared imm ediately and th en will
be set to logic 1 again once all Configuration data is written to the EEPROM memory.
The CALIB bit = 1 when th e Trim data have been sav ed to EEPROM after the SAVETRIM Code is iss ued from the Host.
If CALI B=1 befor e the SA VETRIM c ode is is sued, C ALIB will be cle ared imm ediatel y and then will be s et to l ogic 1 ag ain
once all Trim data is written to the EEPROM memory.
The EEPR EAD and EEPWR ITE bits indicate if an EEPROM r ead or wr ite fault has occurred. T hese bits sh ould be read
and cleared prior to reloading data from the EEPROM memory.
Table 6. EEPROM Status Register
Register Name STATUS_REG EEPROM Status Register
Address 0x01’h
Field bit R/W Default Description
READY 0 R 0 Indicate ready for operation when the trim and configuration data has been loaded
0 = Data not loaded 1 = Chip Ready
CONFIG 1 R 0 Indi cate C onfi guration saved t o EEPROM
0 = Configuration not saved 1 = Configuration Saved
CALIB 2 R 0 Indicate trim data have been saved to EEROM
0 = Trim not saved 1 = Trim saved
Reserved 3 R/W 0 Not Used
Reserved 4 R/W 0 Not Used
Reserved 5 R/W 0 Not Used
EEPREAD 6 R/W 0 EEPROM Read
0 = No Fault 1 = Fault
EEPWRITE 7 R/W 0 EEPROM Write
0 = No Fault 1 = Fault
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Fault Registers (02’h)
This register indicates the over-current flag for each regulator and one global overtemperature (OT). These register bits
are set by an over current condition and reset by writing a logic “0” to each bit by the I²C host.
If the f ault condition p ersist s, the bit will be set to logic “1” again imm ediatel y by the MIC 7400 af ter it is writt en to logic “0”
by the host.
Table 7. Overcurrent Status Fault Register
Register Name FAULT_REG Overcurrent Status Fault Register
Address 0x02’h
Field
bit
R/W
Default
Description
REG1OC 0 R/W 0 Regulator 1 Overcurrent
0 = No Fault 1 = Fault
REG2OC 1 R/W 0 Regulator 2 Overcurrent
0 = No Fault 1 = Fault
REG3OC 2 R/W 0 Regulator 3 Overcurrent
0 = No Fault 1 = Fault
REG4OC 3 R/W 0 Regulator 4 Overcurrent
0 = No Fault 1 = Fault
REG5OC 4 R/W 0 Regulator 5 Overcurrent
0 = No Fault 1 = Fault
REG6OC 5 R/W 0 Regulator 6 Overcurrent
0 = No Fault 1 = Fault
Reserved 6 R/W 0 Reserved
OT 7 R/W 0 Overtemperature
0 = No Fault 1 = Fault
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Standby Register (03’h)
This register controls standby mode operation. Global stand-by mode can either be enabled by I²C or by changing the
logic state of the STBY input pin. Global stand-by is controlled by the STBY_MODEB bit. When STBY_MODEB [6] = 1
then the regulators output voltages are set to their normal-mode output voltage settings, (05’h – 0A’h) registers. When
STB Y_MO DEB [6] = 0 t hen regulators output voltages are set to the stan dby-mode outp ut voltage s ettings, (0B’ h – 10’h)
registers. If STBY [1-6] register is set to logic “0”, then the output is shut off in standby mode.
The glob al po w er go od flag is as s erted when a n output is disabled unles s th e power go od mask bit (PG OOD_M AS K[x]) is
set to 1.
Table 8. Standby Register
Register Name STBY_CTRL_REG Standby Register
Address 0x03’h
Field bit R/W Default Description
STBY1 0 R/W 1 Regulator 1 Standby Voltage Control
0 = OFF 1 = ON
STBY2 1 R/W 1 Regulator 2 Standby Voltage Control
0 = OFF 1 = ON
STBY3 2 R/W 1 Regulator 3 Standby Voltage Control
0 = OFF 1 = ON
STBY4 3 R/W 1 Regulator 4 Standby Voltage Control
0 = OFF 1 = ON
STBY5 4 R/W 1 Regulator 5 Standby Voltage Control
0 = OFF 1 = ON
STBY6 5 R/W 1 Regulator 6 Standby Voltage Control
0 = OFF 1 = ON
STBY_MODEB 6 R/W 1
Global Standby Control
0 = All regulators in Standby Mode
1 = All regulators in Normal Mode
Reserved 7 R/W 0 No t Used
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Enable/Disable Register (04’h)
This r egister controls the enab le/disable of each DC-to-DC regu lators. W hen EN(n) bit trans itions f rom “0” to “1”, then the
regulator(n) is enabled with soft-start unless the STBY_MODEB regis ter bit in register 03’h is set to logic “0”.
The conf igurat ion sav e bit “ SAVE1” shoul d be c leared b y custom er befor e saving c onfiguration data to EEPR OM. This bit
is used during power up to indicate via the Status register (00’h) that configuration data has previously been stored.
Table 9. Enable Register
Register Name EN_REG Enable Register
Address 0x04’h
Field
bit
R/W
Default
Description
EN1 0 R/W 1 Regulator 1 ON/OFF Control bi t
0 = OFF 1 = ON
EN2 1 R/W 1 Regulator 2 ON/OFF Control bi t
0 = OFF 1 = ON
EN3 2 R/W 1 Regulator 3 ON/OFF Control
0 = OFF 1 = ON
EN4 3 R/W 1 Regulator 4 ON/OFF Control
0 = OFF 1 = ON
EN5 4 R/W 1 Regulator 5 ON/OFF Control
0 = OFF 1 = ON
EN6 5 R/W 1 Regulator 6 ON/OFF Control
0 = OFF 1 = ON
Reserved 6 R/W 0 Not Used
SAVE1 7 R/W 0
Save Configuration
0 = Configuration Saved to EEPROM
1 = Not Configuration Saved to EEPROM
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Regulator Output Voltage Setting NORMAL Mode (05’h
−
09’h)
One register for each regulator output (OUT1 – OUT5). Sets output voltage of regulator for NORMAL mode operation.
Table 10. DVC Registers for OUT[1
−
5]
Register Name OUT1-5_REG DVC Registers for OUT[1-5]
Address
OUT1 = 0x05’h
OUT2 = 0x06’h
OUT3 = 0x07’h
OUT4 = 0x08’h
OUT5 = 0x09’h
Field bit R/W Default Description
OUT[1-5] 5:0 R/W See Table 2
Output Voltage setting of OUT[1-5]
DVC from 3.3 V to 0.8V in -50mV steps
000000 = 3.30V 010000 = 2.50V 100000 = 1.70V 110000 = 0.90V
000001 = 3.25V 010001 = 2.45V 100001 = 1.65V 110001 = 0.85V
000010 = 3.20V 010010 = 2.40V 100010 = 1.60V 110010 = 0.80V
000011 = 3.15V 010011 = 2.35V 100011 = 1.55V 110011 = 0.80V
000100 = 3.10V 010100 = 2.30V 100100 = 1.50V 110100 = 0.80V
000101 = 3.05V 010101 = 2.25V 100101 = 1.45V 110101 = 0.80V
000110 = 3.00V 010110 = 2.20V 100110 = 1.40V 110110 = 0.80V
000111 = 2.95V 010111 = 2.15V 100111 = 1.35V 110111 = 0.80V
001000 = 2.90V 011000 = 2.10V 101000 = 1.30V 111000 = 0.80V
001001 = 2.85V 011001 = 2.05V 101001 = 1.25V 111001 = 0.80V
001010 = 2.80V 011010 = 2.00V 101010 = 1.20V 111010 = 0.80V
001011 = 2.75V 011011 = 1.95V 101011 = 1.15V 111011 = 0.80V
001100 = 2.70V 011100 = 1.90V 101100 = 1.10V 111100 = 0.80V
001101 = 2.65V 011101 = 1.85V 101101 = 1.05V 111101 = 0.80V
001110 = 2.60V 011110 = 1.80V 101110 = 1.00V 111110 = 0.80V
001111 = 2.55V 011111 = 1.75V 101111 = 0.95V 111111 = 0.80V
6 0 Not Used
7 0 Not Used
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Boost Regulator Output Voltage Setting NORMAL Mode (0A’h)
Sets output voltage of the boost regulator (OUT6) in NORMAL mode operation.
Table 11. DVC Registers for OUT6
Register Name OUT6_REG DVC Re gisters
Address 0x0A’h
Field bit R/W Default Description
OUT6 5:0 R/W See Table 2
DVC from 14V to 7V in 200mV decrements
000000 = 14.0V 010000 = 10.8V 100000 = 7.6V 110000 = 7.0V
000001 = 13.8V 010001 = 10.6V 100001 = 7.4V 110001 = 7.0V
000010 = 13.6V 010010 = 10.4V 100010 = 7.2V 110010 = 7.0V
000011 = 13.4V 010011 = 10.2V 100011 = 7.0V 110011 = 7.0V
000100 = 13.2V 010100 = 10.0V 100100 = 7.0V 110100 = 7.0V
000101 = 13.0V 010101 = 9.8V 100101 = 7.0V 110101 = 7.0V
000110 = 12.8V 010110 = 9.6V 100110 = 7.0V 110110 = 7.0V
000111 = 12.6V 010111 = 9.4V 100111 = 7.0V 110111 = 7.0V
001000 = 12.4V 011000 = 9.2V 101000 = 7.0V 111000 = 7.0V
001001 = 12.2V 011001 = 9.0V 101001 = 7.0V 111001 = 7.0V
001010 = 12.0V 011010 = 8.8V 101010 = 7.0V 111010 = 7.0V
001011 = 11.8V 011011 = 8.6V 101011 = 7.0V 111011 = 7.0V
001100 = 11.6V 011100 = 8.4V 101100 = 7.0V 111100 = 7.0V
001101 = 11.4V 011101 = 8.2V 101101 = 7.0V 111101 = 7.0V
001110 = 11.2V 011110 = 8.0V 101110 = 7.0V 111110 = 7.0V
001111 = 11.0V 011111 = 7.8V 101111 = 7.0V 111111 = 7.0V
6 0 Not Used
7 0 Not Used
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Regulator Voltage Setting STBY Mode (0B’h – 0F’h)
This register is used to sets the output voltage of regulators 1 − 5 in STBY mode operation.
Table 12. Standby Registers
Register Name
STBY_ OUT1-5_REG
Standby DVC Registe rs
Address
OUT1 = 0x0B’h
OUT2 = 0x0C’h
OUT3 = 0x0D’h
OUT4 = 0x0E’h
OUT5 = 0x0F’h
Field bit R/W Default Description
SB_OUT[1-5] 5:0 R/W See Table 2
Output Voltage setting of OUT[1-5]
DVC from 3.3 V to 0.8V in -50mV steps
000000 = 3.30V 010000 = 2.50V 100000 = 1.70V 110000 = 0.90V
000001 = 3.25V 010001 = 2.45V 100001 = 1.65V 110001 = 0.85V
000010 = 3.20V 010010 = 2.40V 100010 = 1.60V 110010 = 0.80V
000011 = 3.15V 010011 = 2.35V 100011 = 1.55V 110011 = 0.80V
000100 = 3.10V 010100 = 2.30V 100100 = 1.50V 110100 = 0.80V
000101 = 3.05V 010101 = 2.25V 100101 = 1.45V 110101 = 0.80V
000110 = 3.00V 010110 = 2.20V 100110 = 1.40V 110110 = 0.80V
000111 = 2.95V 010111 = 2.15V 100111 = 1.35V 110111 = 0.80V
001000 = 2.90V 011000 = 2.10V 101000 = 1.30V 111000 = 0.80V
001001 = 2.85V 011001 = 2.05V 101001 = 1.25V 111001 = 0.80V
001010 = 2.80V 011010 = 2.00V 101010 = 1.20V 111010 = 0.80V
001011 = 2.75V 011011 = 1.95V 101011 = 1.15V 111011 = 0.80V
001100 = 2.70V 011100 = 1.90V 101100 = 1.10V 111100 = 0.80V
001101 = 2.65V 011101 = 1.85V 101101 = 1.05V 111101 = 0.80V
001110 = 2.60V 011110 = 1.80V 101110 = 1.00V 111110 = 0.80V
001111 = 2.55V 011111 = 1.75V 101111 = 0.95V 111111 = 0.80V
6 0 Not Used
7 0 Not Used
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Boost Regulator Output Volta g e Setting STBY Mode (10’h)
Sets output voltage of the boost regulator (OUT6) for STBY mode operation.
Table 13. Standby DVC Register for OUT6
Register Name STBY _OUT6_REG DVC Regis t ers
Address 0x10’h
Field bit R/W Default Description
SB_OUT6 5:0 R/W See Table 2
DVC from 14V to 7V in 200mV decrements
000000 = 14.0V 010000 = 10.8V 100000 = 7.6V 110000 = 7.0V
000001 = 13.8V 010001 = 10.6V 100001 = 7.4V 110001 = 7.0V
000010 = 13.6V 010010 = 10.4V 100010 = 7.2V 110010 = 7.0V
000011 = 13.4V 010011 = 10.2V 100011 = 7.0V 110011 = 7.0V
000100 = 13.2V 010100 = 10.0V 100100 = 7.0V 110100 = 7.0V
000101 = 13.0V 010101 = 9.8V 100101 = 7.0V 110101 = 7.0V
000110 = 12.8V 010110 = 9.6V 100110 = 7.0V 110110 = 7.0V
000111 = 12.6V 010111 = 9.4V 100111 = 7.0V 110111 = 7.0V
001000 = 12.4V 011000 = 9.2V 101000 = 7.0V 111000 = 7.0V
001001 = 12.2V 011001 = 9.0V 101001 = 7.0V 111001 = 7.0V
001010 = 12.0V 011010 = 8.8V 101010 = 7.0V 111010 = 7.0V
001011 = 11.8V 011011 = 8.6V 101011 = 7.0V 111011 = 7.0V
001100 = 11.6V 011100 = 8.4V 101100 = 7.0V 111100 = 7.0V
001101 = 11.4V 011101 = 8.2V 101101 = 7.0V 111101 = 7.0V
001110 = 11.2V 011110 = 8.0V 101110 = 7.0V 111110 = 7.0V
001111 = 11.0V 011111 = 7.8V 101111 = 7.0V 111111 = 7.0V
6 0 Not Used
7 0 Not Used
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Sequence Register (11’h)
Each regu lator can be ass igned to s tart in an y one of six seque ncing s lots (1 to 6 ). If starting in slo t 1, th e regul ator star ts
immediately. If starting in any other slot the regulator must wait for the PGOOD=1 flags of all regulators assigned to the
preceding slot and then wait for the specified delay time (register 17’h) i.e., all PGOODs in preceding state flag then the
delay timer is started and when delay completes the regulator is enabled.
Each regulator must delay its startup (after the appropriate preceding PGOOD flags) by the delay set in the Delay
Register (17’h), unless the regulator is assigned to sequence state 0.
If all default Enable bits = 0 the IC starts up, but no outputs are ena bled.
Sequencing is only used during initial startup, and not used when outputs are enabled via I²C command. If outputs are
enabled via I²C then soft-start is still active but start-up delays (timed from preceding PGOODs) are not.
Table 14. Sequence State 1 Register
Register Name SEQ1_REG Sequence Register
Address 0x11’h
Field bit R/W Default Description
REG1SQ1 0 R/W 0
0 = No Start 1 = Regulator 1 will Start in Sequence State 1
REG2SQ1 1 R/W 0
0 = No Start 1 = Regulator 2 will Start in Sequence State 1
REG3SQ1 2 R/W 0
0 = No Start 1 = Regulator 3 will Start in Sequence State 1
REG4SQ1 3 R/W 1
0 = No Start 1 = Regulator 4 will Start in Sequence State 1
REG5SQ1 4 R/W 0
0 = No Start 1 = Regulator 5 will Start in Sequence State 1
REG6SQ1 5 R/W 0
0 = No Start 1 = Regulator 6 will Start in Sequence State 1
6 R/W 0 Reserved
7 R/W 0 Reserved
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Table 15. Sequence State 2 Register
Register Name SEQ2_REG Sequence Register
Address 0x12’h
Field bit R/W Default Description
REG1SQ2 0 R/W 0
0 = No Start 1 = Regulator 1 will Start in Sequence State 2
REG2SQ2 1 R/W 1
0 = No Start 1 = Regulator 2 will Start in Sequence State 2
REG3SQ2 2 R/W 1
0 = No Start 1 = Regulator 3 will Start in Sequence State 2
REG4SQ2 3 R/W 0
0 = No Start 1 = Regulator 4 will Start in Sequence State 2
REG5SQ2 4 R/W 0
0 = No Start 1 = Regulator 5 will Start in Sequence State 2
REG6SQ2 5 R/W 0
0 = No Start 1 = Regulator 6 will Start in Sequence State 2
6 R/W 0 Reserved
7 R/W 0 Reserved
Table 16. Sequence State 3 Register
Register Name
SEQ3_REG
Sequence Register
Address 0x13’h
Field bit R/W Default Description
REG1SQ3 0 R/W 1
0 = No Start 1 = Regulator 1 will Start in Sequence State 3
REG2SQ3 1 R/W 0
0 = No Start 1 = Regulator 2 will Start in Sequence State 3
REG3SQ3 2 R/W 0
0 = No Start 1 = Regulator 3 will Start in Sequence State 3
REG4SQ3 3 R/W 0
0 = No Start 1 = Regulator 4 will Start in Sequence State 3
REG5SQ3 4 R/W 0
0 = No Start 1 = Regulator 5 will Start in Sequence State 3
REG6SQ3 5 R/W 0
0 = No Start 1 = Regulator 6 will Start in Sequence State 3
6 R/W 0 Reserved
7 R/W 0 Reserved
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Table 17. Sequence State 4 Register
Register Name SEQ4_REG Sequence Register
Address 0x14’h
Field bit R/W Default Description
REG1SQ4 0 R/W 0
0 = No Start 1 = Regulator 1 will Start in Sequence State 4
REG2SQ4 1 R/W 0
0 = No Start 1 = Regulator 2 will Start in Sequence State 4
REG3SQ4 2 R/W 0
0 = No Start 1 = Regulator 3 will Start in Sequence State 4
REG4SQ4 3 R/W 0
0 = No Start 1 = Regulator 4 will Start in Sequence State 4
REG5SQ4 4 R/W 1
0 = No Start 1 = Regulator 5 will Start in Sequence State 4
REG6SQ4 5 R/W 0
0 = No Start 1 = Regulator 6 will Start in Sequence State 4
6 R/W 0 Reserved
7 R/W 0 Reserved
Table 18. Sequence State 5 Register
Register Name
SEQ5_REG
Sequence Register
Address 0x15’h
Field bit R/W Default Description
REG1SQ5 0 R/W 0
0 = No Start 1 = Regulator 1 will Start in Sequence State 5
REG2SQ5 1 R/W 0
0 = No Start 1 = Regulator 2 will Start in Sequence State 5
REG3SQ5 2 R/W 0
0 = No Start 1 = Regulator 3 wil l Start in Sequenc e State 5
REG4SQ5 3 R/W 0
0 = No Start 1 = Regulator 4 will Start in Sequence State 5
REG5SQ5 4 R/W 0
0 = No Start 1 = Regulator 5 will Start in Sequence State 5
REG6SQ5 5 R/W 0
0 = No Start 1 = Regulator 6 will Start in Sequence State 5
6 R/W 0 Reserved
7 R/W 0 Reserved
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Table 19. Sequence State 6 Register
Register Name SEQ6_REG Sequence Register
Address 0x16’h
Field bit R/W Default Description
REG1SQ6 0 R/W 0
0 = No Start 1 = Regulator 1 will Start in Sequence State 6
REG2SQ6 1 R/W 0
0 = No Start 1 = Regulator 2 will Start in Sequence State 6
REG3SQ6 2 R/W 0
0 = No Start 1 = Regulator 3 will Start in Sequence State 6
REG4SQ6 3 R/W 0
0 = No Start 1 = Regulator 4 will Start in Sequence State 6
REG5SQ6 4 R/W 0
0 = No Start 1 = Regulator 5 will Start in Sequence State 6
REG6SQ6 5 R/W 1
0 = No Start 1 = Regulator 6 will Start in Sequence State 6
6 R/W 0 Reserved
7 R/W 0 Reserved
Delay Register (17’h)
The ST DEL r egister s ets the del a y bet ween poweri ng up of eac h regul ator at init i al po wer up (see Figur e 19). O nce all th e
internal power good registers PGOOD[1-6] are all “1”, then the global PG pin goes high without delay.
The PORDEL register sets the de lay for the POR flag pin. The POR delay time starts as soon as AVIN pin voltage rises
above the system UVLO upper threshold set by the PORUP register (21’h). The POR output goes low without delay if
AVIN falls below the lower UVLO threshold set by the PORDN register (22’h).
Table 20. Delay Register
Register Name
DELAY_CNTL_REG
Delay Register
Address 0x17’h
Field bit R/W Default Description
STDEL 2:0 R/W 001
(1ms)
Delay Time from 0ms to 7ms in 1ms increment
000 = 0ms 010 = 2ms 100 = 4ms 110 = 6ms
001 = 1ms 011 = 3ms 101 = 5ms 111 = 7ms
PORDEL 7:3 R/W 00011
(20ms)
Delay Time from 5ms to 160ms in 5ms increment
00000 = 5ms 01000 = 45ms 10000 = 85ms 11000 = 125ms
00001 = 10ms 01001 = 50ms 10001 = 90ms 11001 = 130ms
00010 = 15ms 01010 = 55ms 10010 = 95ms 11010 = 135ms
00011 = 20ms 01011 = 60ms 10011 = 100ms 11011 = 140ms
00100 = 25ms 01100 = 65ms 10100 = 105ms 11100 = 145ms
00101 = 30ms 01101 = 70ms 10101 = 110ms 11101 = 150ms
00110 = 35ms 01110 = 75ms 10110 = 115ms 11110 = 155ms
00111 = 40ms 01111 = 80ms 10111 = 120ms 11111 = 160ms
Micrel, Inc.
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Soft-Start Registers (18’h
−
1A’h)
When regulator(n) is turned on from either the Enable Register (04’h) in NORMAL mode or from the Standby Register
(03’h) in ST ANDBY m ode, then th e three R EG(n) SS sof t-start bits ar e used to cont rol both th e rising a nd fall ing ram p rate
of the outputs.
In NORMAL mode, the outputs are stepped from the current regulator voltage settings to a newly-programm ed regulator
voltage setting or to the default value.
On power -up, t he r e gu lat or vo lta ge outp ut is s et t o th e lo wes t pos s ible v olt age s et ting whic h is 3F ’h. The v olt age r e gu lator
will change by one step or increment at a time. The amount of time between each step is controlled by the soft-start
registers. Table 21 details the amount of time for each encoded soft-start value.
Table 21. Soft-Start Register Speed Settings
R/W Default Description
SS_SPEED = 0 R/W 000
Soft-Start Time from 4µs to 512µs
000 = 4µs 010 = 16µs 100 = 64µs 110 = 256µs
001 = 8µs 011 = 32µs 101 = 128µs 111 = 512µ s
SS_SPEED = 1 R/W 000
Soft-Start Time from 8µs to 1024µs
000 = 8µs 010 = 32µs 100 = 128µs 110 = 512µ s
001 = 16µs 011 = 64µs 101 = 256µs 111 = 1024µ s
Table 22. Soft-Start Register OUT1 and OUT2
Register Name SS1-2_REG Soft-Start Register for VOUT1 and VOUT2
Address 0x18’h
Field bit R/W Default Description
REG1SS 2:0 R/W 001
(8µs) OUT1 Soft-Start Time
See Table 19 for Soft-Start Settings
REG2SS 5:3 R/W 001
(8µs) OUT2 Soft-Start Time
See Table 19 for Soft-Start Settings
6 R/W 0 Reserved
SS_SPEED 7 R/W 0 Set the speed of the clock to slow or fast for different clock division, see Table 19.
0 = Slow Speed 1 = Fast Speed
Table 23. Soft-Start Register OUT3 and OUT4
Register Name SS3-4_REG Soft-Start Register for VOUT3 and VOUT4
Address 0x19’h
Field bit R/W Default Description
REG3SS 2:0 R/W 001
(8µs) OUT3 Soft-Start Time
See Table 19 for Soft-Start Settings
REG4SS 5:3 R/W 001
(8µs) OUT4 Soft-Start Time
See Table 19 for Soft-Start Settings
6 R/W 0 Reserved
7 R/W 0 Reserved
Micrel, Inc.
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Table 24. Soft-Start Register OUT5 and OUT6
Register Name SS5-6_REG Soft-Start Register for VOUT5 and VOUT6
Address 0x1A’h
Field bit R/W Default Description
REG5SS 2:0 R/W 001
(8µs) OUT5 Soft-Start Time
See Table 19 for Soft-Start Settings
REG6SS 5:3 R/W 010
(16µs) OUT6 Soft-Start Time
See Table 19 for Soft-Start Settings
6 R/W 0 Reserved
7 R/W 0 Reserved
Current-Limit (Normal Mode) Registers (1B’h
−
1D’h)
This register is use to set the current limit for each DC-to-DC regulator in normal mode operatio n.
Table 25. Current-Limit Register IOUT1 and IOUT2
Register Name ILIMIT_1-2_REG Current-Limit Register for VOUT1 and VOUT2
Address 0x1B’h
Field bit R/W Default Description
REG1CL 3:0 R/W 1001
(4.1A)
Normal current-limit for regulator 1 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
REG2CL 7:4 R/W 1001
(4.1A)
Normal current-limit for regulator 2 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
Micrel, Inc.
MIC7400
March
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Table 26. Current-Limit Register IOUT3 and IOUT4
Register Name ILIMIT_3-4_REG Current-Limit Register for VOUT3 and VOUT4
Address 0x1C’h
Field bit R/W Default Description
REG3CL 3:0 R/W 1001
(4.1A)
Normal current-limit for regulator 3 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
REG4CL 7:4 R/W 0101
(6.1A)
Normal current-limit for regulator 4 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
Table 27. Current-Limit Register IOUT 5 and IOUT6
Register Name ILIMIT_5-6_REG Current-Limit Register for VOUT5 and VOUT6
Address 0x1D’h
Field bit R/W Default Description
REG5CL 3:0 R/W 1001
(4.1A)
Normal current-limit for regulator 5 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
REG6CL 6:4 R/W 011
(2.24A)
Current limit from 2.6A to 1.78A in 0.12A dec rements
000 = 2.6A 010 = 2.36A 100 = 2.12A 110 = 1.88A
001 = 2.48A 011 = 2.24A 101 = 2.00A 111 = 1.76A
7 R/W 0 0 = Current Limit On 1 = Current Limit Off
Micrel, Inc.
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3, 2015 65 Revision 2.0
Current-Limit (STBY Mode) Reg isters (1E
−
20’h)
This register is used to set the current limit for each DC-to-DC regulator when in standby (STBY) mode operation.
Table 28. Standby Current-Limit Register IOUT1 and IOUT2
Register Name
STBY_ILIMIT_1-2_REG
Standby Current-Limit Register for V
OUT1
and V
OUT2
Address 0x1E’h
Field bit R/W Default Description
SB1CL 3:0 R/W 1001
(4.1A)
Standby current limit for regulator 1 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
SB2CL 7:4 R/W 1001
(4.1A)
Standby current limit for regulator 2 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
Table 29. Standby Current-Limit Register IOUT3 and IOUT4
Register Name STBY_ILIMIT_3-4_REG Standby Current-Limit Register for VOUT3 and VOUT4
Address 0x1F’h
Field bit R/W Default Description
SB3CL 3:0 R/W 1001
(4.1A)
Standby current limit for regulator 3 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
SB4CL 7:4 R/W 0101
(6.1A)
Standby current limit for regulator 4 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
Micrel, Inc.
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Table 30. Standby Current-Limit Register IOUT5 and IOUT6
Register Name STBY_ILIMIT_5-6_REG Standby Current-Limit Reg ister for VOUT5 and VOUT6
Address 0x20’h
Field bit R/W Default Description
SB5CL 3:0 R/W 1001
(4.1A)
Standby current limit for regulator 5 from 8.6A to 1.1A in 0.5A decrements
0000 = 8. 6A 0100 = 6.6A 1000 = 4.6A 1100 = 2.6 A
0001 = 8. 1A 0101 = 6.1A 1001 = 4.1A 1101 = 2.1A
0010 = 7.6A 0110 = 5.6A 1010 = 3.6A 1110 = 1.6A
0011 = 7.1A 0111 = 5.1A 1011 = 3.1A 1111 = 1.1A
SB6CL 6:4 R/W 011
(2.24A)
Current limit from 2.6A to 1.78A in 0.12A decrement s
000 = 2.6A 010 = 2.36A 100 = 2.12A 110 = 1.88A
001 = 2.48A 011 = 2.24A 101 = 2.00A 111 = 1.76A
7 R/W 0 0 = Current Limit On 1 = Current Limit Off
Power-on-Reset (POR) Threshold Voltage Setting Register (21’h and 22’h)
This register is used to set the rising and falling threshold of power-on-reset (POR) comparator. The POR threshold
voltage set ting is b ased on the l ogic level of the VSLT pin in addit ion to the re gister bits . Refer to T able 20 for PO R time
delay settings.
Table 31. Rising and Falling Power-on-Reset Threshold Voltage Settings
Rising and Falling Power-On-Reset Threshold Voltage Setting
bit R/W Default Description
VSCLT = 0 4:0 R/W 00000
3.3V to 2.3V in 50mV decrements
00000 = 3.25V 01000 = 2.85V 10000 = 2.45V 11000 = 2.25V
00001 = 3.20V 01001 = 2.80V 10001 = 2.40V 11001 = 2.25V
00010 = 3.15V 01010 = 2.75V 10010 = 2.35V 11010 = 2.25V
00011 = 3.10V 01011 = 2.70V 10011 = 2.30V 11011 = 2.25V
00100 = 3.05V 01100 = 2.65V 10100 = 2.25V 11100 = 2.25V
00101 = 3.00V 01101 = 2.60V 10101 = 2.25V 11101 = 2.25V
00110 = 2.95V 01110 = 2.55V 10110 = 2.25V 11110 = 2.25V
00111 = 2.90V 01111 = 2.50V 10111 = 2.25V 11111 = 2.25V
VSCLT = 1 4:0 R/W 00000
4.3V to 3.3V in 50mV decrements
00000 = 4.25V 01000 = 3.85V 10000 = 3.45V 11000 = 3.25V
00001 = 4.20V 01001 = 3.80V 10001 = 3.40V 11001 = 3.25V
00010 = 4.15V 01010 = 3.75V 10010 = 3.35V 11010 = 3.25V
00011 = 4.10V 01011 = 3.70V 10011 = 3.30V 11011 = 3.25V
00100 = 4.05V 01100 = 3.65V 10100 = 3.25V 11100 = 3.25V
00101 = 4.00V 01101 = 3.60V 10101 = 3.25V 11101 = 3.25V
00110 = 3.95V 01110 = 3.55V 10110 = 3.25V 11110 = 3.25V
00111 = 3.90V 01111 = 3.50V 10111 = 3.25V 11111 = 3.25V
The three mos t significant bits [7:5] in registers 21’h and 22’h are used to mask the output voltage power-good flag after
the start-up sequenced is finished.
Micrel, Inc.
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Table 32. Power-on-Reset Rising Threshold Voltage Setting Register (21’h)
Register Name PORUO_REG Power-on-Reset Falling Threshold
Address 0x21’h
Field bit R/W Default Description
PORUP 4:0 R/W 01011 (2.7V) See Table 28
PGOOD_MASK1 5 R/W 1 0 = Do not mask PGOOD1 1 = Mask PGOOD1
PGOOD_MASK2 6 R/W 1 0 = Do not mask PGOOD2 1 = Mask PGOOD2
PGOOD_MASK3 7 R/W 1 0 = Do not mask PGOOD3 1 = Mask PGOOD3
Table 33. Power-on-Reset Falling Threshold Voltage Setting Register (22’h)
Register Name PORDN_REG Power-on-Reset Falling Threshold
Address 0x22’h
Field bit R/W Default Description
PORDN 4:0 R/W 01101 (2.6V) See Table 28
PGOOD_MASK4 5 R/W 1 0 = Do not mask PGOOD4 1 = Mask PGOOD4
PGOOD_MASK5 6 R/W 1 0 = Do not mask PGOOD5 1 = Mask PGOOD5
PGOOD_MASK6 7 R/W 1 0 = Do not mask PGOOD6 1 = Mask PGOOD6
Pull-Down when Disabled Register (23’h)
This register is used to set the preference of enabling/disabling a pull-down FET when the DC-to-DC regulators are
disabled. The pull-down value for buck regulators 1 − 5 is 90Ω. The pull-down current value for the boost regulator 6 is
programmable.
Table 34. Pull-Down when Disabled Register
Register Name PULLDN1-6_REG Pull-Down when Disabled Register
Address 0x23’h
Field bit R/W Default Description
PULLD1 0 R/W 0 Enable/Disable the pull-down on Regulator 1 when power down
0 = No Pull Down 1 = Pull-Down
PULLD2 1 R/W 0 Enable/Disable the pull-down on Regulator 2 when power down
0 = No Pull-Down 1 = Pull-Down
PULLD3 2 R/W 0 Enable/Disable the pull-down on Regulator 3 when power-down
0 = No Pull-Down 1 = Pull Down
PULLD4 3 R/W 0 Enable/Disable the pull-down on Regulator 4 when power down
0 = No Pull-Down 1 = Pull-Down
PULLD5 4 R/W 0 Enable/Disable the pull-down on Regulator 5 when power-down
0 = No Pull-Down 1 = Pull-Down
PULLD6C 6:5 R/W 00 Sets Boost Pull-D ow n Current Lev el
00 = 148mA 01 = 111mA 10 = 74mA 11 = 37mA
PULLD6 7 R/W 0 Enable/Disable the pull-down on Regul ator 6 when power-down
0 = No P ull-Down 1 = Pull-Down
Micrel, Inc.
MIC7400
March
3, 2015 68 Revision 2.0
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