74VHC245MSCX - Fairchild Semiconductor

November 1992

Revised March 1999

74VHC245 Octal Bidi rectional Transceiver with 3-STATE Outputs

74VHC245

Octal Bidirectional Transceiver with 3-STATE Outputs

General Descript ion

The VHC 245 is an adva nced high speed C MOS oct al bus

transceiver fabricated with silicon gate CMOS technology.

It achieves high speed operation similar to equivalent Bipo-

lar Schottky TTL while maintaining the CMOS low power

dissipation . Th e V HC 24 5 is int ended for b idire cti on al asy n-

chronous com munic ation be tween dat a buss es. The dire c-

tion of data transmission is determined by the level of the

T/R input. The enable input can be used to disable the

device so that the busses are effectively isolated. All inputs

are equipped with protection circuits against static dis-

charge.

Features

■High Speed: tPD = 4.0 ns (typ) at VCC = 5V

■High Noise Immunity: VNIH = VNIL = 28% VCC (Min)

■Power Down Protection is provided on all inputs

■Low Noise: VOLP = 0.9V (typ)

■Low Power Dissipation:

ICC = 4 µA (Max) @ TA = 25°C

■Pin and Function Compatible with 74HC245

Ordering Code:

Surface m ount pac k ages are als o available on Ta pe and Reel. Specify by appending the suffix let te r “X” to the or dering code.

Logic Symbol

IEEE/IEC

Pin Description

Connection Diagram

Truth Table

H = HIGH Voltage Level L = LOW V oltage Level X = Immaterial

Any unused bus terminals during HIGH-Z State must be held HIGH or

LOW.

Order Number Package Number Package Description

74VHC245M M20B 20-Lead Small Outline Integrated Package (SOIC), JEDEC MS-013, 0.300” Wide

74VHC245SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHC245MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC245N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Description

Names

OE Output Enable Input

T/R Transmit/Receive Input

A0–A7Side A Inputs or 3-STATE Outputs

B0–B7Side B Inputs or 3-STATE Outputs

Inputs Outputs

OE T/R

L L Bus B Data to Bus A

L H Bus A Data to Bus B

HXHIGH-Z State

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74VHC245

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 2)

Note 1: Absolute Maximum Ratings are values beyond which the device

may be da maged or ha ve its useful li fe impaire d. The datab ook specific a-

tions should be met, without exception, to ensure that the system design is

reliable over its pow er supply, temperatur e, and output/inpu t loadin g vari-

ables. Fa irc hild does not recom mend operation out s ide databook sp ec if ic a-

tions.

Note 2: Unused inputs or I/O pins must be held HIGH or LOW. They may

not float.

DC Electrical Characteristics

Supply Voltage (VCC)−0.5V to +7.0V

DC In put Voltage (VIN) (T/R, OE)−0.5V to 7.0V

DC Output Voltage (VOUT)−0.5V to VCC + 0.5V

Input Diode Current (IIK) (T/ R, OE)−20 mA

Output Diode Current (IOK)±20 mA

DC Output Current (IOUT)±25 mA

DC VCC/GND Current (ICC)±75 mA

Storage Temperature (TSTG)−65°C to +150°C

Lead Temperature (TL)

(Soldering, 10 seconds) 260°C

Supply Voltage (VCC) 2.0V to 5.5V

Input Voltage (VIN)(T/R, OE)0V to 5.5V

Output Voltage (VOUT) 0V to VCC

Operating Temperature (TOPR)−40°C to +85°C

Input Rise and Fall Time (tr, tf)

VCC = 3.3V ± 0.3V 0 ∼ 100 ns/V

VCC = 5.0V ± 0.5V 0 ∼ 20 ns/V

Symbol Parameter VCC

(V)

TA = 25°CT

A = −40°C to +85°CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level 2.0 1.50 1.50 V

Input V oltag e 3.0 − 5.5 0.7 VCC 0.7 VCC

VIL LOW Level 2.0 0.50 0.50 V

Input V oltag e 3.0 − 5.5 0.3 VCC 0.3 VCC

VOH HIGH Level 2.0 1.9 2.0 1.9 VIN = VIH IOH = −50 µA

Output Voltage 3.0 2.9 3.0 2.9 V or VIL

4.5 4.4 4.5 4.4

3.0 2.58 2.48 VIOH = −4 mA

4.5 3.94 3.80 IOH = −8 mA

VOL LOW Level 2.0 0.0 0.1 0.1 VIN = VIH IOL = 50 µA

Output Voltage 3.0 0.0 0.1 0.1 V or VIL

4.5 0.0 0.1 0.1

3.0 0.36 0.44 VIOL = 4 mA

4.5 0.36 0.44 IOL = 8 mA

IOZ 3-STATE Output VIN = VCC or GND

Off-State Current 5.5 ±0.25 ±2.5 µAV

OUT = VCC or GND

VIN OE = VIH or VIL

IIN Input Leakage 0 − 5.5 ±0.1 ±1.0 µAV

IN = 5.5V or GND

(T/R, OE)Current

ICC Quiescent Supply Current 5.5 4.0 40.0 µAV

IN = VCC or GND

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74VHC245

Noise Characteri stics

Note 3: Paramete r guaranteed by des ign.

AC Electrical Characteristics

Note 4: Paramete r guaranteed by des ign. tOSLH = |tPLH max − tP LH min|; t OSHL = |tPHL max − tPHL min|

Note 5: CPD is defin ed as the value of th e internal e quivalent c apacitan ce w hic h is calcul at ed from the opera ti ng c urrent c ons umption w it ho ut load. Avera ge

operati ng c urrent ca n be obtained by the equation: ICC (opr.) = CPD * VCC * fIN + ICC/8 (per Bit).

Symbol Parameter VCC

(V)

TA = 25°CUnits Conditions

Typ Limits

VOLP Quiet Output Maximum 5.0 0.9 1.2 V CL = 50 pF

(Note 3) Dynamic VOL

VOLV Quiet Output Minimum 5.0 −0.9 −1.2 V CL = 50 pF

(Note 3) Dynamic VOL

VIHD Minimum HIGH Level 5.0 3.5 V CL = 50 pF

(Note 3) Dynamic Input Voltage

VILD Maximum LOW Level 5.0 1.5 V CL = 50 pF

(Note 3) Dynamic Input Voltage

Symbol Parameter VCC

(V)

TA = 25°CT

A = −40°C to +85°CUnits Conditions

Min Typ Max Min Max

tPLH Propagation Delay 3.3 ± 0.3 5.8 8.4 1.0 10.0 ns CL = 15 pF

tPHL Time 8.3 11.9 1.0 13.5 CL = 50 pF

5.0 ± 0.5 4.0 5.5 1.0 6.5 ns CL = 15 pF

5.5 7.5 1.0 8.5 CL = 50 pF

tPZL 3-STAT E Output 3.3 ± 0.3 8.5 13.2 1.0 15.5 ns RL = 1 kΩCL = 15 pF

tPZH Enable Time 11.0 16.7 1.0 19.0 CL = 50 pF

5.0 ± 0.5 5.8 8.5 1.0 10.0 ns CL = 15 pF

7.3 10.6 1.0 12.0 CL = 50 pF

tPLZ 3-STATE Output 3.3 ± 0.3 11.5 15.8 1.0 18.0 ns RL = 1 kΩCL = 50 pF

tPHZ Disable Time 5.0 ± 0.5 7.0 9.7 1.0 11.0 CL = 50 pF

tOSLH Output to Output 3.3 ± 0.3 1.5 1.5 ns (Note 4) CL = 50 pF

tOSHL Skew 5.0 ± 0.5 1.0 1.0 CL = 50 pF

CIN Input Capacitance 4 10 10 pF VCC = Open

(T/R, OE)

CI/O Output Capacitance 8 pF VCC = 5.0V

CPD Power Dissipation 21 pF (Note 5)

Capacitance

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74VHC245

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

Package Number M20B

20-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74VHC245

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Packag e Num be r MTC 20

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74VHC245 Octal Bidirecti onal Transceiver with 3-STATE Outputs

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent i n any compon ent of a life su pport

device or system whose failure to perform can be rea-

sonabl y ex pect ed to ca use the fa i lure of the life su pp ort

device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A