© 2002-2011 Microchip Technology Inc. DS21696H-page 1
MCP6541/1R/1U/2/3/4
Features:
• Low Quiescent Curren t: 600 nA/Comp ara tor (ty p.)
• Rail-to-Rail Input: VSS - 0.3V to VDD + 0.3V
• CMOS/TTL-Compatible Output
• Propagation Delay: 4 µs
(typical, 100 mV Overdrive)
• Wide Supply Voltage Range: 1.6V to 5.5V
• Available in Single, Dual and Quad
• Single Available in SOT-23-5, SC-70-5 * Packages
• Chip Select (CS) with MCP6543
• Low Swi tching Cur rent
• Internal Hysteresis: 3.3 mV (typ.)
• Temperature Ranges:
- Industrial: -40°C to +85°C
- Extended: -40°C to +125°C
Typi cal Application s:
• Laptop Computers
• Mobile Phones
• Metering Systems
• Hand-held Electronics
• RC Timers
• Alarm and Monitoring Circuits
• Windowed Comparators
• Multivibrators
Related Devices:
• Open-Drain Output: MCP6546/7/8/9
Description:
The Microchip Technology Inc. MCP6541/1R/1U/2/3/4
family of comparators is offered in single (MCP6541,
MCP6541R , MCP654 1U), sin gle with Ch ip Selec t (CS)
(MCP6543), dual (MCP6542) and quad (MCP6544)
configu r ati ons . T he outp uts a re p ush-pull (C MOS/TTL-
compatible) and are capable of driving heavy DC or
capacitive loads.
These comparators are optimized for low-power,
single-supply operation with greater than rail-to-rail
input operation. The push-pull output of the
MCP6541/1R/1U/2/3/4 family supports rail-to-rail out-
put swing and interfaces with TTL/CMOS logic. The
internal input hysteresis eliminates output switching
due to internal input noise voltage, reducing current
draw. The output limits supply current surges and
dynamic power consumption while switching. This
produ ct fam ily op erates with a s ingle -suppl y vol t age a s
low as 1.6V and draws less than 1 µA/comparator of
quiescent current.
The related MCP6546/7/8/9 family of comparators from
Microchip has an open-drain output. Used with a pull-
up resis tor, these d evice s can b e used as le vel-shi f ters
for any desired voltage up to 10V and in wired-OR
logic.
* SC-70-5 E-Temp part s not avai lab le at this rele as e of
the data sheet.
MCP6541U SOT-23-5 is E-Temp only.
Package Types
VINA+
VIN–
MCP6541
VSS
VDD
OUT
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
PDIP, SOIC, MSOP
4
1
2
3
-
+
5
SOT-23-5
VDD
OUT
VIN+
VSS
VIN–
MCP6542
VINA+
VINA–
VSS
1
2
3
4
8
7
6
5
-
OUTA
+-
+
VDD
OUTB
VINB–
VINB+
VIN+
VIN–
MCP6543
VSS
VDD
OUT
1
2
3
4
8
7
6
5
-
+
NC
CS
NC
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP
MCP6544
VINA+
VINA–
VSS
1
2
3
4
14
13
12
11
-
OUTA
+-
+
VDD
OUTD
VIND–
VIND+
10
9
8
5
6
7
OUTB
VINB–
VINB+V
INC+
VINC-
OUTC
+
--
+
PDIP, SOIC, TSSOP
-
+
MCP6541R
4
1
2
3
5
SC-70-5, SOT-23-5
VSS
VIN+
VIN–
VDD
OUT
MCP6541U
-
+
4
1
2
3
-
+
5
VSS
OUT
VIN+
VDD
VIN–
MCP6541
SC-70-5, SOT-23-5
Push-Pu ll Ou tput Sub-Microamp Comparators
MCP6541/1R/1U/2/3/4
DS21696H-page 2 © 2002-2011 Microchip Technology Inc.
NOTES:
© 2002-2011 Microchip Technology Inc. DS21696H-page 3
MCP6541/1R/1U/2/3/4
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD - VSS .........................................................................7.0V
Current at Analog Input Pin (VIN+, VIN-.........................±2 mA
Analog Input (VIN) ††.................. ....VSS - 1.0V to VDD + 1.0V
All other Inputs and Outputs........... VSS - 0.3V to VDD + 0.3V
Difference Input Voltage ....................................... |VDD - VSS|
Output Sh o rt-Circu it Cu rrent ........ ....... .......... .......Conti n u o us
Current at Input Pins ....................................................±2 mA
Current at Output and Supply Pins ............................±30 mA
Storage Temperature ....................................-65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD Protection on all Pins (HBM;MM) ..................4 kV; 400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current
Limits”
DC CHARACTERISTICS
Electrical S pecific ations: U nless oth erwise in dicat ed, VDD = +1.6V to + 5.5V, VSS = GND, TA = +25°C,VIN+ = V DD/2,
VIN– = VSS, and RL= 100 kΩ to VDD/2 (Refer to Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Power Supply
Supply Voltage VDD 1.6 — 5.5 V
Quiescent Current per comparator IQ0.3 0.6 1.0 µA IOUT = 0
Input
Input Voltage Range VCMR VSS−0.3 — VDD+0.3 V
Common Mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 5.3V
Common Mode Rejection Ratio CMRR 50 65 — dB VDD = 5V, VCM = 2.5V to 5.3V
Common Mode Rejection Ratio CMRR 55 70 — dB VDD = 5V, VCM = -0.3V to 2.5V
Power Supply Rejection Ratio PSRR 63 80 — dB VCM = VSS
Input Offset Voltage VOS -7.0 ±1.5 +7.0 mV VCM = VSS (Note 1)
Drift with Temperature ΔVOS/ΔTA— ±3 — µV/°C TA = -40°C to +125°C, VCM = VSS
Input Hysteresis Volt age VHYST 1.5 3.3 6.5 mV VCM = VSS (Note 1)
Linear Temp. Co. (Note 2)TC1— 6.7—µV/°CT
A = -40°C to +125°C, VCM = VSS
Quadratic Temp. Co. (Note 2)TC2— -0.035 — µV/°C2TA = -40°C to +125°C, VCM = VSS
Input Bias Current IB—1—pAV
CM = VSS
At Te m perat ure (I-Temp parts) IB— 25 100 pA TA = +85°C, VCM = VSS (Note 3)
At Te m perat ure (E-Temp parts) IB— 1200 5000 pA TA = +125°C, VCM = VSS (Note 3)
Input Offset Current IOS — ±1 — pA VCM = VSS
Common Mode Input Impedance ZCM —10
13||4 — Ω||pF
Differential Input Impedance ZDIFF —10
13||2 — Ω||pF
Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = VHYST + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
3: Input bias current at temperature is not tested for SC-70-5 package.
4: Limit the output current to Absolute Maximum Rating of 30 mA.
MCP6541/1R/1U/2/3/4
DS21696H-page 4 © 2002-2011 Microchip Technology Inc.
AC CHARACTERISTICS
Push-Pull Output
High-Level Output Voltage VOH VDD−0.2 — — V IOUT = -2 mA, VDD = 5V
Low-Level Output Voltage VOL ——V
SS+0.2 V IOUT = 2 mA, VDD = 5V
Short-Circuit Current ISC — -2.5, +1.5 — mA VDD = 1.6V (Note 4)
ISC —±30—mAV
DD = 5.5V (Note 4)
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C,
VIN+ = VDD/2, Step = 200 mV, Overdrive = 100 mV, and CL = 36 pF (Refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Rise Time tR—0.85— µs
Fall Time tF—0.85— µs
Propagation Delay (High-to-Low) tPHL —4 8µs
Propagation Delay (Low-to-High) tPLH —4 8µs
Propagation Delay Skew tPDS —±0.2— µs(Note 1)
Maximum Toggle Frequency fMAX —160—kHzV
DD = 1.6V
fMAX —120—kHzV
DD = 5.5V
Input Noise Voltage Eni —200—µV
P-P 10 Hz to 100 kHz
Note 1: Propagation Delay Skew is defined as: tPDS = tPLH - tPHL.
DC CHARACTERISTICS (CONTINUE D)
Electrical S pecifi cations: U nless oth erwise in dicat ed, VDD = +1.6V to + 5.5V, VSS = GND, TA = +25°C,VIN+ = V DD/2,
VIN– = VSS, and RL= 100 kΩ to VDD/2 (Refer to Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Note 1: The input offset voltage is the center (average) of the input-referred trip points. The input hysteresis is the difference
between the input-referred trip points.
2: VHYST at different temperatures is estimated using VHYST (TA) = VHYST + (TA - 25°C) TC1 + (TA - 25°C)2 TC2.
3: Input bias current at temperature is not tested for SC-70-5 package.
4: Limit the output current to Absolute Maximum Rating of 30 mA.
© 2002-2011 Microchip Technology Inc. DS21696H-page 5
MCP6541/1R/1U/2/3/4
FIGURE 1-1: Timing Diagram for the CS
Pin on the MCP6543. FIGURE 1-2: Propagation Delay Timing
Diagram.
MCP6543 CHIP SELECT (CS) CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ =
VDD/2, VIN– = VSS, and CL= 36 pF (Refer to Figures 1-1 and 1-3).
Parameters Sym Min Typ Max Unit s Conditions
CS Low Specifications
CS Log ic Thresh old, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —5.0—pACS = VSS
CS High Specifications
CS Log ic Thresh old, High VIH 0.8 VD
D—V
DD V
CS Input Current, High ICSH —1—pACS = VDD
CS Input High, VDD Current IDD —18—pACS = VDD
CS Input High, GND Current ISS — –20 — pA CS = VDD
Comparator Output Leakage IO(LEAK) —1—pAV
OUT = VDD, CS = VDD
CS Dynamic Specifications
CS Low to Comparator Output
Low Turn-on Time tON —250msCS = 0.2 VDD to VOUT = VDD/2,
VIN– = VDD
CS High to Comp a rato r Outp ut
High Z Turn-off Time tOFF —10—µsCS = 0.8 VDD to VOUT = VDD/2,
VIN– = VDD
CS Hysteresis VCS_HYS
T—0.6— VV
DD = 5V
VIL
Hi-Z
tON
VIH
CS
tOFF
VOUT
-20 pA (typ.)
Hi-Z
ISS
ICS 1pA (typ.) 1pA (typ.)
-20 pA (typ.)
-0.6 µA (typ.)
VOL
tPLH
VOUT
VIN–100 mV
100 mV tPHL
VOL
VIN+ = VDD/2
VOH
MCP6541/1R/1U/2/3/4
DS21696H-page 6 © 2002-2011 Microchip Technology Inc.
TEMP ERATURE CHARACTERISTICS
1.1 Test Circuit Configuration
This test circuit configuration is used to determine the
AC and DC speci fic ati on s.
FIGURE 1-3: AC and DC Test Circuit for
the Push-Pull Output Comparators.
Electrical Specifications: Unless otherwise indicated, VDD = +1.6V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specified Temperature Range TA-40 — +85 °C
Operati ng Tempe ratu r e Range TA-40 — +125 °C Note
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SC-70 θJA —331—°C/W
Thermal Resistance, 5L-SOT-23 θJA —220.7—°C/W
Thermal Resistance, 8L-PDIP θJA — 89.3 — °C/W
Thermal Resistance, 8L-SOIC θJA —149.5—°C/W
Thermal Resistance, 8L-MSOP θJA —211—°C/W
Thermal Resistance, 14L-PDIP θJA —70—°C/W
Thermal Resistance, 14L-SOIC θJA —95.3—°C/W
Thermal Resistance, 14L-TSSOP θJA —100—°C/W
Note: The MCP6541/1R/1U/2/3/4 I-Temp parts operate over this extended temperature range, but with reduced
performance. In any case, the Junction Temperature (TJ) must not exceed the Absolute Maximum
specification of +150°C.
VDD
VSS = 0V
200 kΩ
200 kΩ
200 kΩ
200 kΩ
VOUT
VIN = VSS
36 pF
MCP654X
© 2002-2011 Microchip Technology Inc. DS21696H-page 7
MCP6541/1R/1U/2/3/4
2.0 TYPICAL PE RFORMANCE CURVES
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA = +25°C, VIN+ = VDD/2, VIN– = GND,
RL = 100 kΩ to VDD/2, and CL = 36 pF.
FIGURE 2-1: Input Offset Voltage at
VCM =V
SS.
FIGURE 2-2: Input Offset Voltage Drift at
VCM =V
SS.
FIGURE 2-3: The MCP 6541 /1R/ 1U/2/ 3/4
Comparators Show No Phase Reversal.
FIGURE 2-4: Input Hysteresis Voltage at
VCM =V
SS.
FIGURE 2-5: Input Hysteresis Voltage
Linear Temp. Co. (TC1) at VCM =V
SS.
FIGURE 2-6: Input Hysteresis Voltage
Quadratic Temp. Co. (TC2) at VCM =V
SS.
Note: The gra phs and tab les prov ided fo llow ing this note are a sta tistic al sum mary b ased on a limit ed numb er of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
-7-6-5-4-3-2-101234567
Input Offset Voltage (mV)
Percentage of Occurrences
1200 Samples
VCM = VSS
0%
2%
4%
6%
8%
10%
12%
14%
16%
-14
-12
-10
-8
-6
-4
-2
0
2
4
6
8
10
12
14
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
1200 Samples
VCM = VSS
TA= -40°C to +125°C
-1
0
1
2
3
4
5
6
7
012345678910
Time (1 ms/div)
Inverting Input, Output Voltage
(V)
VOUT
VIN–
VDD = 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
1.6 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0
Input Hysteresis Vol tage (mV)
Percentage of Occurrences
1200 Samples
VCM = VSS
0%
5%
10%
15%
20%
25%
4.6
5.0
5.4
5.8
6.2
6.6
7.0
7.4
7.8
8.2
8.6
9.0
9.4
Input Hysteresi s V oltag e –
Linear Temp. Co.; TC1 (µV/°C)
Percentage of Occurrences
596 Samples
VCM = VSS
TA = -40°C to +125°C
VDD = 1.6VVDD = 5.5V
0%
2%
4%
6%
8%
10%
12%
14%
16%
18%
20%
-0.060
-0.056
-0.052
-0.048
-0.044
-0.040
-0.036
-0.032
-0.028
-0.024
-0.020
-0.016
Input Hysteresi s V oltag e –
Quadratic Temp. Co.; TC2 (µV/°C2)
Percentage of Occurrences
596 Samples
VCM = VSS
TA = -40°C to +125°C
VDD = 5.5V
VDD = 1.6V
MCP6541/1R/1U/2/3/4
DS21696H-page 8 © 2002-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V
IN+=V
DD/2, VIN– = GND,
RL=100kΩ to VDD/2, and CL=36pF.
FIGURE 2-7: Input Offset Voltage vs.
Ambient Temperature at VCM =V
SS.
FIGURE 2-8: Input Offset Voltage vs.
Common Mode Input Voltage at VDD =1.6V.
FIGURE 2-9: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
FIGURE 2-10: Input Hysteresis Voltage vs.
Ambient Temperature at VCM =V
SS.
FIGURE 2-11: Input Hysteresis Voltage vs.
Common Mode Input Voltage at VDD =1.6V.
FIGURE 2-12: Input Hysteresis Voltage vs.
Common Mode Input Voltage at VDD =5.5V.
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
-50-250 255075100125
Ambie nt Tem peratu re (°C)
Input Offset Voltage (mV)
VDD = 1.6V
VDD = 5.5V
VCM = VSS
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Common Mode Input Voltage (V)
Input Offset Voltage (mV)
VDD = 1.6V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +12 5°C
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (mV)
VDD = 5.5V
TA = +85°C
TA = +125°C
TA = -40°C
TA = +25°C
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
6.5
-50 -25 0 25 50 75 100 125
Am b i en t Te mper atu r e (°C)
Input Hysteresis Voltage (mV)
VDD = 1.6V
VDD = 5.5V
VCM = VSS
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
Common Mode Input Voltage (V)
Input Hysteresis Voltage (mV)
TA = -4 0°C
TA = +125°C
TA = +85°C
TA = +25°C
VDD = 1.6V
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Hysteresis Voltage (mV)
VDD = 5.5V TA = +12 5°C
TA = +85 °C
TA = +25 °C
TA = -40°C
© 2002-2011 Microchip Technology Inc. DS21696H-page 9
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V
IN+=V
DD/2, VIN– = GND,
RL=100kΩ to VDD/2, and CL=36pF.
FIGURE 2-13: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-14: Input Bias Current, Input
Offset Current vs. Ambient Temperature.
FIGURE 2-15: Quiescent Current vs.
Common Mode Input Voltage at VDD =1.6V.
FIGURE 2-16: Input Bias Current, Input
Offset Current vs. Common Mode Input Vo ltage.
FIGURE 2-17: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-18: Quiescent Current vs.
Common Mode Input Voltage at VDD =5.5V.
55
60
65
70
75
80
85
90
-50-250 255075100125
Ambient Temperature (°C)
CMRR, PSRR (dB)
Input Referred
PSRR, VIN+ = VSS, VDD = 1.6V to 5.5V
CMRR, VIN+ = -0.3 to 5.3V, VDD = 5.0V
0.1
1
10
100
1000
55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
IB
| IOS |
VDD = 5.5V
VCM = VDD
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.00.20.40.60.81.01.21.41.6
Common Mode Input Voltage (V)
Quiescent Current
per comparator (µA)
VDD = 1.6V
Sweep VIN+, VIN– = VDD/2
Sweep VIN–, VIN+ = VDD/2
0.1
1
10
100
1000
10000
0.00.51.01.52.02.53.03.54.04.55.05.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents (A)
VDD = 5.5V
100f
100p
1p
10p
1n
10n IB, TA = +125°C
IB, TA = +85°C
IOS, TA = +125°C
IOS, TA = +85°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Quiescent Current
per Comparator (µA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -4 0°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.00.51.01.52.02.53.03.54.04.55.05.5
Common Mode Input Voltage (V)
Quiescent Current
per Comparator (µA)
VDD = 5.5V
Sweep VIN+, VIN– = VDD/2
Sweep VIN–, VIN+ = VDD/2
MCP6541/1R/1U/2/3/4
DS21696H-page 10 © 2002-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V
IN+=V
DD/2, VIN– = GND,
RL=100kΩ to VDD/2, and CL=36pF.
FIGURE 2-19: Supply Current vs. Toggle
Frequency.
FIGURE 2-20: Output Voltage Headroom
vs. Output Current at VDD =1.6V.
FIGURE 2-21: High-to-Low Propagation
Delay.
FIGURE 2-22: Output Short Circuit Current
Magnitude vs. Power Supply Voltage.
FIGURE 2-23: Output Voltage Headroom
vs. Output Current at VDD =5.5V.
FIGURE 2-24: Low-to-High Propagation
Delay.
0.1
1
10
0.1 1 10 100
Toggle Frequency (kHz)
Supply Current (µA)
VDD = 5.5V
VDD = 1.6V
100 mV Overdrive
VCM = VDD/2
RL = infinity
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.00.51.01.52.02.53.0
Output Current (mA)
Output Voltage Headroom (V)
VDD = 1.6V
VOL–VSS:
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
VDD–VOH:
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
012345678
High-to-Low Propagation Delay (µs)
Percentage of Occurrences
600 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 5.5VVDD = 1.6V
0
5
10
15
20
25
30
35
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Output Short Circuit Current
Magnitude (mA)
TA = -4 0°C
TA = +25°C
TA = +85°C
TA= +125°C
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 5 10 15 20 25
Output Current (mA)
Output Voltage Headroom (V)
VDD = 5.5V
TA = +12 5°C
TA = +85 °C
TA = +25 °C
TA = -40°C
VDD – VOH:
TA= +125 °C
TA= +85° C
TA= +25° C
TA = -40°C
VOL – VSS:
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
012345678
Low-to-High Propagation Delay (µs )
Percentage of Occurrences
600 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 5.5VVDD = 1.6V
© 2002-2011 Microchip Technology Inc. DS21696H-page 11
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V
IN+=V
DD/2, VIN– = GND,
RL=100kΩ to VDD/2, and CL=36pF.
FIGURE 2-25: Propagation Delay Skew.
FIGURE 2-26: Propagation Delay vs.
Power Supply Voltage.
FIGURE 2-27: Propagation Delay vs.
Common Mode Input Voltage at VDD =1.6V.
FIGURE 2-28: Propagation Delay vs.
Ambient Temperatu re .
FIGURE 2-29: Propagation Delay vs. Input
Overdrive.
FIGURE 2-30: Propagation Delay vs.
Common Mode Input Voltage at VDD =5.5V.
0%
5%
10%
15%
20%
25%
30%
35%
40%
45%
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0
Propagation Delay Skew (µs)
Percentage of Occurrences
600 Samples
100 mV Overdrive
VCM = VDD/2
VDD = 1.6V
VDD = 5.5V
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Propagation Delay (µs)
VCM = VDD/2
tPLH @ 100 mV Overdrive
tPHL @ 100 mV Overdrive
tPLH @ 10 mV Overdrive
tPHL @ 10 mV Overdrive
0
1
2
3
4
5
6
7
8
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Common Mode Input Voltage (V)
Propagation Delay (µs)
VDD = 1.6V
100 mV Overdrive
tPLH
tPHL
0
1
2
3
4
5
6
7
8
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Propagation Delay (µs)
100 mV Overdrive
VCM = VDD/2
tPLH @ VDD = 1.6V tPHL @ VDD = 1.6V
tPLH @ VDD = 5.5V tPHL @ VDD = 5.5V
1
10
100
1 10 100 1000
Input Overdrive (mV)
Propagation Delay (µs)
VCM = VDD/2
tPHL @ VDD = 5.5V
tPLH @ VDD = 1.6V
tPHL @ VDD = 1.6V
tPLH @ VDD = 5.5V
0
1
2
3
4
5
6
7
8
0.00.51.01.52.02.53.03.54.04.55.05.5
Common Mode Input Voltage (V)
Propagation Delay (µs)
VDD = 5.5V
100 mV Overdrive
tPHL
tPLH
MCP6541/1R/1U/2/3/4
DS21696H-page 12 © 2002-2011 Microchip Technology Inc.
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V
IN+=V
DD/2, VIN– = GND,
RL=100kΩ to VDD/2, and CL=36pF.
FIGURE 2-31: Propagation Delay vs. Load
Capacitance.
FIGURE 2-32: Supply Cur rent (shoot
through current) vs. Chip Select (CS) Voltage at
VDD = 1.6V (MCP6543 only).
FIGURE 2-33: Supply Cur rent (char gi ng
current) vs. Chip Select (CS) pulse at VDD =1.6V
(MCP6543 only).
FIGURE 2-34: Chip Select (CS) Step
Response (MCP6543 only).
FIGURE 2-35: Supply Current (shoot
through current) vs. Chip Select (CS) Vo ltage at
VDD = 5.5V (MCP6543 only).
FIGURE 2-36: Supply Current (charging
current) vs. Chip Select (CS) pulse at VDD =5.5V
(MCP6543 only).
0
5
10
15
20
25
30
35
40
45
50
0 102030405060708090
Load Capacitanc e (nF)
Propagation Delay (µs)
100 mV Overdrive
VCM = VDD/2
tPHL @ VDD = 1.6V
tPLH @ VDD = 1.6V
tPLH @ VDD = 5.5V
tPHL @ VDD = 5.5V
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6
Chip Select (CS) Voltage (V)
Supply Current
per Comparator (A)
Comparato
r
Shuts Of
f
Comparator
Turns On
VDD = 1.6V
CS Hysteresis
CS
High-to-Low CS
Low-to-High
1m
1µ
10µ
100n
1n
10n
100p
10p
100µ
0
5
10
15
20
25
30
01234567891011121314
Time (1 ms/div)
Supply Current (µA)
-8.1
-6.5
-4.9
-3.2
-1.6
0.0
1.6
Output Voltage,
Chip Select Voltage (V),
Start-up
IDD
Charging output
capacitance
VDD = 1.6V
VOUT
CS
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
012345678910
Time (ms)
Chip Select, Output Voltage (V)
VOUT
VDD = 5.5V
CS
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
0.00.51.01.52.02.53.03.54.04.55.05.5
Chip Select (CS) Voltage (V)
Supply Current
per Comparator (A)
Comparato
r
Shuts Of
f
Comparator
Turns On
VDD = 5.5V
1m
1µ
10µ
100n
1n
10n
100p
10p
CS
Low-to-High
CS
Hysteresis CS
High-to-Low
100µ
0
20
40
60
80
100
120
140
160
180
200
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Time (0.5 ms/div)
Supply Current
per Comparator (µA)
-24
-21
-18
-15
-12
-9
-6
-3
0
3
6
Output Voltage,
Chip Select Voltage (V)
Start-up IDD
Charging output
capacitance
VDD = 5.5V
VOUT CS
© 2002-2011 Microchip Technology Inc. DS21696H-page 13
MCP6541/1R/1U/2/3/4
Note: Unless otherwise indicated, VDD = +1.6V to +5.5V, VSS = GND, TA=+25°C, V
IN+=V
DD/2, VIN– = GND,
RL=100kΩ to VDD/2, and CL=36pF.
FIGURE 2-37: Input Bias Current vs. Input
Voltage.
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
MCP6541/1R/1U/2/3/4
DS21696H-page 14 © 2002-2011 Microchip Technology Inc.
NOTES:
© 2002-2011 Microchip Technology Inc. DS21696H-page 15
MCP6541/1R/1U/2/3/4
3.0 PIN DESCRIPTIONS
Descrip tions of the pins are listed in Table 3-1.
3.1 Analog Inputs
The comparator non-inverting and inverting inputs are
high-impedance CMOS inputs with low bias currents.
3.2 CS Digital Input
This i s a CMO S, Schmitt-tri ggered i nput that places the
part into a low-power mode of operation.
3.3 Digital Outputs
The comparator outputs are CMOS, push-pull digital
outputs. They are designed to be compatible with
CMOS and TTL logic and are capable of driving heavy
DC or capacitive loads.
3.4 Power Supply (VSS and VDD)
The positive power supply pin (VDD) is 1.6V to 5.5V
higher than the negative power supply pin (VSS). For
normal operation, the other pins are at voltages
between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need a local bypass capacitor (typically 0.01 µF to
0.1µF) within 2mm of the V
DD pi n. These c an s hare a
bulk capacitor with nearby analog parts (within
100 mm), but it is not required.
TABLE 3-1: PIN FUNCTION TABLE
MCP6541
PDIP,
SOIC,
MSOP
MCP6541
SOT-23-5,
SC-70-5
MCP6541R
MCP6541U
SOT-23-5
SC-70-5
MCP6542
MCP6543
MCP6544
Symbol Description
6 1 1 4 1 6 1 OUT, OUTA Digital Output (comparator A)
2443222V
IN–, VINA– Inverting Input (comparator A)
3331333V
IN+, VINA+ Non-i nverti ng Inpu t (com p ar ator A)
7525874V
DD Positive Power Supply
————5—5V
INB+ Non-inverting Inpu t (comp ar ator B)
————6—6V
INB– Inverting Input (comparator B)
— — — — 7 — 7 OUTB Digital Output (comparator B)
— — — — — — 8 OUTC Digital Output (comparator C)
——————9V
INC– Inverting Input (comparator C)
——————10V
INC+ Non-inverting Inpu t (comp ar ator C )
42524411V
SS Negative Power Supply
——————12V
IND+ Non-inverting Inpu t (comp ar ator D )
——————13V
IND– Inverting Input (comparator D)
— — — — — — 14 OUTD Digital Output (comparator D)
—————8—CS
Chip Select
1, 5, 8 — — — — 1, 5 — NC No Internal Connection
MCP6541/1R/1U/2/3/4
DS21696H-page 16 © 2002-2011 Microchip Technology Inc.
NOTES:
© 2002-2011 Microchip Technology Inc. DS21696H-page 17
MCP6541/1R/1U/2/3/4
4.0 APPLICATIONS INFORMATION
The MCP6541/1R/1U/2/3/4 family of push-pull output
comp arator s are fabri cated on Microch ip’s state -of-the-
art CMOS process. They are suitable for a wide range
of applications requiring very low-power consumption.
4.1 Comparator Inputs
4.1.1 PHASE REVERSAL
The MCP6541/1R/1U/2/3/4 comparator family uses
CMOS transistors at the input. They are designed to
prevent phase inversion when the input pins exceed
the supp ly v oltag es. Figure 2-3 shows an input vol t age
exceeding both supplies with no resulting phase
inversion.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
prote ct the inpu t t r ansis tors , and to m in im ize i npu t bia s
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass ESD
events within the specifie d lim it s .
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these amplifiers, t he circuit s they are in must limit the
currents (and voltages) at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electrical Characteristics”). Figure 4-3
shows the recommen ded ap proach to protectin g t hes e
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2, limit the possible current drawn
out of the input pin. Diodes D1 and D2 prevent the inp ut
pin (VIN+ and VIN–) from going too far above VDD.
When imp lemented as sho wn, resistors R1 and R2 als o
limit the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is a lso pos sible to c onnect th e diodes to the left o f the
resistors R1 and R2. In this case, the currents through
the diodes D1 and D2 need to be limited by some other
mechanism. The resistor then serves as in-rush current
limiter; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when th e c om mo n mo de v ol tage (VCM) is bel ow
ground (VSS); see Figure 2-37. Applications that are
high-impedance may need to limit the usable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of this family of devices uses two
differential input stages in parallel: one operates at low
input vo ltages and the o ther at high input vo ltages. With
this topology, the input voltage is 0.3V above VDD and
0.3V below VSS. Therefore, the input offset voltage is
measure d at both VSS - 0.3V a nd VDD + 0.3V to ensu re
proper operation.
The MCP6541/1R/1U/2/3/4 family has internally-set
hysteresis that is small enough to maintain input offset
accurac y (<7 mV) and larg e enough to elimin ate output
chatteri ng caus ed by th e comp arat or’s own inp ut nois e
voltage (200 µVp-p). Figure 4-3 depicts this behavior.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN–
V1MCP654X
R1
VDD
D1
R2
≥
VSS – (minimum expected V2)
2mA
VOUT
V2R2R3
D2
+
–
R1
≥
VSS – (minimum expected V1)
2mA
MCP6541/1R/1U/2/3/4
DS21696H-page 18 © 2002-2011 Microchip Technology Inc.
FIGURE 4-3: The MCP 6541 /1R/ 1U/2/ 3/4
comparators’ internal hy steresis eliminates
output chatter caused by input noise voltage.
4.2 Push-Pull Output
The push-pull out put is designed to be compatible with
CMOS and TTL logic, while the output transistors are
configured to give rail-to-r ail output perfor mance. They
are driven with circuitry that minimizes any switching
current (shoot-through current from supply-to-supply)
when the output is transitioned from high-to-low , or from
low-to-high (see Figures 2-15,2-18, and 2-32 —2-36
for more information).
4.3 MCP6543 Chip Select (CS)
The MCP6543 is a single comparator with Chip Select
(CS). When CS is pulled high, the total current
consumption drops to 20 pA (typ.); 1 pA (typ.) flows
through the CS pin, 1 pA (typ.) flows through the out -
put pin and 18 pA (typ.) flow s through the VDD pin, as
shown in Figure 1-1. When this happens, the
comparator output is put into a high-impedance state.
By pulling CS low , the comparator is enabled. If the CS
pin is left floating, the comparator will not operate
properly. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
The internal CS circuitry is designed to minimize
gli tches wh en c ycli ng t he CS pin. This helps conserve
power , which is especially important in battery-powered
applications.
4.4 Externally Set Hysteresi s
Greater flexibility in selecting hysteresis (or input trip
points) is achieved by using external resistors.
Input off set vo ltag e (VOS) is the cen ter (ave rage) of th e
(input-referred) low-high and high-low trip points. Input
hysteresis voltage (VHYST) is the difference between
the same trip points. Hysteresis reduces output
chattering when one input is slowly moving past the
other and thus reduces dynamic supply cu rrent. It also
helps in systems where it is best not to cycle between
states too frequently (e.g., air conditioner thermostatic
control).
4.4.1 NON-INVERTING CIRCUIT
Figure 4-4 shows a non-inverting circuit for single-
supply applications using just two resistors. The
resulting hysteresis diagram is shown in Figure 4-5.
FIGURE 4-4: Non-inverting Circuit with
Hysteresis for Single-supply.
FIGURE 4-5: Hysteresis Diagram for the
Non-In verting Circuit.
The trip points for Figures 4-4 and 4-5 are:
EQUATION 4-1:
-3
-2
-1
0
1
2
3
4
5
6
7
8
Time (100 ms/div)
Output Voltage (V)
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
Input Voltage (10 mV/ div)
VOUT
VIN–
VDD = 5.0V
Hysteresis
VREF
VIN
VOUT
MCP654X
VDD
R1RF
+
-
VOUT
High-to-Low Low-to-High
VDD
VOH
VOL
VSS
VSS VDD
VTHL VTLH
VIN
VTLH VREF 1R1
RF
-------+
⎝⎠
⎜⎟
⎛⎞
VOL
R1
RF
-------
⎝⎠
⎜⎟
⎛⎞
–=
VTHL VREF 1R1
RF
-------+
⎝⎠
⎜⎟
⎛⎞
VOH
R1
RF
-------
⎝⎠
⎜⎟
⎛⎞
–=
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
© 2002-2011 Microchip Technology Inc. DS21696H-page 19
MCP6541/1R/1U/2/3/4
4.4.2 INVERTING CIRCUIT
Figure 4-6 shows an inverting circuit for single-supply
using three resistors. The resulting hysteresis diagram
is shown in Figure 4-7.
FIGURE 4-6: Inverting Circuit With
Hysteresis.
FIGURE 4-7: Hysteresis Diagram for the
Inverting Circuit.
In order to d ete rmi ne the trip v oltage s (VTHL and VTLH)
for the circuit shown in Figure 4-6, R2 and R3 can be
simplified to the Thevenin equivalent circuit with
respect to VDD, as shown in Figure 4-8.
FIGURE 4-8: Theven in Equ ival ent Cir c uit .
Where:
Using this simplified circuit, the trip voltage can be
calculated using the following equation:
EQUATION 4-2:
Figure 2-20 and Figure 2-23 can be used to determine
typical values for VOH and VOL.
4.5 Bypass Capacitor s
With this family of comparators, the power supply pin
(VDD for single supply) should have a local bypass
capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm for good
edge rate performance.
4.6 Capacitive Loads
Reasonable capacitive loads (e.g., logic gates) have
little impact on propagation delay (see Figure 2-31).
The supply current increases with increasing toggle
frequency (Figure 2-19), especially with higher
capacitive loads.
4.7 Battery Life
In order to maximize battery life in portable
applications, use large resistors and small capacitive
loads. Avoid toggling the output more than necessary.
Do not use Chip Select (CS) frequently to conserve
start-up power. Capacitive loads will draw additional
power at start-up.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
PCB (Printed Circuit Board) surface leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
betwee n nearby traces i s 1012Ω. A 5V dif ference would
cause 5 pA of current to flow. This is greater than the
MCP6541/1R/1U/2/3/4 family’s bias current at 25°C
(1 pA, typ.).
VIN VOUT
MCP654X
VDD
R2
RF
R3
VDD
VOUT
High-to-LowLow-to-High
VDD
VOH
VOL
VSS
VSS VDD
VTLH VTHL
VIN
V23
VOUT
MCP654X
VDD
R23 RF
+
-
VSS
R23 R2R3
R2R3
+
-------------------=
V23 R3
R2R3
+
------------------- V DD
×
=
VTHL VOH R23
R23 RF
+
-----------------------
⎝⎠
⎜⎟
⎛⎞
V23 RF
R23 RF
+
----------------------
⎝⎠
⎛⎞
+=
VTLH VOL R23
R23 RF
+
-----------------------
⎝⎠
⎜⎟
⎛⎞
V23 RF
R23 RF
+
----------------------
⎝⎠
⎛⎞
+=
VTLH = trip voltage from low-to-high
VTHL = trip voltage from high-to-low
MCP6541/1R/1U/2/3/4
DS21696H-page 20 © 2002-2011 Microchip Technology Inc.
The easiest way to reduce surface leakage is to use a
guard ring around se ns itiv e p ins (or t rac es). The gua rd
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-9.
FIGURE 4-9: Example Guard Ring Layout
for Inverting Circuit.
1. Inverting Configuration (Figures 4-6 and 4-9):
a.Connect the guard ring to the non-inverting
input pin (VIN+). This biases the guard ring
to the same reference voltage as the
comparator (e.g., VDD/2 or ground).
b.Connect the inverting pin (VIN–) to the input
pad without touching the guard ring.
2. Non-inverting Configuration (Figure 4-4):
a.Connect the non-inverting pin (VIN+) to the
input pad without touching the guard ring.
b.Connect the guard ring to the inverting input
pin (VIN–).
4.9 Unused Comparators
An unused amplifier in a quad package (MCP6544)
should be configured as shown in Figure 4-10. This
circuit prevents the output from toggling and causing
crosstalk. It uses the minimum number of components
and draws minimal current (see Figure 2-15 and
Figure 2-18).
FIGURE 4-10: Unused Comparators.
4.10 Typical Applications
4.10.1 PRECISE COMPARATOR
Some applications require higher DC precision. An
easy way to solve this problem is to use an amplifier
(such as the MCP6041) to gain-up the input signal
before it re aches the comp arator . Figure 4-11 sh ows an
example of this approach.
FIGURE 4-11: Precise Inverting
Comparator.
4.10.2 WINDOWED COMPARATOR
Figure 4-12 shows one approach to designing a win-
dowed comparator. The AND gate produces a logic ‘1’
when th e input vo ltage is betwe en VRB and VRT (where
VRT > VRB).
FIGURE 4-12: Windowed Comparator.
4.10.3 ASTABLE MULTIVIBRATOR
A simple astable multivibrator design is shown in
Figure 4-13. VREF needs to be between the power
supplies (VSS = GND and VDD) to achieve oscillation.
The output duty cycle changes with VREF.
FIGURE 4-13: Astable Multivibrator.
Guard Ring
VSS
VIN-V
IN+
¼ MCP6544
VDD
–
+
VREF
VDD
VDD
R1R2VOUT
VIN
VREF
MCP6041
MCP654X
VRT
MCP6542
VRB
VIN
1/2
MCP6542
1/2
MCP6541
VDD
R1R2
R3
VREF
C1
VOUT
© 2002-2011 Microchip Technology Inc. DS21696H-page 21
MCP6541/1R/1U/2/3/4
5.0 PACKAGING INFORMATION
5.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) (MCP6541, MCP6542, MCP6543, MCP6544) Example:
8-Lead SOIC (150 mil) (MCP6541, MCP6542, MCP6543, MCP6544) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6541
I/P256
1146
MCP6542
I/SN1146
256
8-Lead MSOP (MCP6541, MCP6542, MCP6543)Example:
XXXXXX
YWWNNN 6543I
146256
5-Lead SOT-23 (MCP6541, MCP6541R, MCP6541U) Example:
XXNN AB25
5-Lead SC-70 (MCP6541, MCP6541U)Example:
XXNN Front)
YWW (Back) BA25 Front)
146 (Back)
Device I-Temp
Code E-Temp
Code
MCP6541 ABNN GTNN
MCP6541R AGNN GUNN
MCP6541U — ATNN
Note: Applies to 5-Lead SOT-23
Device I-Te mp Code E-Temp
Code
MCP6541T-I/LT ABNN Note 2
MCP6541UT-I/LT BANN Note 2
Note 1: I-Temp parts prior to March 2005 are
marked “BAN ”
2: SC-70-5 E-Temp parts not available
at this release of this data sheet.
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the eve nt the full Micro chip p art num ber can not be ma rke d on one li ne, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
MCP6541
E/P^^256
1146
MCP6541E
SN^^1146
256
OR
OR
3
e
3
e
6543E
146256
OR
MCP6541/1R/1U/2/3/4
DS21696H-page 22 © 2002-2011 Microchip Technology Inc.
Package Marking Information (Continue d)
14-Lead PDIP (300 mil) (MCP6544) Example:
14-Lead TSSOP (MCP6544) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXX
YYWW
NNN
MCP6544-I/P
114656
MCP6544I
1146
256
MCP6544E/P
1146256
OR
3
e
MCP6544
I/P
1146256
OR
3
e
14-Lead SOIC (150 mil) (MCP6544) Example:
XXXXXXXXXX
YYWWNNN
XXXXXXXXXX MCP6544ISL
1146256
MCP6544
1146256
I/SL^^
OR
3
e
OR
MCP6544
1146256
E/SL^^
3
e
MCP6544E
1146
256
OR
© 2002-2011 Microchip Technology Inc. DS21696H-page 23
MCP6541/1R/1U/2/3/4
D
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1
23
E1
E
45
ee
c
L
A1
AA2
MCP6541/1R/1U/2/3/4
DS21696H-page 24 © 2002-2011 Microchip Technology Inc.
© 2002-2011 Microchip Technology Inc. DS21696H-page 25
MCP6541/1R/1U/2/3/4
!
φ
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A
A1
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L
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MCP6541/1R/1U/2/3/4
DS21696H-page 26 © 2002-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2002-2011 Microchip Technology Inc. DS21696H-page 27
MCP6541/1R/1U/2/3/4
"#$%!&'#$
N
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NOTE 1
D
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A
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A2
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b1
b
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c
MCP6541/1R/1U/2/3/4
DS21696H-page 28 © 2002-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2002-2011 Microchip Technology Inc. DS21696H-page 29
MCP6541/1R/1U/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6541/1R/1U/2/3/4
DS21696H-page 30 © 2002-2011 Microchip Technology Inc.
"%()!*+&'$
© 2002-2011 Microchip Technology Inc. DS21696H-page 31
MCP6541/1R/1U/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6541/1R/1U/2/3/4
DS21696H-page 32 © 2002-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2002-2011 Microchip Technology Inc. DS21696H-page 33
MCP6541/1R/1U/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6541/1R/1U/2/3/4
DS21696H-page 34 © 2002-2011 Microchip Technology Inc.
,-#$%!&'#$
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be
© 2002-2011 Microchip Technology Inc. DS21696H-page 35
MCP6541/1R/1U/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6541/1R/1U/2/3/4
DS21696H-page 36 © 2002-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2002-2011 Microchip Technology Inc. DS21696H-page 37
MCP6541/1R/1U/2/3/4
MCP6541/1R/1U/2/3/4
DS21696H-page 38 © 2002-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2002-2011 Microchip Technology Inc. DS21696H-page 39
MCP6541/1R/1U/2/3/4
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP6541/1R/1U/2/3/4
DS21696H-page 40 © 2002-2011 Microchip Technology Inc.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
© 2002-2011 Microchip Technology Inc. DS21696H-page 41
MCP6541/1R/1U/2/3/4
APPENDIX A: REVISION HISTORY
Revision H (December 2011)
The following is the list of modifications:
1. Updated Package Types drawings to correctly
show the device representation for the SC-70
package.
1. Updated package’ s temperatures in the Temper-
ature Characteristics table.
2. Corrected the marking information table for the
5-Lead SC-70 package (MCP6541 and
MCP6541U ) in Section 5.1 “Package Marking
Information”.
3. Updated package outline drawings in
Section 5.1 “Package Marking Information”
to show all views for each package.
4. Minor editorial changes.
Revision G (March 2011)
The following is the list of modifications:
1. Updated the marking information for the 5-Lead
SC-70 package in Section 5.1 “Package
Marking Information”.
Revision F (September 2007)
1. Corrected polarity of MCP6541U SOT-23-5 pin
out diagram on front page.
2. Section 5.0 “Packaging Information”:
Updated package outline drawings per
MarCom.
Revision E (September 2006)
The following is the list of modifications:
1. Added MCP6541U pinout for the SOT-23-5
package.
2. Clarified Absolute Maximum Analog Input
Voltage and Current Specifications.
3. Added applications write-ups on unused
comparators.
4. Added disclaimer to package outline drawings.
Revision D (May 2006)
The following is the list of modifications:
1. Added E-temp parts.
2. Changed VHYST temperature specification to
linear and quadratic temperature coefficients.
3. Changed specifications and plots for E-Temp.
4. Added section 3.0 “Pin Desc ription s”.
5. Corrected package marking (See Section 5.1
“Package Marking Information”).
6. Added Appendix A: “Revision History”.
Revision C (September 2003)
• Undocumented changes.
Revision B (November 2002)
• Undocumented changes.
Revision A (March 2002)
• Original Rel ease of this Do cument .
MCP6541/1R/1U/2/3/4
DS21696H-page 42 © 2002-2011 Microchip Technology Inc.
NOTES:
© 2002-2011 Microchip Technology Inc. DS21696H-page 43
MCP6541/1R/1U/2/3/4
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6541: Single Comparator
MCP6541 T: S ingl e Compara tor (Ta pe and Ree l)
(SC-70, SOT-23, SOIC, MSOP)
MCP 6541RT: Single Comparator (Rot ated - Tape and
Reel) (SOT-23 only)
MCP6541 U T: Si ngle Com para tor (Ta pe and Reel )
(SC-70, SO T-23; SOT-23-5 is E-Temp
only)
MCP6542: Dual Comparator
MCP6542T: Dual Comparator
(Tape and Reel for SOIC and MSOP)
MCP6543: Single Comparator with CS
MCP6543T: Single Com para tor wi th CS
(Tape and Reel for SOIC and MSOP)
MCP6544: Quad Comparator
MCP6544T: Quad Comparator
(Tape and Reel for SOIC and TSSOP)
Temperature Range: I = -40°C to +85°C
E * = -40°C to +125°C
* SC-70-5 E-Temp parts not available at this release of the
data sheet.
Package: LT = Plastic Package (SC-70), 5-lead
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil Body), 8-lead, 14-lead
SN = Plastic SOIC (150 mil Body), 8-lead
SL = Plastic SOIC (150 mil Body), 14-lead (MCP6544)
ST = Plastic TSSOP (4.4mm Body), 14-lead (MCP6544)
PART NO. -X /XX
PackageTemperature
Range
Device
Examples:
a) MCP6541T-I/LT: Tape and Reel,
Industrial Temperature,
5LD SC-70.
b) MCP6541T-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT-23.
c) MCP6541-I/MS: Tape and Reel,
Industrial Temperature,
8LD MSOP.
d) MCP65 41- E /P : Extend ed Tem per atu re ,
8LD PDIP.
e) MCP65 41- E /SN : Extend ed Temper atu re ,
8LD SOIC.
f) MCP6541RT-I/OT: Tape and Reel,
Industrial Temperature,
5LD SOT23.
g) MCP6541UT-E/LT: Tape and Reel,
Industrial Temperature,
5LD SC-70
h) MCP6541U T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT23.
a) MCP6542-I/MS: Industrial Temperature,
8LD MSOP.
b) MCP6542T-I/MS: Tape and Reel,
Industrial Temperature,
8LD MSOP.
c) MCP6542-I/P: Industrial Temperature,
8LD PDIP.
d) MCP65 42- E /SN : Extend ed Temper atu re ,
8LD SOIC.
a) MCP6543-I/SN: Industrial Temperature,
8LD SOIC.
b) MCP6543T-I/SN: Tape and Reel,
Industrial Temperature,
8LD SOIC.
c) MCP6543-I/P: Industrial Temperature,
8LD PDIP.
d) MCP65 43- E /SN : Extend ed Temper atu re ,
8LD SOIC.
a) MCP6544T-I/SL: Tape and Reel,
Industrial Temperature,
14LD SOIC.
b) MCP6544T-E/SL: Tape and Reel,
Extend ed Tem per atu re ,
14LD SOIC.
c) MCP6544-I/P: Industrial Temperature,
14LD PDIP.
d) MCP6544T-E/ST: Tape and Reel,
Extend ed Tem per atu re ,
14LD TSSOP.
MCP6541/1R/1U/2/3/4
DS21696H-page 44 © 2002-2011 Microchip Technology Inc.
NOTES:
© 2002-2011 Microchip Technology Inc. DS21696H-page 45
Information contained in this publication regarding device
applications a nd the lik e is provided only f or yo ur convenience
and may be supers ed ed by u pda t es . It is y our responsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI CSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Em bedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, To tal Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2002-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-921-2
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure famili es of its kind on t he market t oday, when used i n t he
intended manner and under normal conditions.
• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Mill ennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21696H-page 46 © 2002-2011 Microchip Technology Inc.
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11/29/11
