(R) OPA OPA4650 465 OPA 0 DEMO BOARD AVAILABLE 465 0 Wideband, Low Power, Quad Voltage Feedback OPERATIONAL AMPLIFIER FEATURES DESCRIPTION LOW POWER: 50mW/channel The OPA4650 is a quad, low power, wideband voltage feedback operational amplifier. It features a high bandwidth of 360MHz as well as a 12-bit settling time of only 20ns. The low input bias current allows its use in high speed integrator applications, while the wide bandwidth and true differential input stage make it suitable for use in a variety of active filter applications. Its low distortion gives exceptional performance for telecommunications, medical imaging and video applications. UNITY GAIN STABLE BANDWIDTH: 360MHz FAST SETTLING TIME: 20ns to 0.01% LOW INPUT BIAS CURRENT: 5A DIFFERENTIAL GAIN/PHASE ERROR: 0.01%/0.025 14-PIN DIP and SO-14 SURFACE MOUNT PACKAGES AVAILABLE APPLICATIONS HIGH RESOLUTION VIDEO MONITOR PREAMPLIFIER CCD IMAGING AMPLIFIER ULTRASOUND SIGNAL PROCESSING ADC/DAC BUFFER AMPLIFIER The OPA4650 is internally compensated for unitygain stability. This amplifier has a fully symmetrical differential input due to its "classical" operational amplifier circuit architecture. Its unusual combination of speed, accuracy and low power make it an outstanding choice for many portable, multi-channel and other high speed applications, where power is at a premium. The OPA4650 is also available in single (OPA650) and dual (OPA2650) configurations. ACTIVE FILTERS HIGH SPEED INTEGRATORS DIFFERENTIAL AMPLIFIER +VS Non-Inverting Input Output Stage Inverting Input Current Mirror Output CC -VS Simplified Schematic 1 of 4 Channels International Airport Industrial Park * Mailing Address: PO Box 11400, Tucson, AZ 85734 * Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 * Tel: (520) 746-1111 * Twx: 910-952-1111 Internet: http://www.burr-brown.com/ * FAXLine: (800) 548-6133 (US/Canada Only) * Cable: BBRCORP * Telex: 066-6491 * FAX: (520) 889-1510 * Immediate Product Info: (800) 548-6132 (c) 1994 Burr-Brown Corporation SBOS044 PDS-1267B Printed in U.S.A. July, 1995 SPECIFICATIONS At TA = +25C, VS = 5V, RL = 100, and RFB = 402, unless otherwise noted. RFB = 25 for a gain of +1. OPA4650P, U PARAMETER CONDITIONS FREQUENCY RESPONSE Closed-Loop Bandwidth(1) Gain Bandwidth Product Slew Rate(2) Over Specified Temperature Rise Time Fall Time Settling Time 0.01% 0.1% 1% Spurious Free Dynamic Range Differential Gain Differential Phase Bandwidth for 0.1dB Flatness Crosstalk OFFSET VOLTAGE Input Offset Voltage Average Drift Power Supply Rejection (+VS) (-VS) INPUT BIAS CURRENT Input Bias Current Over Temperature Input Offset Current Over Temperature MIN G = +1 G = +2 G = +5 G = +10 G = +1, 2V Step 0.2V Step 0.2V Step G = +1, 2V Step G = +1, 2V Step G = +1, 2V Step G = +1, f = 5.0 MHz, VO = 2Vp-p RL = 100 RL = 402 G = +2, NTSC, VO = 1.4Vp, RL = 150 G = +2, NTSC, VO = 1.4Vp, RL = 150 G = +2 Input Referred, 5MHz, all hostile Input Referred, 5MHz, Channel-to-Channel Output Current, Sourcing Over Temperature Range Output Current, Sinking Over Temperature Range Short-Circuit Current Output Resistance POWER SUPPLY Specified Operating Voltage Operating Voltage Range Quiescent Current Over Specified Temperature 360 120 35 16 160 240 220 1 1 20 10.3 7.9 MHz MHz MHz MHz MHz V/s V/s ns ns ns ns ns 68 74 0.01 0.025 21 -63 -66 dBc dBc % Degrees MHz dB dB mV V/C dB dB VCM = 0V 5 VCM = 0V 0.5 20 30 1.0 3.0 A A A A |VS | = 4.5V to 5.5V 60 47 VCM = 0.5V 2.2 65 INPUT IMPEDANCE Differential Common-Mode OUTPUT Voltage Output Over Specified Temperature UNITS 5.5 RS = 10k RS = 50 OPEN-LOOP GAIN Open-Loop Voltage Gain Over Specified Temperature MAX 1 3 76 52 INPUT NOISE Input Voltage Noise Noise Density, f = 100Hz f = 10kHz f = 1MHz f = 1MHz to 100MHz Integrated Noise, BW = 10Hz to 100MHz Input Bias Current Noise Current Noise Density, f = 0.1MHz to 100MHz Noise Figure (NF) INPUT VOLTAGE RANGE Common-Mode Input Range Over Specified Temperature Common-Mode Rejection TYP 43 9.4 8.4 8.4 84 nV/Hz nV/Hz nV/Hz nV/Hz Vp-p 1.2 pA/Hz 4.0 19.5 dBm dBm 2.8 90 V V dB 15 || 1 16 || 1 k || pF M || pF VO = 2V, RL = 100 VO = 2V, RL = 100 45 43 51 dB dB No Load RL = 250 RL = 100 2.2 2.2 2.0 75 65 65 35 3.0 2.5 2.3 110 V V V mA mA mA mA mA 150 0.08 0.1MHz, G = +1 4.5 All Channels TEMPERATURE RANGE Specification: P, U Thermal Resistance, JA P U 85 5 23 -40 5.5 32 35 +85 75 75 V V mA mA C C/W C/W NOTES: (1) Frequency response can be strongly influenced by PC board parasites. The OPA4650 is nominally compensated assuming 2pF parasitic load. The demonstration board, DEM-OPA465xP, shows a low parasitic layout for this part. (2) Slew rate is rate of change from 10% to 90% of output voltage step. (R) OPA4650 2 ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Total Supply Voltage Across Device ................................................... 11V Internal Power Dissipation ........................... See Thermal Considerations Differential Input Voltage .................................................................. 2.7V Common-Mode Input Voltage Range .................................................. VS Storage Temperature Range: P, U, .............................. -40C to +125C Lead Temperature (soldering, 10s) .............................................. +300C (soldering, SOIC 3s) ....................................... +260C Junction Temperature (TJ ) ............................................................ +175C PRODUCT PACKAGE PACKAGE DRAWING NUMBER(1) OPA4650U OPA4650P SO-14 Surface Mount 14-Pin Plastic DIP 235 010 NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix C of Burr-Brown IC Data Book. ORDERING INFORMATION PIN CONFIGURATION Top View DIP/SO-14 Output 1 1 14 Output 4 -Input 1 2 13 -Input 4 +Input 1 3 12 +Input 4 +VS 4 11 -VS +Input 2 5 10 +Input 3 -Input 2 6 9 -Input 3 Output 2 7 8 Output 3 PRODUCT PACKAGE TEMPERATURE RANGE OPA4650U OPA4650P SO-14 Surface Mount 14-Pin Plastic DIP -40C to +85C -40C to +85C ELECTROSTATIC DISCHARGE SENSITIVITY Electrostatic discharge can cause damage ranging from performance degradation to complete device failure. Burr-Brown Corporation recommends that all integrated circuits be handled and stored using appropriate ESD protection methods. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet published specifications. (R) 3 OPA4650 TYPICAL PERFORMANCE CURVES At TA = +25C, VS = 5V, RL = 100, and RFB = 402, unless otherwise noted. RFB = 25 for a gain of +1. COMMON-MODE REJECTION vs INPUT COMMON-MODE VOLTAGE AOL, PSR AND CMRR vs TEMPERATURE 110 AOL, PSR and CMRR (dB) Common-Mode Rejection (dB) 100 90 80 70 100 90 CMRR 80 PSR+ 70 PSR- 60 AOL 50 60 -4 -3 -2 -1 0 1 2 3 -50 4 -25 0 Common-Mode Voltage (V) INPUT BIAS CURRENT AND OFFSET VOLTAGE vs TEMPERATURE 1 5 0 Supply Current (mA) 6 Offset Voltage (mV) Input Bias Current (mA) VOS 50 75 20 -50 100 -25 0 25 50 75 Temperature (C) Temperature (C) OUTPUT CURRENT vs TEMPERATURE INPUT VOLTAGE AND CURRENT NOISE vs FREQUENCY 100 100 Input Current Noise (pA/Hz) 65 I+ O 60 IO- Input Voltage Noise (nV/Hz) 70 Output Current (mA) 22 IQ -1 25 125 24 IB 0 75 26 2 -25 50 SUPPLY CURRENT vs TEMPERATURE 7 4 -50 25 Temperature (C) Voltage Noise 10 Non-inverting and Inverting Current Noise 1 55 -50 -25 0 25 50 75 100 100 (R) OPA4650 1k 10k Frequency (Hz) Temperature (C) 4 100k 1M TYPICAL PERFORMANCE CURVES (CONT) At TA = +25C, VS = 5V, RL = 100, and RFB = 402, unless otherwise noted. RFB = 25 for a gain of +1. RECOMMENDED ISOLATION RESISTANCE vs CAPACITIVE LOAD SMALL SIGNAL TRANSIENT RESPONSE (G = +1) 40 200 120 30 Output Voltage (mV) Isolation Resistance, RISO () 160 25 20 RISO OPA4650 10 CL 80 40 0 -40 -80 -120 1k -160 0 -200 0 20 40 60 80 100 Time (5ns/div) Capacitive Load, C (pF) L LARGE SIGNAL TRANSIENT RESPONSE (G = +1) CLOSED-LOOP BANDWIDTH (G = +1) 6 2.0 1.6 0.8 0 Gain (dB) Output Voltage (V) SO-14/DIP Bandwidth = 360MHz 3 1.2 0.4 0 -0.4 -3 -6 -0.8 -1.2 -9 -1.6 -12 -2.0 1M Time (5ns/div) 10M 100M 1G Frequency (Hz) CLOSED-LOOP BANDWIDTH (G = +5) CLOSED-LOOP BANDWIDTH (G = +2) 21 12 SO-14/DIP Bandwidth = 120MHz 9 17 Gain (dB) Gain (dB) SO-14/DIP Bandwidth = 35MHz 14 6 3 0 11 8 -3 5 -6 2 -1 -9 1M 10M 100M 1M 1G 10M 100M 1G Frequency (Hz) Frequency (Hz) (R) 5 OPA4650 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25C, VS = 5V, RL = 100, and RFB = 402, unless otherwise noted. RFB = 25 for a gain of +1. OPEN-LOOP GAIN AND PHASE vs FREQUENCY CLOSED-LOOP BANDWIDTH (G = +10) 60 SO-14/DIP Bandwidth = 16MHz 23 +45 50 40 17 Gain (dB) Gain (dB) 0 Gain 20 14 11 -45 Phase 30 Phase () 26 -90 20 -135 10 -180 8 5 2 0 1M 10M 100M 1k 1G 10k Frequency (Hz) HARMONIC DISTORTION vs FREQUENCY (G = +1, VO = 2Vp-p) 100M 1G HARMONIC DISTORTION vs TEMPERATURE (fO = 5MHz, G = +1, VO = 2Vp-p) -50 Harmonic Distortion (dB) -50 Harmonic Distortion (dBc) 100k 1M 10M Frequency (Hz) -60 -70 3fO -80 2fO -90 100k 1M 10M -60 3fO -70 2fO -80 -90 -50 100M -25 0 25 50 Frequency (Hz) Temperature (C) 5MHz HARMONIC DISTORTION vs OUTPUT SWING 10MHz HARMONIC DISTORTION vs OUTPUT SWING -60 75 100 -50 Harmonic Distortion (dBc) Harmonic Distortion (dBc) G = +2 -70 -80 3fO 2fO -90 -100 -60 3fO 2fO -70 -80 -90 0.1 1 10 0.1 Output Swing (Vp-p) (R) OPA4650 1 Output Swing (Vp-p) 6 10 TYPICAL PERFORMANCE CURVES (CONT) At TA = +25C, VS = 5V, RL = 100, and RFB = 402, unless otherwise noted. RFB = 25 for a gain of +1. HARMONIC DISTORTION vs GAIN (fO = 5MHz, VO = 2Vp-p) Harmonic Distortion (dBc) 40 50 3fO 2fO 60 70 80 1 2 3 4 5 6 7 8 9 10 Non-Inverting Gain (V/V) (R) 7 OPA4650 DISCUSSION OF PERFORMANCE the package pins. Surface mount feedback resistors directly adjacent to the output and inverting input pins work well for the quad pinout. Other network components, such as noninverting input termination resistors, should also be placed close to the package. Even with a low parasitic capacitance shunting the resistor, excessively high resistor values can create significant time constants and degrade performance. Good metal film or surface mount resistors have approximately 0.2pF in shunt with the resistor. For resistor values > 1.5k, this adds a pole and/or zero below 500MHz that can affect circuit operation. Keep resistor values as low as possible consistent with output loading considerations. The 402 feedback used for the Typical Performance Plots is a good starting point for design. Note that a 25 feedback resistor, rather than a direct short, is suggested for a unity gain follower. This effectively reduces the Q of what would otherwise be a parasitic inductance (the feedback wire) into the parasitic capacitance at the inverting input. d) Connections to other wideband devices on the board may be made with short direct traces or through on-board transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50 to 100 mils) should be used, preferably with ground and power planes opened up around them. Estimate the total capacitive load and set RISO from the plot of recommended RISO vs capacitive load. Low parasitic loads may not need an RISO since the OPA4650 is nominally compensated to operate with a 2pF parasitic load. The OPA4650 is a quad low power, wideband voltage feedback operational amplifier. Each channel is internally compensated to provide unity gain stability. The OPA4650's voltage feedback architecture features true differential and fully symmetrical inputs. This minimizes offset errors, making the OPA4650 well suited for implementing filter and instrumentation designs. As a quad operational amplifier, OPA4650 is an ideal choice for designs requiring multiple channels where reduction of board space, power dissipation and cost are critical. Its ac performance is optimized to provide a gain bandwidth product of 160MHz and a fast 0.1% settling time of 10.3ns, which is an important consideration in high speed data conversion applications. Along with its excellent settling characteristics, the low dc input offset of 1mV and drift of 3V/C support high accuracy requirements. In applications requiring a higher slew rate and wider bandwidth, such as video and high bit rate digital communications, consider the quad current feedback OPA4658. CIRCUIT LAYOUT AND BASIC OPERATION Achieving optimum performance with a high frequency amplifier like the OPA4650 requires careful attention to layout parasitics and selection of external components. Recommendations for PC board layout and component selection include: a) Minimize parasitic capacitance to any ac ground for all of the signal I/O pins. Parasitic capacitance on the output and inverting input pins can cause instability; on the noninverting input it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes. Otherwise, ground and power planes should be unbroken elsewhere on the board. b) Minimize the distance (< 0.25") from the two power pins to high frequency 0.1F decoupling capacitors. At the pins, the ground and power plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power and ground traces to minimize inductance between the pins and the decoupling capacitors. Larger (2.2F to 6.8F) decoupling capacitors, effective at lower frequencies, should also be used. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high frequency performance of the OPA4650. Resistors should be a very low reactance type. Surface mount resistors work best and allow a tighter overall layout. Metal film or carbon composition axially-leaded resistors can also provide good high frequency performance. Again, keep their leads as short as possible. Never use wirewound type resistors in a high frequency application. Since the output pin and the inverting input pin are most sensitive to parasitic capacitance, always position the feedback and series output resistor, if any, as close as possible to If a long trace is required and the 6dB signal loss intrinsic to doubly terminated transmission lines is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50 environment is not necessary on board, and in fact a higher impedance environment will improve distortion as shown in the distortion vs load plot. With a characteristic impedance defined based on board material and desired trace dimensions, a matching series resistor into the trace from the output of the amplifier is used as well as a terminating shunt resistor at the input of the destination device. Remember also that the terminating impedance will be the parallel combination of the shunt resistor and the input impedance of the destination device; the total effective impedance should match the trace impedance. Multiple destination devices are best handled as separate transmission lines, each with their own series and shunt terminations. If the 6dB attenuation loss of a doubly terminated line is unacceptable, a long trace can be series-terminated at the source end only. This will help isolate the line capacitance from the op amp output, but will not preserve signal integrity as well as a doubly terminated line. If the shunt impedance at the destination end is finite, there will be some signal attenuation due to the voltage divider formed by the series and shunt impedances. e) Socketing a high speed part like the OPA4650 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket creates an extremely troublesome parasitic network which can make it almost (R) OPA4650 8 impossible to achieve a smooth, stable response. Best results are obtained by soldering the part onto the board. If socketing for the DIP package is desired, high frequency flush mount pins (e.g., McKenzie Technology #710C) can give good results. The OPA4650 is nominally specified for operation using 5V power supplies. A 10% tolerance on the supplies, or an ECL -5.2V for the negative supply, is within the maximum specified total supply voltage of 11V. Higher supply voltages can break down internal junctions possibly leading to catastrophic failure. Single supply operation is possible as long as common mode voltage constraints are observed. The common mode input and output voltage specifications can be interpreted as a required headroom to the supply voltage. Observing this input and output headroom requirement will allow non-standard or single supply operation. Figure 1 shows one approach to single-supply operation. +VS VOUT = 1/4 OPA4650 47k -VS OPA4650 0.1F (1) R1 R3 = R1 || R2 VIN or Ground Output Trim Range +VS R2 to -V R2 S RTRIM RTRIM NOTE: (1) R3 is optional and can be used to cancel offset errors due to input bias currents. FIGURE 2. Offset Voltage Trim. OPA4650. ESD damage can cause subtle changes in amplifier input characteristics without necessarily destroying the device. In precision operational amplifiers, this may cause a noticeable degradation of offset voltage and drift. ESD handling precautions are strongly recommended when handling the OPA4650. VS + AV VAC 2 ROUT OUTPUT DRIVE CAPABILITY The OPA4650 has been optimized to drive 75 and 100 resistive loads. The device can drive 1Vp-p into a 75 load. This high output drive capability makes the OPA4650 an ideal choice for a wide range of RF, IF and video applications. In many cases, additional buffer amplifiers are unnecessary. RL RF 402 RG 402 R2 RTRIM 20k +VS VS 2 VAC +Vs AV = 1 + RF RG Many demanding high speed applications, such as driving Analog-to-Digital converters, require op amps with low wideband output impedance. For example, low output impedance is essential when driving the signal-dependent capacitance at the input of a flash A/D converter. As shown in Figure 3, the OPA4650 maintains very low closed-loop output impedance over frequency. Closed-loop output impedance increases with frequency since loop gain is decreasing. FIGURE 1. Single Supply Operation. OFFSET VOLTAGE ADJUSTMENT One simple way to null the initial offset voltage while retaining the low offset drift of the OPA4650 is shown in Figure 2. The 20k potentiometer and the 47k series resistor RTRIM create a small correction current which is summed into the inverting node. The 0.1F capacitor keeps high-frequency power supply noise from coupling into the signal path. Although the initial offset will be nulled to zero with this technique, issues of temperature drift must also be considered. The additional resistor R3 is shown matched to the parallel combination R1 and R2 (the RTRIM path is assumed to be negligible in this calculation). This will eliminate the first-order offset drift due to input bias current leaving only the input offset current (IOS) drift multiplied by the feedback resistor R2. SMALL-SIGNAL OUTPUT IMPEDANCE vs FREQUENCY 1k Output Impedance () G = +1 100 10 1 0.1 0.01 ESD PROTECTION ESD damage has been a well recognized source of degradation for MOSFET type circuits, but any semiconductor device can be vulnerable to damage. This becomes more of an issue for very high speed processes like that used for the 10k 100k 1M 10M 100M Frequency (Hz) FIGURE 3. Small-Signal Output Impedance vs Frequency. (R) 9 OPA4650 THERMAL CONSIDERATIONS The OPA4650 will not require heatsinking under most operating conditions. Maximum desired junction temperature will limit the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed +175C. Operating junction temperature (TJ) is given by TA + PDJA. The total internal power dissipation (PD) is a combination of the total quiescent power for all channels (PDQ) and the sum of the powers dissipated in each of the output stages (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required output signal and load but would, for a grounded resistive load, be at a maximum when the output is a fixed dc voltage equal to 1/2 of either supply voltage (assuming equal bipolar supplies). Under this condition, PDL = VS2/ (4*RL) where RL includes feedback network loading. Note that it is the power dissipated in the output stage and not in the load that determines internal power dissipation. As an example, compute the maximum TJ for an OPA4650U at AV = +2, RL = 100, RFB = 402, VS = 5V, with all 4 outputs at |VS/2|, and the specified maximum TA = +85C. PD = 10V*35mA + 4*(52)/(4*(100||804)) = 631mW. Maximum TJ = +85C + 0.641W*75C/W = 133C. FREQUENCY RESPONSE COMPENSATION Each channel of the OPA4650 is internally compensated to be stable at unity gain with a nominal 60 phase margin. This lends itself well to wideband integrator and buffer applications. Phase margin and frequency response flatness will improve at higher gains. Recall that an inverting gain of -1 is equivalent to a gain of +2 for bandwidth purposes, i.e., noise gain = 2. The external compensation techniques developed for voltage feedback op amps can be applied to this device. For example, in the non-inverting configuration, placing a capacitor across the feedback resistor will reduce the gain to +1 starting at f = (1/2RFCF). Alternatively, in the inverting configuration, the bandwidth may be limited without modifying the inverting gain by placing a series RC network to ground on the inverting node. This has the effect of increasing the noise gain at high frequencies, thereby limiting the bandwidth for the inverting input signal through the gain-bandwidth product. At higher gains, the gain-bandwidth of this voltage feedback topology will limit bandwidth according to the open-loop frequency response curve. For applications requiring a wider bandwidth at higher gains, consider the quad current feedback model, OPA4658. In applications where a large feedback resistor is required (such as photodiode transimpedance circuits), precautions must be taken to avoid gain peaking due to the pole formed by the feedback resistor and the summing junction capacitance. This pole can be compensated by connecting a small capacitor in parallel with the feedback resistor, creating a cancelling zero term. In other high-gain applications, use of a three-resistor "T" connection will reduce the feedback network impedance which reacts with the parasitic capacitance at the summing node. DRIVING CAPACITIVE LOADS The OPA4650's output stage has been optimized to drive low resistive loads. Capacitive loads will decrease phase margin which may result in high frequency oscillations or peaking. Capacitive loads greater than 10pF should be isolated by connecting a small resistance (15 to 30) in series with the output as shown in Figure 4. This is especially important when driving the capacitive input of high-speed A/D converters. Increasing the gain from +1 will improve the capacitive load drive due to increased phase margin. In general, capacitive loads should be minimized for optimum high frequency performance. Coax lines can be driven if the cable is properly terminated. The capacitance of coax cable (29pF/ft for RG-58) will not load the amplifier when the cable is source and load terminated in its characteristic impedance. 25 PULSE SETTLING TIME High speed amplifiers like the OPA4650 are capable of extremely fast settling time with a pulse input. Excellent frequency response flatness and phase linearity are required to get the best settling times. As shown in the specifications table, settling time for a 1V step at a gain of +1 for the OPA4650 is extremely fast. The specification is defined as the time required, after the input transition, for the output to settle within a specified error band around its final value. For a 2V step, 1% settling corresponds to an error band of 20mV, 0.1% to an error band of 2mV, and 0.01% to an error band of 0.2mV. For the best settling times, particularly into an ADC capacitive load, little or no peaking in the frequency response can be allowed. Using the recommended RISO for capacitive loads will limit this peaking and reduce the settling times. Fast, extremely fine scale settling (0.01%) requires close attention to ground return currents in the supply decoupling capacitors. For highest performance, consider the OPA642 which isolates the output stage decoupling from the rest of the amplifier. (RISO typically 5 to 20) RISO OPA4650 RL CL FIGURE 4. Driving Capacitive Loads. (R) OPA4650 10 DIFFERENTIAL GAIN AND PHASE Differential Gain (DG) and Differential Phase (DP) are among the more important specifications for video applications. The percentage change in closed-loop gain over a specified change in output voltage level is defined as DG. DP is defined as the change in degrees of the closed-loop phase over the same output voltage change. For the OPA4650, DG and DP are both specified at the NTSC color sub-carrier frequency of 3.58MHz and measured using industry standard video test equipment. -30 G = +1 Crosstalk (dB) -40 Channel-to-Channel -80 0.1 1 10 100 300 Frequency (Hz) FIGURE 6. Channel-to-Channel Isolation and All Hostile Crosstalk. NOISE FIGURE The voltage and current noise spectral density are shown in the Typical Performance Curves. For RF and IF applications, however, Noise Figure (NF) is often the preferred specification. This specification shows a degradation in SNR through a device relative to the thermal noise of the source impedance alone. The NF for the OPA4650, using 1MHz spot noise numbers and an unterminated non-inverting input, is shown in Figure 7. -50 (fO = 5MHz, 2Vp-p) Harmonic Distortion (dBc) -60 -70 DISTORTION The OPA4650's harmonic distortion characteristics for a 100 load are shown in the Typical Performance Curves. Distortion can be improved by increasing the load resistance as illustrated in Figure 5. Remember to include the contribution of the feedback network when calculating the effective load resistance seen by the amplifier. -60 -70 All Hostile -50 2fO 3fO -80 30 -90 NF = 10 LOG 1 + 25 100 4KTRS 1k Noise Figure (dB) 10 en2 + (InRS)2 Load Resistance () FIGURE 5. Harmonic Distortion vs Load Resistance. CROSSTALK Crosstalk is the undesired coupling of one channel's signal into the output of the other channels. Crosstalk is a consideration in all multichannel integrated circuits. The effect of crosstalk is measured by driving one ("channel-to-channel") or more ("all-hostile") channels and observing the output of the undriven channel. The magnitude of this effect is expressed in the crosstalk specification as decibels of gain. "Input referred" points to the fact that there is a direct correlation between gain and crosstalk, therefore output crosstalk increases proportionally at higher gains. In quad devices, the effect of all-hostile crosstalk is observed by driving all three channels concurrently and measuring the output of the undriven fourth channel. The plots in Figure 6 illustrate both channel-to-channel and all-hostile crosstalk for the OPA4650. 20 15 10 5 0 10 100 1k 10k 100k Source Resistance () FIGURE 7. Noise Figure vs Source Resistance. SPICE MODELS AND EVALUATION BOARD Computer simulation using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for Video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. SPICE models and evaluation PC boards are available for the OPA4650. Contact the Burr-Brown Applications Department to receive a SPICE diskette. DEMONSTRATION BOARD PACKAGE PRODUCT DEM-OPA465xP DEM-OPA465xU 8-Pin DIP SO-8 OPA4650P oPA4650U (R) 11 OPA4650 TYPICAL APPLICATION 25 High Pass Output 1/4 OPA4650 1/4 OPA4650 VIN Band Pass Output 1/4 OPA4650 1/4 OPA4650 RIN Low Pass Output FIGURE 8. State-Variable Biquadratic Filter. R17 J8 R32 R18 -InC C2 2.2F R16 1 R12 J5 +5V R30 R13 -InB C1 0.1F 2 GND R11 P1 9 R20 J9 10 +InC R19 R26 J11 4 1/4 8 OPA4650 R15 6 J7 OutC +InB R8 R21 R31 R9 J4 R27 -InD 7 R14 1 R1 J6 OutB R10 R3 J2 5 1/4 OPA4650 R29 R4 -InA R25 R5 13 1/4 14 OPA4650 12 11 R23 J10 +InD R22 R28 2 J12 OutD +InA R5 R24 C3 0.1F 1 GND C4 2.2F 2 -5V P2 FIGURE 9. Circuit Detail for the DEM-OPA465xP Board. (R) OPA4650 R6 J3 12 3 R7 1/4 OPA4650 J1 OutA DEM-OPA465xP Demonstration Board Layout U1 P2 P1 (A) (B) (C) (D) FIGURE 10a. Board Silkscreen (Bottom). 10b. Board Silkscreen (Top). 10c. Board Layout (Solder Side). 10d. Board Layout (Component Side). The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant any BURR-BROWN product for use in life support devices and/or systems. (R) 13 OPA4650 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. Customers are responsible for their applications using TI components. In order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI's publication of information regarding any third party's products or services does not constitute TI's approval, warranty or endorsement thereof. Copyright 2000, Texas Instruments Incorporated