© 1994 Burr-Brown Corporation PDS-1267B Printed in U.S.A. July, 1995
FEATURES
●LOW POWER: 50mW/channel
●UNITY GAIN STABLE BANDWIDTH:
360MHz
●FAST SETTLING TIME: 20ns to 0.01%
●LOW INPUT BIAS CURRENT: 5µA
●DIFFERENTIAL GAIN/PHASE ERROR:
0.01%/0.025°
●14-PIN DIP and SO-14 SURFACE MOUNT
PACKAGES AVAILABLE
DESCRIPTION
The OPA4650 is a quad, low power, wideband voltage
feedback operational amplifier. It features a high band-
width of 360MHz as well as a 12-bit settling time of
only 20ns. The low input bias current allows its use in
high speed integrator applications, while the wide
bandwidth and true differential input stage make it
suitable for use in a variety of active filter applica-
tions. Its low distortion gives exceptional performance
for telecommunications, medical imaging and video
applications.
The OPA4650 is internally compensated for unity-
gain stability. This amplifier has a fully symmetrical
differential input due to its “classical” operational
amplifier circuit architecture. Its unusual combination
of speed, accuracy and low power make it an outstand-
ing choice for many portable, multi-channel and other
high speed applications, where power is at a premium.
The OPA4650 is also available in single (OPA650)
and dual (OPA2650) configurations.
Wideband, Low Power, Quad Voltage Feedback
OPERATIONAL AMPLIFIER
®
OPA4650
Current
Mirror
Output
Stage
C
C
Inverting
Input
Non-Inverting
Input
+V
S
Output
–V
S
Simplified Schematic
1 of 4 Channels
APPLICATIONS
●HIGH RESOLUTION VIDEO
●MONITOR PREAMPLIFIER
●CCD IMAGING AMPLIFIER
●ULTRASOUND SIGNAL PROCESSING
●ADC/DAC BUFFER AMPLIFIER
●ACTIVE FILTERS
●HIGH SPEED INTEGRATORS
●DIFFERENTIAL AMPLIFIER
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
OPA4650
OPA4650
DEMO BOARD
AVAILABLE
SBOS044
2
®
OPA4650
SPECIFICATIONS
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
OPA4650P, U
PARAMETER CONDITIONS MIN TYP MAX UNITS
FREQUENCY RESPONSE
Closed-Loop Bandwidth(1) G = +1 360 MHz
G = +2 120 MHz
G = +5 35 MHz
G = +10 16 MHz
Gain Bandwidth Product 160 MHz
Slew Rate(2) G = +1, 2V Step 240 V/µs
Over Specified Temperature 220 V/µs
Rise Time 0.2V Step 1 ns
Fall Time 0.2V Step 1 ns
Settling Time 0.01% G = +1, 2V Step 20 ns
0.1% G = +1, 2V Step 10.3 ns
1% G = +1, 2V Step 7.9 ns
Spurious Free Dynamic Range G = +1, f = 5.0 MHz, VO = 2Vp-p
RL = 100Ω68 dBc
RL = 402Ω74 dBc
Differential Gain G = +2, NTSC, VO = 1.4Vp, RL = 150Ω0.01 %
Differential Phase G = +2, NTSC, VO = 1.4Vp, RL = 150Ω0.025 Degrees
Bandwidth for 0.1dB Flatness G = +2 21 MHz
Crosstalk Input Referred, 5MHz, all hostile –63 dB
Input Referred, 5MHz, Channel-to-Channel –66 dB
OFFSET VOLTAGE
Input Offset Voltage ±1±5.5 mV
Average Drift ±3µV/°C
Power Supply Rejection (+VS)|V
S
| = 4.5V to 5.5V 60 76 dB
(–VS) 47 52 dB
INPUT BIAS CURRENT
Input Bias Current VCM = 0V 5 20 µA
Over Temperature 30 µA
Input Offset Current VCM = 0V 0.5 1.0 µA
Over Temperature 3.0 µA
INPUT NOISE
Input Voltage Noise
Noise Density, f = 100Hz 43 nV/√Hz
f = 10kHz 9.4 nV/√Hz
f = 1MHz 8.4 nV/√Hz
f = 1MHz to 100MHz 8.4 nV/√Hz
Integrated Noise, BW = 10Hz to 100MHz 84 µVp-p
Input Bias Current Noise
Current Noise Density, f = 0.1MHz to 100MHz 1.2 pA/√Hz
Noise Figure (NF) RS = 10kΩ4.0 dBm
RS = 50Ω19.5 dBm
INPUT VOLTAGE RANGE
Common-Mode Input Range ±2.8 V
Over Specified Temperature ±2.2 V
Common-Mode Rejection VCM = ±0.5V 65 90 dB
INPUT IMPEDANCE
Differential 15 || 1 kΩ || pF
Common-Mode 16 || 1 MΩ || pF
OPEN-LOOP GAIN
Open-Loop Voltage Gain VO = ±2V, RL = 100Ω45 51 dB
Over Specified Temperature VO = ±2V, RL = 100Ω43 dB
OUTPUT
Voltage Output
Over Specified Temperature No Load ±2.2 ±3.0 V
RL = 250Ω±2.2 ±2.5 V
RL = 100Ω±2.0 ±2.3 V
Output Current, Sourcing 75 110 mA
Over Temperature Range 65 mA
Output Current, Sinking 65 85 mA
Over Temperature Range 35 mA
Short-Circuit Current 150 mA
Output Resistance 0.1MHz, G = +1 0.08 Ω
POWER SUPPLY
Specified Operating Voltage ±5V
Operating Voltage Range ±4.5 ±5.5 V
Quiescent Current All Channels ±23 ±32 mA
Over Specified Temperature ±35 mA
TEMPERATURE RANGE
Specification: P, U –40 +85 °C
Thermal Resistance,
θ
JA
P75 °C/W
U75 °C/W
NOTES: (1) Frequency response can be strongly influenced by PC board parasites. The OPA4650 is nominally compensated assuming 2pF parasitic load. The
demonstration board, DEM-OPA465xP, shows a low parasitic layout for this part. (2) Slew rate is rate of change from 10% to 90% of output voltage step.
3
®
OPA4650
ORDERING INFORMATION
PRODUCT PACKAGE TEMPERATURE RANGE
OPA4650U SO-14 Surface Mount –40°C to +85°C
OPA4650P 14-Pin Plastic DIP –40°C to +85°C
PACKAGE INFORMATION
PACKAGE DRAWING
PRODUCT PACKAGE NUMBER(1)
OPA4650U SO-14 Surface Mount 235
OPA4650P 14-Pin Plastic DIP 010
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
Total Supply Voltage Across Device...................................................11V
Internal Power Dissipation........................... See Thermal Considerations
Differential Input Voltage .................................................................. ±2.7V
Common-Mode Input Voltage Range.................................................. ±VS
Storage Temperature Range: P, U, .............................. –40°C to +125°C
Lead Temperature (soldering, 10s) .............................................. +300°C
(soldering, SOIC 3s) ....................................... +260°C
Junction Temperature (TJ )............................................................ +175°C
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Electrostatic discharge can cause damage ranging from per-
formance degradation to complete device failure. Burr-Brown
Corporation recommends that all integrated circuits be handled
and stored using appropriate ESD protection methods.
ESD damage can range from subtle performance degradation
to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric
changes could cause the device not to meet published speci-
fications.
Top View DIP/SO-14
PIN CONFIGURATION
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Output 4
–Input 4
+Input 4
–V
S
+Input 3
–Input 3
Output 3
Output 1
–Input 1
+Input 1
+V
S
+Input 2
–Input 2
Output 2
4
®
OPA4650
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
A
OL
, PSR AND CMRR vs TEMPERATURE
110
100
90
80
70
60
50–50 –25 0 25 50 75 125
A
OL
, PSR and CMRR (dB)
Temperature (°C)
A
OL
PSR–
CMRR
PSR+
COMMON-MODE REJECTION
vs INPUT COMMON-MODE VOLTAGE
100
90
80
70
60–4 –3 –2 –1 0 1 2 3 4
Common-Mode Rejection (dB)
Common-Mode Voltage (V)
INPUT BIAS CURRENT AND OFFSET VOLTAGE
vs TEMPERATURE
7
6
5
4
2
1
0
–1
–50 –25 0 25 50 75 100
Input Bias Current (mA)
Offset Voltage (mV)
Temperature (°C)
V
OS
I
B
SUPPLY CURRENT vs TEMPERATURE
26
24
22
20–50 –25 0 25 50 75 100
Supply Current (±mA)
Temperature (°C)
I
Q
INPUT VOLTAGE AND CURRENT NOISE
vs FREQUENCY
Frequency (Hz)
100 1k 10k 100k 1M
100
10
1
Input Current Noise (pA/√Hz)
Input Voltage Noise (nV/√Hz)
Non-inverting and
Inverting Current Noise
Voltage Noise
OUTPUT CURRENT vs TEMPERATURE
70
65
60
55–50 –25 0 25 50 75 100
Output Current (±mA)
Temperature (°C)
I
O
+
I
O
–
5
®
OPA4650
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
SMALL SIGNAL TRANSIENT RESPONSE
(G = +1)
Time (5ns/div)
200
160
120
80
40
0
–40
–80
–120
–160
–200
Output Voltage (mV)
RECOMMENDED ISOLATION RESISTANCE
vs CAPACITIVE LOAD
40
30
20
10
00 20 40 60 80 100
Isolation Resistance, R
ISO
(Ω)
Capacitive Load, C
L
(pF)
OPA4650
C
L
1kΩ
R
ISO
25Ω
LARGE SIGNAL TRANSIENT RESPONSE
(G = +1)
Time (5ns/div)
2.0
1.6
1.2
0.8
0.4
0
–0.4
–0.8
–1.2
–1.6
–2.0
Output Voltage (V)
CLOSED-LOOP BANDWIDTH (G = +1)
Frequency (Hz)
6
3
0
–3
–6
–9
–121M 10M 100M 1G
SO-14/DIP Bandwidth = 360MHz
Gain (dB)
CLOSED-LOOP BANDWIDTH (G = +2)
Frequency (Hz)
12
9
6
3
0
–3
–6
–91M 10M 100M 1G
Gain (dB)
SO-14/DIP Bandwidth = 120MHz
CLOSED-LOOP BANDWIDTH (G = +5)
Frequency (Hz)
21
17
14
11
8
5
2
–11M 10M 100M 1G
Gain (dB)
SO-14/DIP Bandwidth = 35MHz
6
®
OPA4650
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
CLOSED-LOOP BANDWIDTH (G = +10)
Frequency (Hz)
26
23
20
17
14
11
8
5
21M 10M 100M 1G
Gain (dB)
SO-14/DIP Bandwidth = 16MHz
OPEN-LOOP GAIN AND PHASE
vs FREQUENCY
60
50
40
30
20
10
0
+45
0
–45
–90
–135
–180
1k 10k 100k 1M 10M 100M 1G
Gain (dB)
Phase (°)
Frequency (Hz)
Phase
Gain
5MHz HARMONIC DISTORTION
vs OUTPUT SWING
Output Swing (Vp-p)
–60
–70
–80
–90
–1000.1 1 10
Harmonic Distortion (dBc)
3f
O
2f
O
G = +2
10MHz HARMONIC DISTORTION
vs OUTPUT SWING
Output Swing (Vp-p)
–50
–60
–70
–80
–900.1 1 10
Harmonic Distortion (dBc)
3f
O
2f
O
HARMONIC DISTORTION vs FREQUENCY
(G = +1, V
O
= 2Vp-p)
Frequency (Hz)
–50
–60
–70
–80
–90
100k 1M 10M 100M
Harmonic Distortion (dBc)
2f
O
3f
O
HARMONIC DISTORTION vs TEMPERATURE
(f
O
= 5MHz, G = +1, V
O
= 2Vp-p)
–50
–60
–70
–80
–90–50 –25 0 25 50 75 100
Harmonic Distortion (dB)
Temperature (°C)
3f
O
2f
O
7
®
OPA4650
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±5V, RL = 100Ω, and RFB = 402Ω, unless otherwise noted. RFB = 25Ω for a gain of +1.
HARMONIC DISTORTION vs GAIN
(f
O
= 5MHz, V
O
= 2Vp-p)
40
50
60
70
80 12345678910
Harmonic Distortion (dBc)
Non-Inverting Gain (V/V)
3f
O
2f
O
8
®
OPA4650
DISCUSSION OF
PERFORMANCE
The OPA4650 is a quad low power, wideband voltage
feedback operational amplifier. Each channel is internally
compensated to provide unity gain stability. The OPA4650’s
voltage feedback architecture features true differential and
fully symmetrical inputs. This minimizes offset errors, mak-
ing the OPA4650 well suited for implementing filter and
instrumentation designs. As a quad operational amplifier,
OPA4650 is an ideal choice for designs requiring multiple
channels where reduction of board space, power dissipation
and cost are critical. Its ac performance is optimized to
provide a gain bandwidth product of 160MHz and a fast
0.1% settling time of 10.3ns, which is an important consid-
eration in high speed data conversion applications. Along
with its excellent settling characteristics, the low dc input
offset of ±1mV and drift of ±3µV/°C support high accuracy
requirements. In applications requiring a higher slew rate
and wider bandwidth, such as video and high bit rate digital
communications, consider the quad current feedback
OPA4658.
CIRCUIT LAYOUT AND BASIC OPERATION
Achieving optimum performance with a high frequency am-
plifier like the OPA4650 requires careful attention to layout
parasitics and selection of external components. Recommen-
dations for PC board layout and component selection include:
a) Minimize parasitic capacitance to any ac ground for all
of the signal I/O pins. Parasitic capacitance on the output
and inverting input pins can cause instability; on the non-
inverting input it can react with the source impedance to
cause unintentional bandlimiting. To reduce unwanted ca-
pacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes. Otherwise,
ground and power planes should be unbroken elsewhere on
the board.
b) Minimize the distance (< 0.25") from the two power pins
to high frequency 0.1µF decoupling capacitors. At the pins,
the ground and power plane layout should not be in close
proximity to the signal I/O pins. Avoid narrow power and
ground traces to minimize inductance between the pins and
the decoupling capacitors. Larger (2.2µF to 6.8 µF) decoupling
capacitors, effective at lower frequencies, should also be
used. These may be placed somewhat farther from the
device and may be shared among several devices in the same
area of the PC board.
c) Careful selection and placement of external compo-
nents will preserve the high frequency performance of the
OPA4650. Resistors should be a very low reactance type.
Surface mount resistors work best and allow a tighter overall
layout. Metal film or carbon composition axially-leaded
resistors can also provide good high frequency performance.
Again, keep their leads as short as possible. Never use
wirewound type resistors in a high frequency application.
Since the output pin and the inverting input pin are most
sensitive to parasitic capacitance, always position the feed-
back and series output resistor, if any, as close as possible to
the package pins. Surface mount feedback resistors directly
adjacent to the output and inverting input pins work well for
the quad pinout. Other network components, such as non-
inverting input termination resistors, should also be placed
close to the package.
Even with a low parasitic capacitance shunting the resistor,
excessively high resistor values can create significant time
constants and degrade performance. Good metal film or
surface mount resistors have approximately 0.2pF in shunt
with the resistor. For resistor values > 1.5kΩ, this adds a
pole and/or zero below 500MHz that can affect circuit
operation. Keep resistor values as low as possible consistent
with output loading considerations. The 402Ω feedback
used for the Typical Performance Plots is a good starting
point for design. Note that a 25Ω feedback resistor, rather
than a direct short, is suggested for a unity gain follower.
This effectively reduces the Q of what would otherwise be
a parasitic inductance (the feedback wire) into the parasitic
capacitance at the inverting input.
d) Connections to other wideband devices on the board
may be made with short direct traces or through on-board
transmission lines. For short connections, consider the trace
and the input to the next device as a lumped capacitive load.
Relatively wide traces (50 to 100 mils) should be used,
preferably with ground and power planes opened up around
them. Estimate the total capacitive load and set RISO from
the plot of recommended RISO vs capacitive load. Low
parasitic loads may not need an RISO since the OPA4650 is
nominally compensated to operate with a 2pF parasitic load.
If a long trace is required and the 6dB signal loss intrinsic to
doubly terminated transmission lines is acceptable, imple-
ment a matched impedance transmission line using microstrip
or stripline techniques (consult an ECL design handbook for
microstrip and stripline layout techniques). A 50Ω environ-
ment is not necessary on board, and in fact a higher imped-
ance environment will improve distortion as shown in the
distortion vs load plot. With a characteristic impedance
defined based on board material and desired trace dimen-
sions, a matching series resistor into the trace from the
output of the amplifier is used as well as a terminating shunt
resistor at the input of the destination device. Remember
also that the terminating impedance will be the parallel
combination of the shunt resistor and the input impedance of
the destination device; the total effective impedance should
match the trace impedance. Multiple destination devices are
best handled as separate transmission lines, each with their
own series and shunt terminations.
If the 6dB attenuation loss of a doubly terminated line is
unacceptable, a long trace can be series-terminated at the
source end only. This will help isolate the line capacitance
from the op amp output, but will not preserve signal integrity
as well as a doubly terminated line. If the shunt impedance
at the destination end is finite, there will be some signal
attenuation due to the voltage divider formed by the series
and shunt impedances.
e) Socketing a high speed part like the OPA4650 is not
recommended. The additional lead length and pin-to-pin
capacitance introduced by the socket creates an extremely
troublesome parasitic network which can make it almost
9
®
OPA4650
impossible to achieve a smooth, stable response. Best results
are obtained by soldering the part onto the board. If socket-
ing for the DIP package is desired, high frequency flush
mount pins (e.g., McKenzie Technology #710C) can give
good results.
The OPA4650 is nominally specified for operation using ±5V
power supplies. A 10% tolerance on the supplies, or an ECL
–5.2V for the negative supply, is within the maximum speci-
fied total supply voltage of 11V. Higher supply voltages can
break down internal junctions possibly leading to catastrophic
failure. Single supply operation is possible as long as com-
mon mode voltage constraints are observed. The common
mode input and output voltage specifications can be inter-
preted as a required headroom to the supply voltage. Observ-
ing this input and output headroom requirement will allow
non-standard or single supply operation. Figure 1 shows one
approach to single-supply operation.
OFFSET VOLTAGE ADJUSTMENT
One simple way to null the initial offset voltage while
retaining the low offset drift of the OPA4650 is shown in
Figure 2. The 20kΩ potentiometer and the 47kΩ series
resistor RTRIM create a small correction current which is
summed into the inverting node. The 0.1µF capacitor keeps
high-frequency power supply noise from coupling into the
signal path. Although the initial offset will be nulled to zero
with this technique, issues of temperature drift must also be
considered. The additional resistor R3 is shown matched to
the parallel combination R1 and R2 (the RTRIM path is
assumed to be negligible in this calculation). This will
eliminate the first-order offset drift due to input bias current
leaving only the input offset current (IOS) drift multiplied by
the feedback resistor R2.
ESD PROTECTION
ESD damage has been a well recognized source of degrada-
tion for MOSFET type circuits, but any semiconductor
device can be vulnerable to damage. This becomes more of
an issue for very high speed processes like that used for the
FIGURE 1. Single Supply Operation.
FIGURE 2. Offset Voltage Trim.
OPA4650. ESD damage can cause subtle changes in ampli-
fier input characteristics without necessarily destroying the
device. In precision operational amplifiers, this may cause a
noticeable degradation of offset voltage and drift. ESD
handling precautions are strongly recommended when han-
dling the OPA4650.
OUTPUT DRIVE CAPABILITY
The OPA4650 has been optimized to drive 75Ω and 100Ω
resistive loads. The device can drive 1Vp-p into a 75Ω
load. This high output drive capability makes the OPA4650
an ideal choice for a wide range of RF, IF and video
applications. In many cases, additional buffer amplifiers
are unnecessary.
Many demanding high speed applications, such as driving
Analog-to-Digital converters, require op amps with low
wideband output impedance. For example, low output imped-
ance is essential when driving the signal-dependent capaci-
tance at the input of a flash A/D converter. As shown in
Figure 3, the OPA4650 maintains very low closed-loop
output impedance over frequency. Closed-loop output imped-
ance increases with frequency since loop gain is decreasing.
SMALL-SIGNAL OUTPUT IMPEDANCE
vs FREQUENCY
Frequency (Hz)
1k
100
10
1
0.1
0.0110k 100k 1M 100M10M
Output Impedance (Ω)
G = +1
FIGURE 3. Small-Signal Output Impedance vs Frequency.
R
2
OPA4650
R
3
= R
1
|| R
2(1)
R
1
R
TRIM
+V
s
–V
S
20kΩ
V
IN
or Ground
Output Trim Range +V
S
to –V
S
NOTE: (1) R
3
is optional and can be used to cancel offset errors
due to input bias currents.
≅
R
TRIM
47kΩ
R
2
R
2
R
TRIM
0.1µF
RG
402Ω
1/4
OPA4650
VAC
RF
402Ω
RL
+VS+VS
VS
2
ROUT
VS
2
VOUT = + AV VAC
AV = 1 + RF
RG
10
®
OPA4650
FREQUENCY RESPONSE COMPENSATION
Each channel of the OPA4650 is internally compensated to
be stable at unity gain with a nominal 60° phase margin.
This lends itself well to wideband integrator and buffer
applications. Phase margin and frequency response flatness
will improve at higher gains. Recall that an inverting gain of
–1 is equivalent to a gain of +2 for bandwidth purposes, i.e.,
noise gain = 2. The external compensation techniques devel-
oped for voltage feedback op amps can be applied to this
device. For example, in the non-inverting configuration,
placing a capacitor across the feedback resistor will reduce
the gain to +1 starting at f = (1/2πRFCF). Alternatively, in the
inverting configuration, the bandwidth may be limited with-
out modifying the inverting gain by placing a series RC
network to ground on the inverting node. This has the effect
of increasing the noise gain at high frequencies, thereby
limiting the bandwidth for the inverting input signal through
the gain-bandwidth product.
At higher gains, the gain-bandwidth of this voltage feedback
topology will limit bandwidth according to the open-loop
frequency response curve. For applications requiring a wider
bandwidth at higher gains, consider the quad current feed-
back model, OPA4658. In applications where a large feed-
back resistor is required (such as photodiode transimpedance
circuits), precautions must be taken to avoid gain peaking
due to the pole formed by the feedback resistor and the
summing junction capacitance. This pole can be compen-
sated by connecting a small capacitor in parallel with the
feedback resistor, creating a cancelling zero term. In other
high-gain applications, use of a three-resistor “T” connec-
tion will reduce the feedback network impedance which
reacts with the parasitic capacitance at the summing node.
PULSE SETTLING TIME
High speed amplifiers like the OPA4650 are capable of
extremely fast settling time with a pulse input. Excellent
frequency response flatness and phase linearity are required
to get the best settling times. As shown in the specifications
table, settling time for a ±1V step at a gain of +1 for the
OPA4650 is extremely fast. The specification is defined as
the time required, after the input transition, for the output to
settle within a specified error band around its final value. For
a 2V step, 1% settling corresponds to an error band of
±20mV, 0.1% to an error band of ±2mV, and 0.01% to an
error band of ±0.2mV. For the best settling times, particu-
larly into an ADC capacitive load, little or no peaking in the
frequency response can be allowed. Using the recommended
RISO for capacitive loads will limit this peaking and reduce
the settling times. Fast, extremely fine scale settling (0.01%)
requires close attention to ground return currents in the
supply decoupling capacitors. For highest performance, con-
sider the OPA642 which isolates the output stage decoupling
from the rest of the amplifier.
THERMAL CONSIDERATIONS
The OPA4650 will not require heatsinking under most
operating conditions. Maximum desired junction tempera-
ture will limit the maximum allowed internal power dissipa-
tion as described below. In no case should the maximum
junction temperature be allowed to exceed +175°C.
Operating junction temperature (TJ) is given by TA +
P
D
θ
JA. The total internal power dissipation (PD) is a com-
bination of the total quiescent power for all channels (PDQ)
and the sum of the powers dissipated in each of the output
stages (PDL) to deliver load power. Quiescent power is
simply the specified no-load supply current times the total
supply voltage across the part. PDL will depend on the
required output signal and load but would, for a grounded
resistive load, be at a maximum when the output is a fixed
dc voltage equal to 1/2 of either supply voltage (assuming
equal bipolar supplies). Under this condition, PDL = VS2/
(4•RL) where RL includes feedback network loading. Note
that it is the power dissipated in the output stage and not in
the load that determines internal power dissipation. As an
example, compute the maximum TJ for an OPA4650U at
AV = +2, RL = 100Ω, RFB = 402Ω, ±VS = ±5V, with all 4
outputs at |VS/2|, and the specified maximum TA = +85°C.
PD = 10V•35mA + 4•(52)/(4•(100Ω||804Ω)) = 631mW.
Maximum TJ = +85°C + 0.641W•75°C/W = 133°C.
DRIVING CAPACITIVE LOADS
The OPA4650’s output stage has been optimized to drive
low resistive loads. Capacitive loads will decrease phase
margin which may result in high frequency oscillations or
peaking. Capacitive loads greater than 10pF should be iso-
lated by connecting a small resistance (15Ω to 30Ω) in series
with the output as shown in Figure 4. This is especially
important when driving the capacitive input of high-speed
A/D converters. Increasing the gain from +1 will improve
the capacitive load drive due to increased phase margin.
In general, capacitive loads should be minimized for opti-
mum high frequency performance. Coax lines can be driven
if the cable is properly terminated. The capacitance of coax
cable (29pF/ft for RG-58) will not load the amplifier when
the cable is source and load terminated in its characteristic
impedance.
FIGURE 4. Driving Capacitive Loads.
OPA4650
C
L
R
L
R
ISO
(R
ISO
typically 5Ω to 20Ω)
25Ω
11
®
OPA4650
DIFFERENTIAL GAIN AND PHASE
Differential Gain (DG) and Differential Phase (DP) are
among the more important specifications for video applica-
tions. The percentage change in closed-loop gain over a
specified change in output voltage level is defined as DG.
DP is defined as the change in degrees of the closed-loop
phase over the same output voltage change. For the OPA4650,
DG and DP are both specified at the NTSC color sub-carrier
frequency of 3.58MHz and measured using industry stan-
dard video test equipment.
DISTORTION
The OPA4650’s harmonic distortion characteristics for a
100Ω load are shown in the Typical Performance Curves.
Distortion can be improved by increasing the load resistance
as illustrated in Figure 5. Remember to include the contribu-
tion of the feedback network when calculating the effective
load resistance seen by the amplifier.
FIGURE 6. Channel-to-Channel Isolation and All Hostile
Crosstalk.
0.1 1 10 100 300
Frequency (Hz)
–30
–40
–50
–60
–70
–80
Crosstalk (dB)
G = +1
All Hostile
Channel-to-Channel
FIGURE 5. Harmonic Distortion vs Load Resistance.
–50
–60
–70
–80
–9010 100 1k
Harmonic Distortion (dBc)
Load Resistance (Ω)
3f
O
(f
O
= 5MHz, 2Vp-p)
2f
O
CROSSTALK
Crosstalk is the undesired coupling of one channel’s signal
into the output of the other channels. Crosstalk is a consid-
eration in all multichannel integrated circuits. The effect of
crosstalk is measured by driving one (“channel-to-channel”)
or more (“all-hostile”) channels and observing the output of
the undriven channel. The magnitude of this effect is ex-
pressed in the crosstalk specification as decibels of gain.
“Input referred” points to the fact that there is a direct
correlation between gain and crosstalk, therefore output
crosstalk increases proportionally at higher gains.
In quad devices, the effect of all-hostile crosstalk is observed
by driving all three channels concurrently and measuring the
output of the undriven fourth channel. The plots in Figure 6
illustrate both channel-to-channel and all-hostile crosstalk
for the OPA4650.
FIGURE 7. Noise Figure vs Source Resistance.
Source Resistance (Ω)
30
25
20
15
10
5
010 100 1k 100k10k
Noise Figure (dB)
NF = 10 LOG 1 + e
n2
+ (I
n
R
S
)
2
4KTR
S
SPICE MODELS AND EVALUATION BOARD
Computer simulation using SPICE is often useful when
analyzing the performance of analog circuits and systems.
This is particularly true for Video and RF amplifier circuits
where parasitic capacitance and inductance can have a
major effect on circuit performance. SPICE models and
evaluation PC boards are available for the OPA4650. Con-
tact the Burr-Brown Applications Department to receive a
SPICE diskette.
NOISE FIGURE
The voltage and current noise spectral density are shown in
the Typical Performance Curves. For RF and IF applica-
tions, however, Noise Figure (NF) is often the preferred
specification. This specification shows a degradation in
SNR through a device relative to the thermal noise of the
source impedance alone.
The NF for the OPA4650, using 1MHz spot noise numbers
and an unterminated non-inverting input, is shown in
Figure 7.
DEMONSTRATION BOARD PACKAGE PRODUCT
DEM-OPA465xP 8-Pin DIP OPA4650P
DEM-OPA465xU SO-8 oPA4650U
12
®
OPA4650
TYPICAL APPLICATION
FIGURE 8. State-Variable Biquadratic Filter.
FIGURE 9. Circuit Detail for the DEM-OPA465xP Board.
25Ω
1/4
OPA4650
V
IN
R
IN
1/4
OPA4650 1/4
OPA4650 1/4
OPA4650
High Pass
Output Band Pass
Output
Low Pass
Output
R
23
R
28
Out
D
J
12
1
2
GND
–5V
P2
R
24
R
22
+In
D
R
26
R
31
R
27
R
25
–In
D
J
10
J
11
13
11
14
12
C
3
0.1µF
C
4
2.2µF
R
20
R
15
OPA4650
OPA4650
Out
C
J
7
R
21
R
19
+In
C
R
17
R
18
R
32
R
16
–In
C
J
9
J
8
948
10
C
2
2.2µF
C
1
0.1µF
1/4
1/4
1
2GND
+5V
P1
R
6
R
1
Out
A
J
1
R
7
R
5
+In
A
R
3
R
4
R
29
R
5
–In
A
J
3
J
2
21
3
OPA4650
1/4
R
9
R
14
Out
B
J
6
R
10
R
8
+In
B
R
12
R
13
R
30
R
11
–In
B
J
4
J
5
67
5
OPA4650
1/4
13
®
OPA4650
(C)
(A)
DEM-OPA465xP Demonstration Board Layout
(B)
P2
(D)
U1
FIGURE 10a. Board Silkscreen (Bottom). 10b. Board Silkscreen (Top). 10c. Board Layout (Solder Side). 10d. Board Layout
(Component Side).
P1
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no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
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