Copyright © Alliance Semiconductor. All rights reserved.
®
AS4C4M4E1
4M×4 CMOS DRAM (EDO) family
5/22/01; v.1.29 point> Alliance Semiconductor P. 1 of 14
May 2001
Features
• Organization: 4,194,304 words × 4 bits
• High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
• Low power consumption
- Active: 908 mW max
- Standby: 5.5 mW max, CMOS I/O
• Extended data out
•Refresh
- 2048 refresh cycles, 32 ms refresh interval for
AS4C4M4E1
-RAS
-only or CAS-before-RAS refresh
• TTL-compatible, three-state I/O
• JEDEC standard package
- 300 mil, 24/26-pin SOJ
- 300 mil, 24/26-pin TSOP
• 5V power supply
• Latch-up current ≥ 200 mA
• ESD protection ≥ 2000 volts
• Industrial and commercial temperature available
Pin arrangement
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
VCC GND
GND
I/O3
I/O2
CAS
OE
VCC
I/O0
I/O1
WE
RAS
1
2
3
4
5
24
23
22
21
20
NC A9
619
7
8
9
10
11
18
17
16
15
14
12 13
SOJ
AS4C4M4E0
A8
A7
A6
A5
A4
A10
A0
A1
A2
A3
VCC GND
GND
I/O3
I/O2
CAS
OE
VCC
I/O0
I/O1
WE
RAS
1
2
3
4
5
24
23
22
21
20
NC A9
619
7
8
9
10
11
18
17
16
15
14
12 13
TSOP
AS4C4M4E0
Pin designation
Pin(s) Description
A0 to A10 Address inputs
RAS Row address strobe
CAS Column address strobe
WE Write enable
I/O0 to I/O3 Input/output
OE Output enable
VCC Power
GND Ground
Selection guide
Symbol AS4C4M4E1-50 AS4C4M4E1-60 Unit
Maximum RAS access time tRAC 50 60 ns
Maximum column address access time tCAA 25 30 ns
Maximum CAS access time tCAC 12 15 ns
Maximum output enable (OE) access time tOEA 13 15 ns
Minimum read or write cycle time tRC 85 100 ns
Minimum fast page mode cycle time tPC 25 30 ns
Maximum operating current ICC1 135 120 mA
Maximum CMOS standby current ICC5 2.0 2.0 mA
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Functional description
The AS4C4M4E1 is a high performance 16-megabit CMOS Dynamic Random Access Memories (DRAM) organized as 4,194,304 words × 4
bits. The devices are fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low
power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory
in PC, workstation, router and switch applications.
This product features a high speed page mode operation where read and write operations within a single row (or page) can be executed at
very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the
falling edge of RAS and CAS inputs respectively. Also, RAS is used to make the column address latch transparent, enabling application of
column addresses prior to CAS assertion.
Extended data out (EDO) read mode enables 60MHz operation using 60ns devices. In contrast to 'fast page mode' devices, data remains active
on outputs after CAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output impedance and
prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last occurrance of
RAS and CAS going high.
Refresh on the 2048 address combinations of A0 to A10 must be performed every 32 ms using:
•RAS
-only refresh: RAS is asserted while CAS is held high. Each of the 2048 rows must be strobed. Outputs remain high impedence.
• Hidden refresh: CAS is held low while RAS is toggled. Refresh address is generated internally. Outputs remain low impedence with
previous valid data.
•CAS-before-RAS refresh (CBR): At least one CAS is asserted prior to RAS. Refresh address is generated internally.
Outputs are high-impedence (OE and WE are don't care).
• Normal read or write cycles refresh the row being accessed.
The AS4C4M4E1 is a available in the standard 24/26-pin plastic SOJ and 24/26-pin plastic TSOP packages. The AS4C4M4E1 operates with a
single power supply of 5V ± 0.5V. It provides TTL compatible inputs and outputs.
Logic block diagram for 2K refresh
Recommended operating conditions
†VIL min -3.0V for pulse widths less than 5 ns. Recommended operating conditions apply throughout this document unlesss otherwise specified.
Parameter Symbol Min Nominal Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
GND 0.0 0.0 0.0 V
Input voltage VIH 2.4 – VCC V
VIL –0.5†–0.8V
Ambient operating temperature Commercial TA
0–70
°C
Industrial -40 – 85
RAS clock
generator
Refresh
controller
2048 × 2048 × 4
Array
(16,777,216)
Sense amp
A0
A1
A2
A3
A4
A5
A6
A7
VCC
GND
Address buffers
A8
Row decoder
Column decoder
Substrate bias
generator
Data
I/O
buffers
OE
RAS
CAS
WE clock
generator
WE
I/O0 to I/O3
CAS clock
generator
A9
A10
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Absolute maximum ratings
DC electrical characteristics
Parameter Symbol Min Max Unit
Input voltage Vin -1.0 +7.0 V
Input voltage (DQs) VDQ -1.0 VCC + 0.5 V
Power supply voltage VCC -1.0 +7.0 V
Storage temperature (plastic) TSTG -55 +150 °C
Soldering temperature × time TSOLDER – 260 × 10 oC × sec
Power dissipation PD–1W
Short circuit output current Iout –50mA
Parameter Symbol Test conditions
-50 -60
Unit NotesMin Max Min Max
Input leakage current IIL
0V ≤ Vin ≤ +5.5V,
Pins not under test = 0V -5 +5 -5 +5 µA
Output leakage current IOL DOUT disabled, 0V ≤ Vout ≤ +5.5V -5+5-5+5µA
Operating power
supply current ICC1 RAS, CAS Address cycling; tRC=min – 135 – 120 mA 1,2
TTL standby power
supply current ICC2 RAS = CAS ≥ VIH – 2.0 – 2.0 mA
Average power supply
current, RAS refresh
mode or CBR
ICC3
RAS cycling, CAS ≥ VIH,
tRC = min of RAS low after CAS low. – 120 – 110 mA 1
EDO page mode average
power supply current ICC4
RAS = VIL, CAS
address cycling: tHPC = min – 130 – 120 mA 1, 2
CMOS standby power
supply current ICC5 RAS = CAS = VCC - 0.2V – 2.0 – 2.0 mA
Output voltage VOH IOUT = -5.0 mA 2.4 – 2.4 – V
VOL IOUT = 4.2 mA – 0.4 – 0.4 V
CAS before RAS refresh
current ICC6 RAS or CAS cycling, tRC = min – 120 – 110 mA
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AC parameters common to all waveforms
Read cycle
Symbol Parameter
-50 -60
Unit NotesMinMaxMinMax
tRC Random read or write cycle time 80 – 100 – ns
tRP RAS precharge time 30 – 40 – ns
tRAS RAS pulse width 50 10K 60 10K ns
tCAS CAS pulse width 8 10K 10 10K ns
tRCD RAS to CAS delay time 15 35 15 43 ns 6
tRAD RAS to column address delay time 12 25 12 30 ns 7
tRSH CAS to RAS hold time 10 – 10 – ns
tCSH RAS to CAS hold time 40 – 50 – ns
tCRP CAS to RAS precharge time 5 – 5 – ns
tASR Row address setup time 0 – 0 – ns
tRAH Row address hold time 8 – 10 – ns
tTTransition time (rise and fall) 1 50 1 50 ns 4,5
tREF Refresh period – 32 – 32 ms 16
tCP CAS precharge time 8 – 10 – ns
tRAL Column address to RAS lead time 25 – 30 – ns
tASC Column address setup time 0 – 0 – ns
tCAH Column address hold time 8 10 – ns
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
tRAC Access time from RAS – 50 – 60 ns 6
tCAC Access time from CAS – 12 – 15 ns 6,13
tAA Access time from address – 25 – 30 ns 7,13
tRCS Read command setup time 0 – 0 – ns
tRCH Read command hold time to CAS 0–0–ns9
tRRH Read command hold time to RAS 0–0–ns9
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Write cycle
Read-modify-write cycle
Refresh cycle
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
tWCS Write command setup time 0 – 0 – ns 11
tWCH Write command hold time 10 – 10 – ns 11
tWP Write command pulse width 10 – 10 – ns
tRW L Write command to RAS lead time 10 – 10 – ns
tCWL Write command to CAS lead time 8 – 10 – ns
tDS Data-in setup time 0 – 0 – ns 12
tDH Data-in hold time 8 – 10 – ns 12
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
tRW C Read-write cycle time 113 – 135 – ns
tRW D RAS to WE delay time 67 – 77 – ns 11
tCWD CAS to WE delay time 32 – 35 – ns 11
tAW D Column address to WE delay time 42 – 47 – ns 11
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
tCSR CAS setup time (CAS-before-RAS)5–5–ns3
tCHR CAS hold time (CAS-before-RAS)8–10–ns3
tRPC RAS precharge to CAS hold time 0 – 0 – ns
tCPT CAS precharge time
(CBR counter test) 10 10 – ns
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Hyper page mode cycle
Output enable
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
tCPWD CAS precharge to WE delay time 45 – 52 – ns
tCPA Access time from CAS precharge – 28 – 35 ns 13
tRASP RAS pulse width 50 100K 60 100K ns
tDOH Previous data hold time from CAS 5–5–ns
tREZ Output buffer turn off delay from RAS 013015ns
tWEZ Output buffer turn off delay from WE 013015ns
tOEZ Output buffer turn off delay from OE 013015ns
tHPC Hyper page mode cycle time 20 – 25 – ns
tHPRWC Hyper page mode RMW cycle 47 – 56 – ns
tRHCP RAS hold time from CAS 30 – 35 – ns
Symbol Parameter
-50 -60
Unit NotesMin Max Min Max
tCLZ CAS to output in Low Z 0 – 0 – ns 8
tROH RAS hold time referenced to OE 8–10–ns
tOEA OE access time – 13 – 15 ns
tOED OE to data delay 13 – 15 – ns
tOEZ Output buffer turnoff delay from OE 013015ns8
tOEH OE command hold time 10 – 10 – ns
tOLZ OE to output in Low Z 0 – 0 – ns
tOFF Output buffer turn-off time 0 13 0 15 ns 8,10
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Notes
1I
CC1, ICC3, ICC4, and ICC6 are dependent on frequency.
2I
CC1 and ICC4 depend on output loading. Specified values are obtained with the output open.
3 An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
4 AC Characteristics assume tT = 2 ns. All AC parameters are measured with a load equivalent to two TTL loads and 100 pF, VIL (min) ≥ GND and VIH
(max) ≤ VCC.
5V
IH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL.
6 Operation within the tRCD (max) limit insures that tRAC (max) can be met. tRCD (max) is specified as a reference point only. If tRCD is greater than the
specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
7 Operation within the tRAD (max) limit insures that tRAC (max) can be met. tRAD (max) is specified as a reference point only. If tRAD is greater than the
specified tRAD (max) limit, then access time is controlled exclusively by tAA.
8 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
9Either t
RCH or tRRH must be satisfied for a read cycle.
10 tOFF (max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. tOFF is referenced from
rising edge of RAS or CAS, whichever occurs last.
11 tWCS, tWCH, tRW D, tCWD and tAW D are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
If tWS ≥ tWS (min) and tWH ≥ tWH (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
cycle. If tRW D ≥ tRW D (min), tCWD ≥ tCWD (min) and tAWD ≥ tAW D (min), the cycle is a read-write cycle and the data out will contain data read from the
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
12 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
13 Access time is determined by the longest of tCAA or tCAC or tCPA
14 tASC ≥ tCP to achieve tPC (min) and tCPA (max) values.
15 These parameters are sampled and not 100% tested.
16 These characteristics apply to AS4C4M4E1 5V devices.
AC test conditions
Key to switching waveforms
- Access times are measured with output reference levels of VOH =
2.4V and VOL = 0.4V,
VIH = 2.4V and VIL = 0.8V
- Input rise and fall times: 2 ns
*including scope
and jig capacitance
50 pF* R2 = 295Ω
R1 = 828Ω
Dout
GND
+3.3V
Figure A: Equivalent output load
(AS4LC4M4E1)
Undefined output/don’t careFalling inputRising input
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Read waveform
Early write waveform
tRAS
tRC
tRP
tRSH
tRAD
tRCH
tROH
tCAC
tOEA tOFF (see note 11)
tOEZ
RAS
CAS
Address
WE
OE
DQ
Column address
tCRP
tCSH
tRCD
tASC tCAH
tCAS
tRAL
tRAH
tRCS
tAA
tCLZ
tRRH
Data out
tRAC
tASR
Row address
tROH
tWEZ
tOLZ
tREZ
tRAS
tRC
tRP
tCRP
tRSH
tRCD
tCSH
tCAS
tRAD
tASC
tCAH
tWCS
tCWL
tRW L
tWCH
tWP
tDS tDH
Data in
RAS
CAS
Address
WE
OE
DQ
Row address
tRAL
Column address
tRAH
tASR
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Write waveform OE controlled
Read-modify-write waveform
Row address
tRAS
tRC
tRP
tCRP
tRSH
tRCD
tCSH
tCAS
tRAH
tRAL
tRAD
tCAH
tCWL
tRWL
tOEH
tDS tDH
Data in
RAS
CAS
Address
WE
OE
DQ
Column address
tWP
tASC
tASR
tOED
tRAS
tRW C
tRP
tCRP tRSH
tRCD
tCSH
tCAS
tRAD
tRAL
tAR
tCAH
tCWL
tCWD
tRW L
tAW D
tWP
tOEA
tCLZ
tCAC
tAA
tDS
tDH
Row address Column address
Data inData out
RAS
CAS
Address
WE
OE
DQ
tRAH
tRWD
tRCS
tRAC
tOEZ
tOED
tASC
tASR
tOLZ
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EDO page mode read waveform
EDO page mode early write waveform
Row
tRASP tRP
tCRP tRCD tCAS
tCSH tRSH
tHPC
tASR
tRAD
tRRH
tOEA tOEA
tAA
tRAC
tCAC
tOEZ
Data out Data out Data out
Col address Col address
RAS
CAS
Address
WE
OE
DQ
tAR
tRAH tASC tCAH
tRAL
tRCS
tCLZ
tCP
tOFF
tOEZ
Col address
tRCH
tCPA
tRHCP
tCLZ tCLZ
tOLZ
tCPA
tRAH
tRASP
tRW L
tASC
tWCS tCP
tRAL
tWCH
tCWL
tWP
tDS tDH
tOED
tCAS
Col address Col address Col address
Data in Data In Data in
RAS
CAS
Address
WE
OE
DQ
tPC
tCAH
tCSH
tRCD
tOEH
tHDR
tAR
tRAD
tASR
tCRP
tRSH
Row address
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EDO page mode read-modify-write waveform
CAS before RAS refresh waveform WE = A = VIH or VIL
RAS only refresh waveform WE = OE = VIH or VIL
tRASP tRP
tRCD
tCSH
tCAS tCP tCRP
tASR
tCAH tCAH
tRAL
tCAH
tCWD
tAWD
tCWD tCWL
tCWD
tAWD
tRW L
tWP
tOEZ tOEA
tRAC tDS
tCLZ
tCAC
tCPA
Row ad Col ad Col addressCol ad
Data out
Data inData in
Data outData out
Data in
RAS
CAS
Address
WE
OE
DQ
tRAD
tRAH
tRWD
tRCS
tCWL
tOEA
tAA tDH
tDS
tCLZ
tCAC
tCLZ
tCAC
tOED
tHPRWC
tCPWD
tASC tASC
tASC
tRP
tRC
tRAS
tRPC
tCP
tCSR
tCHR
RAS
CAS
DQ OPEN
tRAS tRP
tRC
tCRP tRPC
tASR tRAH
Row address
RAS
Address
CAS
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Hidden refresh waveform (read)
Hidden refresh waveform (write)
tRAS
tRC
tRP tRAS
tRC
tRP
tCRP
tRCD tRSH tCRP
tCHR
tASR
tRAD
tASC
tRRH
tOEA
tCLZ
tCAC
tOEZ
Col addressRow
Data out
RAS
CAS
Address
WE
OE
DQ
tAR
tRAH
tRAC
tAA
tRCS
tCAH
tOFF
tRAS
tRC
tRP
tCRP tRCD tRSH
tASR
tRAH
tRAD
tAR
tCAH
tWCS tWCH
tDS tDH
Data in
Col addressRow address
RAS
CAS
Address
WE
DQ
OE
tASC
tRWL
tWCR
tWP
tDHR
tRAL
tCHR
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CAS before RAS refresh counter test waveform
tRAS
tRSH tRP
tCSR
tCHR
tCPT
tCAS
tCAH
tCLZ
tCAC
tRCH
tRRH
tROH
tOEA
tRWL
tCWL
tWCS
tWP
tWCH
tDS
tDH
tRCS
tOEA
tDS
tDH
Col address
Data out
Data in
Data out Data in
RAS
CAS
Address
DQ
WE
OE
WE
DQ
OE
WE
OE
DQ
tOED
t AA
tCLZ
tCAC
tOEZ
tWP
tCWL
tRCS
tAA
tOEZ
tAWD
tCWD
tRAL
Read cycleWrite cycleRead-Write cycle
tASC
tOFF
tRWL
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© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the
trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in
this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product
described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and
users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product
described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or
infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to
Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the
user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
Capacitance 15 ƒ = 1 MHz, Ta = Room temperature
AS4C4M4E1 ordering information
AS4C4M4E1 family part numbering system
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN1 A0 to A10 Vin = 0V 5 pF
CIN2 RAS, CAS, WE, OE Vin = 0V 7 pF
DQ capacitance CDQ DQ0 to DQ3 Vin = Vout = 0V 7 pF
Package \ RAS access time 50 ns 60 ns
Plastic SOJ, 300 mil, 24/26-pin 5V AS4C4M4E1-50JC
AS4C4M4E1-50JI
AS4C4M4E1-60JC
AS4C4M4E1-60JI
Plastic TSOP, 300 mil, 24/26-pin 5V AS4C4M4E1-50TC
AS4C4M4E1-50TI
AS4C4M4E1-60TC
AS4C4M4E1-60TI
AS4 C 4M4 E1 –XX X X
DRAM
prefix C = 5V CMOS 4M×4 E1=2K refresh RAS access
time
Package:
J = SOJ 300 mil, 24/26
T = TSOP 300 mil, 24/26
Temperature range
C=Commercial, 0°C to 70°C
I=Industrial, -40°C to 85°C
