MC14076BDR2 - ON Semiconductor

September, 2009 − Rev. 6

1Publication Order Number:

MC14076B/D

MC14076B

4-Bit D-Type Register

with Three-State Outputs

The MC14076B 4−Bit Register consists of four D−type flip−flops

operating synchronously from a common clock. OR gated

output−disable inputs force the outputs into a high−impedance state

for use in bus organized systems. OR gated data−disable inputs cause

the Q outputs to be fed back to the D inputs of the flip−flops. Thus they

are inhibited from changing state while the clocking process remains

undisturbed. An asynchronous master root is provided to clear all four

flip−flops simultaneously independent of the clock or disable inputs.

Features

•Three−State Outputs with Gated Control Lines

•Fully Independent Clock Allows Unrestricted Operation for the Two

Modes: Parallel Load and Do Nothing

•Asynchronous Master Reset

•Four Bus Buffer Registers

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Capable of Driving Two Low−Power TTL Loads or One Low−Power

Schottky TTL Load Over the Rated Temperature Range

•These are Pb−Free Devices*

MAXIMUM RATINGS (Voltages Referenced to VSS)

Symbol Parameter Value Unit

VDD DC Supply Voltage Range −0.5 to +18.0 V

Vin, Vout Input or Output Voltage Range

(DC or Transient)

−0.5 to VDD + 0.5 V

Iin, Iout Input or Output Current

(DC or Transient) per Pin

±10 mA

PDPower Dissipation, per Package

(Note 1)

500 mW

TAAmbient Temperature Range −55 to +125 °C

Tstg Storage Temperature Range −65 to +150 °C

TLLead Temperature

(8−Second Soldering)

260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

http://onsemi.com

MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

MC14076BCP

AWLYYWWG

SOIC−16

D SUFFIX

CASE 751B

14076BG

AWLYWW

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Package

See detailed ordering and shipping information in the package

dimensions section on page 3 of this data sheet.

ORDERING INFORMATION

16

1

16

MC14076B

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2

PIN ASSIGNMENT

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D1

D0

R

VDD

A

B

D3

Q1

B

A

VSS

C

Q3

Q2

Q0

OUTPUT

DISABLE

DATA

DISABLE

{

}

BLOCK DIAGRAM

15

14

13

12

11

10

9

7

2

1

3

4

5

6

RESET

D0

D1

D2

D3

B

A

CLOCK

B

A

DATA

DISABLE

OUTPUT

DISABLE

VDD = PIN 16

VSS = PIN 8

Q0

Q1

Q2

Q3

FUNCTION TABLE

Inputs

Output

Q

Reset Clock

Data Disable Data

D

A B

1 X X X X 0

0 0 X X X Qn

0 1 X X Qn

0 X 1 X Qn

0 0 0 0 0

0 0 0 1 1

When either output disable A or B (or both) is (are) high the

output is disabled to the high−impedance state; however

sequential operation of the flip−flops is not affected.

X = Don’t Care.

MC14076B

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3

ORDERING INFORMATION

Device Package Shipping†

MC14076BCPG PDIP−16

(Pb−Free)

500 Units / Rail

MC14076BDG SOIC−16

(Pb−Free)

48 Units / Rail

MC14076BDR2G SOIC−16

(Pb−Free)

2500 Units / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

MC14076B

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4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ

(Note 2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

−

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

−

ÎÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎÎ

−

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎÎ

−

ÎÎÎ

±0.00001

ÎÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎ

± 1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

5.0

ÎÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

5.0

10

20

ÎÎÎÎ

−

ÎÎÎ

0.005

0.010

0.015

ÎÎÎÎ

5.0

10

20

ÎÎÎ

−

ÎÎÎ

150

300

600

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Notes 3, 4)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

ÎÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (0.75 mA/kHz) f + IDD

IT = (1.50 mA/kHz) f + IDD

IT = (2.25 mA/kHz) f + IDD

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Three−State Leakage Current

ÎÎÎÎ

ITL

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎÎ

−

ÎÎÎ

± 0.0001

ÎÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎ

± 3.0

ÎÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF:

IT(CL) = IT(50 pF) + (CL – 50) Vfk

where: IT is in mA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.002.

MC14076B

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5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 6)

ÎÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Time

tTLH, tTHL = (1.5 ns/pF) CL + 25 ns

tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns

tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns

ÎÎÎÎÎ

tTLH, tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time

Clock to Q

tPLH, tPHL = (1.7 ns/pF) CL + 215 ns

tPLH, tPHL = (0.66 ns/pF) CL + 92 ns

tPLH, tPHL = (0.5 ns/pF) CL + 65 ns

Reset to Q

tPLH, tPHL = (1.7 ns/pF) CL + 215 ns

tPLH, tPHL = (0.66 ns/pF) CL + 92 ns

tPLH, tPHL = (0.5 ns/pF) CL + 65 ns

ÎÎÎÎÎ

tPLH, tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

300

125

90

ÎÎÎÎ

600

250

180

ÎÎÎ

ns

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

300

125

90

ÎÎÎÎ

600

250

180

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

3−State Propagation Delay, Output “1” or “0”

to High Impedance

ÎÎÎÎÎ

tPHZ, tPLZ

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

150

60

45

ÎÎÎÎ

300

120

90

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

3−State Propagation Delay, High Impedance

to “1” or “0” Level

ÎÎÎÎÎ

tPZH, tPZL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

200

80

60

ÎÎÎÎ

400

160

120

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Width

ÎÎÎÎÎ

tWH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

260

110

80

ÎÎÎÎ

130

55

40

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset Pulse Width

ÎÎÎÎÎ

tWH

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

370

150

110

ÎÎÎÎ

185

75

55

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Data Setup Time

ÎÎÎÎÎ

tsu

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

30

10

4

ÎÎÎÎ

15

5

2

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Data Hold Time

ÎÎÎÎÎ

th

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

130

60

50

ÎÎÎÎ

65

30

25

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Data Disable Setup Time

ÎÎÎÎÎ

tsu

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

220

80

50

ÎÎÎÎ

110

40

25

ÎÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Rise and Fall Time

ÎÎÎÎÎ

tTLH, tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎÎ

15

5

4

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Frequency

ÎÎÎÎÎ

fcl

ÎÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎÎ

3.6

9.0

12

ÎÎÎÎ

1.8

4.5

6.0

ÎÎÎ

MHz

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14076B

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6

Figure 1. Timing Diagram

INPUT RISE AND FALL 20 ns

DINPUT

INFORMATION

VDD

VSS

VOH

VOL

VDD

Q OUTPUT

90%

50%

10%

tsu

thtsu

th

20ns

90%

10%

50%

90%

10%

tTLH

tPHL

tTHL

50%

tWH tWL

fcl

RESET = 0

DATA DISABLE A AND B = 0

OUTPUT DISABLE A AND B = 0

Figure 2. Three−State Propagation Delay

Waveshape and Circuit

MC14076B

OTHER

INPUTS

OUTPUT

DISABLE

A OR B

ANY Q

OUTPUT

RL = 1 kW

CL

VDD FOR tPLZ AND tPZL

VSS FOR tPHZ AND tPZH

OUTPUT

DISABLE

A OR B

ANY Q

OUTPUT

ANY Q

OUTPUT

20ns 20ns

VDD

VSS

VOH

90%

50%

50% 10%

tPLZ tPZL

90%

tPZH

tPHZ

90%

10%

≈2.5 V @ VDD = 5 V,

10 V, AND 15 V

≈2 V @ VDD = 5 V

≈6 V @ VDD = 10 V

≈10 V @ VDD = 15 V

VOL

OUTPUTS

CONNECTED

OUTPUTS

DISCONNECTED

OUTPUTS

CONNECTED

tPLH

EQUIVALENT

FUNCTIONAL BLOCK DIAGRAM

OUTPUT DISABLE A

OUTPUT DISABLE B

D0

1

2

14

DATA DISABLE A

DATA DISABLE B

9

10

D1 13

CLOCK 7

D2 12

D3 11

RESET 15

6Q3

5Q2

4Q1

3Q0

DQ

R

CQ

DQ

R

CQ

DQ

R

CQ

DQ

R

CQ

MC14076B

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7

PACKAGE DIMENSIONS

PDIP−16

P SUFFIX

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

MC14076B

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8

PACKAGE DIMENSIONS

SOIC−16

D SUFFIX

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL

IN EXCESS OF THE D DIMENSION AT

MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

89

8X

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

MC14076B/D

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