Device Operating
Temperature Range Package
HIGH PERFORMANCE
CURRENT MODE
CONTROLLERS
ORDERING INFORMATION
UC3842AD
UC3843AD TA = 0° to +70°C
TA = – 25° to +85°C
SO–14
SO–14
PIN CONNECTIONS
Order this document by UC3842A/D
D SUFFIX
PLASTIC PACKAGE
CASE 751A
(SO–14)
N SUFFIX
PLASTIC PACKAGE
CASE 626
1
8
1
14
(Top V iew)
Vref
(Top V iew)
Compensation
V oltage Feedback
Current Sense
RT/CT
Vref
VCC
Output
Gnd
1
2
3
45
6
7
8
Compensation
NC
V oltage Feedback
NC
Current Sense
NC
RT/CT
NC
VCC
VC
Output
Gnd
Power Ground
1
2
3
4
5
6
7
9
8
10
11
12
13
14
UC3842AN
UC3843AN
Plastic
Plastic
UC2842AD
UC2843AD
SO–14
SO–14
UC2842AN
UC2843AN
Plastic
Plastic
1
MOTOROLA ANALOG IC DEVICE DATA
The UC3842A, UC3843A series of high performance fixed frequency
current mode controllers are specifically designed for off–line and dc–to–dc
converter applications offering the designer a cost effective solution with
minimal external components. These integrated circuits feature a trimmed
oscillator for precise duty cycle control, a temperature compensated
reference, high gain error amplifier, current sensing comparator, and a high
current totem pole output ideally suited for driving a power MOSFET.
Also included are protective features consisting of input and reference
undervoltage lockouts each with hysteresis, cycle–by–cycle current limiting,
programmable output deadtime, and a latch for single pulse metering.
These devices are available in an 8–pin dual–in–line plastic package as
well as the 14–pin plastic surface mount (SO–14). The SO–14 package has
separate power and ground pins for the totem pole output stage.
The UCX842A has UYLO thresholds of 16 V (on) and 10 V (off), ideally
suited for off–line converters. The UCX843A is tailored for lower voltage
applications having UVLO thresholds of 8.5 V (on) and 7.6 V (off).
•Trimmed Oscillator Discharge Current for Precise Duty Cycle Control
•Current Mode Operation to 500 kHz
•Automatic Feed Forward Compensation
•Latching PWM for Cycle–By–Cycle Current Limiting
•Internally Trimmed Reference with Undervoltage Lockout
•High Current Totem Pole Output
•Undervoltage Lockout with Hysteresis
•Low Startup and Operating Current
•Direct Interface with Motorola SENSEFET Products
Simplified Block Diagram
5.0V
Reference
Latching
PWM
VCC
Undervoltage
Lockout
Oscillator
Error
Amplifier
7(12)
VC
7(11)
Output
6(10)
Power
Ground
5(8)
3(5)
Current
Sense
Input
Vref
8(14)
4(7)
2(3)
1(1) Gnd 5(9)
RTCT
Voltage
Feedback
Input
R
R
+
–
Vref
Undervoltage
Lockout
Output
Compensation
Pin numbers in parenthesis are for the D suffix SO–14 package.
VCC
Motorola, Inc. 1996 Rev 1
UC3842A, 43A UC2842A, 43A
2MOTOROLA ANALOG IC DEVICE DATA
MAXIMUM RATINGS
Rating Symbol Value Unit
Total Power Supply and Zener Current (ICC + IZ)30 mA
Output Current, Source or Sink (Note 1) IO1.0 A
Output Energy (Capacitive Load per Cycle) W 5.0 µJ
Current Sense and Voltage Feedback Inputs Vin – 0.3 to + 5.5 V
Error Amp Output Sink Current IO10 mA
Power Dissipation and Thermal Characteristics
D Suffix, Plastic Package
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
N Suffix, Plastic Package
Maximum Power Dissipation @ TA = 25°C
Thermal Resistance, Junction–to–Air
PD
RθJA
PD
RθJA
862
145
1.25
100
mW
°C/W
W
°C/W
Operating Junction Temperature TJ+ 150 °C
Operating Ambient Temperature
UC3842A, UC3843A
UC2842A, UC2843A
TA0 to + 70
– 25 to + 85
°C
Storage Temperature Range Tstg – 65 to + 150 °C
ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
UC284XA UC384XA
Characteristics Symbol Min Typ Max Min Typ Max Unit
REFERENCE SECTION
Reference Output Voltage (IO = 1.0 mA, TJ = 25°C) Vref 4.95 5.0 5.05 4.9 5.0 5.1 V
Line Regulation (VCC = 12 V to 25 V) Regline –2.0 20 – 2.0 20 mV
Load Regulation (IO = 1.0 mA to 20 mA) Regload –3.0 25 – 3.0 25 mV
Temperature Stability TS– 0.2 – – 0.2 – mV/°C
Total Output Variation over Line, Load, Temperature V ref 4.9 – 5.1 4.82 – 5.18 V
Output Noise Voltage (f = 10 Hz to 10 kHz, TJ = 25°C) Vn– 50 – – 50 – µV
Long Term Stability (TA = 125°C for 1000 Hours) S – 5.0 – – 5.0 – mV
Output Short Circuit Current ISC – 30 – 85 – 180 – 30 – 85 – 180 mA
OSCILLATOR SECTION
Frequency
TJ = 25°C
TA = Tlow to Thigh
fosc 47
46 52
–57
60 47
46 52
–57
60
kHz
Frequency Change with Voltage (VCC = 12 V to 25 V) ∆fosc/∆V–0.2 1.0 – 0.2 1.0 %
Frequency Change with Temperature
TA = Tlow to Thigh ∆fosc/∆T–5.0 – – 5.0 – %
Oscillator V oltage Swing (Peak–to–Peak) Vosc –1.6 – – 1.6 – V
Discharge Current (Vosc = 2.0 V)
TJ = 25°C
TA = Tlow to Thigh
Idischg 7.5
7.2 8.4
–9.3
9.5 7.5
7.2 8.4
–9.3
9.5
mA
NOTES: 1.Maximum Package power dissipation limits must be observed.
2.Adjust VCC above the Startup threshold before setting to 15 V.
3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible
Tlow =–20°C for UC3842A, UC3843A Thigh = +70°C for UC3842A, UC3843A
Tlow =–25°C for UC2842A, UC2843A Thigh =+85°C for UC2842A, UC2843A
UC3842A, 43A UC2842A, 43A
3
MOTOROLA ANALOG IC DEVICE DATA
ELECTRICAL CHARACTERISTICS (VCC = 15 V, [Note 2], RT = 10 k, CT = 3.3 nF, TA = Tlow to Thigh [Note 3],
unless otherwise noted.)
UC284XA UC384XA
Characteristics Symbol Min Typ Max Min Typ Max Unit
ERROR AMPLIFIER SECTION
Voltage Feedback Input (VO = 2.5 V) VFB 2.45 2.5 2.55 2.42 2.5 2.58 V
Input Bias Current (VFB = 2.7 V) IIB ––0.1 –1.0 – –0.1 –2.0 µA
Open Loop Voltage Gain (VO = 2.0 V to 4.0 V) AVOL 65 90 – 65 90 – dB
Unity Gain Bandwidth (TJ = 25°C) BW 0.7 1.0 – 0.7 1.0 – MHz
Power Supply Rejection Ratio (VCC = 12 V to 25 V) PSRR 60 70 – 60 70 – dB
Output Current
Sink (VO = 1.1 V, VFB = 2.7 V)
Source (VO = 5.0 V, VFB = 2.3 V) ISink
ISource 2.0
–0.5 12
–1.0 –
–2.0
–0.5 12
–1.0 –
–
mA
Output Voltage Swing
High State (RL = 15 k to ground, VFB = 2.3 V)
Low State (RL = 15 k to Vref, VFB = 2.7 V) VOH
VOL 5.0
–6.2
0.8 –
1.1 5.0
–6.2
0.8 –
1.1
V
CURRENT SENSE SECTION
Current Sense Input Voltage Gain (Notes 4 & 5) AV2.85 3.0 3.15 2.85 3.0 3.15 V/V
Maximum Current Sense Input Threshold (Note 4) Vth 0.9 1.0 1.1 0.9 1.0 1.1 V
Power Supply Rejection Ratio
VCC = 12 to 25 V (Note 4) PSRR – 70 – – 70 – dB
Input Bias Current IIB ––2.0 –10 – –2.0 –10 µA
Propagation Delay (Current Sense Input to Output) tPLH(in/out) –150 300 – 150 300 ns
OUTPUT SECTION
Output Voltage
Low State (ISink = 20 mA)
Low State (ISink = 200 mA)
High State (ISink = 20 mA)
High State (ISink = 200 mA)
VOL
VOH
–
–
13
12
0.1
1.6
13.5
13.4
0.4
2.2
–
–
–
–
13
12
0.1
1.6
13.5
13.4
0.4
2.2
–
–
V
Output Voltage with UVLO Activated
VCC = 6.0 V, ISink = 1.0 mA VOL(UVLO) – 0.1 1.1 – 0.1 1.1 V
Output Voltage Rise Time (CL = 1.0 nF, TJ = 25°C) tr– 50 150 – 50 150 ns
Output Voltage Fall Time (CL = 1.0 nF, TJ = 25°C) tf– 50 150 – 50 150 ns
UNDERVOLTAGE LOCKOUT SECTION
Startup Threshold
UCX842A
UCX843A
Vth 15
7.8 16
8.4 17
9.0 14.5
7.8 16
8.4 17.5
9.0
V
Minimum Operating Voltage After T urn–On
UCX842A
UCX843A
VCC(min) 9.0
7.0 10
7.6 11
8.2 8.5
7.0 10
7.6 11.5
8.2
V
PWM SECTION
Duty Cycle
Maximum
Minimum DCmax
DCmin 94
–96
––
094
–96
––
0
%
TOTAL DEVICE
Power Supply Current (Note 2)
Startup:
(VCC = 6.5 V for UCX843A,
(VCC = 14 V for UCX842A) Operating
ICC
–
–0.5
12 1.0
17 –
–0.5
12 1.0
17
mA
Power Supply Zener Voltage (ICC = 25 mA) VZ30 36 – 30 36 – V
NOTES: 2.Adjust VCC above the Startup threshold before setting to 15 V.
3.Low duty cycle pulse techniques are used during test to maintain junction temperature as close to ambient as possible
Tlow =–20°C for UC3842A, UC3843A Thigh = +70°C for UC3842A, UC3843A
Tlow =–25°C for UC2842A, UC2843A Thigh =+85°C for UC2842A, UC2843A
4.This parameter is measured at the latch trip point with VFB = 0 V.
5.Comparator gain is defined as: AV∆V Output Compensation
∆V Current Sense Input
UC3842A, 43A UC2842A, 43A
4MOTOROLA ANALOG IC DEVICE DATA
RT
Ω
, TIMING RESISTOR (k )
Figure 1. Timing Resistor versus
Oscillator Frequency Figure 2. Output Deadtime versus
Oscillator Frequency
Figure 3. Oscillator Discharge Current
versus Temperature Figure 4. Maximum Output Duty Cycle
versus Timing Resistor
Figure 5. Error Amp Small Signal
Transient Response Figure 6. Error Amp Large Signal
Transient Response
0.5
µ
s/DIV
20 mV/DIV
VCC = 15 V
AV = –1.0
TA = 25
°
C
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
fOSC, OSCILLATOR FREQUENCY (Hz)
VCC = 15 V
TA = 25
°
C
10 k 20 k 50 k 100 k 200 k 500 k 1.0 M
fOSC, OSCILLATOR FREQUENCY (Hz)
% DT, PERCENT OUTPUT DEADTIME
VCC = 15 V
TA = 25
°
C
–55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (
°
C)
, DISCHARGE CURRENT (mA)
dischg
I
VCC = 15 V
VOSC = 2.0 V
RT, TIMING RESISTOR (
Ω
)
800 1.0 k 2.0 k 3.0 k 4.0 k 6.0 k 8.0 k
, MAXIMUM OUTPUT DUTY CYCLE (%)
max
D
VCC = 15 V
CT = 3.3 nF
TA = 25
°
C
Idischg = 9.5 mA
Idischg = 7.2 mA
2.55 V
2.5 V
2.45 V
VCC = 15 V
AV = –1.0
TA = 25
°
C
0.1
µ
s/DIV
200 mV/DIV
2.5 V
3.0 V
2.0 V
80
50
20
8.0
5.0
2.0
0.8
100
50
20
10
5.0
2.0
1.0
9.0
8.5
8.0
7.5
7.0
100
90
80
70
60
50
40
UC3842A, 43A UC2842A, 43A
5
MOTOROLA ANALOG IC DEVICE DATA
Figure 7. Error Amp Open Loop Gain and
Phase versus Frequency Figure 8. Current Sense Input Threshold
versus Error Amp Output Voltage
Figure 9. Reference Voltage Change
versus Source Current Figure 10. Reference Short Circuit Current
versus Temperature
Figure 11. Reference Load Regulation Figure 12. Reference Line Regulation
∆
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
O
2.0 ms/DIV
V
∆
, OUTPUT VOLTAGE CHANGE (2.0 mV/DIV)
O
2.0 ms/DIV
V
VCC = 12 V to 25 V
TA = 25
°
C
∆
, REFERENCE VOLTAGE CHANGE (mV)
ref
0 20 40 60 80 100 120
Iref, REFERENCE SOURCE CURRENT (mA)
V
VCC = 15 V
TA = 55
°
C
TA = 125
°
C
, REFERENCE SHORT CIRCUIT CURRENT (mA)
SC
–55 –25 0 25 50 75 100 125
TA, AMBIENT TEMPERATURE (
°
C)
VCC = 15 V
RL
≤
0.1
Ω
I
VCC = 15 V
IO = 1.0 mA to 20 mA
TA = 25
°
C
0
–4.0
–8.0
–12
–16
–20
–24
110
90
70
50
TA = 25
°
C
–20
AVOL, OPEN LOOP VOLTAGE GAIN (dB)
10 M10 f, FREQUENCY (Hz)
Gain
Phase
VCC = 15 V
VO = 2.0 V to 4.0 V
RL = 100 K
TA = 25
°
C
0
30
60
90
120
150
180
100 1.0 k 10 k 100 k 1.0 M
0
20
40
60
80
100
, EXCESS PHASE (DEGREES)
φ
0VO, ERROR AMP OUTPUT VOLTAGE (V)
0
, CURRENT SENSE INPUT THRESHOLD (V)
Vth
0.2
0.4
0.6
0.8
1.0
1.2
2.0 4.0 6.0 8.0
VCC = 15 V
TA = 25
°
C
TA = –55
°
C
TA = 125
°
C
UC3842A, 43A UC2842A, 43A
6MOTOROLA ANALOG IC DEVICE DATA
Figure 13. Output Saturation Voltage
versus Load Current Figure 14. Output Waveform
Figure 15. Output Cross Conduction Figure 16. Supply Current versus
Supply Voltatage
50 ns/DIV
VCC = 15 V
CL = 1.0 nF
TA = 25
°
C
100 ns/DIV
VCC = 30 V
CL = 15 pF
TA = 25
°
C
, SUPPLY CURRENT
100 mA/DIV 20 V/DIV
I, OUTPUT VOLTAGEV
CC O
8006004002000 IO, OUTPUT LOAD CURRENT (mA)
, OUTPUT SATURATION VOLTAGE (V)
sat
V
VCC
TA = 25
°
C
TA = –55
°
C
Gnd
TA = 25
°
C
Source Saturation
(Load to Ground)
TA = –55
°
C
VCC = 15 V
80
µ
s Pulsed Load
120 Hz Rate
010203040
, SUPPLY CURRENT (mA)
CC
VCC , SUPPLY VOLTAGE
I
RT = 10 k
CT = 3.3 nF
VFB = 0 V
ISense = 0 V
TA = 25
°
C
UCX843A
UCX842A
90%
10%
0
1.0
2.0
3.0
–2.0
–1.0
0
25
20
15
10
5
0
Sink Saturation
(Load to VCC)
UC3842A, 43A UC2842A, 43A
7
MOTOROLA ANALOG IC DEVICE DATA
+
–
Sink Only
Positive True Logic
=
RS
+
Internal
Bias
Reference
Regulator
Oscillator
S
RQ
–Vref
UVLO
3.6V
36V
VCC 7(12)
Q1
Vin
VCC
VC
7(11)
6(10)
5(8)
3(5)
+
1.0mA
Error
Amplifier
1(1)
2(3)
4(7)
8(14)
5(9)Gnd
Output
Compensation
Voltage Feedback
Input
RT
CT
Vref
–
–
PWM
Latch
Current Sense
Comparator
R
R
Power Ground
Current Sense Input
2R R1.0V
Pin numbers in parenthesis are for the D suffix SO–14 package.
QT
+
–
+
+
–
+
–
+
VCC
UVLO
Output
2.5V
Figure 17. Representative Block Diagram
Output/
Compensation
Current Sense
Input
Latch
‘‘Reset’ ’ Input
Output
Capacitor CT
Latch
‘‘Set’ ’ Input
Large RT/Small CTSmall R T/Large CT
Figure 18. Timing Diagram
UC3842A, 43A UC2842A, 43A
8MOTOROLA ANALOG IC DEVICE DATA
OPERATING DESCRIPTION
The UC3842A, UC3843A series are high performance,
fixed frequency, current mode controllers. They are
specifically designed for Off–Line and dc–to–dc converter
applications offering the designer a cost effective solution
with minimal external components. A representative block
diagram is shown in Figure 17.
Oscillator
The oscillator frequency is programmed by the values
selected for the timing components RT and CT. Capacitor CT
is charged from the 5.0 V reference through resistor RT to
approximately 2.8 V and discharged to 1.2 V by an internal
current sink. During the discharge of CT, the oscillator
generates and internal blanking pulse that holds the center
input of the NOR gate high. This causes the Output to be in
a low state, thus producing a controlled amount of output
deadtime. Figure 1 shows RT versus Oscillator Frequency
and Figure 2, Output Deadtime versus Frequency, both for
given values of CT. Note that many values of RT and CT will
give the same oscillator frequency but only one combination
will yield a specific output deadtime at a given frequency . The
oscillator thresholds are temperature compensated, and the
discharge current is trimmed and guaranteed to within ± 10%
at TJ = 25°C. These internal circuit refinements minimize
variations of oscillator frequency and maximum output duty
cycle. The results are shown in Figures 3 and 4.
In many noise sensitive applications it may be desirable to
frequency–lock the converter to an external system clock.
This can be accomplished by applying a clock signal to the
circuit shown in Figure 20. For reliable locking, the
free–running oscillator frequency should be set about 10%
less than the clock frequency. A method for multi unit
synchronization is shown in Figure 21. By tailoring the clock
waveform, accurate Output duty cycle clamping can be
achieved.
Error Amplifier
A fully compensated Error Amplifier with access to the
inverting input and output is provided. It features a typical dc
voltage gain of 90 dB, and a unity gain bandwidth of 1.0 MHz
with 57 degrees of phase margin (Figure 7). The noninverting
input is internally biased at 2.5 V and is not pinned out. The
converter output voltage is typically divided down and
monitored by the inverting input. The maximum input bias
current is –2.0 µA which can cause an output voltage error
that is equal to the product of the input bias current and the
equivalent input divider source resistance.
The Error Amp Output (Pin 1) is provide for external loop
compensation (Figure 30). The output voltage is offset by two
diode drops (≈ 1.4 V) and divided by three before it connects
to the inverting input of the Current Sense Comparator. This
guarantees that no drive pulses appear at the Output (Pin 6)
when Pin 1 is at its lowest state (VOL). This occurs when the
power supply is operating and the load is removed, or at the
beginning of a soft–start interval (Figures 23, 24). The Error
Amp minimum feedback resistance is limited by the
amplifier’s source current (0.5 mA) and the required output
voltage (VOH) to reach the comparator’s 1.0 V clamp level:
Rf(min) ≈3.0 (1.0 V) + 1.4 V
0.5 mA = 8800 Ω
Current Sense Comparator and PWM Latch
The UC3842A, UC3843A operate as a current mode
controller, whereby output switch conduction is initiated by
the oscillator and terminated when the peak inductor current
reaches the threshold level established by the Error Amplifier
Output/Compensation (Pin1). Thus the error signal controls
the peak inductor current on a cycle–by–cycle basis. The
current Sense Comparator PWM Latch configuration used
ensures that only a single pulse appears at the Output during
any given oscillator cycle. The inductor current is converted
to a voltage by inserting the ground referenced sense resistor
RS in series with the source of output switch Q1. This voltage
is monitored by the Current Sense Input (Pin 3) and
compared a level derived from the Error Amp Output. The
peak inductor current under normal operating conditions is
controlled by the voltage at pin 1 where:
Ipk = V(Pin 1) – 1.4 V
3 RS
Abnormal operating conditions occur when the power
supply output is overloaded or if output voltage sensing is
lost. Under these conditions, the Current Sense Comparator
threshold will be internally clamped to 1.0 V. Therefore the
maximum peak switch current is:
Ipk(max) = 1.0 V
RS
When designing a high power switching regulator it
becomes desirable to reduce the internal clamp voltage in
order to keep the power dissipation of RS to a reasonable
level. A simple method to adjust this voltage is shown in
Figure 22. The two external diodes are used to compensate
the internal diodes yielding a constant clamp voltage over
temperature. Erratic operation due to noise pickup can result
if there is an excessive reduction of the Ipk(max) clamp
voltage.
A narrow spike on the leading edge of the current
waveform can usually be observed and may cause the power
supply to exhibit an instability when the output is lightly
loaded. This spike is due to the power transformer
interwinding capacitance and output rectifier recovery time.
The addition of an RC filter on the Current Sense Input with a
time constant that approximates the spike duration will
usually eliminate the instability; refer to Figure 26.
UC3842A, 43A UC2842A, 43A
9
MOTOROLA ANALOG IC DEVICE DATA
PIN FUNCTION DESCRIPTION
Pin
Fi
Dii
8–Pin 14–Pin Function Description
1 1 Compensation This pin is Error Amplifier output and is made available for loop compensation.
2 3 Voltage
Feedback This is the inverting input of the Error Amplifier. It is normally connected to the switching power
supply output through a resistor divider.
3 5 Current Sense A voltage proportional to inductor current is connected to this input. The PWM uses this
information to terminate the output switch conduction.
4 7 RT/CTThe Oscillator frequency and maximum Output duty cycle are programmed by connecting
resistor RT to Vref and capacitor CT to ground. Operation to 500 kHz is possible.
5 – Gnd This pin is the combined control circuitry and power ground (8–pin package only).
6 10 Output This output directly drives the gate of a power MOSFET. Peak currents up to 1.0 A are sourced
and sunk by this pin.
7 12 VCC This pin is the positive supply of the control IC.
8 14 Vref This is the reference output. It provides charging current for capacitor CT through
resistor RT.
– 8 Power Ground This pin is a separate power ground return (14–pin package only) that is connected back to the
power source. It is used to reduce the effects of switching transient noise on the control circuitry.
–11 VCThe Output high state (VOH) is set by the voltage applied to this pin (14–pin package only). With
a separate power source connection, it can reduce the effects of switching transient noise on the
control circuitry.
– 9 Gnd This pin is the control circuitry ground return (14–pin package only) and is connected back to the
power source ground.
– 2,4,6,13 NC No connection (14–pin package only). These pins are not internally connected.
Undervoltage Lockout
Two undervoltage lockout comparators have been
incorporated to guarantee that the IC is fully functional before
the output stage is enabled. The positive power supply
terminal (VCC) and the reference output (Vref) are each
monitored by separate comparators. Each has built–in
hysteresis to prevent erratic output behavior as their
respective thresholds are crossed. The VCC comparator
upper and lower thresholds are 16 V/10 V for the UCX842A,
and 8.4 V/7.6 V for the UCX843A. The V ref comparator upper
and lower thresholds are 3.6V/3.4 V. The large hysteresis
and low startup current of the UCX842A makes it ideally
suited in off–line converter applications where efficient
bootstrap startup techniques are required (Figure 33). The
UCX843A is intended for lower voltage dc to dc converter
applications. A 36 V zener is connected as a shunt regulator
form VCC to ground. Its purpose is to protect the IC from
excessive voltage that can occur during system startup. The
minimum operating voltage for the UCX842A is 11 V and
8.2 V for the UCX843A.
Output
These devices contain a single totem pole output stage
that was specifically designed for direct drive of power
MOSFETs. It is capable of up to ±1.0 A peak drive current and
has a typical rise and fall time of 50 ns with a 1.0 nF load.
Additional internal circuitry has been added to keep the
Output in a sinking mode whenever an undervoltage lockout
is active. This characteristic eliminates the need for an
external pull–down resistor.
The SO–14 surface mount package provides separate
pins for VC (output supply) and Power Ground. Proper
implementation will significantly reduce the level of switching
transient noise imposed on the control circuitry. This
becomes particularly useful when reducing the Ipk(max) clamp
level. The separate VC supply input allows the designer
added flexibility in tailoring the drive voltage independent of
VCC. A zener clamp is typically connected to this input when
driving power MOSFET s in systems where VCC is greater that
20 V. Figure 25 shows proper power and control ground
connections in a current sensing power MOSFET
application.
Reference
The 5.0 V bandgap reference is trimmed to ±1.0%
tolerance at TJ = 25°C on the UC284XA, and ± 2.0% on the
UC384XA. Its primary purpose is to supply charging current
to the oscillator timing capacitor. The reference has short
circuit protection and is capable of providing in excess of
20 mA for powering additional control system circuitry.
UC3842A, 43A UC2842A, 43A
10 MOTOROLA ANALOG IC DEVICE DATA
DESIGN CONSIDERATIONS
Do not attempt to construct the converter on
wire–wrap or plug–in prototype boards. High Frequency
circuit layout techniques are imperative to prevent pulsewidth
jitter. This is usually caused by excessive noise pick–up
imposed on the Current Sense or Voltage Feedback inputs.
Noise immunity can be improved by lowering circuit
impedances at these points. The printed circuit layout should
contain a ground plane with low–current signal and
high–current switch and output grounds returning on
separate paths back to the input filter capacitor. Ceramic
bypass capacitors (0.1 µF) connected directly to VCC, VC,
and V ref may be required depending upon circuit layout. This
provides a low impedance path for filtering the high frequency
noise. All high current loops should be kept as short as
possible using heavy copper runs to minimize radiated EMI.
The Error Amp compensation circuitry and the converter
output voltage divider should be located close to the IC and
as far as possible from the power switch and other noise
generating components.
Current mode converters can exhibit subharmonic
oscillations when operating at a duty cycle greater than 50%
with continuous inductor current. This instability is
independent of the regulators closed–loop characteristics
and is caused by the simultaneous operating conditions of
fixed frequency and peak current detecting. Figure 19A
shows the phenomenon graphically. At t0, switch conduction
begins, causing the inductor current to rise at a slope of m1.
This slope is a function of the input voltage divided by the
inductance. At t1, the Current Sense Input reaches the
threshold established by the control voltage. This causes the
switch to turn off and the current to decay at a slope of m2 until
the next oscillator cycle. The unstable condition can be
shown if a pertubation is added to the control voltage,
resulting in a small ∆I (dashed line). With a fixed oscillator
period, the current decay time is reduced, and the minimum
current at switch turn–on (t2) is increased by ∆I + ∆I m2/m1.
The minimum current at the next cycle (t3) decreases to (∆I +
∆I m2/m1) (m2/m1). This pertubation is multiplied by m2.m1 on
each succeeding cycle, alternately increasing and
decreasing the inductor current at switch turn–on. Several
oscillator cycles may be required before the inductor current
reaches zero causing the process to commence again. If
m2/m1 is greater than 1, the converter will be unstable. Figure
19B shows that by adding an artificial ramp that is
synchronized with the PWM clock to the control voltage, the
∆I pertubation will decrease to zero on succeeding cycles.
This compensation ramp (m3) must have a slope equal to or
slightly greater than m2/2 for stability. With m2/2 slope
compensation, the average inductor current follows the
control voltage yielding true current mode operation. The
compensating ramp can be derived from the oscillator and
added to either the Voltage Feedback or Current Sense
inputs (Figure 32).
Figure 19. Continuous Current Waveforms
(A)
(B)
t0t1t2t3
t4t5t6
Control Voltage
∆
Im1 m2
m3
m1 m2
Oscillator Period
Oscillator Period
Control Voltage
∆
I
Inductor
Current
∆
I +
∆
Im2
m1m2
m1
∆
I +
∆
Im2
m1
Inductor
Current
UC3842A, 43A UC2842A, 43A
11
MOTOROLA ANALOG IC DEVICE DATA
Figure 20. External Clock Synchronization Figure 21. External Duty Cycle Clamp and
Multi Unit Synchronization
Figure 22. Adjustable Reduction of Clamp Level Figure 23. Soft–Start Circuit
Figure 24. Adjustable Buffered Reduction of
Clamp Level with Soft–Start Figure 25. Current Sensing Power MOSFET
Virtually lossless current sensing can be achieved with the implementation of a
SENSEFET power switch. For proper operation during over current conditions, a
reduction of the Ipk(max) clamp level must be implemented. Refer to Figures 22 and 24.
The diode clamp is required if the Sync amplitude is large enough to
cause the bottom side of CT to go more than 300 mV below ground.
External
Sync
Input
47
5(9)
R
RBias
Osc
Vref
RT
8(14)
4(7)
2(3)
1(1)
0.01 CT
2RR
EA
+
–
+
5(9)
R
RBias
Osc
8(14)
4(7)
2(3)
1(1)
2RR
EA
+
–
+
7
5.0k
3
8
6
5
1
C
R
S
MC1455
2
RA
+
–
+
–
4
Q
5.0k
5.0k
RB
To Additional
UCX84XA’s
f = 1.44
(RA + 2RB)C Dmax = RB
RA + 2RB
5(9)
R
RBias
Osc
8(14)
4(7)
2(3)
1(1)
2RR
EA
+
–
+
Q1
RS
3(5)
5(8)
1.0V
–
R
SQ
Comp/Latch
5.0Vref
VClamp
Vin
VCC
7(11)
6(10)
–
+
+
–
+
–+
7(12)
+–
R1 R2
R2
VClamp = 1.67
+ 1
+ 0.33 x 10 – 3I
pk(max) = VClamp
RS
Where: 0
≤
VClamp
≤
1.0 V
R2
R1
1.0mA
R1
R1 + R2
5(9)
R
RBias
Osc
8(14)
4(7)
2(3)
1(1)
2RR
EA
+
–
+
1.0V
–
R
SQ
5.0Vref
–
+
+
–
+
C
tSoft–Start
3600C in
µ
F
1.0M
1.0mA
5(9)
R
RBias
Osc
8(14)
4(7)
2(3)
1(1)
2RR
EA
+
–
+
Q1
RS
3(5)
5(8)
1.0V
–
R
SQ
Comp/Latch
5.0Vref
VClamp
Vin
VCC
7(11)
6(10)
–
+
+
–
+
–+
7(12)
+–
MPSA63
R1
R2
C
tSoftstart = – In 1 – VCR1 R2
C
R2
VClamp = 1.67
+ 1 Ipk(max) = VClamp
RS Where: 0
≤
VClamp
≤
1.0 V
1.0mA
R13VClamp R1 + R2
RS
1/4 W
(5)
(8)
–
R
SQ
Comp/Latch
5.0Vref
Vin
VCC
(11)
(10)
–
+
+
–
+
–+
(12)
+–
Power Ground
To Input Source
Return
VPin 5 =
If: SENSEFET = MTP10N10M
RS = 200
Then: Vpin 5 = 0.075 Ipk
SENSEFET
RS Ipk rDS(on)
M
G
D
S
K
Control CIrcuitry
Ground:
To Pin (9)
rDM(on) + RS
UC3842A, 43A UC2842A, 43A
12 MOTOROLA ANALOG IC DEVICE DATA
Figure 26. Current W aveform Spike Suppression Figure 27. MOSFET Parasitic Oscillations
Figure 28. Bipolar T ransistor Drive Figure 29. Isolated MOSFET Drive
Figure 30. Latched Shutdown Figure 31. Error Amplifier Compensation
The totem–pole output can furnish negative base current for enhanced
transistor turn–of f, with the addition of capacitor C1.
Error Amp compensation circuit for stabilizing any current–mode topology except
for boost and flyback converters operating with continuous inductor current.
Error Amp compensation circuit for stabilizing current–mode boost and flyback
topologies operating with continuous inductor current.
The MCR101 SCR must be selected for a holding of less than 0.5 mA at
TA(min). The simple two transistor circuit can be used in place of the SCR as
shown. All resistors are 10 k.
Series gate resistor Rg will damp any high frequency parasitic oscillations
caused by the MOSFET input capacitance and any series wiring inductance
in the gate–source circuit.
The addition of the RC filter will eliminate instability caused by the leading
edge spike on the current waveform.
Q1
RS
3(5)
5(8)
–
R
SQ
Comp/Latch
5.0Vref
Vin
VCC
7(11)
6(10)
–
+
+
–
+
–+
7(12)
+–
R
C
Q1
RS
3(5)
5(8)
–
R
SQ
Comp/Latch
5.0Vref
Vin
VCC
7(11)
6(10)
–
+
+
–
+
–+
7(12)
+–
Rg
Q1
RS
3(5)
5(8)
Vin
6(1)
C1
IB
+
0
–
Base Charge
Removal
É
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
Q1
3(5)
5(8)
–
R
SQ
Comp/Latch
5.0Vref
Vin
VCC
7(11)
6(1)
–
+
+
–
+
–+
7(12)
+–
Np
R
CRSNS
Isolation
Boundary
VGS W aveforms
+
0
–
+
0
–
Ipk = V(pin 1) – 1.4
3 RS
NP
NS
50% DC 25% DC
5(9)
R
RBias
Osc
8(14)
4(7)
2(3)
1(1)
2RR
EA
+
–
+1.0mA
2N
3903
2N
3905
MCR
101
5(9)
2(3)
1(1)
2RR
EA
+
–
+1.0mA
CIRf
Ri
Rd
From VO2.5V
5(9)
2(3)
1(1)
2RR
EA
+
–
+1.0mA
CpCIRf
From VO
Rp
Rd
Ri
2.5V
Figure 32. Slope Compensation
Figure 33. 27 Watt Off–Line Flyback Regulator
The buffered oscillator ramp can be resistively summed with either the voltage feedback or current sense inputs to provide slope compensation.
Ri
Rd
–3.0 m m
1.0V
Vin
VCC
RS
3(5)
5(8)
6(10)
7(11)
7(12)
+
–
+
–
5.0Vref
Bias
Osc
1.0mA
+
2R
R
R
R
R
SQ
CfRfEA
1(1)
2(3)
4(7)
RT
8(14)
MPS3904
RSlope
From VO
5(9)
CT
Comp/Latch
–m
–
+
T1 – Primary: 45 T urns # 26 AWG
T1 – Secondary
±
12 V : 9 Turns # 30 AWG
T1 – (2 strands) Bifiliar Wound
T1 – Secondary 5.0 V : 4 Turns (six strands)
T1 – #26 Hexfiliar Wound
T1 – Secondary Feedback: 10 T urns #30 A WG
T1 – (2 strands) Bifiliar Wound
T1 – Core: Ferroxcube EC35–3C8
T1 – Bobbin: Ferroxcube EC35PCB1
T1 – Gap
≈
0.01” for a primary inductance of 1.0 mH
L1 – 15
µ
H at 5.0 A, Coilcraft Z7156.
L2, L3 – 25
µ
H at 1.0 A, Coilcraft Z7157.
Comp/Latch
S
RQ
1N4935 1N4935
5.0Vref
Bias
Osc
++ 47
100
EA
+
+
7(12)
L1
5.0V/4.0A
2200 1000 +
MUR110
MBR1635
1000
1000 10
++
+L2
5.0V RTN
12V/0.3A
1N4937
L3
MUR110
±
12V RTN
–12V/0.3A
T1
1.0k
470pF
3(5)
5(8)
6(10)
7(11) 22
Ω
1N4937
2.7k
3300pF
4.7k
56k
250
+
115Vac
4.7
Ω
MDA
202
68
5(9)
+
1(1)
2(3)
4(7)
10k
0.01
4700pF
18k
4.7k
MTP
4N50
8(14)
10
+
+
680pF
0.5
Ω
150k
100pF
+
–
+
–
+
––
+
+
–
+
––
+
UC3842A, 43A UC2842A, 43A
13
MOTOROLA ANALOG IC DEVICE DATA
Test Conditions Results
Line Regulation: 5.0 V
± 12 V Vin = 95 Vac to 130 Vac ∆ = 50 mV or ± 0.5%
∆ = 24 mV or ± 0.1%
Load Regulation: 5.0 V
± 12 V Vin = 115 Vac, Iout = 1.0 A to 4.0 A
Vin = 115 Vac, Iout = 100 mA to 300 mA ∆ = 300 mV or ± 3.0%
∆ = 60 mV or ± 0.25%
Output Ripple: 5.0 V
± 12 V Vin = 115 Vac 40 mVpp
80 mVpp
Efficiency Vin = 115 Vac 70%
All outputs are at nominal load currents, unless otherwise noted.
UC3842A, 43A UC2842A, 43A
14 MOTOROLA ANALOG IC DEVICE DATA
OUTLINE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 626–05
ISSUE K
D SUFFIX
PLASTIC PACKAGE
CASE 751A–03
(SO–14)
ISSUE F
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M––– 10 ––– 10
N0.76 1.01 0.030 0.040
__
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
–A–
–B–
G
P7 PL
14 8
71 M
0.25 (0.010) B M
S
B
M
0.25 (0.010) A S
T
–T–
F
RX 45
SEATING
PLANE
D14 PL K
C
J
M
_
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A8.55 8.75 0.337 0.344
B3.80 4.00 0.150 0.157
C1.35 1.75 0.054 0.068
D0.35 0.49 0.014 0.019
F0.40 1.25 0.016 0.049
G1.27 BSC 0.050 BSC
J0.19 0.25 0.008 0.009
K0.10 0.25 0.004 0.009
M0 7 0 7
P5.80 6.20 0.228 0.244
R0.25 0.50 0.010 0.019
____
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the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
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applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
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Opportunity/Af firmative Action Employer .
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UC3842A/D
*UC3842A/D*
◊
