CY7C1565V18 - Cypress Semiconductor

72-Mbit QDR™-II+ SRAM 4-Word Burst

Architecture (2.5 Cycle Read Latency)

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document Number: 001-05384 Rev. *E Revised July 24, 2007

Features

■Separate independent read and write data ports

❐Supports concurrent transactions

■300 MHz to 400 MHz clock for high bandwidth

■4-Word Burst for reducing address bus frequency

■Double Data Rate (DDR) interfaces on both Read and Write

Ports (data transferred at 800 MHz) at 400 MHz

■Read latency of 2.5 clock cycles

■Two input clocks (K and K) for precise DDR timing

❐SRAM uses rising edges only

■Echo clocks (CQ and CQ) simplify data capture in high speed

systems

■Data valid pin (QVLD) to indicate valid data on the output

■Single multiplexed address input bus latches address inputs

for both Read and Write Ports

■Separate port selects for depth expansion

■Synchronous internally self-timed writes

■Available in x8, x9, x18, and x36 configurations

■Full data coherency providing most current data

■Core VDD = 1.8V ± 0.1V; IO VDDQ = 1.4V to VDD[1]

■HSTL inputs and Variable drive HSTL output buffers

■Available in 165-ball FBGA package (15 x 17 x 1.4 mm)

■Offered in both Pb-free and non Pb-free packages

■JTAG 1149.1 compatible test access port

■Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.5 cycles:

CY7C1561V18 – 8M x 8

CY7C1576V18 – 8M x 9

CY7C1563V18 – 4M x 18

CY7C1565V18 – 2M x 36

Functional Description

The CY7C1561V18, CY7C1576V18, CY7C1563V18, and

CY7C1565V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II+ architecture. Similar to QDR-II archi-

tecture, QDR-II+ SRAMs consists of two separate ports to

access the memory array. The Read Port has dedicated data

outputs to support read operations and the Write Port has

dedicated data inputs to support write operations. QDR-II+ archi-

tecture has separate data inputs and data outputs to completely

eliminate the need to “turn-around” the data bus required with

common IO devices. Access to each port is accomplished

through a common address bus. Addresses for read and write

addresses are latched on alternate rising edges of the input (K)

clock. Accesses to the QDR-II+ Read and Write Ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write Ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 8-bit words (CY7C1561V18), 9-bit words

(CY7C1576V18), 18-bit words (CY7C1563V18), or 36-bit words

(CY7C1565V18) that burst sequentially into or out of the device.

Since data can be transferred into and out of the device on every

rising edge of both input clocks (K and K), memory bandwidth is

maximized while simplifying system design by eliminating bus

“turn-arounds”.

Depth expansion is accomplished with port selects for each port.

Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

400 MHz 375 MHz 333 MHz 300 MHz Unit

Maximum Operating Frequency 400 375 333 300 MHz

Maximum Operating Current x8 1400 1300 1200 1100 mA

x9 1400 1300 1200 1100

x18 1400 1300 1200 1100

x36 1400 1300 1200 1100

Note

1. The QDR consortium specification for VDDQ is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting

VDDQ = 1.4V to VDD.

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 2 of 28

Logic Block Diagram (CY7C1561V18)

Logic Block Diagram (CY7C1576V18)

2M x 8 Array

CLK

A(20:0)

Gen.

Control

Logic

Address

D[7:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

NWS[1:0]

VREF

Write Add. Decode

Write

Reg

A(20:0)

2M x 8 Array

DOFF

Q[7:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

2M x 9 Array

CLK

A(20:0)

Gen.

Control

Logic

Address

D[8:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

BWS[0]

VREF

Write Add. Decode

Write

Reg

A(20:0)

2M x 9 Array

DOFF

Q[8:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 3 of 28

Logic Block Diagram (CY7C1563V18)

Logic Block Diagram (CY7C1565V18)

1M x 18 Array

CLK

A(19:0)

Gen.

Control

Logic

Address

D[17:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

BWS[1:0]

VREF

Write Add. Decode

Write

Reg

A(19:0)

1M x 18 Array

DOFF

Q[17:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

512K x 36 Array

CLK

A(18:0)

Gen.

Control

Logic

Address

D[35:0]

Read Add. Decode

Read Data Reg.

RPS

WPS

Control

Logic

Address

Reg.

144

BWS[3:0]

VREF

Write Add. Decode

Write

Reg

A(18:0)

512K x 36 Array

DOFF

Q[35:0]

QVLD

Write

Reg

Write

Reg

Write

Reg

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 4 of 28

Pin Configuration

The Pin Configuration for CY7C1561V18, CY7C1563V18, and CY7C1565V18 follows.[2]

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1561V18 (8M x 8)

1234567891011

ACQ AAWPSNWS1KNC/144M RPS AACQ

BNC NC NC A NC/288M K NWS0ANCNCQ3

CNC NC NC VSS ANCAV

SS NC NC D3

DNC D4 NC VSS VSS VSS VSS VSS NC NC NC

ENC NC Q4 VDDQ VSS VSS VSS VDDQ NC D2 Q2

FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

GNC D5 Q5 VDDQ VDD VSS VDD VDDQ NC NC NC

HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JNC NC NC VDDQ VDD VSS VDD VDDQ NC Q1 D1

KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

LNC Q6 D6 VDDQ VSS VSS VSS VDDQ NC NC Q0

MNC NC NC VSS VSS VSS VSS VSS NC NC D0

NNC D7 NC VSS AAAV

SS NC NC NC

PNC NC Q7 A A QVLD A A NC NC NC

RTDOTCKAAANCAAATMSTDI

CY7C1576V18 (8M x 9)

1234567891011

ACQ AAWPSNC K NC/144M RPS AACQ

BNC NC NC A NC/288M K BWS0ANCNCQ4

CNC NC NC VSS ANCAV

SS NC NC D4

DNC D5 NC VSS VSS VSS VSS VSS NC NC NC

ENC NC Q5 VDDQ VSS VSS VSS VDDQ NC D3 Q3

FNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

GNC D6 Q6 VDDQ VDD VSS VDD VDDQ NC NC NC

HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JNC NC NC VDDQ VDD VSS VDD VDDQ NC Q2 D2

KNC NC NC VDDQ VDD VSS VDD VDDQ NC NC NC

LNC Q7 D7 VDDQ VSS VSS VSS VDDQ NC NC Q1

MNC NC NC VSS VSS VSS VSS VSS NC NC D1

NNC D8 NC VSS AAAV

SS NC NC NC

PNC NC Q8 A A QVLD A A NC D0 Q0

RTDOTCKAAANCAAATMSTDI

Note

2. NC/144M and NC/288M are not connected to the die and can be tied to any voltage level.

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 5 of 28

CY7C1563V18 (4M x 18)

1234567891011

ACQ NC/144M A WPS BWS1KNC/288M RPS AACQ

BNC Q9 D9 A NC K BWS0ANCNCQ8

CNC NC D10 VSS ANCAV

SS NC Q7 D8

DNC D11 Q10 VSS VSS VSS VSS VSS NC NC D7

ENC NC Q11 VDDQ VSS VSS VSS VDDQ NC D6 Q6

FNC Q12 D12 VDDQ VDD VSS VDD VDDQ NC NC Q5

GNC D13 Q13 VDDQ VDD VSS VDD VDDQ NC NC D5

HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JNC NC D14 VDDQ VDD VSS VDD VDDQ NC Q4 D4

KNC NC Q14 VDDQ VDD VSS VDD VDDQ NC D3 Q3

LNC Q15 D15 VDDQ VSS VSS VSS VDDQ NC NC Q2

MNC NC D16 VSS VSS VSS VSS VSS NC Q1 D2

NNC D17 Q16 VSS AAAV

SS NC NC D1

PNC NC Q17 A A QVLD A A NC D0 Q0

RTDOTCKAAANCAAATMSTDI

CY7C1565V18 (2M x 36)

1234567891011

ACQ NC/288M A WPS BWS2KBWS1RPS A NC/144M CQ

BQ27 Q18 D18 A BWS3KBWS

0AD17Q17Q8

CD27 Q28 D19 VSS ANCAV

SS D16 Q7 D8

DD28 D20 Q19 VSS VSS VSS VSS VSS Q16 D15 D7

EQ29 D29 Q20 VDDQ VSS VSS VSS VDDQ Q15 D6 Q6

FQ30 Q21 D21 VDDQ VDD VSS VDD VDDQ D14 Q14 Q5

GD30 D22 Q22 VDDQ VDD VSS VDD VDDQ Q13 D13 D5

HDOFF VREF VDDQ VDDQ VDD VSS VDD VDDQ VDDQ VREF ZQ

JD31 Q31 D23 VDDQ VDD VSS VDD VDDQ D12 Q4 D4

KQ32 D32 Q23 VDDQ VDD VSS VDD VDDQ Q12 D3 Q3

LQ33 Q24 D24 VDDQ VSS VSS VSS VDDQ D11 Q11 Q2

MD33 Q34 D25 VSS VSS VSS VSS VSS D10 Q1 D2

ND34 D26 Q25 VSS AAAV

SS Q10 D9 D1

PQ35 D35 Q26 A A QVLD A A Q9 D0 Q0

RTDOTCKAAANCAAATMSTDI

Pin Configuration

The Pin Configuration for CY7C1561V18, CY7C1563V18, and CY7C1565V18 follows.[2] (continued)

165-Ball FBGA (15 x 17 x 1.4 mm) Pinout

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 6 of 28

Pin Definitions

Pin Name IO Pin Description

D[x:0] Input-

Synchronous

Data input signals. Sampled on the rising edge of K and K clocks during valid write operations.

CY7C1561V18 − D[7:0]

CY7C1576V18 − D[8:0]

CY7C1563V18 − D[17:0]

CY7C1565V18 − D[35:0]

WPS Input-

Synchronous

Write Port Select, Active LOW. Sampled on the rising edge of the K clock. When asserted active,

a write operation is initiated. Deasserting deselects the Write Port. When the Write Port is deselected

D[x:0] is ignored.

NWS0, NWS1,Input-

Synchronous

Nibble Write Select 0, 1, Active LOW (CY7C1561V18 Only). Sampled on the rising edge of the K

and K clocks when write operations are active. Used to select which nibble is written into the device

during the current portion of the write operations. NWS0 controls D[3:0] and NWS1 controls D[7:4].

All the nibble Write Selects are sampled on the same edge as the data. The corresponding nibble of

data is ignored by deselecting a nibble write select and is not written into the device.

BWS0, BWS1,

BWS2, BWS3

Input-

Synchronous

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks

during write operations. Used to select which byte is written into the device during the current portion

of the write operations. Bytes not written remain unaltered.

CY7C1576V18 − BWS0 controls D[8:0]

CY7C1563V18 − BWS0 controls D[8:0] and BWS1 controls D[17:9].

CY7C1565V18 − BWS0 controls D[8:0], BWS1 controls D[17:9], BWS2 controls D[26:18] and BWS3

controls D[35:27].

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

causes the corresponding byte of data to be ignored and not written into the device.

A Input-

Synchronous

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.

These address inputs are multiplexed for both read and write operations. Internally, the device is

organized as 8M x 8 (4 arrays each of 2M x 8) for CY7C1561V18, 8M x 9 (4 arrays each of 2M x 9)

for CY7C1576V18, 4M x 18 (4 arrays each of 1M x 18) for CY7C1563V18 and 2M x 36 (4 arrays

each of 512K x 36) for CY7C1565V18. Therefore, only 21 address inputs are needed to access the

entire memory array of CY7C1561V18 and CY7C1576V18, 20 address inputs for CY7C1563V18,

and 19 address inputs for CY7C1565V18. These inputs are ignored when the appropriate port is

deselected.

Q[x:0] Outputs-

Synchronous

Data Output signals. These pins drive out the requested data during a read operation. Valid data is

driven out on the rising edge of both the K and K clocks during read operations or K and K. When

the Read Port is deselected, Q[x:0] are automatically tri-stated.

CY7C1561V18 − Q[7:0]

CY7C1576V18 − Q[8:0]

CY7C1563V18 − Q[17:0]

CY7C1565V18 − Q[35:0]

RPS Input-

Synchronous

Read Port Select, Active LOW. Sampled on the rising edge of Positive Input Clock (K). When active,

a read operation is initiated. Deasserting causes the Read Port to be deselected. When deselected,

the pending access is allowed to complete and the output drivers are automatically tri-stated following

the next rising edge of the K clock. Each read access consists of a burst of four sequential transfers.

QVLD Valid output

indicator

Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

CQ.

K Input-

Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q[x:0] when in single clock mode. All accesses are initiated on the rising

edge of K.

KInput-

Clock

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device

and to drive out data through Q[x:0] when in single clock mode.

CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

on page 22.

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 7 of 28

Functional Overview

The CY7C1561V18, CY7C1576V18, CY7C1563V18, and

CY7C1565V18 are synchronous pipelined Burst SRAMs

equipped with both a Read Port and a Write Port. The Read Port

is dedicated to read operations and the Write Port is dedicated

to write operations. Data flows into the SRAM through the Write

Port and out through the Read Port. These devices multiplex the

address inputs in order to minimize the number of address pins

required. By having separate Read and Write Ports, the QDR-II+

completely eliminates the need to “turn-around” the data bus and

avoids any possible data contention, thereby simplifying system

design. Each access consists of four 8-bit data transfers in the

case of CY7C1561V18, four 9-bit data transfers in the case of

CY7C1576V18, four 18-bit data transfers in the case of

CY7C1563V18, and four 36-bit data transfers in the case of

CY7C1565V18, in two clock cycles.

Accesses for both ports are initiated on the Positive Input Clock

(K). All synchronous input and output timing are referenced from

the rising edge of the input clocks (K and K).

All synchronous data inputs (D[x:0]) inputs pass through input

registers controlled by the input clocks (K and K). All

synchronous data outputs (Q[x:0]) outputs pass through output

registers controlled by the rising edge of the input clocks (K and

K) as well.

All synchronous control (RPS, WPS, BWS[x:0]) inputs pass

through input registers controlled by the rising edge of the input

clocks (K and K).

CY7C1563V18 is described in the following sections. The same

basic descriptions apply to CY7C1561V18, CY7C1576V18, and

CY7C1565V18.

Read Operations

The CY7C1563V18 is organized internally as 4 arrays of 1M x

18. Accesses are completed in a burst of four sequential 18-bit

data words. Read operations are initiated by asserting RPS

active at the rising edge of the Positive Input Clock (K). The

address presented to Address inputs are stored in the Read

Address Register. Following the next two K clock rise, the corre-

sponding lowest order 18-bit word of data is driven onto the

Q[17:0] using K as the output timing reference. On the subse-

quent rising edge of K the next 18-bit data word is driven onto

the Q[17:0]. This process continues until all four 18-bit data words

have been driven out onto Q[17:0]. The requested data is valid

CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

clock (K) of the QDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

on page 22.

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data

bus impedance. CQ, CQ and Q[x:0] output impedance are set to 0.2 x RQ, where RQ is a resistor

connected between ZQ and ground. Alternately, this pin can be connected directly to VDDQ, which

enables the minimum impedance mode. This pin cannot be connected directly to GND or left uncon-

nected.

DOFF Input DLL Turn Off-Active LOW. Connecting this pin to ground turns off the DLL inside the device.The

timings in the DLL turned off operation are different from those listed in this data sheet. For normal

operation, this pin can be connected to a pull up through a 10 KΩ or less pull up resistor. The device

behaves in QDR-I mode when the DLL is turned off. In this mode, the device can be operated at a

frequency of up to 167 MHz with QDR-I timing.

TDO Output TDO for JTAG.

TCK Input TCK pin for JTAG.

TDI Input TDI pin for JTAG.

TMS Input TMS pin for JTAG.

NC N/A Not connected to the die. Can be tied to any voltage level.

NC/144M N/A Not connected to the die. Can be tied to any voltage level.

NC/288M N/A Not connected to the die. Can be tied to any voltage level.

VREF Input-

Reference

Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs

as well as AC measurement points.

VDD Power Supply Power supply inputs to the core of the device.

VSS Ground Ground for the device.

VDDQ Power Supply Power supply inputs for the outputs of the device.

Pin Definitions (continued)

Pin Name IO Pin Description

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 8 of 28

0.45*ns from the rising edge of the input clock (K or K). In order

to maintain the internal logic, each read access must be allowed

to complete. Each read access consists of four 18-bit data words

and takes 2 clock cycles to complete. Therefore, read accesses

to the device can not be initiated on two consecutive K clock

rises. The internal logic of the device ignores the second read

request. Read accesses can be initiated on every other K clock

rise. Doing so pipelines the data flow such that data is transferred

out of the device on every rising edge of the input clocks (K and

K).

When the Read Port is deselected, the CY7C1563V18 first

completes the pending read transactions. Synchronous internal

circuitry automatically tri-states the outputs following the next

rising edge of the Positive Input Clock (K). This allows for a

seamless transition between devices without the insertion of wait

states in a depth expanded memory.

Write Operations

Write operations are initiated by asserting WPS active at the

rising edge of the Positive Input Clock (K). On the following K

clock rise the data presented to D[17:0] is latched and stored into

the lower 18-bit Write Data Register, provided BWS[1:0] are both

asserted active. On the subsequent rising edge of the Negative

Input Clock (K) the information presented to D[17:0] is also stored

into the Write Data Register, provided BWS[1:0] are both asserted

active. This process continues for one more cycle until four 18-bit

words (a total of 72 bits) of data are stored in the SRAM. The 72

bits of data are then written into the memory array at the specified

location. Therefore, write accesses to the device can not be

initiated on two consecutive K clock rises. The internal logic of

the device ignores the second write request. Write accesses can

be initiated on every other rising edge of the Positive Input Clock

(K). Doing so pipelines the data flow such that 18 bits of data can

be transferred into the device on every rising edge of the input

clocks (K and K).

When deselected, the Write Port ignores all inputs after the

pending write operations have been completed.

Byte Write Operations

Byte Write operations are supported by the CY7C1563V18. A

write operation is initiated as described in the “Write Operations”

section above. The bytes that are written are determined by

BWS0 and BWS1, which are sampled with each set of 18-bit data

words. Asserting the appropriate Byte Write Select input during

the data portion of a write allows the data being presented to be

latched and written into the device. Deasserting the Byte Write

Select input during the data portion of a write allows the data

stored in the device for that byte to remain unaltered. This feature

can be used to simplify Read/Modify/Write operations to a Byte

Write operation.

Concurrent Transactions

The Read and Write Ports on the CY7C1563V18 operate

completely independently of one another. Since each port

latches the address inputs on different clock edges, the user can

read or write to any location, regardless of the transaction on the

other port. If the ports access the same location when a read

follows a write in successive clock cycles, the SRAM delivers the

most recent information associated with the specified address

location. This includes forwarding data from a write cycle that

was initiated on the previous K clock rise.

Read accesses and write access must be scheduled such that

one transaction is initiated on any clock cycle. If both ports are

selected on the same K clock rise, the arbitration depends on the

previous state of the SRAM. If both ports were deselected, the

Read Port takes priority. If a read was initiated on the previous

cycle, the Write Port assumes priority (since read operations can

not be initiated on consecutive cycles). If a write was initiated on

the previous cycle, the Read Port assumes priority (since write

operations can not be initiated on consecutive cycles).

Therefore, asserting both port selects active from a deselected

state results in alternating read and write operations being

initiated, with the first access being a read.

Depth Expansion

The CY7C1563V18 has a port select input for each port. This

allows for easy depth expansion. Both port selects are sampled

on the rising edge of the Positive Input Clock only (K). Each port

select input can deselect the specified port. Deselecting a port

does not affect the other port. All pending transactions (read and

write) are completed prior to the device being deselected.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin

on the SRAM and VSS to allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5X the value of the

intended line impedance driven by the SRAM, The allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15% is between 175Ω and 350Ω, with VDDQ =1.5V. The

output impedance is adjusted every 1024 cycles upon powerup

to account for drifts in supply voltage and temperature.

Echo Clocks

Echo clocks are provided on the QDR-II+ to simplify data capture

on high speed systems. Two echo clocks are generated by the

QDR-II+. CQ is referenced with respect to K and CQ is refer-

enced with respect to K. These are free running clocks and are

synchronized to the input clock of the QDR-II+. The timings for

the echo clocks are shown in “Switching Characteristics” on

page 22.

Valid Data Indicator (QVLD)

QVLD is provided on the QDR-II+ to simplify data capture on high

speed systems. The QVLD is generated by the QDR-II+ device

along with Data output. This signal is also edge-aligned with the

echo clock and follows the timing of any data pin. This signal is

asserted half a cycle before valid data arrives.

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed to

function between 120 MHz and the specified maximum clock

frequency. The DLL may be disabled by applying ground to the

DOFF pin. When the DLL is turned off, the device behaves in

DDR-I mode (with 1.0 cycle latency and a longer access time).

For more information, refer to the application note, “DLL Consid-

erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be

reset by slowing or stopping the input clocks K and K for a

minimum of 30ns. However, it is not necessary for the DLL to be

reset in order to lock to the desired frequency. During Power up,

when the DOFF is tied HIGH, the DLL gets locked after 2048

cycles of stable clock.

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 9 of 28

Application Example

Figure 1 shows four QDR-II+ used in an application.

Figure 1. Application Example

Truth Table

The truth table for CY7C1561V18, CY7C1563V18, and CY7C1565V18 follows.[3, 4, 5, 6, 7, 8]

Operation K RPS WPS DQ DQ DQ DQ

Write Cycle:

Load address on the rising

edge of K; input write data

on two consecutive K and

K rising edges.

L-H H[9] L[10] D(A) at K(t+1) ↑D(A+1) at K(t+1) ↑D(A+2) at K(t+2) ↑D(A + 3) at K(t +2) ↑

Read Cycle:

(2.5 cycle Latency)

Load address on the rising

edge of K; wait two and a

half cycles; read data on

two consecutive K and K

rising edges.

L-H L[10] XQ(A) at K(t+2)↑Q(A+1) at K(t+3) ↑Q(A+2) at K(t+3)↑Q(A + 3) at K(t + 4) ↑

NOP: No Operation L-H H H D = X

Q = High-Z

D = X

Q = High-Z

D = X

Q = High-Z

D = X

Q = High-Z

Standby: Clock Stopped Stopped X X Previous State Previous State Previous State Previous State

BUS MASTER

(CPU or ASIC)

DATA IN

DATA OUT

Address

Source K

CLKIN/CLKIN

SRAM #4

RQ = 250ohms

CQ/CQ

RPS WPS BWS

SRAM #1

RQ = 250ohms

CQ/CQ

RPS WPS BWS

RPS

WPS

BWS

R = 50ohms, Vt = V /2

DDQ

Notes

3. X = “Don't Care,” H = Logic HIGH, L = Logic LOW, ↑represents rising edge.

4. Device powers up deselected with the outputs in a tri-state condition.

5. “A” represents address location latched by the devices when transaction was initiated. A + 1, A + 2, and A +3 represents the address sequence in the burst.

6. “t” represents the cycle at which a read/write operation is started. t + 1, t + 2, and t + 3 are the first, second and third clock cycles respectively succeeding the “t” clock cycle.

7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges also.

8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

9. If this signal was LOW to initiate the previous cycle, this signal becomes a “Don’t Care” for this operation.

10. This signal was HIGH on previous K clock rise. Initiating consecutive read or write operations on consecutive K clock rises is not permitted. The device ignores the

second read or write request.

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Write Cycle Descriptions

The write cycle description table for CY7C1561V18 and CY7C1563V18 follows. [3, 11]

BWS0/

NWS0

BWS1/

NWS1

KKComments

L L L–H – During the data portion of a write sequence :

CY7C1561V18 − both nibbles (D[7:0]) are written into the device,

CY7C1563V18 − both bytes (D[17:0]) are written into the device.

L L – L-H During the data portion of a write sequence :

CY7C1561V18 − both nibbles (D[7:0]) are written into the device,

CY7C1563V18 − both bytes (D[17:0]) are written into the device.

L H L–H – During the data portion of a write sequence :

CY7C1561V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.

CY7C1563V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.

L H – L–H During the data portion of a write sequence :

CY7C1561V18 − only the lower nibble (D[3:0]) is written into the device, D[7:4] remains unaltered.

CY7C1563V18 − only the lower byte (D[8:0]) is written into the device, D[17:9] remains unaltered.

H L L–H – During the data portion of a write sequence :

CY7C1561V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.

CY7C1563V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.

H L – L–H During the data portion of a write sequence :

CY7C1561V18 − only the upper nibble (D[7:4]) is written into the device, D[3:0] remains unaltered.

CY7C1563V18 − only the upper byte (D[17:9]) is written into the device, D[8:0] remains unaltered.

H H L–H – No data is written into the devices during this portion of a write operation.

H H – L–H No data is written into the devices during this portion of a write operation.

Write Cycle Descriptions

The write cycle description table for CY7C1576V18 follows. [3, 11]

BWS0KK

L L–H – During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.

L – L–H During the Data portion of a write sequence, the single byte (D[8:0]) is written into the device.

H L–H – No data is written into the device during this portion of a write operation.

H – L–H No data is written into the device during this portion of a write operation.

Note

11. Assumes a write cycle was initiated per the Write Cycle Descriptions table. NWS0, NWS1, BWS0, BWS1, BWS2, and BWS3 can be altered on different portions of a

write cycle, as long as the setup and hold requirements are achieved.

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Write Cycle Descriptions

The write cycle description table for CY7C1565V18 follows. [3, 11]

BWS0BWS1BWS2BWS3KK Comments

LLLLL–H–During the Data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

LLLL–L–HDuring the Data portion of a write sequence, all four bytes (D[35:0]) are written into

the device.

L H H H L–H – During the Data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

L H H H – L–H During the Data portion of a write sequence, only the lower byte (D[8:0]) is written

into the device. D[35:9] remains unaltered.

H L H H L–H – During the Data portion of a write sequence, only the byte (D[17:9]) is written into

the device. D[8:0] and D[35:18] remains unaltered.

H L H H – L–H During the Data portion of a write sequence, only the byte (D[17:9]) is written into

the device. D[8:0] and D[35:18] remains unaltered.

H H L H L–H – During the Data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains unaltered.

H H L H – L–H During the Data portion of a write sequence, only the byte (D[26:18]) is written into

the device. D[17:0] and D[35:27] remains unaltered.

H H H L L–H – During the Data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

H H H L – L–H During the Data portion of a write sequence, only the byte (D[35:27]) is written into

the device. D[26:0] remains unaltered.

HHHHL–H–No data is written into the device during this portion of a write operation.

HHHH–L–HNo data is written into the device during this portion of a write operation.

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IEEE 1149.1 Serial Boundary Scan (JTAG)

These SRAMs incorporate a serial boundary scan test access

port (TAP) in the FBGA package. This part is fully compliant with

IEEE Standard #1149.1-2001. The TAP operates using JEDEC

standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

(VSS) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to VDD through a pull up resistor. TDO must be left

unconnected. Upon power up, the device comes up in a reset

state which does not interfere with the operation of the device.

Test Access Port–Test Clock

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Test Mode Select

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to leave

this pin unconnected if the TAP is not used. The pin is pulled up

internally, resulting in a logic HIGH level.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers

and can be connected to the input of any of the registers. The

is loaded into the TAP instruction register. For information on

loading the instruction register, see the “TAP Controller State

Diagram” on page 14. TDI is internally pulled up and can be

unconnected if the TAP is unused in an application. TDI is

connected to the most significant bit (MSB) on any register.

Test Data-Out (TDO)

The TDO output pin is used to serially clock data-out from the

registers. The output is active depending upon the current state

of the TAP state machine (see “Instruction Codes” on page 17).

The output changes on the falling edge of TCK. TDO is

connected to the least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (VDD) for five rising

edges of TCK. This RESET does not affect the operation of the

SRAM and may be performed while the SRAM is operating. At

power up, the TAP is reset internally to ensure that TDO comes

up in a high-Z state.

TAP Registers

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test circuitry.

Only one register can be selected at a time through the

instruction registers. Data is serially loaded into the TDI pin on

the rising edge of TCK. Data is output on the TDO pin on the

falling edge of TCK.

Instruction Register

Three-bit instructions can be serially loaded into the instruction

and TDO pins as shown in the “TAP Controller Block Diagram”

on page 15. Upon power up, the instruction register is loaded

with the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

When the TAP controller is in the Capture IR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

and TDO pins. This allows data to be shifted through the SRAM

with minimal delay. The bypass register is set LOW (VSS) when

the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several no connect (NC) pins are also

included in the scan register to reserve pins for higher density

devices.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

pins when the controller is moved to the Shift-DR state. The

EXTEST, SAMPLE/PRELOAD and SAMPLE Z instructions can

be used to capture the contents of the Input and Output ring.

“Boundary Scan Order” on page 18 show the order in which the

bits are connected. Each bit corresponds to one of the bumps on

the SRAM package. The MSB of the register is connected to TDI,

and the LSB is connected to TDO.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in the “Identification Register Definitions”

on page 17.

TAP Instruction Set

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the “Instruction

Codes” on page 18. Three of these instructions are listed as

RESERVED and must not be used. The other five instructions

are described in detail below.

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. During this state, instructions are shifted through the

instruction register through the TDI and TDO pins. To execute

the instruction once it is shifted in, the TAP controller needs to be

moved into the Update-IR state.

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IDCODE

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and allows

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction is

loaded into the instruction register upon power up or whenever

the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to

be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is given

during the “Update IR” state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the

instruction register and the TAP controller is in the Capture-DR

state, a snapshot of data on the inputs and output pins is

captured in the boundary scan register.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because there

is a large difference in the clock frequencies, it is possible that

during the Capture-DR state, an input or output undergoes a

transition. The TAP may then try to capture a signal while in

transition (metastable state). This does not harm the device, but

there is no guarantee what value is captured. Repeatable results

may not be possible.

To guarantee that the boundary scan register captures the

correct value of a signal, the SRAM signal must be stabilized

long enough to meet the TAP controller's capture setup plus hold

times (tCS and tCH). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an issue, it is

still possible to capture all other signals and simply ignore the

value of the CK and CK# captured in the boundary scan register.

Once the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

PRELOAD allows an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells prior

to the selection of another boundary scan test operation.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required—that is, while data captured

is shifted out, the preloaded data can be shifted in.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

EXTEST

The EXTEST instruction enables the preloaded data to be driven

out through the system output pins. This instruction also selects

the boundary scan register to be connected for serial access

between the TDI and TDO in the shift-DR controller state.

EXTEST OUTPUT BUS TRI-STATE

IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tri-state mode.

The boundary scan register has a special bit located at bit #108.

When this scan cell, called the “extest output bus tri-state”, is

latched into the preload register during the “Update-DR” state in

the TAP controller, it directly controls the state of the output

(Q-bus) pins, when the EXTEST is entered as the current

instruction. When HIGH, it enables the output buffers to drive the

output bus. When LOW, this bit places the output bus into a

High-Z condition.

This bit can be set by entering the SAMPLE/PRELOAD or

EXTEST command, and then shifting the desired bit into that cell,

during the “Shift-DR” state. During “Update-DR”, the value

loaded into that shift-register cell latches into the preload

controls the output Q-bus pins. Note that this bit is pre-set HIGH

to enable the output when the device is powered-up, and also

when the TAP controller is in the “Test-Logic-Reset” state.

Reserved

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

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TAP Controller State Diagram

The state diagram for the TAP controller follows.[12]

TEST-LOGIC

RESET

TEST-LOGIC/

IDLE

SELECT

DR-SCAN

CAPTURE-DR

SHIFT-DR

EXIT1-DR

PAUSE-DR

EXIT2-DR

UPDATE-DR

SELECT

IR-SCAN

CAPTURE-IR

SHIFT-IR

EXIT1-IR

PAUSE-IR

EXIT2-IR

UPDATE-IR

Note

12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.

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TAP Controller Block Diagram

TAP Electrical Characteristics

Over the Operating Range[13, 14, 15]

Parameter Description Test Conditions Min Max Unit

VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V

VOH2 Output HIGH Voltage IOH = −100 µA1.6 V

VOL1 Output LOW Voltage IOL = 2.0 mA 0.4 V

VOL2 Output LOW Voltage IOL = 100 µA0.2V

VIH Input HIGH Voltage 0.65VDD VDD + 0.3 V

VIL Input LOW Voltage –0.3 0.35VDD V

IXInput and Output Load Current GND ≤ VI ≤ VDD –5 5 µA

012..

3031

Boundary Scan Register

Identification Register

012..

.108

012

Instruction Register

Bypass Register

Selection

Circuitry Selection

Circuitry

TAP Controller

TDI TDO

TCK

TMS

Notes

13. These characteristics pertain to the TAP inputs (TMS, TCK, TDI and TDO). Parallel load levels are specified in the Electrical Characteristics Table.

14. Overshoot: VIH(AC) < VDDQ + 0.35V (Pulse width less than tCYC/2), Undershoot: VIL(AC) > −0.3V (Pulse width less than tCYC/2).

15. All Voltage referenced to Ground.

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TAP AC Switching Characteristics

Over the Operating Range [16, 17]

Parameter Description Min Max Unit

tTCYC TCK Clock Cycle Time 50 ns

tTF TCK Clock Frequency 20 MHz

tTH TCK Clock HIGH 20 ns

tTL TCK Clock LOW 20 ns

Setup Times

tTMSS TMS Setup to TCK Clock Rise 5 ns

tTDIS TDI Setup to TCK Clock Rise 5 ns

tCS Capture Setup to TCK Rise 5 ns

Hold Times

tTMSH TMS Hold after TCK Clock Rise 5 ns

tTDIH TDI Hold after Clock Rise 5 ns

tCH Capture Hold after Clock Rise 5 ns

Output Times

tTDOV TCK Clock LOW to TDO Valid 10 ns

tTDOX TCK Clock LOW to TDO Invalid 0 ns

TAP Timing and Test Conditions

Figure 2 shows the TAP timing and test conditions.[17]

Figure 2. TAP Timing and Test Conditions

(a)

TDO

= 20 pF

= 50

Ω

GND

0.9V

Ω

1.8V

ALL INPUT PULSES

0.9V

Test Clock

Test Mode Select

TCK

TMS

Test Data In

TDI

Test Data Out

TCYC

TMSH

TMSS

TDIS

TDIH

TDOV

TDOX

TDO

Notes

16. tCS and tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

17. Test conditions are specified using the load in TAP AC Test Conditions. tR/tF = 1 ns.

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Identification Register Definitions

Instruction Field Value Description

CY7C1561V18 CY7C1576V18 CY7C1563V18 CY7C1565V18

Revision Number

(31:29)

000 000 000 000 Version number.

Cypress Device ID

(28:12)

11010010001000100 11010010001001100 11010010001010100 11010010001100100 Defines the type of

SRAM.

Cypress JEDEC ID

(11:1)

00000110100 00000110100 00000110100 00000110100 Allows unique

identification of

SRAM vendor.

ID Register

Presence (0)

1111Indicates the

presence of an ID

Scan Register Sizes

Instruction 3

Bypass 1

ID 32

Boundary Scan 109

Instruction Codes

Instruction Code Description

EXTEST 000 Captures the Input/Output ring contents.

IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.

This operation does not affect SRAM operation.

SAMPLE Z 010 Captures the Input/Output contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

RESERVED 011 Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD 100 Captures the Input/Output ring contents. Places the boundary scan register between TDI and

TDO. Does not affect the SRAM operation.

RESERVED 101 Do Not Use: This instruction is reserved for future use.

RESERVED 110 Do Not Use: This instruction is reserved for future use.

BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM

operation.

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Boundary Scan Order

Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID

0 6R 28 10G 56 6A 84 1J

16P299G575B852J

2 6N 30 11F 58 5A 86 3K

3 7P 31 11G 59 4A 87 3J

47N329F605C882K

5 7R 33 10F 61 4B 89 1K

6 8R 34 11E 62 3A 90 2L

7 8P 35 10E 63 2A 91 3L

8 9R 36 10D 64 1A 92 1M

9 11P 37 9E 65 2B 93 1L

10 10P 38 10C 66 3B 94 3N

11 10N 39 11D 67 1C 95 3M

12 9P 40 9C 68 1B 96 1N

13 10M 41 9D 69 3D 97 2M

14 11N 42 11B 70 3C 98 3P

15 9M 43 11C 71 1D 99 2N

16 9N 44 9B 72 2C 100 2P

17 11L 45 10B 73 3E 101 1P

18 11M 46 11A 74 2D 102 3R

19 9L 47 10A 75 2E 103 4R

20 10L 48 9A 76 1E 104 4P

21 11K 49 8B 77 2F 105 5P

22 10K 50 7C 78 3F 106 5N

23 9J 51 6C 79 1G 107 5R

24 9K 52 8A 80 1F 108 Internal

25 10J 53 7A 81 3G

26 11J 54 7B 82 2G

27 11H 55 6B 83 1H

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Power Up Sequence in QDR-II+ SRAM

QDR-II+ SRAMs must be powered up and initialized in a

predefined manner to prevent undefined operations. During

Power Up, when the DOFF is tied HIGH, the DLL gets locked

after 2048 cycles of stable clock.

Power Up Sequence

■Apply power with DOFF tied HIGH (All other inputs can be

HIGH or LOW)

❐Apply VDD before VDDQ

❐Apply VDDQ before VREF or at the same time as VREF

■Provide stable power and clock (K, K) for 2048 cycles to lock

the DLL.

DLL Constraints

■DLL uses K clock as its synchronizing input. The input must

have low phase jitter, which is specified as tKC Var.

■The DLL functions at frequencies down to 120 MHz.

■If the input clock is unstable and the DLL is enabled, then the

DLL may lock onto an incorrect frequency, causing unstable

SRAM behavior. To avoid this, provide 2048 cycles stable clock

to relock to the desired clock frequency.

Power Up Waveforms

Fix HIGH (tie to VDDQ)

VDD/VDDQ

DOFF

Clock Start (Clock Starts after VDD/VDDQ is Stable)

Unstable Clock > 2048 Stable Clock Start Normal

Operation

VDD/VDDQ Stable (< + 0.1V DC per 50 ns)

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Maximum Ratings

Exceeding maximum ratings may impair the useful life of the

device. These user guidelines are not tested.

Storage Temperature ................................. –65°C to +150°C

Ambient Temperature with Power Applied.. –55°C to +125°C

Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V

Supply Voltage on VDDQ Relative to GND.......–0.5V to +VDD

DC Applied to Outputs in High-Z ........ –0.5V to VDDQ + 0.3V

DC Input Voltage[14]............................... –0.5V to VDD + 0.3V

Current into Outputs (LOW) ........................................ 20 mA

Static Discharge Voltage (MIL-STD-883, M. 3015)... >2001V

Latch-up Current .................................................... >200 mA

Operating Range

Range

Ambient

Temperature (TA) VDD[18] VDDQ[18]

Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to

VDD

Industrial –40°C to +85°C

Electrical Characteristics

DC Electrical Characteristics

Over the Operating Range[15]

Parameter Description Test Conditions Min Typ Max Unit

VDD Power Supply Voltage 1.7 1.8 1.9 V

VDDQ IO Supply Voltage 1.4 1.5 VDD V

VOH Output HIGH Voltage Note 19 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V

VOL Output LOW Voltage Note 20 VDDQ/2 – 0.12 VDDQ/2 + 0.12 V

VOH(LOW) Output HIGH Voltage IOH = −0.1 mA, Nominal Impedance VDDQ – 0.2 VDDQ V

VOL(LOW) Output LOW Voltage IOL = 0.1mA, Nominal Impedance VSS 0.2 V

VIH Input HIGH Voltage[14] VREF + 0.1 VDDQ + 0.15 V

VIL Input LOW Voltage[14] –0.15 VREF – 0.1 V

IXInput Leakage Current GND ≤ VI ≤ VDDQ −2 2 µA

IOZ Output Leakage Current GND ≤ VI ≤ VDDQ, Output Disabled −2 2 µA

VREF Input Reference Voltage[21] Typical Value = 0.75V 0.68 0.75 0.95 V

IDD (x8) VDD Operating Supply VDD = Max,

IOUT = 0 mA,

f = fMAX = 1/tCYC

300 MHz 1100 mA

333 MHz 1200

375 MHz 1300

400 MHz 1400

IDD (x9) VDD Operating Supply VDD = Max,

IOUT = 0 mA,

f = fMAX = 1/tCYC

300 MHz 1100 mA

333 MHz 1200

375 MHz 1300

400 MHz 1400

IDD (x18) VDD Operating Supply VDD = Max,

IOUT = 0 mA,

f = fMAX = 1/tCYC

300 MHz 1100 mA

333 MHz 1200

375 MHz 1300

400 MHz 1400

IDD (x36) VDD Operating Supply VDD = Max,

IOUT = 0 mA,

f = fMAX = 1/tCYC

300 MHz 1100 mA

333 MHz 1200

375 MHz 1300

400 MHz 1400

Notes

18. Power up: Assumes a linear ramp from 0V to VDD(min) within 200 ms. During this time VIH < VDD and VDDQ < VDD.

19. Output are impedance controlled. IOH = −(VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

20. Output are impedance controlled. IOL = (VDDQ/2)/(RQ/5) for values of 175 ohms <= RQ <= 350 ohms.

21. VREF (min) = 0.68V or 0.46VDDQ, whichever is larger, VREF (max) = 0.95V or 0.54VDDQ, whichever is smaller.

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Document Number: 001-05384 Rev. *E Page 21 of 28

ISB1 Automatic Power down Current Max VDD,

Both Ports Deselected,

VIN ≥ VIH or VIN ≤ VIL

f = fMAX = 1/tCYC,

Inputs Static

300 MHz 450 mA

333 MHz 500

375 MHz 525

400 MHz 550

AC Electrical Characteristics

Over the Operating Range[14]

Parameter Description Test Conditions Min Typ Max Unit

VIH Input HIGH Voltage VREF + 0.2 – VDDQ + 0.24 V

VIL Input LOW Voltage –0.24 – VREF – 0.2 V

Capacitance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions Max Unit

CIN Input Capacitance TA = 25°C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V 5 pF

CCLK Clock Input Capacitance 6 pF

COOutput Capacitance 7pF

Thermal Resistance

Tested initially and after any design or process change that may affect these parameters.

Parameter Description Test Conditions 165 FBGA

Package Unit

ΘJA Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods and

procedures for measuring thermal impedance, per

EIA/JESD51.

11.82 °C/W

ΘJC Thermal Resistance

(Junction to Case)

2.33 °C/W

AC Test Loads and Waveforms

Electrical Characteristics (continued)

DC Electrical Characteristics

Over the Operating Range[15]

Parameter Description Test Conditions Min Typ Max Unit

1.25V

0.25V

R = 50Ω

5pF

INCLUDING

JIG AND

SCOPE

ALL INPUT PULSES

Device RL= 50Ω

Z0= 50Ω

VREF = 0.75V

[22]

0.75V

Under

Tes t

0.75V

Device

Under

Te s t

OUTPUT

0.75V

VREF

OUTPUT

(a)

Slew Rate = 2 V/ns

RQ =

250

Ω

(b)

RQ =

250

Ω

Notes

22. Unless otherwise noted, test conditions assume signal transition time of 2V/ns, timing reference levels of 0.75V, Vref = 0.75V, RQ = 250Ω, VDDQ = 1.5V, input pulse

levels of 0.25V to 1.25V, and output loading of the specified IOL/IOH and load capacitance shown in (a) of “AC Test Loads and Waveforms” .

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Document Number: 001-05384 Rev. *E Page 22 of 28

Switching Characteristics

Over the Operating Range[22, 23]

Parameter

Consortium

Parameter Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Min Max Min Max Min Max Min Max

tPOWER VDD(Typical) to the First Access[24] 1111ms

tCYC tKHKH K Clock Cycle Time 2.50 8.40 2.66 8.40 3.0 8.40 3.3 8.40 ns

tKH tKHKL Input Clock (K/K) HIGH 0.4 – 0.4 – 0.4 0.4 – tCYC

tKL tKLKH Input Clock (K/K) LOW 0.4 – 0.4 – 0.4 0.4 – tCYC

tKHKHtKHKHK Clock Rise to K Clock Rise

(rising edge to rising edge)

1.06 – 1.13 – 1.28 – 1.40 – ns

Setup Times

tSA tAVKH Address Setup to K Clock Rise 0.4 – 0.4 – 0.4 – 0.4 – ns

tSC tIVKH Control Setup to K Clock Rise (RPS, WPS) 0.4 – 0.4 – 0.4 – 0.4 – ns

tSCDDR tIVKH Double Data Rate Control Setup to Clock (K, K)

Rise (BWS0, BWS1, BWS2, BWS3)

0.28 – 0.28 – 0.28 – 0.28 – ns

tSD tDVKH D[X:0] Setup to Clock (K/K) Rise 0.28–0.28–0.28–0.28– ns

Hold Times

tHA tKHAX Address Hold after K Clock Rise 0.4 – 0.4 – 0.4 – 0.4 – ns

tHC tKHIX Control Hold after K Clock Rise (RPS, WPS) 0.4 – 0.4 – 0.4 – 0.4 – ns

tHCDDR tKHIX Double Data Rate Control Hold after Clock (K/K)

Rise (BWS0, BWS1, BWS2, BWS3)

0.28 – 0.28 – 0.28 – 0.28 – ns

tHD tKHDX D[X:0] Hold after Clock (K/K) Rise 0.28–0.28–0.28–0.28– ns

Output Times

tCO tCHQV K/K Clock Rise to Data Valid 0.45 – 0.45 – 0.45 – 0.45 ns

tDOH tCHQX Data Output Hold after Output K/K Clock Rise

(Active to Active)

–0.45 – –0.45 – –0.45 – –0.45 – ns

tCCQO tCHCQV K/K Clock Rise to Echo Clock Valid 0.45–0.45–0.45–0.45ns

tCQOH tCHCQX Echo Clock Hold after K/K Clock Rise –0.45 – –0.45 – –0.45 – –0.45 – ns

tCQD tCQHQV Echo Clock High to Data Valid 0.2 0.2 0.2 0.2 ns

tCQDOH tCQHQX Echo Clock High to Data Invalid –0.2 – –0.2 – –0.2 – –0.2 – ns

tCQH tCQHCQL Output Clock (CQ/CQ) HIGH[27] 0.81–0.88–1.03 1.15– ns

tCQHCQHtCQHCQHCQ Clock Rise to CQ Clock Rise[27]

(rising edge to rising edge)

0.81 – 0.88 – 1.03 – 1.15 – ns

tCHZ tCHQZ Clock (K/K) Rise to High-Z

(Active to High-Z)[24,25] 0.45–0.45–0.45–0.45ns

tCLZ tCHQX1 Clock (K/K) Rise to Low-Z[24, 25] –0.45 – –0.45 – –0.45 – –0.45 – ns

tQVLD[28] tCQHQVLD Echo Clock High to QVLD Valid –0.20 0.20 –0.20 0.20 –0.20 0.20 –0.20 0.20 ns

Notes

23. When a part with a maximum frequency above 300 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is being

operated and outputs data with the output timings of that frequency range.

24. This part has a voltage regulator internally; tPOWER is the time that the power needs to be supplied above VDD minimum initially before a read or write operation can

be initiated.

25. tCHZ, tCLZ, are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 100 mV from steady-state voltage.

26. At any given voltage and temperature tCHZ is less than tCLZ and tCHZ less than tCO.

27. These parameters are extrapolated from the input timing parameters (tKHKH - 250ps, where 250ps is the internal jitter. An input jitter of 200ps(tKCVAR) is already included

in the tKHKH). These parameters are only guaranteed by design and are not tested in production.

28. tQVLD spec is applicable for both rising and falling edges of QVLD signal.

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Document Number: 001-05384 Rev. *E Page 23 of 28

DLL Timing

tKC Var tKC Var Clock Phase Jitter – 0.20 – 0.20 – 0.20 – 0.20 ns

tKC lock tKC lock DLL Lock Time (K) 2048 – 2048 – 2048 – 2048 – cycles

tKC Reset tKC Reset K Static to DLL Reset[28] 30–30–30–30– ns

Switching Characteristics

Over the Operating Range[22, 23] (continued)

Parameter

Consortium

Parameter Description 400 MHz 375 MHz 333 MHz 300 MHz Unit

Min Max Min Max Min Max Min Max

Note

29. Hold to >VIH or <VIL.

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Document Number: 001-05384 Rev. *E Page 24 of 28

Switching Waveforms

Read/Write/Deselect Sequence[30, 31, 32]

Figure 3. Waveform for 2.5 Cycle Read Latency

tKH tKL tCYC tKHKH

ttSA HA

SC HC

tHD

tSC tHC

A0 A1 A2 A3

tSD

D11

D10 D12 D13 D30 D31 D32 D33

WPS

RPS

NOPREAD

NOP WRITE READ WRITE

123 4 567

tCQOH

CCQO

CLZ

tCO

tDOH tCQDOH

CQD

ttCH

tCQOH CCQO

tQVLD

QVLD

DON’T CARE UNDEFINED

(Read Latency = 2.5 Cycles)

Q00 Q01 Q20Q02 Q21

Q03 Q22 Q23

tCQH t

CQHCQH

Notes

30. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, i.e., A0+1.

31. Outputs are disabled (High-Z) one clock cycle after a NOP.

32. In this example, if address A2 = A1, then data Q20 = D10 and Q21 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.

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Document Number: 001-05384 Rev. *E Page 25 of 28

Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

Package

Diagram Package Type

Operating

Range

400 CY7C1561V18-400BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-400BZC

CY7C1563V18-400BZC

CY7C1565V18-400BZC

CY7C1561V18-400BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-400BZXC

CY7C1563V18-400BZXC

CY7C1565V18-400BZXC

CY7C1561V18-400BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1576V18-400BZI

CY7C1563V18-400BZI

CY7C1565V18-400BZI

CY7C1561V18-400BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-400BZXI

CY7C1563V18-400BZXI

CY7C1565V18-400BZXI

375 CY7C1561V18-375BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-375BZC

CY7C1563V18-375BZC

CY7C1565V18-375BZC

CY7C1561V18-375BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-375BZXC

CY7C1563V18-375BZXC

CY7C1565V18-375BZXC

CY7C1561V18-375BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1576V18-375BZI

CY7C1563V18-375BZI

CY7C1565V18-375BZI

CY7C1561V18-375BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-375BZXI

CY7C1563V18-375BZXI

CY7C1565V18-375BZXI

CY7C1561V18

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CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 26 of 28

333 CY7C1561V18-333BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-333BZC

CY7C1563V18-333BZC

CY7C1565V18-333BZC

CY7C1561V18-333BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-333BZXC

CY7C1563V18-333BZXC

CY7C1565V18-333BZXC

CY7C1561V18-333BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1576V18-333BZI

CY7C1563V18-333BZI

CY7C1565V18-333BZI

CY7C1561V18-333BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-333BZXI

CY7C1563V18-333BZXI

CY7C1565V18-333BZXI

300 CY7C1561V18-300BZC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Commercial

CY7C1576V18-300BZC

CY7C1563V18-300BZC

CY7C1565V18-300BZC

CY7C1561V18-300BZXC 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-300BZXC

CY7C1563V18-300BZXC

CY7C1565V18-300BZXC

CY7C1561V18-300BZI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Industrial

CY7C1576V18-300BZI

CY7C1563V18-300BZI

CY7C1565V18-300BZI

CY7C1561V18-300BZXI 51-85195 165-Ball Fine Pitch Ball Grid Array (15 x 17 x 1.4 mm) Pb-Free

CY7C1576V18-300BZXI

CY7C1563V18-300BZXI

CY7C1565V18-300BZXI

Ordering Information (continued)

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or

visit www.cypress.com for actual products offered.

Speed

(MHz) Ordering Code

Package

Diagram Package Type

Operating

Range

CY7C1561V18

CY7C1576V18

CY7C1563V18

CY7C1565V18

Document Number: 001-05384 Rev. *E Page 27 of 28

Package Diagram

Figure 4. 165-ball FBGA (15 x 17 x 1.40 mm), 51-85195

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*%$%#2%&%2%.#%-/$%3)'.#

0!#+!'%#/$%""!$

51-85195-*A

Document Number: 001-05384 Rev. *E Revised July 24, 2007 Page 28 of 28

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, IDT, NEC, Renesas, and Samsung. All product and company names mentioned in this document

are the trademarks of their respective holders.

CY7C1561V18

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CY7C1563V18

CY7C1565V18

of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used

for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use

as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support

systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),

United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,

and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress

integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without

the express written permission of Cypress.

Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES

OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not

assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where

a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer

assumes all risk of such use and in doing so indemnifies Cypress against all charges.

Use may be limited by and subject to the applicable Cypress software license agreement.

Document History Page

Document Title: CY7C1561V18/CY7C1576V18/CY7C1563V18/CY7C1565V18, 72-Mbit QDR™-II+ SRAM 4-Word Burst Archi-

tecture (2.5 Cycle Read Latency)

Document Number: 001-05384

REV. ECN NO. ISSUE

DATE

ORIG. OF

CHANGE DESCRIPTION OF CHANGE

** 402911 See ECN VEE New Data Sheet

*A 425251 See ECN VEE Updated the switching waveform

Corrected the typos in DC parameters

Updated the DLL section

Added additional notes in the AC parameter section

Updated the Power up sequence

Added additional parameters in the AC timing

*B 437000 See ECN IGS ECN for Show on web

*C 461934 See ECN NXR Moved the Selection Guide table from page# 3 to page# 1.

Modified Application Diagram.

Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH

from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching

Characteristics table

Modified Power Up waveform.

Included Maximum ratings for Supply Voltage on VDDQ Relative to GND.

Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD.

Changed the Pin Definition of IX from Input Load current to Input Leakage current on

page#18.

*D 497567 See ECN NXR Changed the VDDQ operating voltage to 1.4V to VDD in the Features section, in

Operating Range table and in the DC Electrical Characteristics table

Added foot note in page# 1

Changed the Maximum rating of Ambient Temperature with Power Applied from –10°C

to +85°C to –55°C to +125°C

Changed VREF (Max) spec from 0.85V to 0.95V in the DC Electrical Characteristics

table and in the note below the table

Updated footnote #21 to specify Overshoot and Undershoot Spec

Updated IDD and ISB values

Updated ΘJA and ΘJC values

Removed x9 part and its related information

Updated footnote #25

*E 1351243 See ECN VKN/FSU Converted from preliminary to final

Added x8 and x9 parts

Changed tCYC max spec to 8.4 ns for all speed bins

Updated footnote# 23

Updated Ordering Information table