iChipTM CO561AD-S/P
p/n 50-3100-01
www.connectone.com
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FeaturesDescription
● Microprocessor-controllable through a standard
serial connection or optional parallel bus.
● Supports remote firmware update by host, Email or
direct modem to modem communications.
● Internally includes 128K SRAM and 256K/512K
flash memories.
● Supports external memory extensions.
● Driven by the simple “AT+i" extension to the AT
command set.
● Standalone Internet communication capabilities.
● Internet Protocols and related formats:
PPP, LCP, IPCP, IP, TCP, UDP, DNS, SMTP,
POP3, HTTP and PAP, CHAP or Script
authentication.
● Binary Base64 encoding and MIME.
● Supports data modems with throughput up to 56K
bps.
● Optional Ethernet interface.
● Supports power-saving standby and sleep modes.
● Single, +5V power supply, CMOS technology.
● Supports nonvolatile memory to store all
functional and Internet-related parameters.
● Supports several layers of status reports.-
● Internal self-test procedures.
● Internal "Watch-Dog" guard circuit.
● PLCC68 Package.
iChip is a low-cost intelligent peripheral device,
which provides Internet connectivity solutions to
a myriad of embedded devices. A serial bus
interfaces iChip to a device’s host processor, via
an on-chip UART. An optional 8/16-bit interface
to a host processor is supported as well, by
adding an external UART for low-bandwidth
applications or a dual-port-RAM for high
bandwidth applications. iChip also directly
interfaces a serial or parallel data modem,
through which it supports independent
communications on the Internet via a dial-up ISP
connection. An optional Ethernet connection is
supported by adding an external, 16-bit, MAC.
As an embedded, self-contained Internet engine,
iChip acts as mediator device between a host
processor and an Internet communications
platform. By completely offloading Internet
connectivity and standard protocols, it relieves the
host from the burden of handling Internet
communications. From the perspective of a host
device, the complexity of establishing and
maintaining Internet-related sessions are reduced to
simple, straightforward commands, which are
entirely dealt with within iChip’s domain.
Through its host Application Program Interface,
iChip accepts commands formatted in Connect
One's “AT+i” extension to the renowned Hayes
AT command set. (continued…)
___________________________________________________________________________________________________________________________________________
Functional Block Diagram Pin Diagram
PLCC68
Host Serial
INTERFACE
Local Parallel/Serial
INTERFACE
iChip
Rx,Tx,CTS,RTS,DTR
RESET
LD0-D15
LA0-A19
Rx,Tx,CTS,RTS,DTR
X
1
X2
CS Modem
L
int
LWR
LRD
CS Ext. RAM
Crystal
CPU
Core
RAM
128Kx8
FLASH
128Kx16
-or-
256Kx16
CO561AD-S/P
50-3100-01 9952
©Connect One ‘99
CO561AD-S/P
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iChipTM
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Connect One Ltd. 2 of 46 November 1999
Description (continued)
Commands are available to store and
manipulate functional and Internet-related
nonvolatile parameter data; transmit and
receive textual Email messages; transmit and
receive binary (MIME encoded) Email
messages, fetch HTML web pages; and
download parameter and firmware updates for
the host device or iChip itself. Send command
variants exist for immediate communications or
scheduled "store-and-forward”.
iChip supports several levels of status reporting
to the host. In addition, the iChip is connected
to a modem device, the host may issue standard
AT commands to gain direct access to the
modem. In the presence of AT commands,
iChip automatically operates in transparent
mode, thus emulating a direct host to modem
environment.
Using the attached communications platform,
iChip gains access to the Internet to
independently manage standard Internet
protocols that transmit and receive messages.
When hooked up to a standard data modem
device, iChip provides all the necessary
procedures to dial-up an ISP, authenticate the
user and establish a PPP connection.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 3 of 46 November 1999
Protocol Compliance
iChip complies with the following Internet standards:
RFC 1331 Point-to-Point Protocol (PPP)
RFC 1661 Point-to-Point Protocol (PPP)
RFC 1332 PPP Internet Protocol Control Protocol (IPCP)
RFC 1334 PPP Authentication Protocols (PAP)
RFC 791 Internet Protocol (IP)
RFC 793 Transmission Control Protocol (TCP)
RFC 768 User Datagram Protocol (UDP)
RFC 821 Simple Mail Transfer Protocol (SMTP)
RFC 1939 Post Office Protocol - Version 3 (POP3)
RFC 1957 Some Observations on the Implementations of the Post Office
Protocol (POP3)
RFC 822 Standard for the Format of ARPA Internet Text Messages
RFC-2045 Multipurpose Internet Mail Extensions (MIME) Part One: Format of
Internet Message Bodies
RFC-2046 Multipurpose Internet Mail Extensions (MIME) Part Two: Media
Types
RFC-2047 MIME (Multipurpose Internet Mail Extensions) Part Three: Message
Header Extensions for Non-ASCII Text
RFC-2048 Multipurpose Internet Mail Extensions (MIME) Part Four:
Registration Procedures
RFC-2049 Multipurpose Internet Mail Extensions (MIME) Part Five:
Conformance Criteria and Examples
Table 1. Internet Protocol Compliance
CO561AD-S/P
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iChipTM
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Connect One Ltd. 4 of 46 November 1999
List of Terms and Acronyms
Base64 Encoding scheme, which converts arbitrary binary data into a
64-character subset of US_ASCII. The encoded data is 33% larger
than the original data.
DNS Domain Name System. Defines the structure of internet names and
their association with IP addresses
iChipTM Connect One’s Internet-in-a-chip module for embedded Internet
connectivity.
IP Internet Protocol. Provides for transmitting blocks of data, called
datagrams, from sources to destinations, which are hosts identified
by fixed length addresses. Also provides for fragmentation and
reassemble of long datagrams, if necessary.
IPCP Internet Protocol Control Protocol. Establishes and configures the
Internet Protocol over PPP. Also negotiates Van Jacobson TCP/IP
header compression with PPP
ISP Internet Service Provider. Commercial company that provides
internet access to end (mostly PC) users through a dial-up
connection.
LCP Link Control Protocol. Negotiates data link characteristics and
tests the integrity of the link.
MIME Multipurpose Internet Mail Extensions. Extends the format of
mail message bodies to allow multi-part textual and non-textual data
to be represented and exchanged between internet mail servers.
PAP Password Authentication Protocol. Used optionally by the PPP
protocol to identify the user to the ISP.
CHAP Challenge Authentication Protocol. Extends the PAP procedure by
introducing advanced elements of security.
POP3 Post Office Protocol Version 3. Allows a workstation/PC to
dynamically retrieve mail from a mailbox kept on a remote server.
PPP Point-to-Point Protocol. Communications protocol used to send
data across serial communication links, such as modems.
RFC Request For Comments. Collections of standards that define the
way remote computers communicate over the internet.
SMTP Simple Mail Transfer Protocol. Provides for transferring mail
reliably and efficiently over the internet.
TCP Transmission Control Protocol. Provides reliable stream-oriented
connections over the internet. Works in conjunction with its
underlying IP protocol.
AT+i Connect One's Internet extension to the industry-standard Hayes
AT command set. Supports simplified Internet connectivity
commands in the spirit of the AT syntax.
"Leave on
Server"
An option designating whether retrieved Email messages are to be
left intact on the server for subsequent downloads or are to be
deleted from the server after a successful download.
Table 2. Terms and Acronyms
CO561AD-S/P
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iChipTM
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Connect One Ltd. 5 of 46 November 1999
1. Functional Description
1.1 Overview
The Connect One iChip is an integrated, firmware driven,
self-contained Internet engine, available in a 68-pin PLCC
package. iChip accepts simple ASCII commands from a host
CPU via a serial communication bus, and manages an Internet
communication session to send and receive Email messages
through a linked modem optional Ethernet communications
platform. For dial-up modem configurations, iChip is available
in two forms: CO561AD-S interfaces a serial modem, while
CO561AD-P interfaces a parallel modem. CO561AD-S is also
available mounted on a carrier board, CO561AD-C, that is
pin-compatible with Conexant’s SocketModem.
iChip contains nonvolatile FLASH memory to store its
firmware and Internet-related operational parameters. Remote
firmware and parameter updates are supported through the host
link, by Email or directly through the communications platform.
1.2 Technical Specifications
1.2.1 General
iChip constitutes a complete Internet messaging solution for
non-PC embedded devices. It acts as a mediator device to
completely offload the host processor of Internet related
software and activities. An industry-standard asynchronous
serial link connects iChip to the host processor. Programming,
monitoring and control are fully supported using Connect One’s
AT+i extension to the standard AT command set.
An additional industry-standard asynchronous serial link
connects iChip CO561AD-S to a standard serial modem and a
16-bit parallel bus connects iChip CO561AD-P to an 8/16- bit
parallel modem or optional Ethernet MAC for Internet access.
In serial/parallel modem configurations, iChip supports direct
host-to-modem operations using the standard AT command set.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 6 of 46 November 1999
1.2.2 Data Rates
iChip supports standard baud rate configurations from 4800 bps
up to 38400 bps on the host asynchronous serial
communications bus. As shipped, iChip defaults to a
preliminary connection rate of 9600 bps. The default baud rate
may be changed permanently by using the AT+iBDR
command. In serial modem configurations, using iChip
CO561AD-S, a rate of 38400 bps is used to accommodate
modems with communication speeds up to V.90 56K bps.
1.2.3 Operation
All iChip Internet and parameter operations are controlled by
AT+i commands.
1.2.3.1 Transparent Mode
In modem configurations, iChip defaults to transparent mode,
allowing the host to control the modem device directly. Control
is implemented by issuing standard AT commands to iChip. In
this mode iChip transparently echoes the AT commands to the
modem, as well as echoing the modem responses back to the
host. In addition, hardware flow control signals are emulated on
the host side to reflect the levels set by the modem and
vice-versa. iChip supports interlacing AT+i and AT commands,
while the modem is in command mode.
When the modem is put into data mode, by issuing a dial
command, transparent mode is sustained throughout the
data-mode session.
1.2.3.2 Command Mode
iChip commands are implemented using the AT+i command
set. Command flow exists only on the host serial bus, between
the host and iChip.
1.2.3.3 Internet Mode
iChip enters Internet mode after being issued an Internet
messaging command to send or receive an Email message.
iChip attempts to establish an Internet connection and carry out
the required activity through the communication platform link.
While in this mode, AT+i commands are supported to monitor
and control the process when needed. All other AT+i
commands return with an I/BUSY response.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 7 of 46 November 1999
1.2.3.4 Direct Modem Firmware Update Mode
In a modem configuration, issuing an AT+iFU command enters
this mode. iChip monitors the modem for an incoming call by
detecting the ‘RING’ response. When called, iChip instructs the
modem to answer the call and assumes a YMODEM session to
receive a file containing a firmware update. The incoming file
contents are downloaded and authenticated. If the new firmware
image checks out the existing firmware is replaced in the
on-chip flash memory and iChip is reinitialized.
1.2.4 Host Serial Connection
iChip supports a full-duplex, TTL-level, serial communications
link with the host processor. Full EIA-232-D hardware flow
control, including Tx, Rx, CTS, RTS, and DTR lines, is
supported.
1.2.5 Serial Connection to Dial-up Modem
iChip CO561AD-S supports a full-duplex, TTL-level, serial
communications link with the modem device. Full EIA-232-D
hardware flow control, including Tx, Rx, CTS, RTS, and DTR
lines, is supported.
1.2.6 Parallel Connection to Dial-up Modem
iChip CO561AD-P supports a parallel modem configuration
using an 8-bit or 16-bit, TTL-level parallel bus. A CE
(chip-enable), Read, Write, IRQ and Address lines are available
for a complete hardware interface.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 8 of 46 November 1999
2. Hardware Interface
iChip interfaces between a host CPU and a modem.
2.1 Host Interface
The host interface is a serial DTE interface. iChip can change
the rate and format of the data sent and received from the host
CPU. Speeds of 4800, 7200, 9600, 19200, and 38400 bps are
supported in the following data formats:
Parity Data Length
(No. of Bits)
No. of
Stop Bits
Character
Length
(No. of Bits)
None 7 2 10
Odd 7 1 10
Even 7 1 10
None 8 1 10
CO561AD-S/P
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iChipTM
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Connect One Ltd. 9 of 46 November 1999
2.2 Modem Interface.
There are two versions of iChip, which differ by modem
interface: serial and parallel.
2.2.1 Serial version.
Fig. 2-1. Block diagram of the iChip with a serial modem interface
In addition to a serial modem interface, iChip supports a
memory expansion option, used to increase the store and
forward buffer.
iChip CO561AD-S
Serial Version
Rx,Tx,
CTS,RTS,DTR,DSR,
RI,CD
Rx,Tx,
CTS,RTS,DTR,DSR,
RI,CD
UART with auto
baud rate
UART
Local Addr
Bus 20-bit
Data Bus
16-bit
Local Bus Interface Unit
CPU
Core
Three 16-bit
Timers
Interrupt
Controller
WR
RD
Internal FLASH
128Kx16 or
256Kx16
Internal RAM
128KB x 8
WDT
RAM expansion
CS
DMA
Controller
CO561AD-S/P
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iChipTM
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Connect One Ltd. 10 of 46 November 1999
2.2.2 Parallel Version
Fig. 2-2. Block diagram of iChip with a parallel modem interface
A parallel modem is interfaced with the iChip's local bus using
a dedicated CS (chip select) line. A separate CS line is used for
memory expansion option.
iChip CO561AD-P
Parallel Version
Rx,Tx,
CTS,RTS,DTR,DSR,
RI,CD
UART with auto
baud rate
Local Addr
Bus 20-bit
Data Bus
16-bit
Local Bus Interface Unit
CPU
Core
Three 16-bit
Timers
Interrupt
Controller
WR
RD
Modem CS
Modem INT
Internal FLASH
128kx16 or
256Kx16
Internal RAM
128KB x 8
WDT
RAM expansion
CS
DMA
Controller
CO561AD-S/P
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iChipTM
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Connect One Ltd. 11 of 46 November 1999
3. Pin Descriptions
3.1 Pin Assignments
3.1.1 Serial Version
Fig. 3-1. PLCC68 Package serial version: iChip CO561AD-S
~CTSM
~DTRM
VCC
AD5
AD4
AD3
AD2
AD1
AD0
A17
AD7
AD14
AD13
~RES
AD11
NC
~DSRH
AD10
AD9
A16
A13
A19
A15
A12
A14
A5
CLKO
X2
X1
NC
GND
A18
A8
A7
A4
A3
A11
A9
GND
A10
A
0
~CDH
GND
~RIH
MDSEL
~DSR
~CD
GND
~RD
A2
A6
~RTSM
RXD
TXDM
RXDM
TXDH
AD15
AD6
AD12
AD8
NC
~DT
R
A19
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
52 ~WR
~BHE
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
34
~RTSH
~CTSH
NC
CO561AD-S
CO561AD-S/P
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iChipTM
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Connect One Ltd. 12 of 46 November 1999
3.1.2 Parallel Version
Figure 3-2. PLCC68 Package, parallel version: iChip CO561AD-P
VCC
AD5
AD4
AD3
AD2
AD1
AD0
A17
AD7
AD14
AD13
~RES
AD11
NC
~DSRH
AD10
AD9
A16
A13
A19
A15
A12
A14
A5
CLKO
X2
X1
ALE
GND
A18
A8
A7
A4
A3
A11
A
9
GND
A10
A0
~RTSH
~CTSH
~CDH
NC
GND
~RIH
MDSEL
~MDCS
NC
GND
~RD
A2
A6
~RTS
RXD
TXD
RXD
NC
TXDH
AD15
AD6
AD12
AD8
~DT
R
A1
9
MDINT
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
52 ~WR
~BHE
33
32
31
30
2
9
28
27
26
25
24
23
22
21
20
19
18
34
NC
CO561AD-P
CO561AD-S/P
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iChipTM
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Connect One Ltd. 13 of 46 November 1999
3.2 iChip Pin Functional Descriptions
3.2.1 Local Bus Signals
A19–A0
Address Bus (output, three-state, synchronous)
These pins supply non-multiplexed memory or I/O addresses to the system one half of a CLKO period
earlier than the multiplexed address and data bus AD15–AD0.
During a bus hold or reset condition, the address bus is in a high-impedance state.
AD15–AD0
Address and Data Bus (input/output, three-state, synchronous, level-sensitive)
AD15–AD0—These time-multiplexed pins supply memory or I/O addresses and data to the system.
This bus can supply an address to the system during the first period of a bus cycle. It supplies data to
the system during the remaining periods of that cycle.
When ~WR is deasserted, these pins are three-stated.
ALE
Address Latch Enable (output, synchronous)
This pin indicates to the system that an address appears on the address and data bus
AD15–AD0).
The address is guaranteed to be valid on the trailing edge of ALE.
This pin is not three-stated during a bus hold or reset.
~BHE
Bus High Enable (three-state, output, synchronous)
During a memory access, this pin and the least-significant address bit (AD0 or A0) indicate to the
system which bytes of the data bus (upper, lower, or both) participate in a bus cycle. The ~BHE and
AD0 pins are encoded as shown in the table below.
Table 3.2.1 Data Byte Encoding
~BHE AD0 Type of bus cycle
0 0 Word Transfer
1 0 Even Byte Transfer
0 1 Odd Byte Transfer
11N/A
BHE floats during bus hold and reset.
During refresh cycles, the A bus and the AD bus are not guaranteed to provide the same address during
the address phase of the AD bus cycle.
For this reason, the A0 signal cannot be used in place of the AD0 signal to determine refresh cycles.
CLKO
Clock Output.
This pin Supplies the internal clock to the system. CLKO remains active during RESET.
~RD
Read Strobe (output, synchronous, three-state)
This pin indicates to the system that the iChip is performing a memory or I/O read cycle.
~RD is guaranteed to not be asserted before the address and data bus is floated during the
address-to-data transition. ~RD floats during a bus hold condition.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 14 of 46 November 1999
~RES
Reset (input, asynchronous, level-sensitive)
This pin requires the iChip to perform a reset.
When ~RES is asserted, the iChip immediately terminates its present activity and clears its internal
logic.
~RES must be held Low for at least 1 ms.
~RES can be asserted asynchronously to CLKO because ~RES is synchronized internally. For proper
initialization, VCC must be within specifications, and CLKO must be stable for more than four CLKO
periods during which RES is asserted.
The iChip begins fetching instructions approximately 6.5 CLKO periods after ~RES is de-asserted.
This input is provided with a Schmidt trigger to facilitate power-on RES generation via an RC network.
~WR
Write Strobe (output, synchronous)
This pin indicates to the system that the data on the bus is to be written to a memory or I/O device.
~WR floats during reset condition.
X1
Crystal Input (input)
This pin and the X2 pin provide connections for a fundamental mode or third-overtone,
parallel-resonant crystal used by the internal oscillator circuit. To provide the iChip with an external
clock source, connect the source to the X1 pin and leave the X2 pin unconnected.
X2
Crystal Output (output)
This pin and the X1 pin provide connections for a fundamental mode or third-overtone,
parallel-resonant crystal used by the internal oscillator circuit. To provide the iChip with an external
clock source, leave the X2 pin unconnected and connect the source to the X1 pin.
GND
Ground
Ground pins connect the iChip to the system ground.
VCC
Power Supply (input)
These pins supply power (+5 V) to the iChip.
3.2.2 Host Interface Signals
TXDH
Transmit Data (output, asynchronous)
This pin supplies asynchronous serial transmit data to the system from serial port.
RXDH
Receive Data 1 (input, asynchronous)
This pin supplies asynchronous serial receive data from the system to asynchronous serial port.
~CTSH
Clear-to-Send 1 (input, asynchronous)
This pin provides the Clear to Send signal for asynchronous serial port 1 when the hardware flow
control is enabled for the port. The ~CTSH signal gates the transmission of data from the associated
serial port transmit register. When ~CTSH is asserted, the transmitter begins transmission of a frame of
data, if any is available. If ~CTSH is de-asserted, the transmitter holds the data in the serial port
transmit register. The value of ~CTSH is checked only at the beginning of the transmission of the
frame.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 15 of 46 November 1999
~RTSH
Host Interface Ready-to-Send (output, asynchronous)
This pin provides the Ready to Send signal for asynchronous serial port when the hardware flow
control is enabled for the port. The ~RTSH signal is asserted when the associated serial port transmit
register contains data which has not been transmitted.
~DSRH
Data Set Ready (input, synchronous)
When flow control is enabled, this pin is Data Set Ready Input
~DTRH
Data Terminal Ready (output, synchronous)
When flow control is enabled, this pin operates as Data Terminal Ready Output
~CDH
Channel 1 Carrier Detect (output, synchronous)
This pin indicates to the system that a carrier was detected by the communication device (modem).
~RIH
Channel Ring Indicator (output, synchronous)
This pin indicates to the system that a Ring signal was detected by communication device (modem).
MDSEL
Mode Select Input
When this pin is held Low during power up, for at least 5 seconds, the iChip will automatically enter
firmware update mode.
During a firmware update procedure, when an external modem dials to the iChip, pulling this pin down
to Low will cause the iChip to immediately answer the call and begin the update session.
3.2.3 Version Specific Signals
3.2.3.1 Serial Version
RXDM
Receive Data 0 (input, asynchronous)
This pin supplies asynchronous serial receive data from the system to asynchronous serial port 0.
TXDM
Transmit Data (output, asynchronous)
This pin supplies asynchronous serial transmit data to the system from serial port 0.
~CDM
Carrier Detect (input, asynchronous, internal pull-up)
When configured in Serial-to-Serial mode, this pin is Channel 0 Carrier Detect input.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 16 of 46 November 1999
~DSRM
Data Set Ready (input, asynchronous).
When Flow control is enabled, this pin is Channel 0 Data Set Ready input.
~RTSM
Ready-to-Send 0 (output, asynchronous)
This pin provides the Ready to Send signal for asynchronous serial port 0 when the hardware flow
control is enabled for the port. The ~RTSM signal is asserted when the associated serial port transmit
register contains data that has not been transmitted.
~CTSM
Clear-to-Send (input, asynchronous)
Enable-Receiver-Request M (input, asynchronous)
This pin provides the Clear to Send signal for asynchronous serial port when flow control option is
enabled. The ~CTSM signal gates the transmission of data from the associated serial port transmit
register. When ~CTSM is asserted, the transmitter begins transmission of a frame of data, if any is
available. If ~CTSM is de-asserted, the transmitter holds the data in the serial port transmit register.
The value of ~CTSM is checked only at the beginning of the transmission of the frame.
~DTRM
Host Interface Data Terminal Ready (Output, asynchronous)
When flow control is enabled, this pin is Channel Data Terminal Ready Output
3.2.3.2 Parallel Version
~MDCS
Modem Chip Select.
Active low signal used to select parallel modem.
MODINT
Maskable Interrupt Request (input, asynchronous, edge-triggered)
This pin is used as Modem Interrupt Request.
It is edge-triggered only and must be held until the interrupt is acknowledged.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 17 of 46 November 1999
4. AT+i Commands
The AT+i commands are an extension to the industry standard
AT command set used for modem control. Each command must
begin with an AT+i prefix and is terminated with a Carriage
return (CR – ASCII 013) character. The ISO 646 character set
(CCITT T.50 International Alphabet 5, American Standard
Code for Information Interchange) is used for the issuance of
commands and responses. Only the low-order 7 bits of each
character are used for commands or parameters; the high-order
bit is ignored. Upper case characters are equivalent to lower
case characters. A command line may contain only a single
command and is limited to 240 characters.
The AT+i command is restricted to printable ASCII characters
(032 - 126). Space characters (ASCII 032) and control
characters other than CR and BS (ASCII 010) in the command
string are ignored. Characters that precede the AT+i prefix are
ignored. The command line interpretation begins upon receipt
of the carriage return character. If a syntax error is found
anywhere in a command, the remainder of the line will be
ignored and the I/ERROR result code will be returned.
Commands will only be accepted by iChip once the previous
command has been fully executed, which is normally indicated
by the return of an appropriate result code.
The AT+i extension is described in full detail in the “AT+i
Programmers Manual for iChip and iModem”, Publication
Number 20-5000-01.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 18 of 46 November 1999
4.1 Result Codes
Response String Code Denotation
I/OK 30 Command was successfully executed.
I/BUSY 31 iChip Busy. Command discarded.
I/DONE 32 iChip completed Internet activity. Returned to command mode
I/RCV 33 Marks beginning of Email Retrieve mode. iChip will not
respond to any commands, excluding ‘+++’ (Break).
I/EOM 34 Marks end of Email message during retrieve.
I/MBE 35 This flag is returned when attempting to retrieve mail from an
empty mailbox.
I/ERROR (nnn) Command Error Encountered. Command Discarded.
nnn:
41 Illegal delimiter 74 Connection with ISP lost
42 Illegal value 75 Access denied to ISP server
43 CRLF expected 76 Unable to locate POP3 server
44 Number expected 77 POP3 server timed out
45 CRLF or ‘,’ expected 78 Access denied to POP3 server
46 DNS expected 79 POP3 failed
47 ‘:’ or ‘~’ expected 80 No suitable message in mailbox
48 String expected 81 Unable to locate SMTP server
49 ‘:’ or ‘=’ expected 82 SMTP server timed out
50 Text expected 83 SMTP failed
51 Syntax error 100 Error restoring default parameters
52 ‘,’ expected 101 No ISP access numbers defined
53 Illegal command code 102 No USRN defined
54 Error when setting
parameter value
103 No PWD entered
55 Error when getting
parameter value
104 No DNS defined
56 User abort 105 No POP3 defined
57 Error when trying to
establish PPP
106 No MBX (mailbox) defined
58 Error when trying to
establish SMTP
107 No MPWD (mailbox password)
defined
59 Error when trying to
establish POP3
108 No TOA (addressee) defined
61 Internal memory failure 109 No REA (return address) defined
70 Modem failed to respond 110 No SMTP defined
71 No dial tone response
72 No carrier modem response
73 Dial failed
Table 4-1. AT+i Result Code Summary
CO561AD-S/P
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iChipTM
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Connect One Ltd. 19 of 46 November 1999
4.2 AT+i Command Set Summary
Command Function Parameters/Description
AT+i Command Prefix Required to precede all commands
Host Interface
En Echo Mode n=0 -- Do not echo host characters.
n=1 -- Echo all host characters.
This command is equivalent to and interchangeable
with ATEn.
Parameter Database Maintenance
<par>=value
or
<par>:value
Set Parameter value stored in parameter <par> in nonvolatile
memory. <par> will retain set value across power
down, indefinitely. For description of all available
parameters see section 4.3
<par>~value Assign single
session parameter
value
value is assigned to parameter <par> for the
duration of a single Internet session. Following the
session the original value is restored.
<par>? Read parameter Parameter value is returned
<par>=? Parameter what? Returns the allowed values for this parameter.
FD Factory Defaults Restores all parameters to Factory Defaults.
Status Report
RP<i> Request Status
report
Returns a status report value or sets a status report
mode based on <i>
Email Send
EMA:<text> Send textual
Email immediate
Defines the textual contents of the Email body.
Following this command several text lines may be
sent in sequence. Sending a CR.CR (line containing
only a period) terminates the text body. After
termination the Email is sent automatically. Total
<text> size is limited to 96K.
Retrieve Email from Mailbox
RML Retrieve Mail List Retrieves an indexed, short form, list of all
qualifying messages in mailbox.
RMH:<i> Retrieve Header Retrieves only the Email header part from the <i>'th
Email in the mailbox.
RMM:<i> Retrieve Email Retrieves all Email contents (header + body) of the
<i>'th Email in the mailbox.
Remote Update
FU Firmware update In a modem configuration, enters firmware update
mode.
Table 4-2. AT+i Command Summary
CO561AD-S/P
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iChipTM
_____________________________________________________________________________________________________________________________
Connect One Ltd. 20 of 46 November 1999
5. Parameter Database
5.1 Overview
iChip contains an internal database of operational parameters,
which are required to designate the Internet related account
information, Email message structure and default modes of
operation. Parameter values are stored internally in nonvolatile
flash memory. This feature facilitates parameter value setup, by
supporting one-time programming by the embedded host or an
external system. Parameters must be setup for iChip to
successfully conduct Internet sessions. Parameters SET and
READ operations are available using AT+i commands.
5.2 Parameter Set Summary
Parameter Type Range Default Description
LVS Byte 0..1 1(YES) Leave on Server: 1(YES) 0(NO)
HDL Byte 0..255 0(no
limit)
Limit number of header lines retrieved.
XFH Byte 0..1 1 Transfer Email headers. 1(Enable) 0(Disable)
FLS String 62chars NULL --
(no filter)
Filter string must exist in message header to
qualify for Retrieve.
SBJ String 96chars NULL Contents of the Email subject field.
TOA String 32chars NULL Primary Addressee, to where Email will be sent.
TO String 96chars NULL Addressee Description/Name in Email header.
REA String 32chars NULL Return Email Address
FRM String 96chars NULL Sender Description/Name in Email header.
CCn String 32chars NULL Alternate Addressee (CC: field) <n>:1..4
ISPn Phone # 32chars NULL ISP's access phone number. <n>:1..2
ATH Byte 0..2 1(PAP) Use CHAP(2), PAP(1) or Script(0) authentication.
USRN String 32chars NULL ISP Connection User name
PWD String 32chars NULL ISP Connection PassWord
DNSn IP address 0.0.0.0 Domain Name Server IP address. <n>:1..2
SMTP String 32chars NULL SMTP server name.
POP3 String 32chars NULL POP3 server name
MBX String 32chars NULL MailBox User name
MPWD String 32chars NULL MailBox password
RDL Byte 0..20 5 Number of Redial tries.
RTO Byte 0..255 180 Timeout before redialing
BDR Byte 4..7 5 (9600) Defines default baud rate on Host connection
Note: Default is reset to 5 every power up.
XRC Byte 0..4 4 Extended Return code. Same as ATXn.
MIS String 126 chars “AT&FE
0V1X4Q0
&D2M1L
3\r”
Modem initialization string.
Table 5-1. iChip Parameter Set
CO561AD-S/P
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iChipTM
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Connect One Ltd. 21 of 46 November 1999
6. Operation
6.1 Parameter Setup
Table 5.1 lists the available iChip parameters and associated
attributes. All parameters are manipulated by issuing
appropriate AT+i commands. A summary of the AT+i
commands used to SET and READ parameter values are listed
in table 4.2.
When a parameter is SET using the '=' operator the value is
stored permanently, however the '~' operator is also available as
an alternative to set a parameter value temporarily for the
duration of a single Internet session. Parameters which are set
permanently will retain the set value indefinitely and across
power down. Temporary settings retain the set value for the
duration of the next Internet SEND or RECEIVE session,
whether the session completed successfully or failed. After each
Internet session, iChip reverts all parameter settings to their
original (permanent) value.
6.1.1 Internet Account Parameters
The following parameters contain the Internet account
information and are required before it is possible to establish a
PPP connection with an Internet Service Provider (ISP):
ISP -- Telephone number string. Used to dial up
the ISP.
ATH -- Preferred authentication method. The
actual authenticate method with the ISP is
defined as a combination of the ATH
parameter value and the ISP capabilities as
received in the LCP protocol.
USRN -- The account login User Name.
PWD -- The account login password.
ISP Capabilities
ATH value CHAP PAP Script
CHAP CHAP PAP Script
PAP PAP PAP Script
Script Script Script Script
Table 6-1. Authentication Levels
CO561AD-S/P
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iChipTM
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Connect One Ltd. 22 of 46 November 1999
6.1.2 Operational Parameters
Several parameters are dedicated to define general modes of
operations:
BDR -- The default host link baud rate. After
power up this value is always 5 (9600 bps).
When issuing a command to change this
parameter, the iChip will issue an I/OK in
the current baud rate and then switch to the
new rate defined in the command.
XRC -- For a modem configuration this parameter
contains the modems extended return code,
as defined by the ATXn command. This
parameter is very useful to define a "blind
dial" mode in environments where the dial
tone cannot be detected by the modem.
RDL -- For a modem configuration this parameter
defines the number of redial attempts when
attempting to dial in to an ISP. The iChip
will redial the ISP in the event that the line
was busy, the ISP did not pick up the line
after 45 seconds or the negotiation /
authentication process failed.
RTO -- For a modem configuration this parameter
defines the delay time between redial
attempts.
6.1.3 General Internet Parameters
The following parameters define general Internet attributes:
DNS -- This parameter defines the major and
(optionally) minor DNS IP addresses to use
when locating SMTP or POP3 servers on
the Internet for when sending or receiving
Email messages.
6.1.4 Email Send
Email messages are sent by the iChip according to the
following parameter values:
SMTP -- This parameter defines the SMTP server
to be used for message transmittal. Most
ISP's have an associated SMTP server,
which must be used when logged on to that
ISP. The SMTP server may be defined as a
direct IP address or a server name, which
will be resolved through the supplied DNS
addresses.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 23 of 46 November 1999
TOA -- This parameter contains the primary
destination Email address, which will
receive the Email message.
CCn -- This parameter contains 4 fields (n=1..4),
each containing an Email address to be
copied with the original Email message
sent.
6.1.5 Email Retrieve
Email messages are received by the iChip according to the
following parameter values:
POP3 -- This parameter defines the POP3 server to
be used for message retrieval. The POP3
server may be defined as a direct IP
address or a server name, which will be
resolved through the supplied DNS
addresses.
MBX -- This parameter contains the POP3
mailbox address from which Emails will be
retrieved.
MPWD -- This parameter contains the POP3 account
password. This password is required in
order to retrieve messages from the
mailbox. It is not necessarily equal to the
ISP account password.
HDL -- This parameter limits the number of
header lines transferred to the host, when
returning the contents of an Email
message. If additional lines exist, they are
discarded.
XFH -- This parameter specifies if Email header
lines shall or shall not be returned before
the message body. (1-Enable header lines
return, 0-Disable headers return).
FLS -- When this parameter contains a value, it is
used as a key to filter Emails. Only
messages that contain the filter key will be
retrieved.
CO561AD-S/P
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iChipTM
_____________________________________________________________________________________________________________________________
Connect One Ltd. 24 of 46 November 1999
6.2 Send Textual Email
After initial setup of all the required parameters an Email send
message may be issued to iChip. Following the 'AT+iEMA:'
prefix, textual Email-body lines are sent in free format to iChip.
iChip accepts text lines including intervening CR/LF characters,
until the terminator line, which is defined as CR/LF.CR/LF (a
period character in the first column of an otherwise empty line).
Upon receipt of the terminator line, iChip will enter Internet
mode and attempt to dial the ISP, connect, authenticate the user,
locate the SMTP server, construct and send the Email message
and then logoff in an orderly fashion. Internet mode is
completely driven by the iChip engine and does not require any
host intervention. The host may issue AT+iRPn commands in
order to follow up on iChip's progress. Other AT+i commands
will be responded to with an 'I/BUSY' string.
6.3 Receive Emails in Mailbox
Once all the required setup parameters for receiving Email are
in place, iChip can be issued AT+i commands to download
Email messages. Following an 'AT+iRMM', the iChip will
enter Internet mode and attempt to dial the ISP, connect,
authenticate the user, locate the POP3 server and download all
existing messages in the mailbox. If the FLS field contains a
qualification filter key, only qualifying messages will be
retrieved. iChip will stream the message headers to the host,
based on the values stored in the XFH and XDL parameters.
Following headers, if any, iChip will stream the Email message
contents. Each message will be terminated with a 'CR/LFEnd of
MessageCR/LF' sequence.
Following the last message, iChip sends a 'No More Messages'
string sequence to the host. When the mailbox does not contain
any messages, iChip will return a 'Mailbox Empty' string. iChip
will accept and respond to, 'AT+iRPn' commands during
Internet mode, except when actually downloading Email
message headers and contents, at which time it will discard the
RPn commands.
Following an 'AT+iRMH' command, the preceding sequence
will be executed, but only Email headers will be returned. Email
body contents will not be downloaded at all. This provides the
host a quick method to verify the quantity and quality of Email
messages that exist in the mailbox.
CO561AD-S/P
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iChipTM
_____________________________________________________________________________________________________________________________
Connect One Ltd. 25 of 46 November 1999
6.4 Firmware Update
In a modem configuration, iChip includes a built-in facility to
download new firmware. Following an 'AT+iFU' command,
iChip will enter the firmware update mode and iChip responds
to the host with a two-line sequence:
I/OK
Waiting for call…
Following this sequence, iChip will not respond to additional
commands from the host. iChip then polls the modem for an
incoming call. When a call arrives, iChip will instruct the
modem to pick-up the call and negotiate a connection.
Following a successful connection, iChip invokes a standard
YMODEM client routine to upload a file from the remote
caller. The received file is stored in a spare section of iChip's
flash device, designated as the 'flash pocket'. After completing
the download process, the flash pocket contents are
checksum'ed and authenticated as a correct and legal firmware
image for iChip. If an error is detected, the new firmware is
discarded; otherwise iChip will proceed to replace the existing
firmware with the new one, followed by an automatic reboot
sequence.
CO561AD-S/P
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iChipTM
_____________________________________________________________________________________________________________________________
Connect One Ltd. 26 of 46 November 1999
6.5 AT+i Usage Examples
Following are several AT+i exemplary sessions that
demonstrate iChip parameter setup, Email SEND and Email
RETRIEVE.
6.5.1 Parameter Setup
AT+i
I/OK
AT+iISP1=’9,4357701’ …Number to dial
I/OK
AT+iUSRN=someuser …Account
I/OK
AT+iPWD=ApassWord
I/OK
AT+iDNS1=192.15.201.55 …Major,Minor DNS
I/OK
AT+iSMTP=mail.domain.com …SMTP server name
I/OK
AT+iXRC=0 …Blind dial
I/OK
AT+iTOA=sombody@domain.com …Define Recipient address
I/OK
AT+iFRM=iChip@domain.com …Define Originator address
I/OK
CO561AD-S/P
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iChipTM
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Connect One Ltd. 27 of 46 November 1999
6.5.2 Email SEND
AT+iTOA~onetimeaddress@somewhere.com …Temporary Recipient
I/OK
AT+iSBJ~Hello form iChip …Temporary Subject
I/OK
AT+iEMA:These characters will be sent in …Email Body
the email body.
Intervening CR/LF characters are allowed
to format the lines of the Email.
The maximum number of characters
allowed in a single Email
transmission is 96K.
.…Terminator line
I/OK
AT+iRP2 …Request Status
Connecting to ISP
AT+iRP2
Establishing SMTP Connection
AT+iRP2
Sending Message
I/DONE …Message sent
6.5.3 Email Retrieve
AT+iRMM …Request Retrieve
I/OK …iChip Acknowledge
These characters will be sent in …Retrieved Message
the email body.
Intervening CR/LF characters are allowed
to format the lines of the Email.
The maximum number of characters
allowed in a single Email
transmission is 96K.
End of Message …End of Message
No More Messages …End of Mailbox
I/DONE …Exit Internet Mode
CO561AD-S/P
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iChipTM
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Connect One Ltd. 28 of 46 November 1999
7. Electrical/Mechanical
Specifications
7.1 Environmental Specifications
7.1.1 Absolute Maximum Ratings
Parameter Rating
Voltage at any pin with respect to ground -1.0 to +7.0 Volts
Operating temperature 0°C to 70°C (32 to 158°F)
Storage temperature -60°C to 120°C (–76 to 248°F)
Soldering temperature (max. 10 sec.) 220°C (428°F)
Package dissipation 1.5 Watts
7.1.2 Recommended Operating Conditions
Parameter Min Nom Max Units
DC Supply 4.75 5.0 5.25 Volts
7.1.3 DC Operating Characteristics
Parameter Min Typical Max Units
High-level Input 2.0 VCC+0.5 Volts
Low-level Input -0.5 0.8 Volts
High-level Output12.4 VCC Volts
Low-level Output 0.45 Volts
Input leakage current +/- 10 µA
Power supply current
(Operating Mode)2
160 250 mA
Power supply current
(Power Save Mode)
10 mA
Input capacitance 20 pF
Notes: 1 IOL = 2mA 2 20 MHz clock
CO561AD-S/P
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iChipTM
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Connect One Ltd. 29 of 46 November 1999
7.2 Interface Timing and Waveforms
7.2.1 Local Bus Read Cycle
A19-A0 Address
AD15-AD0
(Read)
ALE
CLKO
Tclk-3
Tclk
10
~MCS,
~MDCS
~RD
~BHE
2Tclk-15
~BHE
0-250-25
Data
3
25 25
CO561AD-S/P
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iChipTM
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Connect One Ltd. 30 of 46 November 1999
7.2.2 Local bus Write Cycle
A19-A0 Address
AD15-AD0
(Read)
ALE
CLKO
Tclk-3
Tclk
~MCS,
~MDCS
~WR
~BHE
2Tclk-10
~BHE
0-250-20
Data
0
25 25
15
CO561AD-S/P
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iChipTM
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Connect One Ltd. 31 of 46 November 1999
7.3 Mechanical Dimensions
0.990”
0.050”
0.070”
0.106”
0.215
CO561AD-S/P
iChi
p
TM
CO561AD-S/P
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iChipTM
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Connect One Ltd. 32 of 46 November 1999
8. iChip Designs
8.1 General Hardware Architecture in
Embedded Modem Environment
8.1.1 Serial Modem Environment
8.1.2 Parallel Modem Environment
Data
Modem
Seria
l
iChip
Embedded
CPU (Host) Tel.
Seria
l
Data
Modem
iChip
Embedded
CPU (Host) Tel.
Serial
D0-7
A0-2
RD
WR
IRQ
CS
CO561AD-S/P
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iChipTM
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Connect One Ltd. 33 of 46 November 1999
8.2 Reference Design for Embedded
iModem using CO561AD-S
CO561AD-S/P
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iChipTM
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Connect One Ltd. 34 of 46 November 1999
8.3 Bill of Materials for CO561AD-S
Reference Design
Qty Reference Designator P/N, Description Manufacture
4 C1,C2,C3,C4 1UF/16V, Tantalum
4 C5,C6,C8,C14,C16 0.1UF, Ceramic
2 C7,C13 10UF/6.3V
1 C9 33PF, Ceramic
1 C10 22PF, Ceramic
2 C11,C12 1NF/3KV
1 C15 1000UF/25V
16 C17,C18,C19,C20,C21,C22, 56pF, Ceramic
C23,C24,C25,C26,C27,C28,
C29,C30,C31,C32
2 C33,C34 10UF/16V
5 D1,D2,D3,D4,D5 LED, 10mA
1 J1 DC-JACK-MALE
1 J2 DB-9/FEMALE
1 J3 RJ11
1 LS1 HPE1206
8 L1,L2,L3,L4,L5,L6,L7,L8 BK2125HS601 "Taiyoyuden Co., Ltd."
2 L9,L10 2961666681 Fair Rite Inc.
1 RV1 P3100SB Teccor
1 R1 10, 0.125W
2 R2,R3 18R, 0.75W
2 R7,R9 4.7K, 0.125W
2 R4,R8 470, 0.125W
1 S1 PB Switch
1 U1 CO561AD-S Connect One Ltd.
1 U2 SFV56ACFH1D5A0P1 Conexant
1 U3 MC7805AT Motorola
1 U4 MC34164P Motorola
1 U5 MAX237CWG Maxim Inc.
1 U6 LM386D National Semi.
1 Y1 18.432MHZ, HC49
CO561AD-S/P
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iChipTM
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Connect One Ltd. 35 of 46 November 1999
8.4 Reference Design for Embedded
iModem using CO561AD-P
CO561AD-S/P
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iChipTM
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Connect One Ltd. 36 of 46 November 1999
8.5 Bill of Materials for CO561AD-P
Reference Design
Qty Reference Designator P/N, Description Manufacture
4 C1,C2,C3,C4 1UF/16V, Tantalum
4 C5,C6,C8,C14,C16 0.1UF, Ceramic
2 C7,C13 10UF/6.3V
1 C9 33PF, Ceramic
1 C10 22PF, Ceramic
2 C11,C12" 1NF/3KV
1 C15 1000UF/25V
16 C17,C18,C19,C20,C21,C22, 56pF, Ceramic
C23,C24,C25,C26,C27,C28,
C29,C30,C31,C32
2 C33,C34 10UF/16V
1 D1 LED, 10Ma
1 J1 DC-JACK-MALE
1 J2 DB-9/FEMALE
1 J3 RJ11
1 LS1 HPE1206
8 L1,L2,L3,L4,L5,L6,L7,L8 BK2125HS601 "Taiyoyuden Co., Ltd."
2 L9,L10 2961666681 Fair Rite Inc.
1 RV1 P3100SB Teccor
1 R1 10, 0.125W
2 R2,R3 18R, 0.75W
2 R7,R9 4.7K, 0.125W
2 R4,R8 470, 0.125W
1 S1 PB Switch
1 U1 CO561AD-P Connect One Ltd.
1 U2 SFV56ACFH0D5A0P1 Conexant
1 U3 MC7805AT Motorola
1 U4 MC34164P Motorola
1 U5 MAX237CWG Maxim Inc.
1 U6 LM386D National Semi.
1 U7 74HCT245D Motorola
1 Y1 18.432MHZ, HC49
CO561AD-S/P
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iChipTM
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Connect One Ltd. 37 of 46 November 1999
9. PCB Design and Layout
Considerations
9.1 DESIGN CONSIDERATIONS
Good engineering practices must be adhered to when designing
a printed circuit board (PCB) containing the SocketModem
module. Suppression of noise is essential to the proper
operation and performance of the modem itself and for
surrounding equipment.
Two aspects of noise in an OEM board design containing the
Conexant SocketModem module must be considered:
on-board/off-board generated noise that can affect analog signal
levels and analog-to-digital conversion (ADC)/digital-to-analog
conversion (DAC), and on-board generated noise that can
radiate off-board.
Both on-board and off-board generated noise that is coupled
on-board can affect interfacing signal levels and quality,
especially in low level analog signals. Of particular concern is
noise in frequency ranges affecting modem performance.
On-board generated electromagnetic interference (EMI) noise
that can be radiated or conducted off-board is a separate, but
equally important, concern. This noise can affect the operation
of surrounding equipment. Most local governing agencies have
stringent certification requirements that must be met for use in
specific environments.
Proper PC board layout (component placement, signal routing,
trace thickness and geometry, etc.), component selection
(composition, value, and tolerance), interface connections, and
shielding are required for the board design to achieve desired
modem performance and to attain EMI certification.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 38 of 46 November 1999
9.2 PC BOARD LAYOUT GUIDELINES
1. In a 2-layer design, all unused space around and under
components should be filled with copper connected to the board
ground on both sides of the board, and connected in such a
manner as to avoid small islands. Isolated islands should be
avoided by connecting all grounds on the same side at several
points and to the ground plane on the opposite side through the
board at several points. Connect SocketModem DGND and
AGND pins to the ground plane.
2. In a 4-layer design, provide an adequate ground plane
covering the entire board. SocketModem DGND and AGND
pins are tied together on the SocketModem.
3. As a general rule, route digital signals on the component side
of the PCB and the analog signals on the solder side. The sides
may be reversed to match particular OEM requirements. Route
the digital traces perpendicular to the analog traces to minimize
signals cross coupling.
4. Route the modem signals to provide maximum isolation
between noise sources and noise sensitive inputs. When layout
requirements necessitate routing these signals together, they
should be separated by neutral signals.
5. All power and ground traces should be at least 0.05 in. wide.
6. 0.1 UF ceramic capacitors should be placed as close as
possible to the power pins. When internal power plane is used,
the traces connecting between the power pins of the
components and the vias should be kept short and to have
bypass capacitor between the via and the pin.
7. TIP and RING signal traces are to be no closer than 0.062"
from any other traces for U.S. applications. TIP and RING
signal traces are to be no closer than 2.5mm (0.1”) from any
other traces for European applications. 2.5mm spacing must be
used if the host board is to support both U.S. and European
Socket Modems. In multi layer design, power and ground
planes should be cleared underneath the traces, which belong to
the primary (TIP and RING) circuit.
8. If the SocketModem is mounted flush with the host PCB, the
host PCB should be clear of all traces directly underneath the
SocketModem oscillator section. It is strongly suggested that
the SocketModem be mounted at least 0.130 inch above the
host board.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 39 of 46 November 1999
9.2.1 Electromagnetic Interference (EMI) Considerations
The following guidelines are offered to specifically help
minimize EMI generation. Some of these guidelines are the
same as, or similar to, the general guidelines but are mentioned
again to reinforce their importance. In order to minimize the
contribution of the SocketModem-based design to EMI, the
designer must understand the major sources of EMI and how to
reduce them to acceptable levels.
1. Keep traces carrying high frequency signals as short as
possible.
2. Decouple power from ground with decoupling capacitors as
close to the active components’ power pins as possible.
3. Eliminate ground loops, which are unexpected current return
paths to the power source and ground.
4. Decouple the telephone line cables at the telephone line
jacks. Typically, use common mode chokes and shunt
capacitors. Methods to decouple telephone lines are similar to
decoupling power lines, however, telephone line decoupling
may be more difficult and deserves additional attention. A
commonly used design aid is to place footprints for these
components and populate as necessary during performance/EMI
testing and certification.
5. Decouple the power cord at the power cord interface with
decoupling capacitors. Methods to decouple power lines are
similar to decoupling telephone lines.
6. Locate cables and connectors so as to avoid coupling from
high frequency circuits.
7. Avoid right angle turns on high frequency traces. Forty-five
degree corners are good, however, radius turns are better.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 40 of 46 November 1999
9.2.2 OTHER CONSIDERATIONS
The pins of all SocketModems are grouped according to
function. The DAA interface, host interface, and LED interface
pins are all conveniently arranged, easing the host board layout
design. Conexant has tested each of the W.Class
SocketModems for compliance with their respective country’s
PTT requirements and has received PTT certificates that cover,
without additional expense to the user, all applications that use
these SocketModems in their respective countries. The
certificates apply only to designs that route TIP and RING (pins
1 and 2) directly to the telco jack. Only specified EMI filtering
components are allowed on these two signals.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 41 of 46 November 1999
10. Conexant SocketModemTM
Pin-Compatible Socket
iChipTM Carrier Board
10.1 Pin Assignments
Figure 10-1. Carrier board CO561AD-C pinout
Component Side
SQT--111-03--L-S-MW
SQT--109-03--L-S-MW SQT--109-03--L-S-MW
MMS-109-02-L-SV-K
PT64(SPKR)
PT54(~VC)
PT53(~VOICE)
PT56(~CALLID)
T
PT57(LCS)
PT58(TELOU)
PT59(TELIN)
PT60(MICM)
VCC
PT62(MICV)
GND
64
56
57
58
59
60
61
62
54
63
53
9
8
7
6
5
4
3
2
1PT1(TIP)
PT2(RING)
PT5(ACOUT1)
PT6(ACOUT2)
PT7(XFMR1)
PT8(XFMR2)
PT9(RDET/CID)
PT3(RDETIN1)
PT4(RDETIN2)
32
31
30
29
28
27
26
24
25
DGND
PT24(~RESET)
PT25(NC)
PT27(~RDL)
PT29(DCDIN)
PT30(RXIND)
PT31(DTRIND)
PT32(TXIND)
PT28(~PULSE)
TMM-109-01-L-S-SM
~DSRH
~DCDH
~DTRH
GND
~RTSH
~RIH
~CTSH
~TXDH
~RXDH
35B
41B
40B
39B
38B
37B
36B
34B
33B
35B
Print Side
Connector
~TXD
~DSR
~DCD
~DTR
~CTS
~RTS
~RXD
~RI
GND
41T
40T
39T
38T
37T
36T
35T
34T
33T
CO561AD-S/P
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iChipTM
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Connect One Ltd. 42 of 46 November 1999
10.2 Pin Functional Descriptions
10.2.1 Socket Modem Interface Signals
PTx
Pass-Through connections.
The board provides pass-through connection between a motherboard and a socket modem
mounted on top of the CO561AD-CT/R.
Pins PT1 .. PT9 are dedicated for TNV signals.
The CO561AD-CT/R board layout meets EN 60950:1992 +A1/A2:1993 +A3:1995 requirements for
creepage distance and clearance.
Signal names in brackets correspond to Conexants’ Socket modem data sheet.
VCC
+5VDC
DGND
Digital Ground.
Connect to Digital Ground on the interface circuit.
~RESET
Modem Reset.
The Active Low ~RESET input resets both the iChip and a SocketModem logic and returns
the AT command set to the original factory default values and to "stored values" in NVRAM.
AGND
Analog Ground.
Connect to Analog Ground on the interface circuit. Note that AGND is connected to DGND on
the SocketModem.
~CTS,
Clear To Send (TTL Active Low, EIA-232 Active High), Input
~CTS is used to condition the iChip for data transmission.
On a full-duplex channel, CTS OFF maintains the iChip in a non-transmit mode.
CTS OFF may be ignored if the flow control option is disabled; this allows the iChip to
transmit to the Host CPU even though CTS is OFF.
CTS input ON causes the iChip to transmit data on TXD when ~CTS becomes active.
~RTS,
Ready To Send (TTL Active Low, EIA-232 Active High).
~RTS is controlled by the iChip to indicate whether it is ready to transmit data.
~RTS ON, together with the ~CTS ON, ~DTR ON, and ~DSR ON (where implemented),
indicates to the Host CPU that signals presented on TXD will be transmitted.
~RTS OFF indicates to the Host CPU that it won’t be receiving data across the interface on
RXD. ~RTS ON is a response to ~DTR ON and ~CTS, delayed as may be appropriate for the
iChip to process the data.
~TXD,
Transmitted Data (TTL Active Low, EIA-232 Active High), Output.
The iChip uses the ~TXD line to send data received and processed from the Socket Modem
to the Host CPU and to send iChip responses to the Host. During command mode, ~TXD
data represents the iChip responses to the iChip. iChip responses take priority over incoming
data when the two signals are in competition for ~TXD.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 43 of 46 November 1999
~RXD,
Received Data (TTL Active Low, EIA-232 Active High), Input.
The Host uses the ~RXD line to send data to the iChip for transmission over the telephone
line or to transmit commands to the iChip. The iChip should hold this circuit in the mark state
when no data is being transmitted or during intervals between characters.
~DTR,
Data Terminal Ready (TTL Active Low, EIA-232 Active High), Output.
~DTR indicates iChip status to the Host.
~DTR OFF (high) indicates that the Host is to disregard all signals appearing on the
interchange circuits except Ring Indicator (~RI). ~DTR output is controlled by the AT&Sn
command.
If the AT&S1 option is selected, ~DTR will come ON in the handshaking state when carrier is
detected in the originate mode or when carrier is first sent in the answer mode. In addition, if a
test mode is entered (AT&T1, AT&T3, AT&T6-AT&T8), ~DTR will go off while the test is
running.
~DTR goes OFF if ~DSR goes OFF.
If AT&Q0 and AT&S0 are selected, ~DTR will remain on at all times regardless of the iChip's
current state.
~DSR,
Data Set Ready (TTL Active Low, EIA-232 Active High), Input.
The ~DSR input is turned ON (low) by the Host when the Host is ready to transmit or receive
data. ~DSR ON prepares the iChip to be connected to the modem line, and maintains the
connection established by the Host (manual answering) or internally (automatic answering).
~DSR OFF places the iChip in the disconnect state under control of the &Dn and &Qn
commands. The effect of ~DSR ON and ~DSR OFF depends on the &Dn and &Qn
commands.
~RI,
Ring Indicate (TTL Active Low, EIA-232 Active High), Output.
~RI output ON (low) indicates the presence of an ON segment of a ring signal on the
telephone line.
~DCD,
Data Carrier Detect (TTL Active Low, EIA-232 Active High), Output.
When AT&C0 command is not in effect, ~DCD output is ON when a carrier is detected on the
telephone line or OFF when carrier is not detected.
~DCD can be strapped ON using AT&C0 command.
10.2.2 Host Interface Signals
CO561AD-CT/R Interfaces to a Host CPU via asynchronous serial interface with TTL (T) or
EIA-232 (R) signal levels.
~ TXDH
TXD232
Transmit Data (output, asynchronous)
This pin supplies asynchronous serial transmit data to the system from serial port.
~RXDH
RXD232
Receive Data 1 (input, asynchronous)
This pin supplies asynchronous serial receive data from the system to asynchronous serial
port.
CO561AD-S/P
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iChipTM
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Connect One Ltd. 44 of 46 November 1999
~CTSH
CTS232
Clear-to-Send 1 (input, asynchronous)
This pin provides the Clear to Send signal for asynchronous serial port 1 when the hardware
flow control is enabled for the port. The ~CTSH signal gates the transmission of data from the
associated serial port transmit register. When ~CTSH is asserted, the transmitter begins
transmission of a frame of data, if any is available. If ~CTSH is de-asserted, the transmitter
holds the data in the serial port transmit register. The value of ~CTSH is checked only at the
beginning of the transmission of the frame.
~RTSH
RTS232
Host Interface Ready-to-Send (output, asynchronous)
This pin provides the Ready to Send signal for asynchronous serial port when the hardware
flow control is enabled for the port. The ~RTSH signal is asserted when the associated serial
port transmit register contains data which has not been transmitted.
~DSRH,
DSR232
Data Set Ready (input, synchronous)
When flow control is enabled, this pin is Data Set Ready Input
~DTRH
DTR232
Data Terminal Ready (input, synchronous)
When flow control is enabled, this pin operates as Data Terminal Ready Output
~CDH
CD232
Channel 1 Carrier Detect (output, synchronous)
This pin indicates to the system that carrier was detected by communication device (modem).
~RIH
RI232
Channel Ring Indicator (output, synchronous)
This pin indicates to the system that Ring signal was detected by communication device
(modem).
CO561AD-S/P
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iChipTM
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Connect One Ltd. 45 of 46 November 1999
10.3 Socket iChip™ Package
Dimensions
CO561AD-S/P
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iChipTM
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Connect One Ltd. 46 of 46 November 1999
10.4 Reference Design for CO561AD-C
based Modem.