MPQ8636HGL-10-P - Monolithic Power Systems (MPS)

MPQ8636_MPQ8636H

High Efficiency, 10A, 18V

Synchronous, Step-Down Converter

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DESCRIPTION

The MPQ8636-10/MPQ8636H-10 is a fully-

integrated, high-frequency, synchronous, rectified,

step-down, switch-mode converter. It offers a very

compact solution to achieve either a 10A output

current over a wide input supply range, with

excellent load and line regulation. The MPQ8636-

10/MPQ8636H-10 operates at high efficiency

over a wide output-current–load range.

The MPQ8636-10/MPQ8636H-10 uses Constant-

On-Time (COT) control to provide a fast transient

response and ease loop stabilization.

An external resistor programs the operating

frequency from 200kHz to 1MHz, and the

frequency keeps nearly constant as input

supply varies with the feed-forward

compensation.

The default under-voltage lockout threshold is

internally set at 4.1V, but a resistor network on

the enable pin can increase this threshold. The

soft-start pin controls the output-voltage startup

ramp. An open-drain power-good signal

indicates that the output is within nominal

voltage range.

It has fully-integrated protection features that

include over-current protection, over-voltage

protection and thermal shutdown.

The MPQ8636-10/MPQ8636H-10 requires a

minimal number of readily-available, standard,

external components and is available in a

3mm×4mm QFN package.

FEATURES

 Wide 4.5V-to-18V Operating Input Range

 10A Output Current

 Low RDS(ON) Internal Power MOSFETs

 Proprietary Switching-Loss–Reduction

Technique

 Adaptive COT for Ultrafast Transient

Response

 0.5% Reference Voltage Over 0°C to 70°C

Junction Temperature Range

 Programmable Soft-Start Time

 Pre-Bias Start-Up

 Programmable Switching Frequency from

200kHz to 1MHz

 Non-Latch OCP, OVP, and Thermal

Shutdown

 Optional OVP Mode: Latch-Off Mode

(MPQ8636-10) and Non-Latch Mode

(MPQ8636H-10)

 Output Adjustable from 0.611V to 13V

APPLICATIONS

 Telecom and Networking Systems

 Base Stations

 Servers

 Personal Video Recorders

 Flat-Panel Televisions and Monitors

 Distributed Power Systems

All MPS parts are lead-free and adhere to the RoHS directive. For MPS green

status, please visit MPS website under Products, Quality Assurance page.

“MPS” and “The Future of Analog IC Technology” are registered trademarks of

Monolithic Power Systems, Inc.

TYPICAL APPLICATION

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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ORDERING INFORMATION

Part Number

Package

Top Marking

MPQ8636GL-10*

QFN(3x4mm)

MP8636

10

MPQ8636HGL-10**

QFN(3x4mm)

MP8636H

10

* For Tape & Reel, add suffix –Z (e.g. MPQ8636GL-10–Z)

** For Tape & Reel, add suffix –Z (e.g. MPQ8636HGL-10-Z)

PACKAGE REFERENCE

TOP VIEW

PGND

4

IN

2

BST

111213

910

8

7

6

VCC

PG

AGND

SS

FB

FREQ

EN

PGND

SW

3

1

SW

5

PGND

4

IN

2

BST

111213

910

8

7

6

VCC

PG

AGND

SS

FB

FREQ

EN

PGND

SW

3

1

SW

5

Part Number**

Package

Part Number***

Package

MPQ8636GL-10

QFN (3x4mm)

MPQ8636HGL-10

QFN (3x4mm)

Junction Temperature

Top Marking

Junction Temperature

Top Marking

–40°C to +125°C

MP8636

10

–40°C to +125°C

MP8636H

10

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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ABSOLUTE MAXIMUM RATINGS (1)

Supply Voltage VIN ....................................... 21V

VSW ....................................... -0.3V to VIN + 0.3V

VSW (30ns) ..................................-3V to VIN + 3V

VBST .....................................................VSW + 6V

Enable Current IEN(2)................................ 2.5mA

All Other Pins ................................ –0.3V to +6V

Continuous Power Dissipation (TA=+25°)(3)

QFN3X4……………………….…..…………2.7W

Junction Temperature .............................. 150°C

Lead Temperature ................................... 260°C

Storage Temperature ............... -65°C to +150°C

Recommended Operating Conditions (4)

Supply Voltage VIN .......................... 4.5V to 18V

Output Voltage VOUT .................... 0.611V to 13V

Enable Current IEN ...................................... 1mA

Operating Junction Temp. (TJ). -40°C to +125°C

Thermal Resistance (5) θJA θJC

QFN (3x4mm) ........................ 46 ....... 9 .... °C/W

Notes:

1) Exceeding these ratings may damage the device.

2) Refer to the section “Configuring the EN Control”.

3) The maximum allowable power dissipation is a function of the

maximum junction temperature TJ(MAX), the junction-to-

ambient thermal resistance θJA, and the ambient temperature

TA. The maximum allowable continuous power dissipation at

any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-

TA)/θJA. Exceeding the maximum allowable power dissipation

will cause excessive die temperature, and the regulator will go

into thermal shutdown. Internal thermal shutdown circuitry

protects the device from permanent damage.

4) The device is not guaranteed to function outside of its

operating conditions.

5) Measured on JESD51-7, 4-layer PCB.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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ELECTRICAL CHARACTERISTICS

VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.

Parameters

Symbol

Condition

Min

Typ

Max

Units

Supply Current

Supply Current (Shutdown)

IIN

VEN = 0V

0

1

μA

Supply Current (Quiescent)

IIN

VEN = 2V, VFB = 1V

700

860

950

μA

MOSFET

High-Side Switch-On

Resistance

HSRDS-ON

TJ =25°C

19.6

mΩ

Low-Side Switch-On Resistance

LSRDS-ON

TJ =25°C

5.7

mΩ

Switch Leakage

SWLKG

VEN = 0V, VSW = 0V or 12V

0

10

μA

Current Limit

High-Side Peak Current Limit

ILIMIT_PEAK

MPQ8636-10

13

17.3

21.6

A

Low-Side Valley Current Limit(6)

ILIMIT_VALLEY

MPQ8636-10

9.5

11

12.5

A

MPQ8636H-10

10

13

16

Low-Side Negative Current

Limit(6)

ILIMIT_NEGATIVE

-6.5

-5

-4.5

A

Timer

One-Shot ON Time

τON

RFREQ=453kΩ, VOUT=1.2V

250

ns

Minimum On Time(6)

τON_MIN

MPQ8636-10

80

100

120

ns

MPQ8636H-10

20

30

40

Minimum OFF Time(6)

τOFF_MIN

MPQ8636-10

50

100

150

ns

MPQ8636H-10

200

360

420

Over-Voltage and Under-Voltage Protection

OVP Latch Threshold(6)

VOVP_LATCH

MPQ8636-10

127%

130%

133%

VFB

OVP Non-Latch Threshold

VOVP_NON-

LATCH

MPQ8636-10, MPQ8636H-

10

117%

120%

123%

VFB

OVP Delay

τOVP

2

μs

UVP Threshold(6)

VUVP

47%

50%

53%

VFB

Reference and Soft Start

Reference Voltage

VREF

TJ = 0°C to +70°C

608

611

614

mV

TJ = 0°C to +125°C

605

611

617

mV

TJ = -40°C to +125°C

602

611

620

mV

Feedback Current

IFB

VFB = 611mV

50

100

nA

Soft Start Charging Current

ISS

VSS=0V

16

20

25

μA

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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ELECTRICAL CHARACTERISTICS (continued)

VIN = 12V, TJ = -40°C to +125°C, unless otherwise noted.

Parameters

Symbol

Condition

Min

Typ

Max

Units

Enable And UVLO

Enable Input, Low Voltage

VILEN

1.1

1.3

1.5

V

Enable, Hysteresis

VEN-HYS

250

mV

Enable, Input Current

IEN

VEN = 2V

0

μA

VEN = 0V

0

VCC Regulator

VCC Under-Voltage Lockout,

Threshold Rising

VCCVth

3.8

V

VCC Under-Voltage Lockout,

Threshold Hysteresis

VCCHYS

500

mV

VCC Regulator

VCC

4.8

V

VCC Load Regulation

Icc=5mA

0.5

%

Power-Good

Power-Good, Rising Threshold

PGVth-Hi

87%

91%

94%

VFB

Power-Good, Falling Threshold

PGVth-Lo

80%

VFB

Power-Good, Low-to High-Delay

PGTd

2.5

ms

Power Good, Sink Current

Capability

IOL

VOL=600mA

12

mA

Power Good, Leakage Current

IPG_LEAK

VPG = 3.3V

10

nA

Thermal Protection

Thermal Shutdown(6)

TSD

150

°C

Thermal Shutdown, Hysteresis

25

°C

Note:

6) Guaranteed by design.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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PIN FUNCTIONS

MPQ8636GL-10, MPQ8636HGL-10

PIN #

Name

Description

1

EN

Enable. Digital input that turns the regulator on or off. Drive EN high to turn on the

regulator; drive it low to turn it off. Connect EN to IN through a pull-up resistor or a

resistive voltage divider for automatic startup. Do not float this pin.

2

FREQ

Frequency Set. Require a resistor connected between FREQ and IN to set the switching

frequency. The input voltage and the resistor connected to the FREQ pin determine the

ON time. The connection to the IN pin provides line feed-forward and stabilizes the

frequency during input voltage’s variation.

3

FB

Feedback. Connect to the tap of an external resistor divider from the output to GND to

set the output voltage. FB is also configured to realize over-voltage protection (OVP) by

monitoring output voltage. MPQ8636-10 and MPQ8636H-10 provide different OVP

mode. Please refer to the section “Over-Voltage-Protection (OVP)”. Place the resistor

divider as close to FB pin as possible. Avoid using vias on the FB traces.

4

SS

Soft-Start. Connect an external capacitor to program the soft start time for the switch

mode regulator.

5

AGND

Analog Ground. The control circuit reference.

6

PG

Power-Good. The output is an open drain signal. Requires a pull-up resistor to a DC

voltage to indicate HIGH if the output voltage exceeds 91% of the nominal voltage.

There is a delay from FB ≥ 91% to when PG goes high.

7

VCC

Internal 4.8V LDO Output. Powers the driver and control circuits. Decouple with a ≥1µF

ceramic capacitor as close to the pin as possible. For best results, use X7R or X5R

dielectric ceramic capacitors for their stable temperature characteristics.

8

BST

Bootstrap. Require a capacitor connected between SW and BST pins to form a floating

supply across the high-side switch driver.

9,10

SW

Switch Output. Connect to the inductor and bootstrap capacitor. The high-side switch

drives these pins up to VIN during the PWM duty cycle’s ON time. The inductor current

drives the SW pin negative during the OFF-time. The low-side switch’s ON-resistance

and the internal Schottky diode holds the negative voltage. Connect using wide PCB

traces.

11,12

PGND

System Ground. Reference ground of the regulated output voltage. PCB layout requires

extra care. Connect using wide PCB traces.

13

IN

Supply Voltage. Supplies power to the internal MOSFET and regulator. The MPQ8636-

10/MPQ8636H-10 operates from a 4.5V-to-18V input rail. Requires an input decoupling

capacitor. Connect using wide PCB traces and multiple vias.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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TYPICAL CHARACTERISTICS

MPQ8636-10, MPQ8636H-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25°C, unless otherwise noted.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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TYPICAL CHARACTERISTICS

(continued)

MPQ8636-10, MPQ8636H-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25°C, unless otherwise noted.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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TYPICAL PERFORMANCE CHARACTERISTICS

MPQ8636-10, MPQ8636H-10, VIN = 12V, VOUT = 1V, L = 1µH, TA = 25°C, unless otherwise noted.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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TYPICAL PERFORMANCE CHARACTERISTICS

(continued)

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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TYPICAL PERFORMANCE CHARACTERISTICS

(continued)

MPQ8636GL-10, VIN=12V, VOUT =1V, L=1µH, TA=+25°C, unless otherwise noted.

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BLOCK DIAGRAM

FREQ

VCC

EN

SS

FB

PG

IN

BST

SW

GND

AGND

HS-FET

HS

Driver

LS-FET

LS

Driver

ZCD

Current

Modulator

LOGIC

BST

BIAS

FB

Comparator

UV

OV

UV Detect

Comparator

OV Detect

Comparator

PGOOD

Comparator

SOFT START

REFERENCE

VCC

LDO

ON

Timer

Minimum

OFF Timer

VCC

LS Current

Limit

Figure 1: Functional Block Diagram

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OPERATION

The MPQ8636-10/MPQ8636H-10 is a fully-

integrated, synchronous, rectified, step-down,

switch-mode converter. It uses constant-on-time

(COT) control to provide a fast transient

response and ease loop stabilization.

At the beginning of each cycle, the high-side

MOSFET (HS-FET) turns ON when the feedback

voltage (VFB) drops below the reference voltage

(VREF), which indicates an insufficient output

voltage. The input voltage and the frequency-set

resistor determine the ON period as follows:

40

35 .)V(V )k(R.

)ns(IN

FREQ

ON 





(1)

After the ON period elapses, the HS-FET turns

off. It turns ON again when VFB drops below VREF.

By repeating this operation, the converter

regulates the output voltage. The integrated low-

side MOSFET (LS-FET) turns on when the HS-

FET is OFF to minimize the conduction loss.

There is a dead short (or shoot-through) between

input and GND if both HS-FET and LS-FET turn

on at the same time. A dead-time (DT) internally

generated between HS-FET OFF and LS-FET

ON, or LS-FET OFF and HS-FET ON avoids

shoot-through.

PWM Operation

MPQ8636-10/MPQ8636H-10 always functions in

continuous-conduction mode (CCM), meaning

the inductor current can go negative in light-load

conditions. Figure 2 shows CCM operation.

When VFB is below VREF, HS-FET turns on for a

fixed interval determined by the one- shot on-

timer, as per equation 1. When the HS-FET

turns off, the LS-FET turns on until the next

period.

Figure 2: PWM Operation

In CCM operation, the switching frequency is

fairly constant and is also called PWM mode.

Switching Frequency

Selecting the switching frequency requires

trading off between efficiency and component

size. Low-frequency operation increases

efficiency by reducing MOSFET switching losses,

but requires larger inductor and capacitor values

to minimize the output voltage ripple.

For MPQ8636-10/MPQ8636H-10，set the ON

time using the FREQ pin to set the frequency for

steady-state operation on CCM.

The MPQ8636-10/MPQ8636H-10 uses adaptive

constant-on-time (COT) control, though the IC

lacks a dedicated oscillator. Connect the FREQ

pin to the IN pin through the resistor (RFREQ) so

that the input voltage is feed-forwarded to the

one-shot ON-time timer. When operating in

steady state at CCM, the duty ratio stays at

VOUT/VIN, so the switching frequency is fairly

constant over the input voltage range. Set the

switching frequency as follows:

)ns(

)V(V )V(V

.)V(V )k(R.

)kHz(f

DELAY

OUT

IN

FREQ

SW 







40

35 106

(2)

Where τDELAY is the comparator delay of about

40ns.

Typically, the MPQ8636-10/MPQ8636H-10 is set

to 200kHz to 1MHz applications. It is optimized to

operate at high switching frequencies at high

efficiency: high switching frequencies allow for

physically smaller LC filter components to reduce

the PCB footprint.

Jitter and FB Ramp Slope

Figure 3 shows jitter occurring in PWM mode.

When there is noise on the VFB descending slope,

the HS-FET ON time deviates from its intended

point and produces jitter, and influences system

stability. The VFB ripple’s slope steepness

dominates the noise immunity, though its

magnitude has no direct effect.

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Figure 3: Jitter in PWM Mode

Ramp with a Large ESR Capacitor

Using POSCAPs or other large-ESR capacitors

as the output capacitor results in the ESR ripple

dominating the output ripple . The ESR also

significantly influences the VFB slope. Figure 4

shows the simplified equivalent circuit in PWM

mode with the HS-FET OFF and without an

external ramp circuit.

R1

R2

ESR

POSCAP

SW VOUT

L

FB

Figure 4: Simplified Circuit in PWM Mode without

External Ramp Compensation

To realize the stability without an external ramp,

usually select the ESR value as follows:

OUT

ONSW

ESR C2π0.7

R











(3)

Where τSW is the switching period.

Ramp with a Small ESR Capacitor

Use an external ramp when using ceramic output

capacitors because the ESR ripple is not high

enough to stabilize the system.

R1

R2

Ceramic

SW

FB

VOUT

L

R4 C4

IR4 IC4

IFB

R9

Figure 5: Simplified Circuit in PWM Mode with

External Ramp Compensation

Figure 5 shows the simplified equivalent circuit in

PWM mode with the HS-FET OFF and an

external ramp compensation circuit (R4, C4).

Design the external ramp based on the inductor

ripple current. Select C4, R9, R1 and R2 to meet

the following condition:



















 R9

R2R1 R2R1

5

1

C4f2π

1

SW

(4)

Where:

4CFB4C4R IIII 

(5)

Then estimate the ramp on VFB as:





















R9R1//R2

R1//R2

C4R4 VV

VON

OUTIN

RAMP

(6)

The descending slope of the VFB ripple then

follows:

C4R4

V

VOUT

OFF

RAMP

SLOPE 









(7)

Equation 7 shows that if there is instability in

PWM mode, reduce either R4 or C4. If C4 is

irreducible due to equation 4 limitations, then

reduce R4. For a stable PWM operation, design

Vslope based on equation 8.

SW ON -3

ESR OUT OUT

SLOPE OUT

OUT SW ON

RC I 10

0.7 π2

VV

2 L C



   



   

    

(8)

Where IOUT is the load current.

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Configuring the EN Control

The regulator turns on when EN goes HIGH;

conversely it turns off when EN goes low. Do not

float the pin.

For automatic start-up. pull the EN pin up to input

voltage through a resistive voltage divider.

Choose the values of the pull-up resistor (RUP

from the IN pin to the EN pin) and the pull-down

resistor (RDOWN from the EN pin to GND) to

determine the automatic start-up voltage:

UP DOWN

IN START DOWN

(R R )

V 1.5 (V)

R







(9)

For example, for RUP=100kΩ and RDOWN=51kΩ,

the VIN-START is set at 4. 44V.

To reduce noise, add a 10nF ceramic capacitor

from EN to GND.

An internal zener diode on the EN pin clamps the

EN pin voltage to prevent runaway. The

maximum pull-up current, assuming the worst-

case 6V, for the internal zener clamp should be

less than 1mA.

Therefore, when driving EN with an external logic

signal, use an EN voltage less than 6V. When

connecting EN to IN through a pull-up resistor or

a resistive voltage divider, select a resistance

that ensures a maximum pull-up current of less

than 1mA.

If using a resistive voltage divider and VIN

exceeds 6V, then the minimum resistance for the

pull-up resistor, RUP, should meet:

IN

UP DOWN

V 6V 6V 1mA

RR



(10)

With only RUP (the pull-down resistor, RDOWN, is

not connected), then the VCC UVLO threshold

determines VIN-START, so the minimum resistor

value is:

IN

UP V 6V

R ( )

1mA





(11)

A typical pull-up resistor is 100kΩ.

Soft Start

The MPQ8636-10/MPQ8636H-10 employs a soft

start (SS) mechanism to ensure a smooth output

during

power-up. When the EN pin goes HIGH, an

internal current source (20μA) charges the SS

capacitor. The SS capacitor voltage overtakes

the REF voltage to the PWM comparator. The

output voltage smoothly ramps up with the SS

voltage. Once the SS voltage reaches the REF

voltage, it continues ramping up while VREF takes

over the PWM comparator. At this point, soft-start

finishes and the device enters steady-state

operation.

Determine the SS capacitor value as follows:

     

 

  

SS SS

SS REF

ms I A

C nF VV

(12)

If the output capacitors are large, then avoid

setting a short SS time or risk hitting the current

limit during SS. Use a minimum value of 4.7nF if

the output capacitance value exceeds 330μF.

Pre-Bias Startup

The MPQ8636-10/MPQ8636H-10 has been

designed for monotonic startup into pre-biased

loads. If the output is pre-biased to a certain

voltage during startup, the IC will disable

switching for both high-side and low-side

switches until the voltage on the soft-start

capacitor exceeds the sensed output voltage at

the FB pin.

Power Good (PG)

The MPQ8636-10/MPQ8636H-10 has a power-

good (PG) output. The PG pin is the open drain

of a MOSFET. Connect it to VCC or some other

voltage source that measures less than 5.5V

through a pull-up resistor (typically 100kΩ). After

applying the input voltage, the MOSFET turns on

so that the PG pin is pulled to GND before the

SS is ready. After the FB voltage reaches 91% of

the REF voltage, the PG pin is pulled HIGH after

a 2.5ms delay.

When the FB voltage drops to 80% of the REF

voltage or exceeds 120% of the nominal REF

voltage, the PG pin is pulled LOW. If the input

DC source fails to power the MPQ8636-

10/MPQ8636H-10, the PG pin is also pulled low

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even though this pin is tied to an external DC

source through a pull-up resistor (typically

100kΩ).

Over-Current Protection (OCP)

The MPQ8636-10/MPQ8636H-10 features three

current-limit levels for over-current conditions:

high-side peak current limit, low-side valley

current limit and low-side negative current limit.

However, the OCP operation mechanism of

MPQ8636-10 and MPQ8636H-10 are different.

For MPQ8636GL-10:

High-Side Peak Current Limit: The part has a

cycle-by-cycle over-current limiting function. The

device monitors the inductor current during the

HS-FET ON state. When the sensed inductor

current hits the peak current limit, the output of

over-current comparator goes HIGH, the device

enters OCP mode immediately and turns off the

HS-FET and turns on the LS-FET.

Low-Side Valley Current Limit: The device also

monitors the inductor current during the LS-FET

ON state. When ILIM=1 and at the end of the

OFF time, the LS-FET sourcing current is

compared to the internal positive-valley–current

limit. If the valley current limit is less than the LS-

FET sourcing current, the HS-FET remains OFF

and the LS-FET remains ON for the next ON time.

When the LS-FET sourcing current drops below

the valley current limit, the HS-FET turns on

again.

For MPQ8636H-10:

The part enters OCP mode if only the LS-FET

sourcing valley current exceeds the valley current

limit. Once the OCP is triggered, the LS-FET

keeps ON state until the LS-FET sourcing valley

current is less than the valley current limit. And

then the LS-FET turns off, the HS-FET turns on

for a fixed time determined by frequency-set

resistor RFREQ and input voltage.

During OCP, the device tries to recover from the

over-current fault with hiccup mode: the chip

disables the output power stage, discharges the

soft-start capacitor and then automatically retries

soft-start. If the over-current condition still holds

after soft-start ends, the device repeats this

operation cycle until the over-current conditions

disappear and then output rises back to

regulation level: OCP offers non-latch protection.

Low-Side Negative Current Limit: If the sensed

LS-FET negative current exceeds the negative

current limit, the LS-FET turns off immediately

and stays OFF for the remainder of the OFF

period. In this situation, both MOSFETs are OFF

until the end of a fixed interval. The HS-FET body

diode conducts the inductor current for the fixed

time.

Over-Voltage Protection (OVP)

The MPQ8636-10/MPQ8636H-10 monitors the

output voltage using the FB pin connected to the

tap of a resistor divider to detect output over-

voltage. MPQ8636-10 and MPQ8636H-10

provide Latch-Off and Non-Latch OVP mode as

showed in Table 1.

Table 1—OVP Mode

OVP Mode

Non-Latch Mode

Latch-Off Mode

Part #

MPQ8636H-10

MPQ8636-10

For MPQ8636-10:

If the FB voltage exceeds the nominal REF

voltage but remains lower than 120% of the REF

voltage (0.611V), both MOSFETs are off.

If the FB voltage exceeds 120% of the REF

voltage but remains below 130%, the LS-FET

turns on while the HS-FET remains off. The LS-

FET remains on until the FB voltage drops below

110% of the REF voltage or the low-side

negative current limit is hit.

If the FB voltage exceeds 130% of the REF

voltage, then the device is latched off. Need

cycle the input power supply or EN to restart.

For MPQ8636H-10:

Even the FB voltage exceeds 130% of the REF

voltage, the part enters a non-latch off mode.

Once the FB voltage comes back to the

reasonable value, they will exit this OVP mode

and operate normally again.

UVLO Protection

The MPQ8636-10/MPQ8636H-10 has under-

voltage lockout protection (UVLO). When the

VCC voltage exceeds the UVLO rising-threshold

voltage, the MPQ8636-10/MPQ8636H-10 powers

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up. It shuts off when the VCC voltage falls below

the UVLO falling threshold voltage. This is non-

latch protection.

The MPQ8636-10/MPQ8636H-10 is disabled

when the VCC voltage falls below 3.3 V. If an

application requires a higher UVLO threshold,

use the two external resistors connected to the

EN pin as shown in Figure 6 to adjust the startup

input voltage. For best results, use the enable

resistors to set the input-voltage falling threshold

(VSTOP) above 3.6V. Set the rising threshold

(VSTART) to provide enough hysteresis to account

for any input supply variations.

EN ComparatorRUP

RDOWN

IN

EN

Figure 6: Adjustable UVLO Threshold

Thermal Shutdown

The MPQ8636-10/MPQ8636H-10 has thermal

shutdown. The IC internally monitors the junction

temperature. If the junction temperature exceeds

the threshold value (minimum 150°C), the

converter shuts off. This is a non-latch protection.

There is about 25°C hysteresis. Once the

junction temperature drops to about 125°C, it

initiates a soft startup.

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APPLICATION INFORMATION

Selecting the Output-Voltage-Large-ESR

Capacitors

For applications that electrolytic capacitor or POS

capacitor with a large ESR is set as output

capacitors. The feedback resistors—R1 and R2,

as shown in Figure 7—set the output voltage.

R1

R2

ESR

POSCAP

SW VOUT

L

FB

Figure 7: Simplified POSCAP Circuit

First, choose a value for R2 that balances

between high quiescent current loss (low R2) and

high noise sensitivity on FB (high R2). A typical

value falls within 5kΩ to 50kΩ, using a

comparatively larger R2 when VOUT is low, and a

smaller R2 when VOUT is high. Then calculate R1

as follows, which considers the output ripple:

OUT OUT REF

REF

1

V V V

2

R1 R2

V

   



(13)

Where

OUT

V

is the output ripple determined by

equation 22.

Selecting the Output-Voltage Small-ESR

Capacitors

R1

R2

Ceramic

SW

FB

VOUT

L

R9

R4 C4

Figure 8: Simplified Ceramic Capacitor Circuit

When using a low-ESR ceramic capacitor on the

output, add an external voltage ramp to the FB

pin consisting of R4 and C4. The ramp voltage,

VRAMP, and the resistor divider influence the

output voltage, as shown in Figure 8. Calculate

VRAMP as shown in equation 6. Select R2 to

balance between high quiescent current loss and

FB noise sensitivity. Choose R2 within 5kΩ to

50kΩ, using a larger R2 when VOUT is low, and a

smaller R2 when VOUT is high. Determine the

value of R1 as follows:

R9R4

R2

VV VR2

R1

FB(AVG)OUT

FB(AVG)







(14)

Where VFB(AVG) is the average FB voltage. VFB(AVG)

varies with the VIN, VOUT, and load condition,

where the load regulation is strictly related to the

VFB(AVG). Also the line regulation is related to the

VFB(AVG); improving the load or line regulation

involves a lower VRAMP that meets equation 8.

For PWM operation, estimate VFB(AVG) from

equation 15.

9R2R//1R 2R//1R

V

2

1

VV RAMPREF)AVG(FB 



(15)

Usually, R9 is 0Ω, though it can also be set

following equation 16 for better noise immunity. It

should also be less than 20% of R1//R2 to

minimize its influence on VRAMP.

1 R1 R2

R9 5 R1 R2



 

(16)

Using equations 14 and 15 to calculate the

output voltage can be complicated. To simplify

the R1 calculation in equation 14, add a DC-

blocking capacitor, CDC, to filter the DC influence

from R4 and R9. Figure 9 shows a simplified

circuit with external ramp compensation and a

DC-blocking capacitor. The addition of this

capacitor, simplifies the R1 calculation as per

equation 17 for PWM mode operation.

OUT REF RAMP

REF RAMP

1

V V V

2

R1 R2

1

VV

2

  





(17)

For best results, select a CDC value at least

10×C4 for better DC-blocking performance, but

smaller than 0.47µF to account for start-up

performance. To use a larger CDC for better FB

noise immunity, reduce R1 and R2 to limit effects

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on system start-up. Note that even with CDC, the

load and line regulation are still related to VRAMP.

R1

R2

Ceramic

SW

FB

VOUT

L

CDC

R4 C4

Figure 9: Simplified Ceramic Capacitor Circuit with

DC-Blocking Capacitor

Input Capacitor

The input current to the step-down converter is

discontinuous, and therefore, requires a

capacitor to supply the AC current to the step-

down converter while maintaining the DC input

voltage. Use ceramic capacitors for best

performance. During layout, place the input

capacitors as close to the IN pin as possible.

The capacitance can vary significantly with

temperature. Use capacitors with X5R and X7R

ceramic dielectrics because they are fairly stable

over a wide temperature range.

The capacitors must also have a ripple current

rating that exceeds the converter’s maximum

input ripple current. Estimate the input ripple

current as follows:

)

V

1(

V

II IN

OUT

IN

OUT

OUTCIN 

(18)

The worst-case condition occurs at VIN = 2VOUT,

where:

2

I

IOUT

CIN 

(19)

For simplification, choose an input capacitor with

an RMS current rating that exceeds half the

maximum load current.

The input capacitance value determines the

converter input voltage ripple. Select a capacitor

value that meets any input-voltage–ripple

requirements.

Estimate the input voltage ripple as follows:

)

V

(1

V

Cf I

ΔV

IN

OUT

IN

OUT

INSW

OUT

IN 





(20)

The worst-case condition occurs at VIN = 2VOUT,

where:

INSW

OUT

IN Cf I

4

1

ΔV 



(21)

Output Capacitor

The output capacitor maintains the DC output

voltage. Use ceramic capacitors or POSCAPs.

Estimate the output voltage ripple as:

)

Cf8 1

(R)

V

(1

LfV

ΔV

OUTSW

ESR

IN

OUT

SW

OUT

OUT 







(22)

When using ceramic capacitors, the capacitance

dominates the impedance at the switching

frequency. The capacitance also dominates the

output voltage ripple. For simplification, estimate

the output voltage ripple as:

)

V

(1

CLf8 V

ΔV

IN

OUT

2

SW

OUT

OUT 





(23)

The ESR only contributes minimally to the output

voltage ripple, thus requiring an external ramp to

stabilize the system. Design the external ramp

with R4 and C4 as per equations 4, 7 and 8.

The ESR dominates the switching-frequency

impedence for POSCAPs. The ESR ramp

voltage is high enough to stabilize the system,

thus eliminating the need for an external ramp.

Select a minimum ESR value around 12mΩ to

ensure stable converter operation. For

simplification, the output ripple can be

approximated as:

ESR

IN

OUT

SW

OUT

OUT R)

V

(

LfV

V



 1

(24)

Inductor

The inductor supplies constant current to the

output load while being driven by the switching

input voltage. A larger-value inductor results in

less ripple current and lower output-ripple voltage,

but is larger physical size, has a higher series

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resistance, and/or lower saturation current.

Generally, select an inductor value that allows

the inductor peak-to-peak ripple current to equal

30% to 40% of the maximum switch current limit.

Also, design for a peak inductor current that is

below the maximum switch current limit. The

inductance value can be calculated as:

)

V

(

If V

LIN

OUT

LSW

OUT 



1

(25)

Where ΔIL is the peak-to-peak inductor ripple

current.

Choose an inductor that will not saturate under

the maximum inductor peak current. The peak

inductor current can be calculated as:

)

V

(

Lf

V

II IN

OUT

SW

OUT

OUTLP 



 1

2

(26)

Table 2 lists a few highly-recommended high-

efficiency inductors.

Table 2—Inductor Selector Guide

Part Number

Manufacturer

Inductance

(µH)

DCR

(mΩ)

Current

Rating (A)

Dimensions L

x W x H (mm3)

Switching

Frequency

(kHz)

744325072

Wurth

0.72

1.35

35

10.2 x 10.5 x 4.7

500

FDU1250C-1R0M

TOKO

1

1.72

31.3

13.3 x 12.1 x 5

500

FDA1055-1R5M

TOKO

1.5

2.8

24

11.6 x 10.8 x 5.5

500

744325180

Wurth

1.8

3.5

18

10.2 x 10.5 x 4.7

500

Typical Design Parameter Tables

The following tables include recommended

component values for typical output voltages (1V,

2.5V, 3.3V) and switching frequency (500kHz).

Refer to Table 3 for design cases without

external ramp compensation and Table 4 for

design cases with external ramp compensation.

An external ramp is not needed when using high-

ESR capacitors, such as electrolytic or

POSCAPs. Use an external ramp when using

low-ESR capacitors, such as ceramic capacitors.

For cases not listed in this datasheet, an excel

spreadsheet provided by local sales

representatives can assist with the calculations.

Table 3—fSW=500kHz, VIN=12V

VOUT

(V)

L

(μH)

R1

(kΩ)

R2

(kΩ)

R7

(kΩ)

1

0.72

13.3

20

357

2.5

1.5

63.4

20

887

3.3

1.8

91

20

1200

Table 4—fSW=500kHz, VIN=12V

VOUT

(V)

L

(μH)

R1

(kΩ)

R2

(kΩ)

R4

(kΩ)

C4

(pF)

R7

(kΩ)

1

0.72

13.7

20

750

220

357

2.5

1.5

66.5

20

1000

220

887

3.3

1.8

95.3

20

1200

220

1200

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TYPICAL APPLICATION (7)

Figure 10 — Typical Application Circuit with No External Ramp

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1V, IOUT=10A, fSW=500kHz

Figure 11 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1V, IOUT=10A, fSW=500kHz

Figure 12 — Typical Application Circuit with Low ESR Ceramic Capacitor

and DC-Blocking Capacitor.

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1V, IOUT=10A, fSW=500kHz

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Figure 13 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1V, IOUT=1A-10A, fSW=500kHz

Figure 14 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1V, IOUT=10A, fSW=300kHz

Figure 15 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1V, IOUT=1A-10A, fSW=300kHz

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Figure 16 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1V, IOUT=10A, fSW=800kHz

Figure 17 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1V, IOUT=1A-10A, fSW=800kHz

Figure 18 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=0.8V, IOUT=10A, fSW=300kHz

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Figure 19 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=0.8V, IOUT=1A-10A, fSW=300kHz

Figure 20 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=0.8V, IOUT=10A, fSW=500kHz

Figure 21 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=0.8V, IOUT=1A-10A, fSW=500kHz

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Figure 22 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.2V, IOUT=10A, fSW=300kHz

Figure 23 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.2V, IOUT=1A-10A, fSW=300kHz

Figure 24 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.2V, IOUT=10A, fSW=500kHz

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Figure 25 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.2V, IOUT=1A-10A, fSW=500kHz

Figure 26 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.2V, IOUT=10A, fSW=800kHz

Figure 27 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.2V, IOUT=1A-10A, fSW=800kHz

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Figure 28 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.5 V, IOUT=10A, fSW=300kHz

Figure 29 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.5V, IOUT=1A-10A, fSW=300kHz

Figure 30 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.5 V, IOUT=10A, fSW=500kHz

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Figure 31 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.5V, IOUT=1A-10A, fSW=500kHz

Figure 32 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.5 V, IOUT=10A, fSW=800kHz

Figure 33 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.5V, IOUT=1A-10A, fSW=800kHz

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Figure 34 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.8 V, IOUT=10A, fSW=300kHz

Figure 35 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.8V, IOUT=1A-10A, fSW=300kHz

Figure 36 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.8 V, IOUT=10A, fSW=500kHz

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Figure 37 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.8V, IOUT=1A-10A, fSW=500kHz

Figure 38 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=1.8 V, IOUT=10A, fSW=800kHz

Figure 39 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=1.8V, IOUT=1A-10A, fSW=800kHz

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

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Figure 40 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=3.3 V, IOUT=10A, fSW=300kHz

Figure 41 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=3.3V, IOUT=1A-10A, fSW=300kHz

Figure 42 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=3.3 V, IOUT=10A, fSW=500kHz

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

MPQ8636-10, MPQ8636H-10 Rev. 1.22 www.MonolithicPower.com 32

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Figure 43 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=3.3V, IOUT=1A-10A, fSW=500kHz

Figure 44 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=3.3 V, IOUT=10A, fSW=800kHz

Figure 45 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=3.3V, IOUT=1A-10A, fSW=800kHz

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

MPQ8636-10, MPQ8636H-10 Rev. 1.22 www.MonolithicPower.com 33

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Figure 46 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=5 V, IOUT=10A, fSW=300kHz

Figure 47 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=5V, IOUT=1A-10A, fSW=300kHz

Figure 48 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=5 V, IOUT=10A, fSW=500kHz

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

MPQ8636-10, MPQ8636H-10 Rev. 1.22 www.MonolithicPower.com 34

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Figure 49 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=5V, IOUT=1A-10A, fSW=500kHz

Figure 50 — Typical Application Circuit with Low ESR Ceramic Capacitor

MPQ8636-10, MPQ8636H-10, VIN=12V, VOUT=5 V, IOUT=10A, fSW=800kHz

Figure 51 — Efficiency Curve

MPQ8636-10, MPQ8636H-10, VOUT=5V, IOUT=1A-10A, fSW=800kHz

NOTE:

7) The all application circuits’ steady states are OK, but other performances are not tested.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

MPQ8636-10, MPQ8636H-10 Rev. 1.22 www.MonolithicPower.com 35

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LAYOUT RECOMMENDATION

1. Place high current paths (GND, IN, and SW)

very close to the device with short, direct and

wide traces.

2. Two-layer IN copper layers are required to

achieve better performance. Respectively put

at least a decoupling capacitor on both Top

and Bottom layers and as close to the IN and

GND pins as possible. Also, several vias with

18mil diameter and 8mil hole- size are

required to be placed under the device and

near input capacitors to help on the thermal

dissipation, also reduce the parasitic

inductance.

3. Put a decoupling capacitor as close to the

VCC and AGND pins as possible.

4. Keep the switching node (SW) plane as small

as possible and far away from the feedback

network.

5. Place the external feedback resistors next to

the FB pin. Make sure that there are no vias

on the FB trace. The feedback resistors

should refer to AGND instead of PGND.

6. Keep the BST voltage path (BST, C3, and

SW) as short as possible.

7. Recommend strongly a four-layer layout to

improve thermal performance.

Figure 52—Schematic for PCB Layout Guide

IN

R3

R1

R3

R2

R3

R4 R3

C4

R3

C6

L1

R3

C2

VIN

GND

SW

VOUT

EN

FREQ

FB

SS

AGND

PG

VCC

BST

PGND

SW

R3

C1A

R3

R5

R3

C3

R3

C5

R3

GND

R3

RFREQ

R3

C1B

Top Layer

GND

Inner1 Layer

GND

Inner2 Layer

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

MPQ8636-10, MPQ8636H-10 Rev. 1.22 www.MonolithicPower.com 36

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R3

C1C

VIN

GND

Bottom Layer

Figure 53—PCB Layout Guide for MPQ8636-

10 and MPQ8636H-10

Design Example

Below is a design example following the

application guidelines for the specifications:

Table 5—Design Example

VIN

4.5-18V

VOUT

1V

fSW

500kHz

The detailed application schematic is shown in

Figure 11. The typical performance and circuit

waveforms have been shown in the Typical

Performance Characteristics section. For more

device applications, please refer to the related

Evaluation Board Datasheets.

MPQ8636-10_MPQ8636H-10 — 10A, 18V, SYNCHRONOUS, STEP-DOWN CONVERTER

NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third

party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not

assume any legal responsibility for any said applications.

MPQ8636-10, MPQ8636H-10 Rev. 1.22 www.MonolithicPower.com 37

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PACKAGE INFORMATION QFN (3×4mm)

PACKAGE OUTLINE DRAWING FOR 13L FCQFN (3X4MM)

MF-PO-D-0128 revision 0.0

SIDE VIEW

BOTTOM VIEW

NOTE:

1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) EXPOSED PADDLE SIZE DOES NOT

INCLUDE MOLD FLASH.

3) LEAD COPLANARITY SHALL BE 0.10

MILLIMETERS MAX.

4) JEDEC REFERENCE IS MO-220.

5) DRAWING IS NOT TO SCALE.

TOP VIEW

RECOMMENDED LAND PATTERN

PIN 1 ID

MARKING

PIN 1 ID

INDEX AREA

PIN 1 ID

0.125 x45 ? YP.

0.125x45

°

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