1. General description
The 74LVC2G38 provides a 2-input NAND function.
The outputs of the 74LVC2G38 devices are open-drain and can be connected to other
open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND
functions.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 Vand 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the outpu t, preventing the damaging ba ckflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
±24 mA output drive (VCC =3.0V)
CMOS low power consumption
Open-drain outputs
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
Specified from −40 °C to +85 °C and −40 °Cto+125°C
74LVC2G38
Dual 2-input NAND gate; open drain
Rev. 10 — 28 June 2012 Product data sheet
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 2 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
3. Ordering information
4. Marking
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
Tabl e 1. Ordering information
Type number Package
Temperatur e ra nge Name Description Version
74LVC2G38DP −40 °C to +125 °C TSSOP8 plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm SOT505-2
74LVC2G38DC −40 °C to +125 °C VSSOP8 plastic very thin shrink small outline package; 8 leads;
body width 2.3 mm SOT765-1
74LVC2G38GT −40 °C to +125 °C XSON8 plastic extremely thin small outline package; no leads;
8 terminals; body 1 × 1.95 × 0.5 mm SOT833-1
74LVC2G38GF −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 ×1×0.5 mm SOT1089
74LVC2G38GD −40 °C to +125 °C XSON8U plastic extremely thin small outline package; no leads;
8 terminals; UT LP based; body 3 × 2 × 0.5 mm SOT996-2
74LVC2G38GM −40 °C to +125 °C XQFN8 plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 ×1.6 ×0.5 mm SOT902-2
74LVC2G38GN −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.2 ×1.0 ×0.35 mm SOT1116
74LVC2G38GS −40 °C to +125 °C XSON8 extremely thin small outline package; no leads;
8 terminals; body 1.35 ×1.0 ×0.35 mm SOT1203
Table 2. Marking codes
Type number Marking code[1]
74LVC2G38DP Y38
74LVC2G38DC Y38
74LVC2G38GT Y38
74LVC2G38GF YB
74LVC2G38GD Y38
74LVC2G38GM Y38
74LVC2G38GN YB
74LVC2G38GS YB
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 3 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
5. Functional diagram
6. Pinning information
6.1 Pinning
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aah753
1A
1B 1Y
2A
2B 2Y
001aah754
&
&
Fig 3. Functional diagram (on e ga te )
mnb131
Y
GND
B
A
Fig 4. Pin configuration SOT505-2 and SOT765-1 Fig 5. Pin configuration SOT833-1 , SOT1089,
SOT111 6 and SOT1203
74LVC2G38
1A VCC
1B 1Y
2Y 2B
GND 2A
001aab829
1
2
3
4
6
5
8
7
74LVC2G38
2B
1Y
V
CC
2A
2Y
1B
1A
GND
001aab830
36
27
18
45
Transparent top view
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 4 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
6.2 Pin description
7. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
Fig 6. Pin configu ration SOT996-2 Fig 7. Pin configuration SOT902 -2
001aaj792
74LVC2G38
Transparent top view
8
7
6
5
1
2
3
4
1A
1B
2Y
GND
V
CC
1Y
2B
2A
001aae979
1B2B
1A
V
CC
2Y
1Y
GND
2A
Transparent top view
3
6
4
1
5
8
7
2
terminal 1
index area
74LVC2G38
Table 3. Pin description
Symbol Pin Description
SOT505-2, SOT765-1, SOT833-1, SOT1089,
SOT996-2, SOT1116 and SOT1203 SOT902-2
1A, 2A 1, 5 7, 3 data input
1B, 2B 2, 6 6, 2 data input
GND 4 4 ground (0 V)
1Y, 2Y 7, 3 1, 5 data output
VCC 8 8 supply voltage
Table 4. Function table[1]
Input Output
nA nB nY
LLZ
LHZ
HLZ
HHL
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 5 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
8. Limiting values
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] When VCC = 0 V (Power-down mode), the output voltage can be 5.5 V in normal operation.
[3] For TSSOP8 package: above 55 °C the value of Ptot derates linearly with 2.5 mW/K.
For VSSOP8 package: above 110 °C the value of Ptot derates linearly with 8 mW/K.
For XSON8, XSON8U and XQFN8 packages: above 118 °C the value of Ptot derates linearly with 7.8 mW/K.
9. Recommended operating conditions
Table 5. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage −0.5 +6.5 V
VIinput voltage [1] −0.5 +6.5 V
VOoutput voltage Active mode [1][2] −0.5 +6.5 V
Power-down mode [1][2] −0.5 +6.5 V
IIK input clamping current VI < 0 V −50 - mA
IOK output clamping current VO > VCC or VO < 0 V - ±50 mA
IOoutput current VO = 0 V to VCC -±50 mA
ICC supply current - 100 mA
IGND ground current −100 - mA
Tstg storage temperature −65 +150 °C
Ptot total power dissipation Tamb = −40 °C to +125 °C[3] - 300 mW
Table 6. Operating conditions
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 1.65 5.5 V
VIinput voltage 0 5.5 V
VOoutput voltage Active mode 0 VCC V
disable mode 0 5.5 V
Power-down mode 0 5.5 V
Tamb ambient temperature −40 +125 °C
Δt/ΔV input transition rise and fall rate VCC = 1.65 V to 2.7 V - 20 ns/V
VCC = 2.7 V to 5.5 V - 10 ns/V
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 6 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Tamb = −40 °C to +85 °C[1]
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 × VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 × VCC V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - 0.08 0.45 V
IO = 8 mA; VCC = 2.3 V - 0.14 0.3 V
IO = 12 mA; VCC = 2.7 V - 0.19 0.4 V
IO = 24 mA; VCC = 3.0 V - 0.37 0.55 V
IO = 32 mA; VCC = 4.5 V - 0.43 0.55 V
IIinput leakage current VI=5.5VorGND; V
CC =0Vto5.5V - ±0.1 ±5μA
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - ±0.1 ±10 μA
ICC supply current VI=5.5VorGND;
VCC = 1.65 V to 5.5 V; IO=0A -0.110μA
ΔICC additional supply current per pin; VI = VCC − 0.6 V; IO=0A;
VCC = 2.3 V to 5.5 V -5500μA
CIinput capacitance - 2.5 - pF
Tamb = −40 °C to +125 °C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V 0.65 × VCC -- V
VCC = 2.3 V to 2.7 V 1.7 - - V
VCC = 2.7 V to 3.6 V 2.0 - - V
VCC = 4.5 V to 5.5 V 0.7 × VCC -- V
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V - - 0.35 × VCC V
VCC = 2.3 V to 2.7 V - - 0.7 V
VCC = 2.7 V to 3.6 V - - 0.8 V
VCC = 4.5 V to 5.5 V - - 0.3 × VCC V
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 μA; VCC = 1.65 V to 5.5 V - - 0.1 V
IO = 4 mA; VCC = 1.65 V - - 0.70 V
IO = 8 mA; VCC = 2.3 V - - 0.45 V
IO = 12 mA; VCC = 2.7 V - - 0.60 V
IO = 24 mA; VCC = 3.0 V - - 0.80 V
IO = 32 mA; VCC = 4.5 V - - 0.80 V
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 7 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
[1] All typical values are measured at Tamb = 25 °C.
11. Dynamic characteristics
[1] Typical values are measured at nominal VCC and at Tamb = 25 °C.
[2] CPD is used to determine the dynamic power dissipation (PD in μW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
Σ(CL × VCC2 × fo) = sum of outputs.
IIinput leakage current VI=5.5VorGND; V
CC =0Vto5.5V - - ±20 μA
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V - - ±20 μA
ICC supply current VI=5.5VorGND;
VCC = 1.65 V to 5.5 V; IO=0A --40μA
ΔICC additional supply current per pin; VI = VCC − 0.6 V; IO=0A;
VCC = 2.3 V to 5.5 V - - 5000 μA
Table 7. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ Max Unit
Table 8. Dynamic characteristics
Voltages are referenced to GND (ground 0 V); for test circuit see Figure 9.
Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °CUnit
Min Typ[1] Max Min Max
tPZL OFF-state to LOW
propagation delay nA, nB to nY; see Figure 8
VCC = 1.65 V to 1.95 V 1.2 3.0 8.6 1.2 10.8 ns
VCC = 2.3 V to 2.7 V 0.7 1.8 4.8 0.7 6.0 ns
VCC = 2.7 V 0.7 2.5 4.4 0.7 5.5 ns
VCC = 3.0 V to 3.6 V 0.7 2.1 4.1 0.7 5.2 ns
VCC = 4.5 V to 5.5 V 0.5 1.5 3.3 0.5 4.2 ns
tPLZ LOW to OFF-state
propagation delay nA, nB to nY; see Figure 8
VCC = 1.65 V to 1.95 V 1.2 3.0 8.6 1.2 10.8 ns
VCC = 2.3 V to 2.7 V 0.7 1.8 4.8 0.7 6.0 ns
VCC = 2.7 V 0.7 2.5 4.4 0.7 5.5 ns
VCC = 3.0 V to 3.6 V 0.7 2.1 4.1 0.7 5.2 ns
VCC = 4.5 V to 5.5 V 0.5 1.5 3.3 0.5 4.2 ns
CPD power dissipation
capacitance per gate; VI = GND to VCC [2] -5-- -pF
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 8 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
12. Waveforms
Measurement points are given in Table 9
Fig 8. Inputs nA and nB to output nY propagation delay time s
mnb132
t
PLZ
V
X
nY output
nA, nB input
V
I
V
CC
V
M
V
OL
GND t
PZL
V
M
Table 9. Measurement points
Supply voltage Input Output
VCC VMVXVM
1.65 V to 1.95 V 0.5 × VCC VOL + 0.15 V 0.5 × VCC
2.3 V to 2.7 V 0.5 × VCC VOL + 0.15 V 0.5 × VCC
2.7 V 1.5 V VOL + 0.3 V 1.5 V
3.0 V to 3.6 V 1.5 V VOL + 0.3 V 1.5 V
4.5 V to 5.5 V 0.5 × VCC VOL + 0.3 V 0.5 × VCC
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 9 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Test data is given in Table 10
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 9. Test circuit for measuring switching times
Table 10. Test data
Supply voltage Input Load VEXT
VCC VItr, tfCLRLtPLZ, tPZL
1.65 V to 1.95 V VCC ≤ 2.0 ns 30 pF 1 kΩ2 × VCC
2.3 V to 2.7 V VCC ≤ 2.0 ns 30 pF 500 Ω2 × VCC
2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω6 V
3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω6 V
4.5 V to 5.5 V VCC ≤ 2.5 ns 50 pF 500 Ω2 × VCC
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 10 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
13. Package outline
Fig 10. Package outline SOT505-2 (TSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(1) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.95
0.75 0.38
0.22 0.18
0.08 3.1
2.9 3.1
2.9 0.65 4.1
3.9 0.70
0.35 8°
0°
0.13 0.10.20.5
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
0.47
0.33
SOT505-2 - - - 02-01-16
wM
bp
D
Z
e
0.25
14
85
θ
A2A1
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
TSSOP8: plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm SOT505-2
1.1
pin 1 index
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 11 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Fig 11. Package outline SOT765-1 (VSSOP8)
UNIT A1
A
max. A2A3bpLHELpwyv
ceD(1) E(2) Z(1) θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.00 0.85
0.60 0.27
0.17 0.23
0.08 2.1
1.9 2.4
2.2 0.5 3.2
3.0 0.4
0.1 8°
0°
0.13 0.10.20.4
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.40
0.15
Q
0.21
0.19
SOT765-1 MO-187 02-06-07
wM
bp
D
Z
e
0.12
14
85
θ
A2A1
Q
Lp
(A3)
detail X
A
L
HE
E
c
vMA
X
A
y
2.5 5 mm0
scale
VSSOP8: plastic very thin shrink small outline package; 8 leads; body width 2.3 mm SOT765-1
1
pin 1 index
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 12 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Fig 12. Package outline SOT833-1 (XSON8)
terminal 1
index area
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT833-1 - - -
MO-252
- - -
SOT833-1
07-11-14
07-12-07
DIMENSIONS (mm are the original dimensions)
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
D
E
e1
e
A1
b
L
L1
e1e1
0 1 2 mm
scale
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
UNIT
mm 0.25
0.17 2.0
1.9 0.35
0.27
A1
max b E
1.05
0.95
Dee
1L
0.40
0.32
L1
0.50.6
A(1)
max
0.5 0.04
1
8
2
7
3
6
4
5
8×
(2)
4×
(2)
A
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 13 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Fig 13. Package outline SOT1089 (XSON8)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1089 MO-252
sot1089_po
10-04-09
10-04-12
Unit
mm max
nom
min
0.5 0.04 1.40
1.35
1.30
1.05
1.00
0.95 0.55 0.35 0.35
0.30
0.27
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1 x 0.5 mm SOT1089
A1bL
1
0.40
0.35
0.32
0.20
0.15
0.12
DEee
1L
0 0.5 1 mm
scale
terminal 1
index area
E
D
detail X
A
A1
L
L1
b
e1
e
terminal 1
index area
1
4
8
5
(4×)(2)
(8×)(2)
X
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 14 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Fig 14. Package outline SOT996-2 (XSON8U)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT996-2 - - -- - -
SOT996-2
07-12-18
07-12-21
UNIT A
max
mm 0.5 0.05
0.00 0.35
0.15 3.1
2.9 0.5 1.5 0.5
0.3 0.6
0.4 0.1 0.05
A1
DIMENSIONS (mm are the original dimensions)
XSON8U: plastic extremely thin small outline package; no leads;
8 terminals; UTLP based; body 3 x 2 x 0.5 mm
0 1 2 mm
scale
b D
2.1
1.9
E e e1L L1
0.15
0.05
L2v w
0.05
y y1
0.1
C
y
C
y1
X
b
14
85
e1
eAC B
vMCw M
L2
L1
L
terminal 1
index area
B A
D
E
detail X
AA1
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 15 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Fig 15. Package outline SOT902-2 (XQFN8)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT902-2 - - -
MO-255
- - -
sot902-2_po
10-11-02
11-03-31
Unit(1)
mm max
nom
min
0.5 0.05
0.00
1.65
1.60
1.55
1.65
1.60
1.55 0.55 0.5 0.15
0.10
0.05 0.1 0.05
A
Dimensions
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
XQFN8: plastic, extremely thin quad flat package; no leads;
8 terminals; body 1.6 x 1.6 x 0.5 mm SOT902-2
A1b
0.25
0.20
0.15
DEee
1L
0.35
0.30
0.25
L1vw
0.05
yy
1
0.05
0 1 2 mm
scale
terminal 1
index area
BA
D
E
X
C
y
C
y1
terminal 1
index area
3
L
L1
b
e1
eAC B
vCw
2
1
5
6
7
metal area
not for soldering
8
4
A1
A
detail X
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 16 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Fig 16. Package outline SOT1116 (XSON8)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1116
sot1116_po
10-04-02
10-04-07
Unit
mm max
nom
min
0.35 0.04 1.25
1.20
1.15
1.05
1.00
0.95 0.55 0.3 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.2 x 1.0 x 0.35 mm SOT1116
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2) A1A
e1e1e1
e
L
L1
b
4321
5678
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 17 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Fig 17. Package outline SOT1203 (XSON8)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1203
sot1203_po
10-04-02
10-04-06
Unit
mm max
nom
min
0.35 0.04 1.40
1.35
1.30
1.05
1.00
0.95 0.55 0.35 0.40
0.35
0.32
A(1)
Dimensions
Note
1. Including plating thickness.
2. Visible depending upon used manufacturing technology.
XSON8: extremely thin small outline package; no leads;
8 terminals; body 1.35 x 1.0 x 0.35 mm SOT1203
A1b
0.20
0.15
0.12
DEee
1L
0.35
0.30
0.27
L1
0 0.5 1 mm
scale
terminal 1
index area
E
D
(4×)(2)
(8×)(2)
A
A1
e
L
L1
b
e1e1e1
1
8
2
7
3
6
4
5
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 18 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
14. Abbreviations
15. Revision history
Table 11. Abbreviations
Acronym Description
CMOS Complementary Metal-Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 12. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVC2 G38 v.10 20120628 Product data sheet - 74LVC2G38 v.9
Modifications: •For type number 74LVC2G38GM the SOT code has changed to SOT902-2.
74LVC2 G38 v.9 20111128 Product data sheet - 74LVC2G38 v.8
Modifications: •Legal pages updated.
74LVC2 G38 v.8 20101104 Product data sheet - 74LVC2G38 v.7
74LVC2 G38 v.7 20090320 Product data sheet - 74LVC2G38 v.6
74LVC2 G38 v.6 20080219 Product data sheet - 74LVC2G38 v.5
74LVC2 G38 v.5 20070904 Product data sheet - 74LVC2G38 v.4
74LVC2 G38 v.4 20060516 Product data sheet - 74LVC2G38 v.3
74LVC2G38 v.3 20050201 Product specification - 74LVC2G38 v.2
74LVC2G38 v.2 20041018 Product specification - 74LVC2G38 v.1
74LVC2G38 v.1 20031027 Product specification - -
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 19 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short dat a sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incident al,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whethe r or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applicat ions where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by custo mer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and product s using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third p arty
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Not hing in this document may be interpret ed or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyri ghts, patent s or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVC2G38 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 28 June 2012 20 of 21
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is a utomotive qualified,
the product is not suitable for automotive use. It i s neither qua lified nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applicat ions, use and specifications, and (b)
whenever cust omer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from custome r design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All refe renced brands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVC2G38
Dual 2-input NAND gate; open drain
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 28 June 2012
Document identifier : 74L VC2G38
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 3
6 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
7 Functional description . . . . . . . . . . . . . . . . . . . 4
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
9 Recommended operating conditions. . . . . . . . 5
10 Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
11 Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 18
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 18
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 19
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 19
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20
17 Contact information. . . . . . . . . . . . . . . . . . . . . 20
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21