TPS782xxDDC
TSOT23-5
(TOPVIEW)
OUT
GND
IN
GND
EN
1
2
3
5
4
TPS782xxDRV
2mmx2mmSON-6
(TOPVIEW)
IN
GND
EN
6
5
4
OUT
N/C
GND
1
2
3
Thermal
Pad
TPS782xx
www.ti.com
SBVS115B –AUGUST 2008–REVISED MAY 2010
500nA, I
Q
150mA, Ultra-Low Quiescent Current
Low-Dropout Linear Regulator
1FEATURES DESCRIPTION
2• Low IQ: 500nA The TPS782 family of low-dropout regulators (LDOs)
offers the benefits of ultra-low power (IQ= 1mA), and
• 150mA, Low-Dropout Regulator miniaturized packaging (2×2 SON).
• Low-Dropout at +25°C, 130mV at 150mA This LDO is designed specifically for battery-powered
• Low-Dropout at +85°C, 175mV at 150mA applications where ultra-low quiescent current is a
• 3% Accuracy Over Load/Line/Temperature critical parameter. The TPS782, with ultra-low IQ
• Available in Fixed Voltage Options (2.5V, 2.7V, (1mA), is ideal for microprocessors, memory cards,
and 2.8V) Using Innovative Factory EEPROM and smoke detectors.
Programming The ultra-low power and miniaturized packaging allow
• Stable with a 1.0mF Ceramic Capacitor designers to customize power consumption for
specific applications. Consult with your local factory
• Thermal Shutdown and Overcurrent Protection representative for exact voltage options and ordering
• CMOS Logic Level-Compatible Enable Pin information; minimum order quantities may apply.
• Available in DDC (TSOT23-5) or DRV (2mm x The TPS782 family is designed to be compatible with
2mm SON-6) Packages the TI MSP430 and other similar products. The
enable pin (EN) is compatible with standard CMOS
APPLICATIONS logic. This LDO is stable with any output capacitor
• TI MSP430 Attach Applications greater than 1.0mF. Therefore, this device requires
• Power Rails with Programming Mode minimal board space because of miniaturized
packaging and a potentially small output capacitor.
• Wireless Handsets, Smartphones, PDAs, MP3 The TPS782 series also features thermal shutdown
Players, and Other Battery-Operated Handheld and current limit to protect the device during fault
Products conditions. All packages have an operating
temperature range of TJ= –40°C to +125°C. For
high-performance applications that require a
dual-level voltage option, consider the TPS780
series, with an IQof 500nA and dynamic voltage
scaling.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2008–2010, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TPS782xx
SBVS115B –AUGUST 2008–REVISED MAY 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1) (2)
PRODUCT VOUT
TPS782xx yyy z XX is the nominal output voltage
YYY is the package designator.
Zis the tape and reel quantity (R = 3000, T = 250).
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(2) Additional output voltage combinations are available on a quick-turn basis using innovative, factory EEPROM programming.
Minimum-order quantities apply; contact your sales representative for details and availability
ABSOLUTE MAXIMUM RATINGS(1)
At TJ= –40°C to +125°C, unless otherwise noted. All voltages are with respect to GND.
PARAMETER TPS782xx UNIT
Input voltage range, VIN –0.3 to +6.0 V
Enable –0.3 to VIN + 0.3V V
Output voltage range, VOUT –0.3 to VIN + 0.3V V
Maximum output current, IOUT Internally limited
Output short-circuit duration Indefinite
Total continuous power dissipation, PDISS See the Dissipation Ratings table
Human body model (HBM) 2 kV
ESD rating Charged device model (CDM) 500 V
Operating junction temperature range, TJ–40 to +125 °C
Storage temperature range, TSTG –55 to +150 °C
(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may
degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those specified is not implied.
DISSIPATION RATINGS DERATING FACTOR
BOARD PACKAGE RqJC RqJA ABOVE TA= +25°C TA< +25°C TA= +70°C TA= +85°C
High-K(1) DRV 20°C/W 65°C/W 15.4mW/°C 1540mW 845mW 615mW
High-K(1) DDC 90°C/W 200°C/W 5.0mW/°C 500mW 275mW 200mW
(1) The JEDEC high-K (2s2p) board used to derive this data was a 3-inch × 3-inch, multilayer board with 1-ounce internal power and
ground planes and 2-ounce copper traces on top and bottom of the board.
2Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
TPS782xx
www.ti.com
SBVS115B –AUGUST 2008–REVISED MAY 2010
ELECTRICAL CHARACTERISTICS
Over operating temperature range (TJ= –40°C to +125°C), VIN = VOUT(NOM) + 0.5V or 2.2V, whichever is greater;
IOUT = 100mA, VEN = VIN, COUT = 1.0mF, fixed VOUT test conditions, unless otherwise noted. Typical values at TJ= +25°C.
TPS782xx
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIN Input voltage range 2.2 5.5 V
Nominal TJ= +25°C –2 ±1 +2 %
VOUT DC output accuracy Over VIN, IOUT, VOUT + 0.5V ≤VIN ≤5.5V, –3.0 ±2.0 +3.0 %
temperature 0mA ≤IOUT ≤150mA
ΔVOUT/ΔVIN Line regulation VOUT(NOM) + 0.5V ≤VIN ≤5.5V, IOUT = 5mA ±1.0 %
ΔVOUT/ΔIOUT Load regulation 0mA ≤IOUT ≤150mA ±2.0 %
VDO Dropout voltage(1) VIN = 95% VOUT(NOM), IOUT = 150mA 130 250 mV
BW = 100Hz to 100kHz, VIN = 2.2V,
VNOutput noise voltage 86 mVRMS
VOUT = 1.2V, IOUT = 1mA
ICL Output current limit VOUT = 0.90 × VOUT(NOM) 150 230 400 mA
IOUT = 0mA 0.42 1.3 mA
IGND Ground pin current IOUT = 150mA 8 mA
VEN ≤0.4V, 2.2V ≤VIN < 5.5V,
ISHDN Shutdown current (IGND) 18 130 nA
TJ= –40°C to +100°C
IEN EN pin current VEN = 5.5V 40 nA
f = 10Hz 40 dB
VIN = 4.3V,
PSRR Power-supply rejection ratio VOUT = 3.3V, f = 100Hz 20 dB
IOUT = 150mA f = 1kHz 15 dB
COUT = 1.0mF, VOUT = 10% VOUT(NOM) to
tSTR Startup time(2) 500 ms
VOUT = 90% VOUT(NOM)
IOUT = 150mA, COUT = 1.0mF, VOUT = 2.8V,
tSHDN Shutdown time(3) VOUT = 90% VOUT(NOM) to VOUT = 10% 500(4) ms
VOUT(NOM)
Shutdown, temperature increasing +160 °C
TSD Thermal shutdown temperature Reset, temperature decreasing +140 °C
TJOperating junction temperature –40 +125 °C
(1) VDO is not measured for devices with VOUT(NOM) ≤2.3V because minimum VIN = 2.2V.
(2) Time from VEN = 1.2V to VOUT = 90% (VOUT(NOM)).
(3) Time from VEN = 0.4V to VOUT = 10% (VOUT(NOM)).
(4) See Shutdown in the Application Information section for more details.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Thermal
Shutdown
10kW
Current
Limit
Bandgap
IN
EN
OUT
EEPROM
Mux
Logic
Active
Pull-
Down
GND
OUT
GND(1)
IN
GND(1)
EN
1
2
3
5
4
IN
GND(1)
EN
6
5
4
OUT
N/C
GND(1)
1
2
3
Thermal
Pad(2)
TPS782xx
SBVS115B –AUGUST 2008–REVISED MAY 2010
www.ti.com
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DDC PACKAGE DRV PACKAGE
TSOT23-5 2mm x 2mm SON-6
(TOP VIEW) (TOP VIEW)
(1) All ground pins must be connected to ground for proper operation.
(2) It is recommended that the thermal pad be grounded.
Table 1. PIN DESCRIPTIONS
PIN
NAME DRV DDC DESCRIPTION
Regulated output voltage pin. A small (1mF) ceramic capacitor is needed from this pin to
OUT 1 5 ground to assure stability. See the Input and Output Capacitor Requirements in the
Application Information section for more details.
N/C 2 — Not connected.
Driving the enable pin (EN) over 1.2V turns ON the regulator. Driving this pin below 0.4V
EN 4 3 puts the regulator into shutdown mode, reducing operating current to 18nA typical.
GND 3, 5 2, 4 ALL ground pins must be tied to ground for proper operation.
Input pin. A small capacitor is needed from this pin to ground to assure stability. Typical input
IN 6 1 capacitor = 1.0mF. Both input and output capacitor grounds should be tied back to the IC
ground with no significant impedance between them.
Thermal pad Thermal pad — It is recommended that the thermal pad on the SON-6 package be connected to ground.
4Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
V (%)
OUT
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
T =+85°
JC
T = 40- °
JC
T =+25°
JC
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
V (%)
OUT
3
2
1
0
-1
-2
-3
TJ=+85°C
T 40- °
J= C
TJ=+25°C
0 25 50 75 100 125 150
I (mA)
OUT
V (%)
OUT
3
2
1
0
-1
-2
-3
TJ=+85°C
T = 40- °
JC
TJ=+25°C
0 25 50 75 100 125 150
I (mA)
OUT
V (V V-
DO IN OUT)(mV)
250
200
150
100
50
0
TJ=+125°C
TJ=+85°C
T = 40- °
JC
TJ=+25°C
TPS782xx
www.ti.com
SBVS115B –AUGUST 2008–REVISED MAY 2010
TYPICAL CHARACTERISTICS
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is greater; IOUT =
100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
LINE REGULATION LINE REGULATION
IOUT = 5mA, VOUT = 2.7V (typ) IOUT = 150mA, VOUT = 2.7V (typ)
TPS78227 TPS78227
Figure 1. Figure 2.
LOAD REGULATION DROPOUT VOLTAGE vs OUTPUT CURRENT
VIN = 3.8V, VOUT = 2.7V VOUT = 2.7V (typ), VIN = 0.95 × VOUT (typ)
TPS78227 TPS78227
Figure 3. Figure 4.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 5
-40 -25 -10 1251109580655035205
TJ( C)°
V (V V-
DO IN OUT)(mV)
250
200
150
100
50
0
150mA
100mA
50mA
10mA
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
I ( A)m
GND
6
5
4
3
2
1
0
T =+125 C°
J
T =+85 C°
J
T 40- °
J= C
T =+25 C°
J
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
V (%)
OUT
3
2
1
0
-1
-2
-3
TJ=+85°C
T 40- °
J= C
TJ=+25°C
TPS782xx
SBVS115B –AUGUST 2008–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is
greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
DROPOUT VOLTAGE vs JUNCTION TEMPERATURE GROUND PIN CURRENT vs INPUT VOLTAGE
VOUT = 2.7V (typ), VIN = 0.95 × VOUT (typ) IOUT = 0mA, VOUT = 3.3V
TPS78227 TPS78233
Figure 5. Figure 6.
GROUND PIN CURRENT vs INPUT VOLTAGE GROUND PIN CURRENT vs INPUT VOLTAGE
IOUT = 50mA, VOUT = 2.7V IOUT = 150mA, VOUT = 2.7V
TPS78227 TPS78227
Figure 7. Figure 8.
6Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
CurrentLimit(mA)
300
290
280
270
260
250
240
230
220
210
200
TJ=+125°C
TJ=+85°C
T = 40- °
JC
TJ=+25°C
3.8 4.0 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6
V (V)
IN
I (nA)
EN
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
TJ=+85°C
T = 40- °
JC
TJ=+25°C
-40 -25 -10 1251109580655035205
T ( C)°
J
V (V)
EN
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
V On
EN
V Off
EN
TPS782xx
www.ti.com
SBVS115B –AUGUST 2008–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is
greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
CURRENT LIMIT vs INPUT VOLTAGE ENABLE PIN CURRENT vs INPUT VOLTAGE
VOUT = 95% VOUT (typ), VOUT = 2.7V (typ) IOUT = 100mA, VOUT = 2.7V
TPS78227 TPS78227
Figure 9. Figure 10.
%ΔVOUT vs JUNCTION TEMPERATURE
ENABLE PIN HYSTERESIS vs JUNCTION TEMPERATURE VIN = 3.3V, VOUT = 2.7V (typ)
IOUT = 1mA, TPS78227 TPS78227
Figure 11. Figure 12.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 7
10 100 1k 10k 100k
Frequency(Hz)
OutputSpectralNoiseDensity( V/ )m ÖHz
100
10
1
0.1
0.01
0.001
150mA
109 VmRMS
50mA
109 VmRMS
1mA
108 VmRMS
Voltage(1V/div)
Time(20ms/div)
LoadCurrent
Enable VOUT
VIN V =0.0Vto
IN 5.0V
V =3.3V
OUT
I =150mA
OUT
C =10 Fm
OUT
0V
Current(50mA/div)
TPS782xx
SBVS115B –AUGUST 2008–REVISED MAY 2010
www.ti.com
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is
greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
%ΔVOUT vs JUNCTION TEMPERATURE OUTPUT SPECTRAL NOISE DENSITY vs FREQUENCY
VIN = 3.7V, VOUT = 2.7V (typ) CIN = 1mF, COUT = 2.2mF, VIN = 3.2V
TPS78227 TPS78227
Figure 13. Figure 14.
RIPPLE REJECTION vs FREQUENCY
VIN = 4.2V, VOUT = 2.7V, COUT = 2.2mF INPUT VOLTAGE RAMP vs OUTPUT VOLTAGE
TPS78227 TPS78233
Figure 15. Figure 16.
8Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
Voltage(1V/div)
Time(20ms/div)
V =5.5V
IN
V =3.3V
OUT
I =150mA
OUT
C =10 Fm
OUT
VIN
VOUT LoadCurrent
Enable
0V
Current(50mA/div)
Voltage(1V/div)
Time(1ms/div)
LoadCurrent
V =0.0Vto5.5V
IN
V =2.2V
OUT
I =100mA
OUT
C =10 Fm
OUT
VIN
VOUT
0A
0V
Current(50mA/div)
Voltage
(100mV/div)
Time(5ms/div)
Load
Current
V =5.5V
IN
V =3.3V
OUT
I =0mAto10mA
OUT
C =10 Fm
OUT
VOUT
Enable
VIN
Current
(10mA/div)
0A
Voltage(1V/div)
Time(1ms/div)
LoadCurrent
V =5.50V
IN
V =3.3V
OUT
I =150mA
OUT
COUT =10mF
VIN VOUT
Enable
0V
Current(50mA/div)
Voltage(1V/div)
Time(1ms/div)
Load
Current
V =5.5V
IN
V =3.3V
OUT
I =150mA
OUT
C =10 Fm
OUT
VIN VOUT
Enable
0V
Current(50mA/div)
TPS782xx
www.ti.com
SBVS115B –AUGUST 2008–REVISED MAY 2010
TYPICAL CHARACTERISTICS (continued)
Over the operating temperature range of TJ= –40°C to +125°C, VIN = VOUT(TYP) + 0.5V or 2.2V, whichever is
greater; IOUT = 100mA, VEN = VIN, COUT = 1mF, and CIN = 1mF, unless otherwise noted.
OUTPUT VOLTAGE vs ENABLE (SLOW RAMP) INPUT VOLTAGE vs DELAY TO OUTPUT
TPS78233 TPS78222
Figure 17. Figure 18.
ENABLE PIN vs OUTPUT VOLTAGE RESPONSE
LOAD TRANSIENT RESPONSE AND OUTPUT CURRENT
TPS78233 TPS78233
Figure 19. Figure 20.
ENABLE PIN vs OUTPUT VOLTAGE DELAY
TPS78233
Figure 21.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 9
TPS78227
GND
EN
IN OUT
VIN VOUT
1 Fm
1 Fm
4.2Vto5.5V 2.7V
On
Off
TPS782xx
SBVS115B –AUGUST 2008–REVISED MAY 2010
www.ti.com
APPLICATION INFORMATION
The TPS782 series are designed to be stable with
standard ceramic capacitors with values of 1.0mF or
APPLICATION EXAMPLES larger at the output. X5R- and X7R-type capacitors
The TPS782 family of LDOs is factory-programmable are best because they have minimal variation in value
to have a fixed output. Note that during startup or and ESR over temperature. Maximum ESR should be
steady-state conditions, it is important that the EN pin less than 1.0Ω. With tolerance and dc bias effects,
voltage never exceed VIN + 0.3V. the minimum capacitance to ensure stability is 1mF.
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
To improve ac performance (such as PSRR, output
noise, and transient response), it is recommended
that the printed circuit board (PCB) be designed with
separate ground planes for VIN and VOUT, with each
ground plane connected only at the GND pin of the
device. In addition, the ground connection for the
output capacitor should connect directly to the GND
pin of the device. High ESR capacitors may degrade
PSRR.
Figure 22. Typical Application Circuit INTERNAL CURRENT LIMIT
INPUT AND OUTPUT CAPACITOR The TPS782 is internally current-limited to protect the
REQUIREMENTS regulator during fault conditions. During current limit,
the output sources a fixed amount of current that is
Although an input capacitor is not required for largely independent of output voltage. For reliable
stability, it is good analog design practice to connect operation, the device should not be operated in a
a 0.1mF to 1.0mF low equivalent series resistance current limit state for extended periods of time.
(ESR) capacitor across the input supply near the
regulator. This capacitor counteracts reactive input The PMOS pass element in the TPS782 series has a
sources and improves transient response, noise built-in body diode that conducts current when the
rejection, and ripple rejection. A higher-value voltage at OUT exceeds the voltage at IN. This
capacitor may be necessary if large, fast rise-time current is not limited, so if extended reverse voltage
load transients are anticipated, or if the device is not operation is anticipated, external limiting to 5% of
located near the power source. If source impedance rated output current may be appropriate.
is not sufficiently low, a 0.1mF input capacitor may be
necessary to ensure stability.
10 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
t=3
10k RWL
´
10kW+RL
COUT
´
TPS78227
GND
EN
IN OUT
VIN VOUT
1 Fm
1 Fm
4.2Vto5.5V 2.7V
TPS782xx
www.ti.com
SBVS115B –AUGUST 2008–REVISED MAY 2010
SHUTDOWN DROPOUT VOLTAGE
The enable pin (EN) is active high and is compatible The TPS782 series use a PMOS pass transistor to
with standard and low-voltage CMOS levels. When achieve low dropout. When (VIN – VOUT) is less than
shutdown capability is not required, EN should be the dropout voltage (VDO), the PMOS pass device is
connected to the IN pin, as shown in Figure 23. The the linear region of operation and the input-to-output
TPS782 series, with internal active output pull-down resistance is the RDS(ON) of the PMOS pass element.
circuitry, discharges the output to within 5% VOUT with VDO approximately scales with output current
a time (t) shown in Equation 1: because the PMOS device behaves like a resistor in
dropout. As with any linear regulator, PSRR and
transient response are degraded as (VIN – VOUT)
approaches dropout. This effect is shown in the
(1) Typical Characteristics section. Refer to application
report SLVA207, Understanding LDO Dropout,
Where: available for download from www.ti.com.
RL= output load resistance
COUT = output capacitance TRANSIENT RESPONSE
As with any regulator, increasing the size of the
output capacitor reduces over/undershoot magnitude
but increases duration of the transient response. For
more information, see Figure 19.
ACTIVE VOUT PULL-DOWN
In the TPS782 series, the active pull-down discharges
VOUT when the device is off. However, the input
voltage must be greater than 2.2V for the active
pull-down to work.
Figure 23. Circuit Showing EN Tied High when MINIMUM LOAD
Shutdown Capability is Not Required The TPS782 series are stable with no output load.
Traditional PMOS LDO regulators suffer from lower
loop gain at very light output loads. The TPS782
employs an innovative, low-current circuit under very
light or no-load conditions, resulting in improved
output voltage regulation performance down to zero
output current. See Figure 19 for the load transient
response.
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 11
P =(V V ) I- ´
D IN OUT OUT
TPS782xx
SBVS115B –AUGUST 2008–REVISED MAY 2010
www.ti.com
THERMAL INFORMATION
The internal protection circuitry of the TPS782 series
THERMAL PROTECTION has been designed to protect against overload
conditions. However, it is not intended to replace
Thermal protection disables the device output when proper heatsinking. Continuously running the TPS782
the junction temperature rises to approximately series into thermal shutdown degrades device
+160°C, allowing the device to cool. Once the reliability.
junction temperature cools to approximately +140°C,
the output circuitry is enabled. Depending on power
dissipation, thermal resistance, and ambient POWER DISSIPATION
temperature, the thermal protection circuit may cycle The ability to remove heat from the die is different for
on and off again. This cycling limits the dissipation of each package type, presenting different
the regulator, protecting it from damage as a result of considerations in the PCB layout. The PCB area
overheating. around the device that is free of other components
Any tendency to activate the thermal protection circuit moves the heat from the device to the ambient air.
indicates excessive power dissipation or an Performance data for JEDEC low- and high-K boards
inadequate heatsink. For reliable operation, junction are given in the Dissipation Ratings table. Using
temperature should be limited to +125°C maximum. heavier copper increases the effectiveness in
To estimate the margin of safety in a complete design removing heat from the device. The addition of plated
(including heatsink), increase the ambient through-holes to heat-dissipating layers also
temperature until the thermal protection is triggered; improves the heatsink effectiveness. Power
use worst-case loads and signal conditions. For good dissipation depends on input voltage and load
reliability, thermal protection should trigger at least conditions. Power dissipation (PD) is equal to the
+35°C above the maximum expected ambient product of the output current times the voltage drop
condition of your particular application. This across the output pass element (VIN to VOUT), as
configuration produces a worst-case junction shown in Equation 2:
temperature of +125°C at the highest expected (2)
ambient temperature and worst-case load.
PACKAGE MOUNTING
Solder pad footprint recommendations for the
TPS782 series are available from the Texas
Instruments web site at www.ti.com through the
TPS782 series product folders.
12 Submit Documentation Feedback Copyright © 2008–2010, Texas Instruments Incorporated
TPS782xx
www.ti.com
SBVS115B –AUGUST 2008–REVISED MAY 2010
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September, 2008) to Revision B Page
• Updated title of data sheet .................................................................................................................................................... 1
• Changed first bullet of Features list ...................................................................................................................................... 1
• Changed ground pin current, IOUT = 0mA typical specification from 1.0mA to 0.42mA .......................................................... 3
• Added Figure 6 ..................................................................................................................................................................... 6
Copyright © 2008–2010, Texas Instruments Incorporated Submit Documentation Feedback 13
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS78218DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78218DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78222DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78222DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78223DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78223DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78225DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78225DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78225DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78225DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78225DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78225DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78225DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78225DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78227DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78227DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78227DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS78227DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78227DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78227DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78227DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78227DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78228DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78228DDCRG4 ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78228DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78228DDCTG4 ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78228DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78228DRVRG4 ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78228DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78228DRVTG4 ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78230DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78230DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78230DRVR ACTIVE SON DRV 6 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78230DRVT ACTIVE SON DRV 6 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78233DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS78233DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS78236DDCR ACTIVE SOT DDC 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS78236DDCT ACTIVE SOT DDC 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TPS78225, TPS78227, TPS78228, TPS78230 :
•Automotive: TPS78225-Q1, TPS78227-Q1, TPS78228-Q1, TPS78230-Q1
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 23-Mar-2012
Addendum-Page 4
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS78218DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78218DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78222DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78222DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78223DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78223DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78225DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78225DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78225DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78225DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78227DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78227DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78227DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78227DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78228DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78228DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78228DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78228DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Mar-2012
Pack Materials-Page 1
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS78230DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78230DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78230DRVR SON DRV 6 3000 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78230DRVT SON DRV 6 250 179.0 8.4 2.2 2.2 1.2 4.0 8.0 Q2
TPS78233DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78233DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78236DDCR SOT DDC 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
TPS78236DDCT SOT DDC 5 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS78218DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS78218DRVT SON DRV 6 250 203.0 203.0 35.0
TPS78222DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS78222DRVT SON DRV 6 250 203.0 203.0 35.0
TPS78223DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS78223DDCT SOT DDC 5 250 195.0 200.0 45.0
TPS78225DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS78225DDCT SOT DDC 5 250 195.0 200.0 45.0
TPS78225DRVR SON DRV 6 3000 203.0 203.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Mar-2012
Pack Materials-Page 2
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS78225DRVT SON DRV 6 250 203.0 203.0 35.0
TPS78227DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS78227DDCT SOT DDC 5 250 195.0 200.0 45.0
TPS78227DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS78227DRVT SON DRV 6 250 203.0 203.0 35.0
TPS78228DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS78228DDCT SOT DDC 5 250 195.0 200.0 45.0
TPS78228DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS78228DRVT SON DRV 6 250 203.0 203.0 35.0
TPS78230DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS78230DDCT SOT DDC 5 250 195.0 200.0 45.0
TPS78230DRVR SON DRV 6 3000 203.0 203.0 35.0
TPS78230DRVT SON DRV 6 250 203.0 203.0 35.0
TPS78233DDCR SOT DDC 5 3000 203.0 203.0 35.0
TPS78233DDCT SOT DDC 5 250 203.0 203.0 35.0
TPS78236DDCR SOT DDC 5 3000 195.0 200.0 45.0
TPS78236DDCT SOT DDC 5 250 195.0 200.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 22-Mar-2012
Pack Materials-Page 3
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