PLCC
S1GND
V– S2
GND V+
S4GND
GND S3
V–
GND
D4
S3
Dual-In-Line
D3
GND
GND GND
S4
GND
S2
V+
GND
IN1
IN3
IN2
S1
IN4
D1D2
DG540 DG540
DG540/541/542
Siliconix
S-53694—Rev. E, 28-May-97 1
Wideband/Video “T” Switches
Features Benefits Applications
Wide Bandwidth: 500 MHz
Low Crosstalk: –85 dB
High Off-Isolation: –80 dB @ 5 MHz
“T” Switch Configuration
TTL Logic Compatible
Fast Switching—tON: 45 ns
Low rDS(on): 30
Flat Frequency Response
High Color Fidelity
Low Insertion Loss
Improved System Performance
Reduced Board Space
Reduced Power Consumption
Improved Data Throughput
RF and Video Switching
RGB Switching
Local and Wide Area Networks
Video Routing
Fast Data Acquisition
ATE
Radar/FLR Systems
Video Multiplexing
Description
The DG540/541/542 are high performance monolithic
wideband/video switches designed for switching RF, video
and digital signals. By utilizing a “T” switch configuration
on each channel, these devices achieve exceptionally low
crosstalk and high off-isolation. The crosstalk and
off-isolation of the DG540 are further improved by the
introduction of extra GND pins between signal pins.
To achieve TTL compatibility, low channel capacitances
and fast switching times, the DG540 family is built on the
Siliconix proprietary D/CMOS process. Each switch
conducts equally well in both directions when on.
Functional Block Diagrams and Pin Configurations
Truth Table
Logic Switch
0 OFF
1 ON
Logic “0” 0.8 V
Lo
g
ic “1” 2 V
Logic
1
2
V
Updates to this data sheet may be obtained via facsimile by calling Siliconix FaxBack, 1-408-970-5600. Please request FaxBack document #70055.
DG540/541/542
2 Siliconix
S-53694—Rev. E, 28-May-97
Functional Block Diagrams and Pin Configurations (Cont’d)
IN1IN2
D1D2
S1S2
V– V+
GND GND
S4S3
D4D3
IN4IN3
DG541
DG542
IN1IN2
D1D2
GND GND
S1S2
V– V+
S4S3
GND GND
D4D3
Dual-In-Line and SOIC
0 OFF
1 ON
Logic “0” 0.8 V
Logic “1” 2 V
0 OFF ON
1 ON OFF
Logic “0” 0.8 V
Logic “1” 2 V
Ordering Information
Temp Range Package Part Number
DG540
–
40to 85
_
C
20-Pin Plastic DIP DG540DJ
–
40
t
o
85_C
20-Pin PLCC DG540DN
–
55 to 125
_
C
20
-
Pin Sidebraze
DG540AP
–
55
t
o
125_C
20
-
Pi
n
Sid
e
b
raze DG540AP/883
DG541
–
40 to 85
_
C
16-Pin Plastic DIP DG541DJ
–
40
t
o
85_C
16-Pin Narrow SOIC DG541DY
–
55 to 125
_
C
16
-
Pin Sidebraze
DG541AP
–
55
t
o
125_C
16
-
Pi
n
Sid
e
b
raze DG541AP/883
DG542
–
40 to 85
_
C
16-Pin Plastic DIP DG542DJ
–
40
t
o
85_C
16-Pin Narrow SOIC DG542DY
–
55 to 125
_
C
16
-
Pin Sidebraze
DG542AP
–
55
t
o
125_C
16
-
Pi
n
Sid
e
b
raze DG542AP/883
DG540/541/542
Siliconix
S-53694—Rev. E, 28-May-97 3
Absolute Maximum Ratings
V+ to V– –0.3 V to 21 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V+ to GND –0.3 V to 21 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
V– to GND –19 V to +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital Inputs (V–) –0.3 V to (V+) +0.3 V. . . . . . . . . . . . . . . . . . . . . . . .
or 20 mA, whichever occurs first
VS, VD(V–) –0.3 V to (V–) +14 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
or 20 mA, whichever occurs first
Continuous Current (Any Terminal) 20 mA. . . . . . . . . . . . . . . . . . . . . .
Current, S or D (Pulsed 1 ms, 10% duty cycle max) 40 mA. . . . . . . . . .
Storage Temperature (AP Suffix) –65 to 150_C. . . . . . . . . . . . . .
(DJ, DN, DY Suffixes) –65 to 125_C. . . . .
Power Dissipation (Package)a
16-Pin Plastic DIPb470 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin Plastic DIPc800 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-Pin Narrow Body SOICd640 mW. . . . . . . . . . . . . . . . . . . . . . . . . . .
20-Pin PLCCd800 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16-, 20-Pin Sidebraze DIPe900 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Notes:
a. All leads welded or soldered to PC Board.
b. Derate 6.5 mW/_C above 25_C
c. Derate 7 mW/_C above 25_C
d. Derate 10 mW/_C above 75_C
e. Derate 12 mW/_C above 75_C
Schematic Diagram (Typical Channel)
Figure 1.
V+
IN
V–
GND
–
+
S
D
VREF
DG540/541/542
4 Siliconix
S-53694—Rev. E, 28-May-97
Specificationsa
Test Conditions
Unless Specified
V+ 15 V V 3 V
A Suffix
–55 to 125_CD Suffixes
–40 to 85_C
Parameter Symbol V+ = 15 V, V– = –3 V
VINH = 2 V, VINL = 0.8 VfTempbTypcMindMaxdMindMaxdUnit
Analog Switch
Analog Signal Range VANALOG V– = –5 V, V+ = 12 V Full –5 5 –5 5 V
Drain-Source
On-Resistance rDS(on) IS = –10 mA, VD = 0 V
Room
Full 30 60
100 60
75 W
rDS(on) Match DrDS(on)
S,D
Room 2 6 6
Source Off
Leakage Current IS(off) VS = 0 V, VD = 10 V Room
Full –0.05 –10
–500 10
500 –10
–100 10
100
Drain Off
Leakage Current ID(off) VS = 10 V, VD = 0 V Room
Full –0.05 –10
–500 10
500 –10
–100 10
100 nA
Channel On
Leakage Current ID(on) VS = VD = 0 V Room
Full –0.05 –10
–1000 10
1000 –10
–100 10
100
Digital Control
Input Voltage High VINH Full 2 2
V
Input Voltage Low VINL Full 0.8 0.8
V
Input Current IIN VIN = GND or V+ Room
Full 0.05 –1
–20 1
20 –1
–20 1
20 mA
Dynamic Characteristics
On State Input CapacitanceeCS(on) VS = VD = 0 V Room 14 20 20
Off State Input CapacitanceeCS(off) VS = 0 V Room 2 4 4 pF
Off State Output CapacitanceeCD(off) VD = 0 V Room 2 4 4
Bandwidth BW RL = 50 W, See Figure 5 Room 500 MHz
Turn On Time
tON
W
DG540
DG541 Room
Full 45 70
130 70
130
T
urn
O
n
Ti
me
t
ON RL = 1 kW
CL = 35 pF DG542 Room
Full 55 100
160 100
160
ns
Turn Off Time
tOFF
Lp
50% to 90%
See Figure 2 DG540
DG541 Room
Full 20 50
85 50
85
ns
T
urn
Off
Ti
me
t
OFF DG542 Room
Full 25 60
85 60
85
Charge Injection Q CL = 1000 pF, VS = 0 V
See Figure 3 Room –25 pC
RIN = 75 W
R75W
DG540 Room –80
Off Isolation OIRR RL = 75 W
f = 5 MHz DG541 Room –60
f
=
5
MHz
See Figure 4 DG542 Room –75 dB
All Hostile Crosstalk XTALK(AH) RIN = 10 W, RL = 75 W
f = 5 MHz, See Figure 6 Room –85
Power Supplies
Positive Supply Current I+
All Channels On or Off
Room
Full 3.5 6
96
9
mA
Negative Supply Current I–
All
Channels
On
or
Off
Room
Full –3.2 –6
–9 –6
–9
mA
Notes:
a. Refer to PROCESS OPTION FLOWCHART.
b. Room = 25_C, Full = as determined by the operating temperature suffix.
c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing.
d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet.
e. Guaranteed by design, not subject to production test.
f. VIN = input voltage to perform proper function.
DG540/541/542
Siliconix
S-53694—Rev. E, 28-May-97 5
Typical Characteristics
Supply Curent vs. Temperature ID(off), IS(off) vs. Temperature
rDS(on) vs. Drain Voltage V+ Constant V– Constant
Temperature (_C) Temperature (_C)
VD – Drain Voltage (V) V– – Negative Supply (V) V+ – Positive Supply (V)
I (mA)
6
5
4
3
2
1
0
–1
–2
–3
–4
–5
–55 –35 –15 5 25 45 65 85 105 125
IGND
0–55 125
100 nA
10 nA
1 nA
100 pA
10 pA
1 pA
0.1 pA –25 25 50 75 100
160
140
120
100
80
60
40
20
0–3 –1 1 3 5 7 9 11
V+ = 15 V
V– = –3 V
125_C
–55_C
42
40
38
36
34
32
30
20
18 10 11 12 13 14 15 16
42
40
38
36
34
32
30
20
18–5 –4 –3 –2 –1 0
V+ = 12 V
V+ = 15 V
V– = –5 V
V– = –1 V
V+ = 10 V
I–
I+
– LeakageI , I
S(off) D(off)
rDS(on) – Drain-Source On-Resistance (
rDS(on) – Drain-Source On-Resistance (
25_CV– = –3 V
On Capacitance Off Isolation
VD – Drain Voltage (V) f – Frequency (MHz)
C (pF)
ISO (dB)
22
20
18
16
14
12
10
8
60 2 4 6 8 10 12 14 110 100
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
DG541
DG540
DG542
DG540/541/542
6 Siliconix
S-53694—Rev. E, 28-May-97
Typical Characteristics (Cont’d)
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
Charge Injection vs. VSSwitching Times vs. Temperature
(DG540/541)
Off Isolation vs. Frequency and Load Resistance
(DG540) All Hostile Crosstalk
f – Frequency (MHz) f – Frequency (MHz)
VS – Source Voltage (V) Temperature (_C)
OIRR (dB)
(dB)
TALK
X
Q (pC)
Time (ns)
110 100
DG541
DG540
DG542
40
30
20
10
0
–10
–20
–30
–40–3 –2 –1 0 1 2 3 4 5 6 7 8
CL = 1000 pF
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
01 10 100
RL = 75
1 k
10 k
180
90
70
60
50
40
30
20
10
0–55 –25 125
80
tON
tOFF
0 25 50 75 100
Switching and Break-Before-Make Time
vs. Temperature (DG542)
Temperature (_C)
Time (ns)
90
70
60
50
40
30
20
10
0–55 –25 125
80
0 25 50 75 100
tON
tOFF
tBBM
Operating Supply Voltage Range
V+ – Positive Supply (V)
V– – Negative Supply (V)
20
18
16
14
12
10 0 –1–2–3–4–5–6
Operating
Voltage
Area
DG540/541/542
Siliconix
S-53694—Rev. E, 28-May-97 7
Test Circuits
Figure 2. Switching Time
RL
RL + rDS(on)
VO = VS
CL (includes fixture and stray capacitance)
V–
V+
IN
S
CL
35 pF
D
RL
1 kW
VO
–3 V
GND
+15 V
3 V
0
90%
50%
tOFF
tON
VS
tr <20 ns
tf <20 ns
Logic
Input
Switch
Input
Switch
Output
C+15 V
Figure 3. Charge Injection
ON ONOFF
VO
DVO
INX
DVO = measured voltage error due to charge injection
The charge injection in coulombs is DQ = CL x DVO
CL
1000 pF
3 V
Vg
VO
–3 V
D
GND
V+
RgS
IN
V–
+15 V
Figure 4. Off Isolation
S
IN RL
75 W
D
Rg = 75 W
VSVO
0 V, 2.4 V
Off Isolation = 20 log VS
VO
V+
–3 V
GND V– C
C+15 V
C = RF Bypass
S
RL
50 W
D
Rg = 50 W
VSVO
–3 V
GND
V+
V– C
Figure 5. Bandwidth
IN
0 V, 2.4 V
DG540/541/542
8 Siliconix
S-53694—Rev. E, 28-May-97
Test Circuits (Cont’d)
S2
S3
S4
XTALK(AH) 20 log10
VOUT
VIN
VO
10 WRL
75 W
INX
S1V+
V–
+15 V
–15 V C
C
GND
2.4 V
D2
D3
D1
D4
RL
RL
RL
Figure 6. All Hostile Crosstalk
Applications
Device Description
The DG540/541/542 family of wideband switches offers
true bidirectional switching of high frequency analog or
digital signals with minimum signal crosstalk, low insertion
loss, and negligible non-linearity distortion and group
delay.
Built on the Siliconix D/CMOS process, these “T” switches
provide excellent off-isolation with a bandwidth of around
500 MHz (350 MHz for DG541). Silicon-gate D/CMOS
processing also yields fast switching speeds.
An on-chip regulator circuit maintains TTL input
compatibility over the whole operating supply voltage
range, easing control logic interfacing.
Circuit layout is facilitated by the interchangeability of
source and drain terminals.
Frequency Response
A single switch on-channel exhibits both resistance
[rDS(on)] and capacitance [CS(on)]. This RC combination has
an attenuation effect on the analog signal – which is
frequency dependent (like an RC low-pass filter). The
–3-dB bandwidth of the DG540 is typically 500 MHz (into
50 W). This measured figure of 500 MHz illustrates that
the switch channel can not be represented by a two stage RC
combination. The on capacitance of the channel is
distributed along the on-resistance, and hence becomes a
more complex multi stage network of R’s and C’s making
up the total rDS(on) and CS(on). See Application Note AN502
for more details.
Off-Isolation and Crosstalk
Off-isolation and crosstalk are affected by the load
resistance and parasitic inter-electrode capacitances.
Higher off-isolation is achieved with lower values of RL.
However , low values of RL increase insertion loss requiring
gain adjustments down the line. Stray capacitances, even a
fraction of 1 pF, can cause a large crosstalk increase. Good
layout and ground shielding techniques can considerably
improve your ac circuit performance.
DG540/541/542
Siliconix
S-53694—Rev. E, 28-May-97 9
Applications (Cont’d)
Power Supplies
A useful feature of the DG54X family is its power supply
flexibility. It can be operated from a single positive supply
(V+) if required (V– connected to ground).
Note that the analog signal must not exceed V– by more
than –0.3 V to prevent forward biasing the substrate p-n
junction. The use of a V– supply has a number of
advantages:
1. It allows flexibility in analog signal handling, i.e.,
with V- = -5 V and V+ = 12 V; up to 5ĆV ac
signals can be controlled.
2. The value of on capacitance [CS(on)] may be
reduced. A property known as `the bodyĆeffect' on
the DMOS switch devices causes various
parametric effects to occur. One of these effects is
the reduction in CS(on) for an increasing V
body-source. Note, however, that to increase V-
normally requires V+ to be reduced (since V+ to
V- = 21 V max.). Reduction in V+ causes an
increase in rDS(on), hence a compromise has to be
achieved. It is also useful to note that optimum
video linearity performance (e.g., differential phase
and gain) occurs when V- is around -3 V.
3. V- eliminates the need to bias the analog signal
using potential dividers and large coupling
capacitors.
Decoupling
It is an established RF design practice to incorporate
sufficient bypass capacitors in the circuit to decouple the
power supplies to all active devices in the circuit. The
dynamic performance of the DG54X is adversely affected
by poor decoupling of power supply pins. Also, of even
more significance, since the substrate of the device is
connected to the negative supply, adequate decoupling of
this pin is essential.
Rules:
1. Decoupling capacitors should be incorporated on
all power supply pins (V+, V-). (See Figure 7.)
2. They should be mounted as close as possible to the
device pins.
3. Capacitors should have good high frequency
characteristics - tantalum bead and/or monolithic
ceramic types are adequate.
Suitable decoupling capacitors are 1Ć to 10ĆmF
tantalum bead, plus 10Ć to 100ĆnF ceramic.
+
+
–3 V
GNDs
+15 V
DG540
V+
V–
S1
S2
S3
S4
D1
D2
D3
D4
C1C2
C1C2
C1 = 10 mF Tantalum
C2 = 0.1 mF Ceramic
Figure 7. Supply Decoupling
Board Layout
PCB layout rules for good high frequency performance
must be observed to achieve the performance boasted by the
DG540. Some tips for minimizing stray ef fects are:
1. Use extensive ground planes on double sided PCB,
separating adjacent signal paths. Multilayer PCB is
even better.
2. Keep signal paths as short as practically possible,
with all channel paths of near equal length.
3. Careful arrangement of ground connections is also
very important. Star connected system grounds
eliminate signal current flowing through ground
path parasitic resistance from coupling between
channels.
DG540/541/542
10 Siliconix
S-53694—Rev. E, 28-May-97
Applications (Cont’d)
Figure 8 shows a 4-channel video multiplexer using a DG540.
+
–
TTL Channel Select
A = 2
75
75
75
75
75
250
250
Si582
CH1
CH2
CH3
CH4
DG540
DIS
Figure 8. 4 by 1 Video Multiplexing Using the DG540
V+
V–
–3 V
+15 V
Figure 9 shows an RGB selector switch using two DG542s.
Red Out
Green Out
DG542
Blue Out
Sync Out
DG542
V+
V–
Sync 1 Sync 2
–3 V
+15 V Si584
75
R2
75
R1
75
G1
75
B1
75
75
G2
75
B2
75
RGB Source Select
Figure 9. RGB Selector Using Two DG542s
V+
V–
–3 V
+15 V
