LMV7291 www.ti.com SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 LMV7291 Single 1.8V Low Power Comparator with Rail-to-Rail Input Check for Samples: LMV7291 FEATURES DESCRIPTION * The LMV7291 is a rail-to-rail input low power comparator, characterized at supply voltage 1.8V, 2.7V and 5.0V. It consumes only 9uA supply current per channel while achieving a 800ns propagation delay. 1 2 * * * * * * * (VS = 1.8V, TA = 25C, Typical Values unless Specified) Single Supply Ultra Low Supply Current 9A per Channel Low Input Bias Current 10nA Low Input Offset Current 200pA Low ensured VOS 4mV Propagation Delay 880ns (20mV Overdrive) Input Common Mode Voltage Range 0.1V beyond Rails The LMV7291 is available in SC70 package. With this tiny package, the PC board area can be significantly reduced. It is ideal for low voltage, low power and space critical designs. The LMV7291 features a push-pull output stage which allows operation with minimum power consumption when driving a load. The LMV7291 is built with Texas Instruments' advance submicron silicon-gate BiCMOS process. It has bipolar inputs for improved noise performance and CMOS outputs for rail-to-rail output swing. APPLICATIONS * * * * Mobile Communications Laptops and PDA's Battery Powered Electronics General Purpose Low Voltage Applications Typical Circuit VIN VCC R1 C1 = 0.1F C2 = 10F + VOUT R2 - VREF Figure 1. Threshold Detector These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2004-2013, Texas Instruments Incorporated LMV7291 SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 Absolute Maximum Ratings www.ti.com (1) (2) ESD Tolerance VIN Differential 2KV (3) 200V (4) Supply Voltage Supply Voltage (V+ - V-) 5.5V V+ +0.1V, V- -0.1V Voltage at Input/Output pins Soldering Information Infrared or Convection (20 sec.) 235C Wave Soldering (10 sec.) 260C -65C to +150C Storage Temperature Range Junction Temperature (1) (2) (3) (4) (5) (5) +150C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human body model, 1.5k in series with 100pF. Machine Model, 0 in series with 200pF. Typical values represent the most likely parametric norm. Operating Ratings (1) Operating Temperature Range Package Thermal Resistance (2) -40C to +85C (2) SC70 (1) (2) 2 265C/W Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. The maximum power dissipation is a function of TJ(MAX), JA, and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) - TA)/JA. All numbers apply for packages soldered directly into a PC board. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 LMV7291 www.ti.com SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 1.8V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 1.8V, V- = 0V. Boldface limits apply at the temperature extremes. (1) Symbol Parameter Condition Min (2) Typ (3) Max (2) Units 0.3 4 6 mV VOS Input Offset Voltage TC VOS Input Offset Temperature Drift 10 uV/C IB Input Bias Current 10 nA IOS Input Offset Current 200 pA IS Supply Current LMV7291 ISC Output Short Circuit Current Sourcing, VO = 0.9V VCM = 0.9V (4) 9 3.5 6 4 6 IO = 0.5mA 1.7 1.74 IO = 1.5mA 1.58 1.63 Sinking, VO = 0.9V VOH Output Voltage High VOL Output Voltage Low VCM Input Common Mode Voltage Range 12 14 mA V IO = -0.5mA 52 70 IO = -1.5mA 166 220 CMRR > 45 dB A mV 1.9 V -0.1 V CMRR Common Mode Rejection Ratio 0 < VCM < 1.8V 47 78 dB PSRR Power Supply Rejection Ratio V+ = 1.8V to 5V 55 80 dB ILEAKAGE Output Leakage Current VO = 1.8V 2 pA (1) (2) (3) (4) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. 1.8V AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 1.8V, V- = 0V, VCM = 0.5V, VO = V+/2 and RL > 1M to V-. Boldface limits apply at the temperature extremes. (1) Symbol tPHL tPLH (1) (2) (3) Parameter Propagation Delay (High to Low) Propagation Delay (Low to High) Condition Min (2) Typ (3) Max (2) Units Input Overdrive = 20mV Load = 50pF//5k 880 ns Input Overdrive = 50mV Load = 50pF//5k 570 ns Input Overdrive = 20mV Load = 50pF//5k 1100 ns Input Overdrive = 50mV Load = 50pF//5k 800 ns Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 3 LMV7291 SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 www.ti.com 2.7V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 2.7V, V- = 0V. Boldface limits apply at the temperature extremes. (1) Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units 0.3 4 6 mV VOS Input Offset Voltage TC VOS Input Offset Temperature Drift 10 V/C IB Input Bias Current 10 nA IOS Input offset Current 200 pA IS Supply Current LMV7291 ISC Output Short Circuit Current Sourcing, VO = 1.35V 12 15 Sinking, VO = 1.35V 12 15 IO = 0.5mA 2.63 2.66 IO = 2.0mA 2.48 2.55 VOH Output Voltage High VOL Output Voltage Low VCM Input Common Voltage Range VCM = 1.35V (4) 9 13 15 mA V IO = -0.5mA 50 70 IO = -2mA 155 220 CMRR > 45dB A 2.8 -0.1 mV V V CMRR Common Mode Rejection Ratio 0 < VCM < 2.7V 47 78 dB PSRR Power Supply Rejection Ratio V+ = 1.8V to 5V 55 80 dB ILEAKAGE Output Leakage Current VO = 2.7V 2 pA (1) (2) (3) (4) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. 2.7V AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 2.7V, V- = 0V, VCM = 0.5V, VO = V+/2 and RL > 1M to V-. Boldface limits apply at the temperature extremes. (1) Symbol tPHL tPLH (1) (2) (3) 4 Parameter Propagation Delay (High to Low) Propagation Delay (Low to High) Condition Min (2) Typ (3) Max (2) Units Input Overdrive = 20mV Load = 50pF//5k 1200 ns Input Overdrive = 50mV Load = 50pF//5k 810 ns Input Overdrive = 20mV Load = 50pF//5k 1300 ns Input Overdrive = 50mV Load = 50pF//5k 860 ns Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 LMV7291 www.ti.com SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 5V Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 5V, V- = 0V. Boldface limits apply at the temperature extremes. (1) Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units 0.3 4 6 mV VOS Input Offset Voltage TC VOS Input Offset Temperature Drift 10 V/C IB Input Bias Current 10 nA IOS Input Offset Current 200 pA IS Supply Current LMV7291 ISC Output Short Circuit Current Sourcing, VO = 2.5V 28 34 Sinking, VO = 2.5V 28 34 IO = 0.5mA 4.93 4.96 IO = 4.0mA 4.70 4.77 VOH Output Voltage High VOL Output Voltage Low VCM Input Common Voltage Range VCM = 2.5V (4) 10 14 16 mA V IO = -0.5mA 27 70 IO = -4.0mA 225 300 CMRR > 45dB A mV 5.1 V -0.1 CMRR Common Mode Rejection Ratio 0 < VCM < 5.0V 47 78 dB PSRR Power Supply Rejection Ratio V+ = 1.8V to 5V 55 80 dB ILEAKAGE Output Leakage Current VO = 5V 2 pA (1) (2) (3) (4) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change. 5.0V AC Electrical Characteristics Unless otherwise specified, all limits ensured for TJ = 25C, V+ = 5.0V, V- = 0V, VCM = 0.5V, VO = V+/2 and RL > 1M to V-. Boldface limits apply at the temperature extremes. (1) Symbol tPHL tPLH (1) (2) (3) Parameter Propagation Delay (High to Low) Propagation Delay (Low to High) Condition Min (2) Typ (3) Max (2) Units Input Overdrive = 20mV Load = 50pF//5k 2100 ns Input Overdrive = 50mV Load = 50pF//5k 1380 ns Input Overdrive = 20mV Load = 50pF//5k 1800 ns Input Overdrive = 50mV Load = 50pF//5k 1100 ns Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical tables under conditions of internal self heating where TJ > TA. Absolute Maximum Ratings indicate junction temperature limits beyond which the device may be permanently degraded, either mechanically or electrically. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 5 LMV7291 SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 www.ti.com Connection Diagram 1 5 VOUT + V 2 GND 3 4 +IN -IN Figure 2. 5-Pin SC70 - Top View See Package Number DCK 6 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 LMV7291 www.ti.com SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 Typical Performance Characteristics (TA = 25C, Unless otherwise specified). VOS vs. VCM VOS vs. VCM VSUPPLY = 0.9V 800 800 VSUPPLY = 1.35V -40C -40C 400 400 VOS (PV) VOS (PV) 25C 0 0 85C -400 -400 25C 85C -800 -800 -0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9 0 0.45 VOS vs. VCM Short Circuit vs. Supply Voltage SHORT CIRCUIT OUTPUT CURRENT (mA) Figure 4. -40C VOS (PV) -0.45 Figure 3. 400 0 -400 25C 85C -800 -2.5 -2 -0.9 VCM (V) VSUPPLY = 2.5V 800 -1.35 VCM (V) -1 0 1 2 2.5 0.9 1.35 40 SOURCE 30 20 SINK 10 0 1.8 2.44 VCM (V) 3.08 3.72 4.36 5.0 SUPPLY VOLTAGE (V) Figure 5. Figure 6. Supply Current vs. Supply Voltage Supply Current vs. Supply Voltage 25 10 SUPPLY CURRENT (PA) SUPPLY CURRENT (PA) 85C 9 85C 85C 8 25C 7 6 20 15 25C 10 -40C 5 -40C VOUT = HIGH 0 5 1.8 2.44 3.08 3.72 4.36 5.0 1.5 2 2.5 3 3.5 4 4.5 5 VSUPPLY (V) SUPPLY VOLTAGE (V) Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 7 LMV7291 SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) (TA = 25C, Unless otherwise specified). Supply Current vs. Supply Voltage Output Positive Swing vs. VSUPPLY 600 25 500 V - VOUT (mV) 15 10 25C + SUPPLY CURRENT (PA) ISOURCE 85C 20 -40C 400 4mA 300 2mA 200 1.5mA 5 100 0.5mA VOUT = LOW 0 0 1.5 2 2.5 3 3.5 4 1.8 5 4.5 2.3 2.8 3.3 3.8 4.3 4.8 VSUPPLY (V) VSUPPLY (V) Figure 9. Figure 10. Output Negative Swing vs. VSUPPLY Output Positive Swing vs. ISOURCE 600 0.8 VSUPPLY = 1.8V ISINK 0.7 500 85C V - VOUT (V) 400 4mA - VOUT - V (mV) 0.6 300 + 2mA 200 0.5 25C 0.4 0.3 1.5mA 0.2 -40C 100 0.1 0.5mA 0 0 1.8 2.3 2.8 3.3 3.8 4.3 4.8 0 0.5 1 1.5 2 2.5 3 3.5 4 ISOURCE (mA) VSUPPLY (V) Figure 11. Figure 12. Output Negative Swing vs. ISINK Output Positive Swing vs. ISOURCE 0.5 0.8 VSUPPLY = 1.8V VSUPPLY = 2.7V 0.45 0.7 85C 85C 0.4 0.6 V - VOUT (V) - VOUT - V (V) 0.35 0.5 25C + 0.4 0.3 25C 0.3 0.25 0.2 0.15 0.2 -40 0.1 -40C 0.1 0.05 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 ISINK (mA) 0.5 1 1.5 2 2.5 3 3.5 4 ISOURCE (mA) Figure 13. 8 0 Figure 14. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 LMV7291 www.ti.com SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 Typical Performance Characteristics (continued) (TA = 25C, Unless otherwise specified). Output Negative Swing vs. ISINK Output Negative Swing vs. ISINK 0.5 0.4 VSUPPLY = 2.7V 0.45 VSUPPLY = 5V 85C 85C 0.4 25C - 0.3 VOUT - V (V) - VOUT - V (V) 0.3 0.35 25C 0.25 0.2 0.2 0.15 0.1 0.1 -40C -40C 0.05 0 0 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 Figure 15. OUTPUT VOLTAGE (V) VSUPPLY = 5V 85C 3.5 4 25C 5 VCC = 1.8V TEMP = 25C LOAD = 5k: 50pF 4 3 50mV 20mV 2 1 0 0.2 | INPUT VOLTAGE (mV) + V - VOUT (V) 0.3 0.1 -40C 0 0 0.5 1 1.5 2 2.5 3 3.5 | 100 0 OVERDRIVE -100 4 0 500 1000 Figure 17. Propagation Delay (tPHL) Propagation Delay (tPLH) OUTPUT VOLTAGE (V) VCC = 1.8 V 4 TEMP = 25C 3 LOAD = 5k: 50pF 50mV 1 2500 3000 Figure 18. 5 2 1500 2000 TIME (ns) ISOURCE (mA) OUTPUT VOLTAGE (V) 3 Propagation Delay (tPLH) 0.4 20mV 5 VCC = 2.7V TEMP = 25C LOAD = 5k: 50pF 4 3 2 1 50mV 20mV 0 | | 100 OVERDRIVE 0 -100 500 1000 1500 INPUT VOLTAGE (mV) 0 INPUT VOLTAGE (mV) 2.5 Figure 16. Output Positive Swing vs. ISOURCE 0 2 ISINK (mA) ISINK (mA) 2000 2500 3000 | | 100 0 OVERDRIVE -100 0 500 1000 1500 2000 2500 3000 TIME (ns) TIME (ns) Figure 19. Figure 20. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 9 LMV7291 SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 www.ti.com Typical Performance Characteristics (continued) (TA = 25C, Unless otherwise specified). Propagation Delay (tPLH) VCC = 2.7 V TEMP = 25C LOAD = 5k: 50pF 4 3 2 50mV 1 5 OUTPUT VOLTAGE (V) OUTPUT VOLTAGE (V) Propagation Delay (tPHL) 5 20mV VCC = 5.0V TEMP = 25C 3 LOAD = 5k: 50pF 20mV 2 1 0 | | 100 INPUT VOLTAGE (mV) INPUT VOLTAGE (mV) 0 OVERDRIVE 0 -100 0 500 1000 1500 | | 100 0 OVERDRIVE -100 2000 2500 3000 0 500 1000 1500 2000 2500 3000 TIME (ns) Figure 21. Figure 22. Propagation Delay (tPHL) tPHL vs. Overdrive 5 8 VCC = 5.0 V TEMP = 25C 3 LOAD = 5k: 50pF 7 4 VS = 5V 6 2 50mV 1 0 tPHL (PS) OUTPUT VOLTAGE (V) TIME (ns) INPUT VOLTAGE (mV) 50mV 4 20mV | | 100 OVERDRIVE 5 4 VS = 2.7V 3 2 0 1 -100 VS = 1.8V 0 0 500 1000 1500 2000 2500 3000 0 TIME (ns) 10 100 1000 OVERDRIVE (mV) Figure 23. Figure 24. tPLH vs. Overdrive 5 VS = 5V 4.5 4 tPLH (PS) 3.5 3 2.5 VS = 2.7V 2 1.5 1 VS = 1.8V 0.5 0 1 10 100 1000 OVERDRIVE (mV) Figure 25. 10 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 LMV7291 www.ti.com SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 APPLICATION NOTES BASIC COMPARATOR A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 26, the comparator compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output (VO) is low. However, if VIN is greater than VREF, the output voltage (VO) is high. V VREF + VOLTS VO VO VIN + VREF V - TIME VIN Figure 26. LMV7291 Basic Comparator RAIL-TO-RAIL INPUT STAGE The LMV7291 has an input common mode voltage range (VCM) of -0.1V below the V- to 0.1V above V+. This is achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN pair is on and the PNP pair is off. When the VCM is near V-, the NPN pair is off and the PNP pair is on. The crossover point between the NPN and PNP input stages is around 950mV from V+. Since each input stage has its own offset voltage (VOS), the VOS of the comparator becomes a function of the VCM. See Figure 3, Figure 4, and Figure 5 in Typical Performance Characteristics. In application design, it is recommended to keep the VCM away from the crossover point to avoid problems. The wide input voltage range makes LMV7291 ideal in power supply monitoring circuits, where the comparators are used to sense signals close to gnd and power supplies. OUTPUT STAGE The LMV7291 has a push-pull output stage. This output stage keeps the total system power consumption to the absolute minimum. The only current consumed is the low supply current and the current going directly into the load. When output switches, both PMOS and NMOS at the output stage are on at the same time for a very short time. This allows current to flow directly between V+ and V- through output transistors. The result is a short spike of current (shoot-through current) drawn from the supply and glitches in the supply voltages. The glitches can spread to other parts of the board as noise. To prevent the glitches in supply lines, power supply bypass capacitors must be installed. See CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS for details. HYSTERESIS It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation, and to avoid excessive noise on the output because the comparator is a good amplifier of its own noise. Inverting Comparator with Hysteresis The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply voltage VCC of the comparator (Figure 27). When VIN at the inverting input is less than VA, the voltage at the noninverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VO switches as high as VCC). The three network resistors can be represented as R1||R3 in series with R2. The lower input trip voltage VA1 is defined as Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 11 LMV7291 SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 VA1 = www.ti.com VCC R2 (R1||R3) + R2 (1) When VIN is greater than VA (VIN > VA), the output voltage is low and very close to ground. In this case the three network resistors can be presented as R2//R3 in series with R1. The upper trip voltage VA2 is defined as VA2 = VCC (R2||R3) R1 + (R2||R3) (2) The total hysteresis provided by the network is defined as VA = VA1 - VA2 (3) A good typical value of VA would be in the range of 5 to 50 mV. This is easily obtained by choosing R3 as 1000 to 100 times (R1||R2) for 5V operation, or as 300 to 30 times (R1||R2) for 1.8V operation. Figure 27. Inverting Comparator with Hysteresis Non-Inverting Comparator with Hysteresis A non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the inverting input (Figure 28). When VIN is low, the output is also low. For the output to switch from low to high, VIN must rise up to VIN1, where VIN1 is calculated by (4) 12 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 LMV7291 www.ti.com SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 When VIN is high, the output is also high. To make the comparator switch back to its low state, VIN must equal VREF before VA will again equal VREF. VIN can be calculated by: (5) The hysteresis of this circuit is the difference between VIN1 and VIN2. VIN = VCCR1/R2 (6) Figure 28. Non-Inverting Comparator with Hysteresis CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS Feedback to almost any pin of a comparator can result in oscillation. In addition, when the input signal is a slow voltage ramp or sine wave, the comparator may also burst into oscillation near the crossing point. To avoid oscillation or instability, PCB layout should be engineered thoughtfully. Several precautions are recommended: 1. Power supply bypassing is critical, and will improve stability and transient response. Resistance and inductance from power supply wires and board traces increase power supply line impedance. When supply current changes, the power supply line will move due to its impedance. Large enough supply line shift will cause the comparator to mis-operate. To avoid problems, a small bypass capacitor, such as 0.1uF ceramic, should be placed immediately adjacent to the supply pins. An additional 6.8F or greater tantalum capacitor should be placed at the point where the power supply for the comparator is introduced onto the board. These capacitors act as an energy reservoir and keep the supply impedance low. In dual supply application, a 0.1F capacitor is recommended to be placed across V+ and V- pins. 2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize any unwanted coupling from any high-level signals (such as the output). The comparators can easily oscillate if the output lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only during the output voltage transition intervals as the comparator changes states. Try to avoid a long loop which could act as an inductor (coil). 3. It is a good practice to use an unbroken ground plane on a printed circuit board to provide all components with a low inductive ground connection. Make sure ground paths are low-impedance where heavier currents are flowing to avoid ground level shift. Preferably there should be a ground plane under the component. 4. The output trace should be routed away from inputs. The ground plane should extend between the output and inputs to act as a guard. Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 13 LMV7291 SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 www.ti.com 5. When the signal source is applied through a resistive network to one input of the comparator, it is usually advantageous to connect the other input with a resistor with the same value, for both DC and AC consideration. Input traces should be laid out symmetrically if possible. 6. All pins of any unused comparators should be tied to the negative supply. Typical Applications POSITIVE PEAK DETECTOR A positive peak detect circuit is basically a comparator operated in a unity gain follower configuration, with a capacitor as a load to maintain the highest voltage. A diode is added at the output to prevent the capacitor from discharging through the output, and a 1M resistor added in parallel to the capacitor to provide a high impedance discharge path. When the input VIN increases, the inverting input of the comparator follows it, thus charging the capacitor. When it decreases, the cap discharges through the 1M resistor. The decay time can be modified by changing the resistor. The output should be accessed through a follower circuit to prevent loading. +VCC VIN + - VOUT C1 10 PF + R2 1 M: Figure 29. Positive Peak Detector NEGATIVE PEAK DETECTOR For the negative detector, the output transistor of the comparator acts as a low impedance current sink. Since there is no pull-up resistor, the only discharge path will be the 1M resistor and any load impedance used. Decay time is changed by varying the 1M resistor. +VCC VIN + VOUT - R1 1M: + C1 10PF -VCC Figure 30. Negative Peak Detector SQUARE WAVE GENERATOR A typical application for a comparator is as a square wave oscillator. The circuit below generates a square wave whose period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is limited by the large signal propagation delay of the comparator, and by the capacitive loading at the output, which limits the output slew rate. 14 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 LMV7291 www.ti.com SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 R4 = 100 k: C1 = 750 pF VC VO + R1 = 100 k: V + VA R3 = 100 k: + R2 = 100 k: V 0 f | 10 kHz Figure 31. Squarewave Oscillator To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than the non-inverting input (VA). This causes the C1 to get charged through R4, and the voltage VC increases till it is equal to the non-inverting input. The value of VA at this point is VCC.R2 VA1 = R2 + R1||R3 (7) If R1 = R2 = R3 then VA1 = 2VCC/3 At this point the comparator switches pulling down the output to the negative rail. The value of VA at this point is VCC (R2||R3) VA2 = R1 + (R2||R3) (8) If R1 = R2 = R3 then VA2 = VCC/3 The capacitor C1 now discharges through R4, and the voltage VC decreases till it is equal to VA2, at which point the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it takes to discharge C1 from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is: F = 1/(2.R4.C1.ln2) Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 15 LMV7291 SNOSA86E - FEBRUARY 2004 - REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision D (March 2013) to Revision E * 16 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 15 Submit Documentation Feedback Copyright (c) 2004-2013, Texas Instruments Incorporated Product Folder Links: LMV7291 PACKAGE OPTION ADDENDUM www.ti.com 1-Nov-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LMV7291MG NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C36 LMV7291MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C36 LMV7291MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C36 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMV7291MG SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7291MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 LMV7291MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 23-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV7291MG SC70 DCK 5 1000 210.0 185.0 35.0 LMV7291MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0 LMV7291MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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