VIN
R1
R2
VREF
VCC
VOUT
+
-
C1 =
0.1µF
C2 =
10µF
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LMV7291 Single 1.8V Low Power Comparator with Rail-to-Rail Input
Check for Samples: LMV7291
1FEATURES DESCRIPTION
The LMV7291 is a rail-to-rail input low power
2• (VS= 1.8V, TA= 25°C, Typical comparator, characterized at supply voltage 1.8V,
Values unless Specified) 2.7V and 5.0V. It consumes only 9uA supply current
• Single Supply per channel while achieving a 800ns propagation
• Ultra Low Supply Current 9µA per Channel delay.
• Low Input Bias Current 10nA The LMV7291 is available in SC70 package. With this
tiny package, the PC board area can be significantly
• Low Input Offset Current 200pA reduced. It is ideal for low voltage, low power and
• Low ensured VOS 4mV space critical designs.
• Propagation Delay 880ns (20mV Overdrive) The LMV7291 features a push-pull output stage
• Input Common Mode Voltage Range 0.1V which allows operation with minimum power
beyond Rails consumption when driving a load.
The LMV7291 is built with Texas Instruments'
APPLICATIONS advance submicron silicon-gate BiCMOS process. It
• Mobile Communications has bipolar inputs for improved noise performance
• Laptops and PDA's and CMOS outputs for rail-to-rail output swing.
• Battery Powered Electronics
• General Purpose Low Voltage Applications
Typical Circuit
Figure 1. Threshold Detector
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2004–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
LMV7291
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Absolute Maximum Ratings (1)(2)
ESD Tolerance 2KV (3)
200V (4)
VIN Differential ±Supply Voltage
Supply Voltage (V+- V−) 5.5V
Voltage at Input/Output pins V++0.1V, V−−0.1V
Soldering Information
Infrared or Convection (20 sec.) 235°C
Wave Soldering (10 sec.) 260°C
Storage Temperature Range −65°C to +150°C
Junction Temperature (5) +150°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
(3) Human body model, 1.5kΩin series with 100pF.
(4) Machine Model, 0Ωin series with 200pF.
(5) Typical values represent the most likely parametric norm.
Operating Ratings (1)
Operating Temperature Range (2) −40°C to +85°C
Package Thermal Resistance (2)
SC70 265°C/W
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX),θJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/θJA. All numbers apply for packages soldered directly into a PC board.
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1.8V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 1.8V, V−= 0V. Boldface limits apply at the temperature
extremes. (1)
Symbol Parameter Condition Min(2) Typ(3) Max(2) Units
VOS Input Offset Voltage 0.3 4 mV
6
TC VOS Input Offset Temperature Drift VCM = 0.9V (4) 10 uV/C
IBInput Bias Current 10 nA
IOS Input Offset Current 200 pA
ISSupply Current LMV7291 9 12 µA
14
ISC Output Short Circuit Current Sourcing, VO= 0.9V 3.5 6 mA
Sinking, VO= 0.9V 4 6
VOH Output Voltage High IO= 0.5mA 1.7 1.74 V
IO= 1.5mA 1.58 1.63
VOL Output Voltage Low IO=−0.5mA 52 70 mV
IO=−1.5mA 166 220
VCM Input Common Mode Voltage Range CMRR > 45 dB 1.9 V
−0.1 V
CMRR Common Mode Rejection Ratio 0 < VCM < 1.8V 47 78 dB
PSRR Power Supply Rejection Ratio V+= 1.8V to 5V 55 80 dB
ILEAKAGE Output Leakage Current VO= 1.8V 2 pA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ> TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
(4) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
1.8V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 1.8V, V−= 0V, VCM = 0.5V, VO= V+/2 and RL> 1MΩto V−.
Boldface limits apply at the temperature extremes. (1)
Symbol Parameter Condition Min(2) Typ(3) Max(2) Units
tPHL Propagation Delay Input Overdrive = 20mV 880 ns
(High to Low) Load = 50pF//5kΩ
Input Overdrive = 50mV 570 ns
Load = 50pF//5kΩ
tPLH Propagation Delay Input Overdrive = 20mV 1100 ns
(Low to High) Load = 50pF//5kΩ
Input Overdrive = 50mV 800 ns
Load = 50pF//5kΩ
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ> TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
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2.7V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7V, V−= 0V. Boldface limits apply at the temperature
extremes. (1)
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
VOS Input Offset Voltage 0.3 4 mV
6
TC VOS Input Offset Temperature Drift VCM = 1.35V (4) 10 µV/C
IBInput Bias Current 10 nA
IOS Input offset Current 200 pA
ISSupply Current LMV7291 9 13 µA
15
ISC Output Short Circuit Current Sourcing, VO= 1.35V 12 15 mA
Sinking, VO= 1.35V 12 15
VOH Output Voltage High IO= 0.5mA 2.63 2.66 V
IO= 2.0mA 2.48 2.55
VOL Output Voltage Low IO=−0.5mA 50 70 mV
IO=−2mA 155 220
VCM Input Common Voltage Range CMRR > 45dB 2.8 V
−0.1 V
CMRR Common Mode Rejection Ratio 0 < VCM < 2.7V 47 78 dB
PSRR Power Supply Rejection Ratio V+= 1.8V to 5V 55 80 dB
ILEAKAGE Output Leakage Current VO= 2.7V 2 pA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ> TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
(4) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
2.7V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 2.7V, V−= 0V, VCM = 0.5V, VO= V+/2 and RL> 1MΩto V−.
Boldface limits apply at the temperature extremes. (1)
Symbol Parameter Condition Min(2) Typ(3) Max(2) Units
tPHL Propagation Delay Input Overdrive = 20mV 1200 ns
(High to Low) Load = 50pF//5kΩ
Input Overdrive = 50mV 810 ns
Load = 50pF//5kΩ
tPLH Propagation Delay Input Overdrive = 20mV 1300 ns
(Low to High) Load = 50pF//5kΩ
Input Overdrive = 50mV 860 ns
Load = 50pF//5kΩ
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ> TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
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5V Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5V, V−= 0V. Boldface limits apply at the temperature
extremes. (1)
Symbol Parameter Conditions Min(2) Typ(3) Max(2) Units
VOS Input Offset Voltage 0.3 4 mV
6
TC VOS Input Offset Temperature Drift VCM = 2.5V (4) 10 µV/C
IBInput Bias Current 10 nA
IOS Input Offset Current 200 pA
ISSupply Current LMV7291 10 14 µA
16
ISC Output Short Circuit Current Sourcing, VO= 2.5V 28 34 mA
Sinking, VO= 2.5V 28 34
VOH Output Voltage High IO= 0.5mA 4.93 4.96 V
IO= 4.0mA 4.70 4.77
VOL Output Voltage Low IO=−0.5mA 27 70 mV
IO=−4.0mA 225 300
VCM Input Common Voltage Range CMRR > 45dB 5.1 V
−0.1
CMRR Common Mode Rejection Ratio 0 < VCM < 5.0V 47 78 dB
PSRR Power Supply Rejection Ratio V+= 1.8V to 5V 55 80 dB
ILEAKAGE Output Leakage Current VO= 5V 2 pA
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ> TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
(4) Offset Voltage average drift determined by dividing the change in VOS at temperature extremes into the total temperature change.
5.0V AC Electrical Characteristics
Unless otherwise specified, all limits ensured for TJ= 25°C, V+= 5.0V, V−= 0V, VCM = 0.5V, VO= V+/2 and RL> 1MΩto V−.
Boldface limits apply at the temperature extremes. (1)
Symbol Parameter Condition Min(2) Typ(3) Max(2) Units
tPHL Propagation Delay Input Overdrive = 20mV 2100 ns
(High to Low) Load = 50pF//5kΩ
Input Overdrive = 50mV 1380 ns
Load = 50pF//5kΩ
tPLH Propagation Delay Input Overdrive = 20mV 1800 ns
(Low to High) Load = 50pF//5kΩ
Input Overdrive = 50mV 1100 ns
Load = 50pF//5kΩ
(1) Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ= TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self heating where TJ> TA. Absolute Maximum Ratings indicate junction temperature limits beyond
which the device may be permanently degraded, either mechanically or electrically.
(2) All limits are specified by testing or statistical analysis.
(3) Typical values represent the most likely parametric norm.
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1.5 2 2.5 3 3.5 4 4.5
VSUPPLY (V)
0
5
10
15
20
25
SUPPLY CURRENT (PA)
5
VOUT = HIGH
85°C
25°C
-40°C
1.8 2.44 3.08 3.72 4.36 5.0
5
6
7
8
9
10
SUPPLY CURRENT (PA)
SUPPLY VOLTAGE (V)
85°C
25°C
-40°C
85°C
-2.5 -2 -1 0 1 2 2.5
-800
-400
0
400
800
VOS (PV)
VCM (V)
VSUPPLY = ±2.5V
85°C
-40°C
25°C
1.8 2.44 3.08 3.72 4.36 5.0
0
10
20
30
40
SHORT CIRCUIT OUTPUT CURRENT (mA)
SUPPLY VOLTAGE (V)
SOURCE
SINK
-0.9 -0.7 -0.5 -0.3 -0.1 0.1 0.3 0.5 0.7 0.9
-800
-400
0
400
800
VOS (PV)
VCM (V)
VSUPPLY = ±0.9V
25°C
85°C
-40°C
-1.35 -0.9 -0.45 0 0.45 0.9 1.35
-800
-400
0
400
800
VOS (PV)
VCM (V)
VSUPPLY = ±1.35V
85°C
-40°C
25°C
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Typical Performance Characteristics
(TA= 25°C, Unless otherwise specified).
VOS VOS
vs. vs.
VCM VCM
Figure 3. Figure 4.
VOS Short Circuit
vs. vs.
VCM Supply Voltage
Figure 5. Figure 6.
Supply Current Supply Current
vs. vs.
Supply Voltage Supply Voltage
Figure 7. Figure 8.
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00.5 1 1.5 2 2.5 3 3.5 4
ISINK (mA)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
VOUT - V- (V)
VSUPPLY = 1.8V
85°C
25°C
-40°C
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
V+ - VOUT (V)
ISOURCE (mA)
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45 VSUPPLY = 2.7V
85°C
25°C
-40°
00.5 1 1.5 2 2.5 3 3.5 4
ISOURCE (mA)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
V+ - VOUT (V)
VSUPPLY = 1.8V
85°C
25°C
-40°C
1.8 2.3 2.8 3.3 3.8 4.3 4.8
VSUPPLY (V)
0
100
200
300
400
500
600
VOUT - V- (mV)
ISINK
4mA
2mA 1.5mA
0.5mA
1.5 2 2.5 3 3.5 4 4.5
VSUPPLY (V)
0
5
10
15
20
25
SUPPLY CURRENT (PA)
5
VOUT = LOW
85°C
25°C
-40°C
1.8 2.3 2.8 3.3 3.8 4.3 4.8
VSUPPLY (V)
0
100
200
300
400
500
600
V+ - VOUT (mV)
ISOURCE
4mA
2mA
1.5mA
0.5mA
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Typical Performance Characteristics (continued)
(TA= 25°C, Unless otherwise specified).
Supply Current Output Positive Swing
vs. vs.
Supply Voltage VSUPPLY
Figure 9. Figure 10.
Output Negative Swing Output Positive Swing
vs. vs.
VSUPPLY ISOURCE
Figure 11. Figure 12.
Output Negative Swing Output Positive Swing
vs. vs.
ISINK ISOURCE
Figure 13. Figure 14.
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INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 1.8 V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 2.7V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
00.5 1 1.5 2 2.5 3 3.5 4
ISOURCE (mA)
0
0.1
0.2
0.3
0.4
V+ - VOUT (V)
85°C
25°C
-40°C
VSUPPLY = 5V
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV 20mV
VCC = 1.8V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
0 0.5 1 1.5 2 2.5 3 3.5 4
0
0.5
VOUT - V- (V)
ISINK (mA)
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45 85°C
25°C
-40°C
VSUPPLY = 2.7V
00.5 1 1.5 2 2.5 3 3.5 4
ISINK (mA)
0
0.1
0.2
0.3
0.4
VOUT - V- (V)
85°C
25°C
-40°C
VSUPPLY = 5V
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Typical Performance Characteristics (continued)
(TA= 25°C, Unless otherwise specified).
Output Negative Swing Output Negative Swing
vs. vs.
ISINK ISINK
Figure 15. Figure 16.
Output Positive Swing
vs.
ISOURCE Propagation Delay (tPLH)
Figure 17. Figure 18.
Propagation Delay (tPHL) Propagation Delay (tPLH)
Figure 19. Figure 20.
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110 100 1000
OVERDRIVE (mV)
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
tPLH (PS)
VS = 5V
VS = 2.7V
VS = 1.8V
010 100 1000
OVERDRIVE (mV)
0
1
2
3
4
5
6
7
8
tPHL (PS)
VS = 1.8V
VS = 2.7V
VS = 5V
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 5.0 V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 2.7 V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
INPUT VOLTAGE
(mV) OUTPUT VOLTAGE
(V)
0 500 1000 1500 2000 2500 3000
-100
0
100
0
1
2
3
4
5
TIME (ns)
50mV
20mV
VCC = 5.0V
TEMP = 25°C
LOAD = 5k:50pF
OVERDRIVE
||
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Typical Performance Characteristics (continued)
(TA= 25°C, Unless otherwise specified).
Propagation Delay (tPHL) Propagation Delay (tPLH)
Figure 21. Figure 22.
tPHL
vs.
Propagation Delay (tPHL) Overdrive
Figure 23. Figure 24.
tPLH
vs.
Overdrive
Figure 25.
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VOLTS
VREF
VO
TIME
VIN
V+
VREF
VIN
VO
-
+
V-
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SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
APPLICATION NOTES
BASIC COMPARATOR
A comparator is often used to convert an analog signal to a digital signal. As shown in Figure 26, the comparator
compares an input voltage (VIN) to a reference voltage (VREF). If VIN is less than VREF, the output (VO) is low.
However, if VIN is greater than VREF, the output voltage (VO) is high.
Figure 26. LMV7291 Basic Comparator
RAIL-TO-RAIL INPUT STAGE
The LMV7291 has an input common mode voltage range (VCM) of −0.1V below the V−to 0.1V above V+. This is
achieved by using paralleled PNP and NPN differential input pairs. When the VCM is near V+, the NPN pair is on
and the PNP pair is off. When the VCM is near V−, the NPN pair is off and the PNP pair is on. The crossover point
between the NPN and PNP input stages is around 950mV from V+. Since each input stage has its own offset
voltage (VOS), the VOS of the comparator becomes a function of the VCM. See Figure 3,Figure 4, and Figure 5 in
Typical Performance Characteristics. In application design, it is recommended to keep the VCM away from the
crossover point to avoid problems. The wide input voltage range makes LMV7291 ideal in power supply
monitoring circuits, where the comparators are used to sense signals close to gnd and power supplies.
OUTPUT STAGE
The LMV7291 has a push-pull output stage. This output stage keeps the total system power consumption to the
absolute minimum. The only current consumed is the low supply current and the current going directly into the
load. When output switches, both PMOS and NMOS at the output stage are on at the same time for a very short
time. This allows current to flow directly between V+and V−through output transistors. The result is a short spike
of current (shoot-through current) drawn from the supply and glitches in the supply voltages. The glitches can
spread to other parts of the board as noise. To prevent the glitches in supply lines, power supply bypass
capacitors must be installed. See CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR
APPLICATIONS for details.
HYSTERESIS
It is a standard procedure to use hysteresis (positive feedback) around a comparator, to prevent oscillation, and
to avoid excessive noise on the output because the comparator is a good amplifier of its own noise.
Inverting Comparator with Hysteresis
The inverting comparator with hysteresis requires a three resistor network that are referenced to the supply
voltage VCC of the comparator (Figure 27). When VIN at the inverting input is less than VA, the voltage at the non-
inverting node of the comparator (VIN < VA), the output voltage is high (for simplicity assume VOswitches as high
as VCC). The three network resistors can be represented as R1||R3in series with R2. The lower input trip voltage
VA1 is defined as
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VA2 = VCC (R2||R3)
R1 + (R2||R3)
VA1 = VCC R2
(R1||R3) + R2
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(1)
When VIN is greater than VA(VIN > VA), the output voltage is low and very close to ground. In this case the three
network resistors can be presented as R2//R3in series with R1. The upper trip voltage VA2 is defined as
(2)
The total hysteresis provided by the network is defined as
ΔVA= VA1 - VA2 (3)
A good typical value of ΔVAwould be in the range of 5 to 50 mV. This is easily obtained by choosing R3as 1000
to 100 times (R1||R2) for 5V operation, or as 300 to 30 times (R1||R2) for 1.8V operation.
Figure 27. Inverting Comparator with Hysteresis
Non-Inverting Comparator with Hysteresis
A non-inverting comparator with hysteresis requires a two resistor network, and a voltage reference (VREF) at the
inverting input (Figure 28). When VIN is low, the output is also low. For the output to switch from low to high, VIN
must rise up to VIN1, where VIN1 is calculated by
(4)
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When VIN is high, the output is also high. To make the comparator switch back to its low state, VIN must equal
VREF before VAwill again equal VREF. VIN can be calculated by:
(5)
The hysteresis of this circuit is the difference between VIN1 and VIN2.
ΔVIN = VCCR1/R2(6)
Figure 28. Non-Inverting Comparator with Hysteresis
CIRCUIT TECHNIQUES FOR AVOIDING OSCILLATIONS IN COMPARATOR APPLICATIONS
Feedback to almost any pin of a comparator can result in oscillation. In addition, when the input signal is a slow
voltage ramp or sine wave, the comparator may also burst into oscillation near the crossing point. To avoid
oscillation or instability, PCB layout should be engineered thoughtfully. Several precautions are recommended:
1. Power supply bypassing is critical, and will improve stability and transient response. Resistance and
inductance from power supply wires and board traces increase power supply line impedance. When supply
current changes, the power supply line will move due to its impedance. Large enough supply line shift will
cause the comparator to mis-operate. To avoid problems, a small bypass capacitor, such as 0.1uF ceramic,
should be placed immediately adjacent to the supply pins. An additional 6.8μF or greater tantalum capacitor
should be placed at the point where the power supply for the comparator is introduced onto the board. These
capacitors act as an energy reservoir and keep the supply impedance low. In dual supply application, a
0.1μF capacitor is recommended to be placed across V+and V−pins.
2. Keep all leads short to reduce stray capacitance and lead inductance. It will also minimize any unwanted
coupling from any high-level signals (such as the output). The comparators can easily oscillate if the output
lead is inadvertently allowed to capacitively couple to the inputs via stray capacitance. This shows up only
during the output voltage transition intervals as the comparator changes states. Try to avoid a long loop
which could act as an inductor (coil).
3. It is a good practice to use an unbroken ground plane on a printed circuit board to provide all components
with a low inductive ground connection. Make sure ground paths are low-impedance where heavier currents
are flowing to avoid ground level shift. Preferably there should be a ground plane under the component.
4. The output trace should be routed away from inputs. The ground plane should extend between the output
and inputs to act as a guard.
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 13
Product Folder Links: LMV7291
VIN +
-
+VCC
R1
1M:
VOUT
+
-C1
10PF
-VCC
VIN +
-
+VCC
R2
1 M:
C1
10 PF
VOUT
-
+
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
5. When the signal source is applied through a resistive network to one input of the comparator, it is usually
advantageous to connect the other input with a resistor with the same value, for both DC and AC
consideration. Input traces should be laid out symmetrically if possible.
6. All pins of any unused comparators should be tied to the negative supply.
Typical Applications
POSITIVE PEAK DETECTOR
A positive peak detect circuit is basically a comparator operated in a unity gain follower configuration, with a
capacitor as a load to maintain the highest voltage. A diode is added at the output to prevent the capacitor from
discharging through the output, and a 1MΩresistor added in parallel to the capacitor to provide a high
impedance discharge path. When the input VIN increases, the inverting input of the comparator follows it, thus
charging the capacitor. When it decreases, the cap discharges through the 1MΩresistor. The decay time can be
modified by changing the resistor. The output should be accessed through a follower circuit to prevent loading.
Figure 29. Positive Peak Detector
NEGATIVE PEAK DETECTOR
For the negative detector, the output transistor of the comparator acts as a low impedance current sink. Since
there is no pull-up resistor, the only discharge path will be the 1MΩresistor and any load impedance used.
Decay time is changed by varying the 1MΩresistor.
Figure 30. Negative Peak Detector
SQUARE WAVE GENERATOR
A typical application for a comparator is as a square wave oscillator. The circuit below generates a square wave
whose period is set by the RC time constant of the capacitor C1and resistor R4. The maximum frequency is
limited by the large signal propagation delay of the comparator, and by the capacitive loading at the output,
which limits the output slew rate.
14 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
VA2 = VCC (R2||R3)
R1 + (R2||R3)
VA1 = VCC.R2
R2 + R1||R3
C1 = 750 pF
R4 = 100 k:
VO
R2 = 100 k:
R3 = 100 k:
R1 = 100 k:VA
+
-
VC
V+
0f |10 kHz
V+
LMV7291
www.ti.com
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
Figure 31. Squarewave Oscillator
To analyze the circuit, consider it when the output is high. That implies that the inverted input (VC) is lower than
the non-inverting input (VA). This causes the C1to get charged through R4, and the voltage VCincreases till it is
equal to the non-inverting input. The value of VAat this point is
(7)
If R1= R2= R3then VA1 = 2VCC/3
At this point the comparator switches pulling down the output to the negative rail. The value of VAat this point is
(8)
If R1= R2= R3then VA2 = VCC/3
The capacitor C1now discharges through R4, and the voltage VCdecreases till it is equal to VA2, at which point
the comparator switches again, bringing it back to the initial stage. The time period is equal to twice the time it
takes to discharge C1from 2VCC/3 to VCC/3, which is given by R4C1.ln2. Hence the formula for the frequency is:
F = 1/(2.R4.C1.ln2)
Copyright © 2004–2013, Texas Instruments Incorporated Submit Documentation Feedback 15
Product Folder Links: LMV7291
LMV7291
SNOSA86E –FEBRUARY 2004–REVISED MARCH 2013
www.ti.com
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 15
16 Submit Documentation Feedback Copyright © 2004–2013, Texas Instruments Incorporated
Product Folder Links: LMV7291
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMV7291MG NRND SC70 DCK 5 1000 TBD Call TI Call TI -40 to 85 C36
LMV7291MG/NOPB ACTIVE SC70 DCK 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C36
LMV7291MGX/NOPB ACTIVE SC70 DCK 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 C36
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 1-Nov-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMV7291MG SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7291MG/NOPB SC70 DCK 5 1000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
LMV7291MGX/NOPB SC70 DCK 5 3000 178.0 8.4 2.25 2.45 1.2 4.0 8.0 Q3
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMV7291MG SC70 DCK 5 1000 210.0 185.0 35.0
LMV7291MG/NOPB SC70 DCK 5 1000 210.0 185.0 35.0
LMV7291MGX/NOPB SC70 DCK 5 3000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 23-Sep-2013
Pack Materials-Page 2
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