IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX5972A provides a complete interface for a
powered device (PD) to comply with the IEEE® 802.3af/
at standard in a power-over-Ethernet (PoE) system. The
MAX5972A provides the PD with a detection signature,
classification signature, and an integrated isolation
power switch with inrush current control. During the
inrush period, the MAX5972A limits the current to less
than 180mA before switching to the higher current limit
(720mA to 880mA) when the isolation power MOSFET
is fully enhanced. The device features an input UVLO
with wide hysteresis and long deglitch time to compen-
sate for twisted-pair cable resistive drop and to assure
glitch-free transition during power-on/-off conditions. The
MAX5972A can withstand up to 100V at the input.
The MAX5972A supports a 2-event classification method
as specified in the IEEE 802.3at standard and provides a
signal to indicate when probed by Type 2 power-sourcing
equipment (PSE). The device detects the presence of
a wall adapter power-source connection and allows a
smooth switch over from the PoE power source to the
wall power adapter.
The MAX5972A also provides a power-good (PG) signal,
two-step current limit and foldback, overtemperature
protection, and di/dt limit.
The MAX5972A is available in a 16-pin, 5mm x 5mm,
TQFN power package. This device is rated over the
-40NC to +85NC extended temperature range.
Applications
IEEE 802.3af/at-Powered Devices
IP Phones, Wireless Access Nodes, IP Security
Cameras
WiMAXK Base Station
Features
S IEEE 802.3af/at Compliant
S 2-Event Classification or an External Wall Adapter
Indicator Output
S Simplified Wall Adapter Interface
S PoE Classification 0 to 5
S 100V Input Absolute Maximum Rating
S Inrush Current Limit of 180mA Maximum
S Current Limit During Normal Operation Between
720mA and 880mA
S Current Limit and Foldback
S Legacy UVLO at 36V
S Overtemperature Protection
S Thermally Enhanced, 5mm x 5mm, 16-Pin TQFN
19-4924; Rev 1; 2/10
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Ordering Information
Pin Configuration
WiMAX is a trademark of WiMAX Forum.
IEEE is a registered service mark of the Institute of Electrical
and Electronics Engineers, Inc.
TQFN
(5mm × 5mm)
TOP VIEW
*EP = EXPOSED PAD. CONNECT TO VSS.
+
3
4
2
1
10
9
11
VSS
RTN
VSS
EP*
N.C.
N.C.
N.C.
5 6
VDD
8
16 15 13
DET
I.C.
CLS
2EC
PG
WAD
MAX5972A
RTN N.C.
7
14
N.C. 12
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-
PACKAGE
SLEEP
MODE
MAX5972AETE+ -40NC to +85NC16 TQFN-EP* ––
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
2 ______________________________________________________________________________________
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
VDD to VSS ..........................................................-0.3V to +100V
DET, RTN, WAD, PG, 2EC to VSS .......................-0.3V to +100V
CLS to VSS ..............................................................-0.3V to +6V
Maximum Current on CLS (100ms maximum) .................100mA
Continuous Power Dissipation (TA = +70NC) (Note 1)
16-Pin TQFN (derate 28.6mW/NC above +70NC)
Multilayer Board .....................................................2285.7mW
Package Thermal Resistance (Note 2)
BJA ...............................................................................35NC/W
BJC .............................................................................2.7NC/W
Operating Temperature Range .......................... -40NC to +85NC
Maximum Junction Temperature .....................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) .............................. +300NC
ELECTRICAL CHARACTERISTICS
(VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS,
unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3)
ABSOLUTE MAXIMUM RATINGS
Note 1: Maximum power dissipation is obtained using JEDEC JESD51-5 and JESD51-7 specifications.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DETECTION MODE
Input Offset Current IOFFSET VIN = 1.4V to 10.1V (Note 4) 10 FA
Effective Differential Input
Resistance dR VIN = 1.4V up to 10.1V with 1V step,
VDD = RTN = WAD = PG = 2EC (Note 5) 23.95 25.00 25.50 kI
CLASSIFICATION MODE
Classification Disable
Threshold VTH,CLS VIN rising (Note 6) 22.0 22.8 23.6 V
Classification Stability Time 0.2 ms
Classification Current ICLASS
VIN = 12.5V to
20.5V, VDD =
RTN = WAD =
PG = 2EC
Class 0, RCLS = 615I0 3.96
mA
Class 1, RCLS = 117I9.12 11.88
Class 2, RCLS = 66.5I17.2 19.8
Class 3, RCLS = 43.7I26.3 29.7
Class 4, RCLS = 30.9I36.4 43.6
Class 5, RCLS = 21.3I52.7 63.3
TYPE 2 (802.3at) CLASSIFICATION MODE
Mark Event Threshold VTHM VIN falling 10.1 10.7 11.6 V
Hysteresis on Mark Event
Threshold 0.84 V
Mark Event Current IMARK VIN falling to enter mark event, 5.2V P VIN
P 10.1V 0.25 0.85 mA
Reset Event Threshold VTHR VIN falling 2.8 4 5.2 V
POWER MODE
VIN Supply Voltage Range 60 V
VIN Supply Current IQ0.27 0.55 mA
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VIN = (VDD - VSS) = 48V, RDET = 24.9kω, RCLS = 615ω. RTN, WAD, PG, and 2EC unconnected, all voltages are referenced to VSS,
unless otherwise noted. TA = TJ = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Note 3)
Note 3: This device is 100% production tested at TA = +25NC. Limits over temperature are guaranteed by design.
Note 4: The input offset current is illustrated in Figure 1.
Note 5: Effective differential input resistance is defined as the differential resistance between VDD and VSS. See Figure 1.
Note 6: Classification current is turned off whenever the device is in power mode.
Note 7: UVLO hysteresis is guaranteed by design, not production tested.
Note 8: A 20V glitch on input voltage that takes VDD below VON shorter than or equal to tOFF_DLY does not cause the MAX5972A
to exit power-on mode.
Note 9: In power mode, current-limit foldback is used to reduce the power dissipation in the isolation MOSFET during an overload
condition across VDD and RTN.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VIN Turn-On Voltage VON VIN rising 34.3 35.4 36.6 V
VIN Turn-Off Voltage VOFF VIN falling 30 V
VIN Turn-On/-Off Hysteresis VHYST_UVLO (Note 7) 4.2 V
VIN Deglitch Time tOFF_DLY VIN falling from 40V to 20V (Note 8) 30 120 Fs
Inrush to Operating Mode
Delay tDELAY tDELAY = minimum PG current pulse width
after entering into power mode 80 96 112 ms
Isolation Power MOSFET
On-Resistance RON_ISO IRTN = 600mA
TJ = +25NC0.7 1.1
ITJ = +85NC0.9 1.5
TJ = +125NC1.15
RTN Leakage Current IRTN_LKG VRTN = 12.5V to 30V 10 FA
CURRENT LIMIT
Inrush Current Limit IINRUSH During initial turn-on period,
VRTN = 1.5V 90 135 180 mA
Current Limit During Normal
Operation ILIM After inrush completed,
VRTN = 1V 720 800 880 mA
Foldback Threshold VRTN (Note 9) 13 16.5 V
LOGIC
WAD Detection Threshold VWAD-REF VWAD rising, VIN = 14V to 48V (referenced
to RTN) 8 9 10
V
WAD Detection Threshold
Hysteresis
VWAD falling, VRTN = 0V, VSS
unconnected 0.725
WAD Input Current IWAD-LKG VWAD = 10V (referenced to RTN) 3.5 FA
2EC Sink Current V2EC = 3.5V (referenced to RTN), VSS
unconnected 1 1.5 2.25 mA
2EC Off-Leakage Current V2EC = 48V 1FA
PG Sink Current VRTN = 1.5V, VPG = 0.8V, during inrush
period 125 230 375 FA
PG Off-Leakage Current VPG = 60V 1 FA
THERMAL SHUTDOWN
Thermal-Shutdown Threshold TSD TJ rising +140 NC
Thermal-Shutdown Hysteresis TJ falling +28 NC
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
4 ______________________________________________________________________________________
Figure 1. Effective Differential Input Resistance/Offset Current
Typical Operating Characteristics
(VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω, RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.)
IIN
IINi + 1
IINi
IOFFSET
dRi
1VVINi VINi + 1
IOFFSET = IINi - VINi
dRi
dRi = (VINi + 1 - VINi) = 1V
(IINi + 1 - IINi) (IINi + 1 - IINi)
VIN
DETECTION CURRENT
vs. INPUT VOLTAGE
MAX5972A toc01
VIN (V)
IIN (mA)
8642
0.1
0.2
0.3
0.4
0.5
0
0 10
IIN = IVDD + IDET
RDET = 24.9kI
RTN = 2EC = PG = WAD = VDD
-40°C P TA P +85NC
SIGNATURE RESISTANCE
vs. INPUT VOLTAGE
R
SIGNATURE
(k
I
)
8642
24.5
25.0
25.5
26.0
24.0
0 10
MAX5972A toc02
VIN (V)
IIN = IVDD + IDET
RDET = 24.9kI
RTN = 2EC = PG = WAD = VDD
TA = -40NC
TA = +85NC
TA = +25NC
INPUT OFFSET CURRENT
vs. INPUT VOLTAGE
INPUT OFFSET CURRENT (FA)
8642
-2
0
2
4
-4
0 10
MAX5972A toc03
VIN (V)
TA = +85NC
TA = -40NC
TA = +25NC
CLASSIFICATION CURRENT vs.
INPUT VOLTAGE
MAX5972A toc04
VIN (V)
IIN (mA)
252015105
10
20
30
40
50
60
70
0
0 30
CLASS 5
CLASS 4
CLASS 3
CLASS 2
CLASS 1
CLASS 0
CLASSIFICATION SETTLING TIME
MAX5972A toc05
VIN
10V/div
0V
IIN
0A
200mA/div
0V
VCLS
1V/div
100Fs/div
RCLS = 30.9I
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
_______________________________________________________________________________________ 5
Typical Operating Characteristics (continued)
(VIN = (VDD - VSS) = 54V, RDET = 24.9kω, RCLS = 615ω, RTN, WAD, PG, and 2EC unconnected; all voltages are referenced to VSS.)
2EC SINK CURRENT vs. 2EC VOLTAGE
V2EC (V)
I2EC (mA)
5040302010
0.4
0.8
1.2
1.6
2.0
0
0 60
MAX5972A toc06
VSS UNCONNECTED
V2EC REFERENCED TO RTN
VWAD = 14V
TA = -40NC
TA = +85NC
TA = +25NC
PG SINK CURRENT vs. PG VOLTAGE
VPG (V)
IPG (FA)
5040302010
100
150
200
250
300
50
0 60
MAX5972A toc07
TA = -40NC
TA = +85NC
TA = +25NC
INRUSH CURRENT LIMIT
vs. RTN VOLTAGE
MAX5972A toc08
VRTN (V)
INRUSH CURRENT LIMIT (mA)
5040302010
70
90
110
130
150
50
0 60
NORMAL OPERATION CURRENT LIMIT
vs. RTN VOLTAGE
MAX5972A toc09
VRTN (V)
CURRENT LIMIT (mA)
504010 20 30
200
300
400
500
600
700
800
900
100
0 60
INRUSH CONTROL WAVEFORM WITH
TYPE 2 CLASSIFICATION
MAX5972A toc10
0V
0V
0A
0V
VRTN
50V/div
IRTN
100mA/div
VDD
50V/div
V2EC
50V/div
200µs/div
USING TYPICAL APPLICATION CIRCUIT
2EC PULLED UP TO VDD WITH 10kI
ENTERING POWER MODE WITH
TYPE 2 CLASSIFICATION
MAX5972A toc11
VPG
10V/div0V
0V
0V
0A
0V
VRTN
50V/div
IRTN
200mA/div
VDD
50V/div
20ms/div
V2EC
40V/div
USING TYPICAL APPLICATION CIRCUIT
2EC PULLED UP TO VDD WITH 10kI
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
6 ______________________________________________________________________________________
Pin Description
PIN NAME FUNCTION
1, 13–16 N.C. No Connection. Not internally connected.
2 VDD Positive Supply Input. Connect a 68nF (min) bypass capacitor between VDD and VSS.
3 DET Detection Resistor Input. Connect a signature resistor (RDET = 24.9kI) from DET to VDD.
4 I.C. Internally Connected. Leave unconnected.
5, 6 VSS Negative Supply Input. VSS connects to the source of the integrated isolation n-channel power
MOSFET.
7, 8 RTN
Drain of Isolation MOSFET. RTN connects to the drain of the integrated isolation n-channel power
MOSFET. Connect RTN to the downstream DC-DC converter ground as shown in the Typical
Application Circuit.
9 WAD
Wall Power Adapter Detector Input. Wall adapter detection is enabled the moment VDD - VSS crosses
the mark event threshold. Detection occurs when the voltage from WAD to RTN is greater than 9V.
When a wall power adapter is present, the isolation n-channel power MOSFET turns off, 2EC current
sink turns on. Connect WAD directly to RTN when the wall power adapter or other auxiliary power
source is not used.
10 PG
Open-Drain Power-Good Indicator Output. PG sinks 230FA to disable the downstream DC-DC con-
verter while turning on the hot-swap MOSFET switch. PG current sink is disabled during detection,
classification, and in the steady-state power mode. The PG current sink is turned on to disable the
downstream DC-DC converter when the device is in sleep mode.
11 2EC
Active-Low 2-Event Classification Detect or Wall Adapter Detect Output. A 1.5mA current sink is
enabled at 2EC when a Type 2 PSE or a wall adapter is detected. When powered by a Type 2 PSE,
the 2EC current sink is enabled after the isolation MOSFET is fully on until VIN drops below the UVLO
threshold. 2EC is latched when powered by a Type 2 PSE until VIN drops below the reset threshold.
2EC also asserts when a wall adapter supply, typically greater than 9V, is applied between WAD and
RTN. 2EC is not latched if asserted by WAD.
12 CLS
Classification Resistor Input. Connect a resistor (RCLS) from CLS to VSS to set the desired classification
current. See the classification current specifications in the Electrical Characteristics table to find the
resistor value for a particular PD classification.
–– EP
Exposed Pad. Do not use EP as an electrical connection to VSS. EP is internally connected to VSS
through a resistive path and must be connected to VSS externally. To optimize power dissipation, sol-
der the exposed pad to a large copper power plane.
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
_______________________________________________________________________________________ 7
Simplified Block Diagram
1.5mA
46µA
VDD
EN CLS
2EC
VDD
5V
D Q
Q
SET
CLR
DET
VSS
5V REGULATOR
THERMAL
SHUTDOWN
Q
R
S
VDD
VDD
VDD
WAD
RTN
VON/VOFF
VDD
D Q
Q
SET
CLR
9V
230µA
PG
CLASSIFICATION
ISWITCH
K x ISWITCH
ISOLATION
SWITCH
S
MUX
I0
I1
1/K
MAX5972A
tDELAY
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
8 ______________________________________________________________________________________
Typical Operating Circuit
Detailed Description
Operating Modes
Depending on the input voltage (VIN = VDD - VSS), the
MAX5972A operates in four different modes: PD detec-
tion, PD classification, mark event, and PD power. The
device enters PD detection mode when the input voltage
is between 1.4V and 10.1V. The device enters PD clas-
sification mode when the input voltage is between 12.6V
and 20V. The device enters PD power mode once the
input voltage exceeds VON.
Detection Mode (1.4V ≤ VIN ≤ 10.1V)
In detection mode, the power source equipment (PSE)
applies two voltages on VIN in the range of 1.4V to 10.1V
(1V step minimum) and then records the current measure-
ments at the two points. The PSE then computes DV/DI
to ensure the presence of the 24.9kω signature resistor.
Connect the signature resistor (RDET) from VDD to DET for
proper signature detection. The MAX5972A pulls DET low
in detection mode. DET goes high impedance when the
input voltage exceeds 12.5V. In detection mode, most of
the MAX5972A internal circuitry is off and the offset cur-
rent is less than 10µA.
If the voltage applied to the PD is reversed, install pro-
tection diodes at the input terminal to prevent internal
damage to the MAX5972A (see the Typical Application
Circuit). Since the PSE uses a slope technique (DV/DI) to
calculate the signature resistance, the DC offset due to
the protection diodes is subtracted and does not affect
the detection process.
Classification Mode (12.6V ≤ VIN ≤ 20V)
In the classification mode, the PSE classifies the PD
based on the power consumption required by the PD. This
allows the PSE to efficiently manage power distribution.
Class 0 to 5 is defined as shown in Table 1. (The IEEE
802.3af/at standard defines only Class 0 to 4 and Class 5
for any special requirement.) An external resistor (RCLS)
connected from CLS to VSS sets the classification current.
2-EVENT
CLASSIFICATION
DETECTION
-54V
MAX5972A
VDD
RTN
WAD
PG
2EC/WAD
2EC
24V/48V
BATTERY
1.5mA
68nF
RJ-45
AND
BRIDGE
RECTIFIER
GND
SMAJ58A
RDET
24.9kI
RCLS
VSS
DET
CLS
ENABLE
DC-DC
CONVERTER
IN+
IN-
GND
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
_______________________________________________________________________________________ 9
Table 1. Setting Classification Current
*VIN is measured across the MAX5972A input VDD to VSS.
The PSE determines the class of a PD by applying
a voltage at the PD input and measuring the current
sourced out of the PSE. When the PSE applies a volt-
age between 12.6V and 20V, the MAX5972A exhibits a
current characteristic with a value shown in Table 1. The
PSE uses the classification current information to classify
the power requirement of the PD. The classification cur-
rent includes the current drawn by RCLS and the supply
current of the MAX5972A so the total current drawn by
the PD is within the IEEE 802.3af/at standard figures. The
classification current is turned off whenever the device is
in power mode.
2-Event Classification and Detection
During 2-event classification, a Type 2 PSE probes PD
for classification twice. In the first classification event, the
PSE presents an input voltage between 12.6V and 20.5V
and the MAX5972A presents the programmed load
ICLASS. The PSE then drops the probing voltage below
the mark event threshold of 10.1V and the MAX5972A
presents the mark current (IMARK). This sequence is
repeated one more time.
When the MAX5972A is powered by a Type 2 PSE, the
2-event identification output 2EC asserts low after the
internal isolation n-channel MOSFET is fully turned on.
2EC current sink is turned off when VDD goes below the
UVLO threshold (VOFF) and turns on when VDD goes
above the UVLO threshold (VON), unless VDD goes
below VTHR to reset the latched output of the Type 2
PSE detection flag.
Alternatively, the 2EC output also serves as a wall
adapter detection output when the MAX5972A is pow-
ered by an external wall power adapter. See the Wall
Power Adapter Detection and Operation section for more
information.
Power Mode (Wake Mode)
The MAX5972A enters power mode when VIN rises
above the undervoltage lockout threshold (VON). When
VIN rises above VON, the MAX5972A turns on the inter-
nal n-channel isolation MOSFET to connect VSS to RTN
with inrush current limit internally set to 135mA (typ). The
isolation MOSFET is fully turned on when the voltage at
RTN is near VSS and the inrush current is reduced below
the inrush limit. Once the isolation MOSFET is fully turned
on, the MAX5972A changes the current limit to 800mA.
The open-drain power-good output (PG) remains low for
a minimum of tDELAY until the power MOSFET fully turns
on to keep the downstream DC-DC converter disabled
during inrush.
Undervoltage Lockout
The MAX5972A operates up to a 60V supply voltage with
a turn-on UVLO threshold (VON) at 35.4V and a turn-off
UVLO threshold (VOFF) at 31V. When the input voltage is
above VON, the MAX5972A enters power mode and the
internal MOSFET is turned on. When the input voltage
goes below VOFF for more than tOFF_DLY, the MOSFET
turns off.
Power-Good Output
An open-drain output (PG) is used to allow disabling
downstream DC-DC converter until the n-channel isola-
tion MOSFET is fully turned on. PG is pulled low to VSS
for a period of tDELAY and until the internal isolation
MOSFET is fully turned on. The PG is also pulled low
during sleep mode and coming out of thermal shutdown.
Thermal-Shutdown Protection
The MAX5972A includes thermal protection from exces-
sive heating. If the junction temperature exceeds the
thermal-shutdown threshold of +140NC, the MAX5972A
CLASS
MAXIMUM
POWER USED
BY PD
(W)
RCLS
(I)
VIN*
(V)
CLASS CURRENT SEEN AT
VIN (mA)
IEEE 802.3at PD
CLASSIFICATION CURRENT
SPECIFICATION (mA)
MIN MAX MIN MAX
0 0.44 to 12.95 615 12.6 to 20 0 4 0 5
1 0.44 to 3.94 117 12.6 to 20 9 12 8 13
2 3.84 to 6.49 66.5 12.6 to 20 17 20 16 21
3 6.49 to 12.95 43.7 12.6 to 20 26 30 25 31
4 12.95 to 25.5 30.9 12.6 to 20 36 44 35 45
5 > 25.5 21.3 12.6 to 20 52 64 51 68
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
10 _____________________________________________________________________________________
turns off the internal power MOSFET and 2EC current
sink. When the junction temperature falls below +112NC,
the devices enter inrush mode and then return to power
mode. Inrush mode ensures the downstream DC-DC
converter is turned off as the internal power MOSFET is
turned on.
Wall Power Adapter Detection
and Operation
For applications where an auxiliary power source such
as a wall power adapter is used to power the PD,
the MAX5972A features wall power adapter detection.
The MAX5972A gives highest priority to the WAD and
smoothly switches the power supply to WAD when it is
detected. Once the input voltage (VDD - VSS) exceeds
the mark event threshold, the MAX5972A enables wall
adapter detection. The wall power adapter is connected
from WAD to RTN. The MAX5972A detects the wall
power adapter when the voltage from WAD to RTN is
greater than 9V. When a wall power adapter is detected,
the internal n-channel isolation MOSFET turns off, 2EC
current sink turns on, and classification current is dis-
abled if VIN is in the classification range.
Applications Information
Operation with 12V Adapter
Layout Procedure
Careful PCB layout is critical to achieve high efficiency
and low EMI. Follow these layout guidelines for optimum
performance:
1) Place the input capacitor, classification resistor, and
transient voltage suppressor as close as possible to
the MAX5972A.
2) Use large SMT component pads for power dissipat-
ing devices such as the MAX5972A and the external
diodes.
3) Use short and wide traces for high-power paths.
4) Use the MAX5972A evaluation kit layout as a refer-
ence.
5) Place enough vias in the pad for the EP of the
MAX5972A so that heat generated inside can be
effectively dissipated by the PCB copper. The rec-
ommended spacing for the vias is 1mm to 1.2mm
pitch. The thermal vias should be plated (1oz cop-
per) and have a small barrel diameter (0.3mm to
0.33mm).
Figure 2. Typical Configuration When Using a 12V Wall Power Adapter
68nF
2-EVENT
CLASSIFICATION
(ASSERTED ON)
ENABLE
DC-DC
CONVERTER
IN+
IN-
RJ-45
AND
BRIDGE
RECTIFIER
GND
GND
-54V
SMAJ58A
MAX5972A
RDET
24.9kI
RCLS
VDD
VSS RTN
WAD
PG
DET
CLS
2EC/WAD
2EC
12V
BATTERY
1.5mA
THIS CIRCUIT ACHIEVES
PROPER 2EC LOGIC WHEN
BATTERY IS < 12.5V
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
______________________________________________________________________________________ 11
Typical Application Circuit
68nF
ISOLATED 2-EVENT
CLASSIFICATION
OUTPUT
GND
VAC
VAC
GND
-54V
SMAJ58A
MAX5972A
24.9kI
43.7I
VDD
VSS RTN
WAD
PG
PG
DET
CLS
2EC/WAD
2EC
24/48V
BATTERY
1.5mA
RTN
MAX15000
ULVO/EN IN
VCC
UFLG
FB
COMP
CS
PG
CS
VCC
VCC
CS
RTN
ISOLATED +5.3V/2A
ISOLATED RTN
ISOLATED RTN
GND
RTN
GND 33kI
10kI
249I
22.1I
0.75I
1kI
619I8.2nF
330pF
649I
4.99kI1kI100pF
33nF
8.06I
2.49kI
1kI18.1kI
RTN
4.99kI
NDRV
GND
RT
51.5kI
1.37MI0.1µF
0.1µF 0.1µF
0.1µF
22µF
4.7µF
2.2nF
8.06kI
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
12 _____________________________________________________________________________________
Chip Information
PROCESS: BiCMOS
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
16 TQFN-EP T1655+4 21-0140
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
IEEE 802.3af/at-Compliant, Powered Device Interface
Controller with Integrated Power MOSFET
MAX5972A
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 13
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 8/09 Initial release —
1 2/10 Removed the MAX5972B from the data sheet. 1–13
