24AA32A/SMRVB - Microchip Technology, Inc.

 1999 Microchip Technology Inc. DS21162D-page 1

FEATURES

• Single supply with operation down to 1.8V

- Maximu m write cur rent 3 mA at 6.0V

- Stan dby curre nt 1 µA max at 1.8V

• 2-wire serial interface b us, I2C compatible

• 100 kHz (1.8V) and 400 kHz (5V) compatibility

• Self-timed ERASE and WRITE cycles

• Power on/off data protection circuitry

• Hardware write protect

• 1,000,000 Erase/Write cycles guaranteed

• 32 byte page or byte write modes available

• Schmitt trigger inputs for noise suppression

• Output slope control to eliminate ground bounce

• 2 ms typical write cycle time, byte or page

• Up to eight devices may be connected to the

same bus for up to 256K bits total memory

• Electrostatic discharge protection > 4000V

• Data retention > 200 years

• 8-pin PDIP and SOIC packages

• Temperature ranges

DESCRIPTION

The Microchip Technology Inc. 24AA32A is a 4K x 8

(32K bit) Serial Electrically Erasable PROM capable of

operation across a broad voltage range (1.8V to 6.0V).

It has been developed for advanced, low power appli-

cations such as personal communications or data

acquis iti on. The 24AA32A a lso has a pag e-w rite cap a-

bility of up to 32 bytes of data. The 24AA32A is capable

of both random and sequential reads up to the 32K

boundary. Functional address lines allow up to eight

24AA32A de vices on the same bus, for up to 256K bits

address space. Advanced CMOS technology and

broad voltage range make this device ideal for low-

power/low-voltage, nonvolatile code and data applica-

tions. The 24AA32A is available in the standard 8-pin

plastic DIP and both 150 mil and 200 mil SOIC pack-

ages.

- Commercial (C): 0°C to +70°C

PACKAGE TYPE

BLOCK DIAG RAM

24AA32A 24AA32A

Vss

Vcc

SCL

SDA

Vss

Vcc

SCL

SDA

PDIP

SOIC

HV GENERATOR

EEPROM

ARRAY

PAGE LATCHES

YDEC

XDEC

SENSE AMP

R/W CONTROL

MEMORY

CONTROL

LOGIC

I/O

CONTROL

LOGIC

SDA

SCL

VCC

VSS

I/O

A2A1A0

24AA32A

32K 1.8V I2C™ Serial EEPROM

I2C is a trademark of Philips Corporation.

24AA32A

DS21162D-page 2  1999 Microchip Technology Inc.

1.0 ELECTRICAL CHARA CTERISTICS

1.1 Maximum Ratings*

VCC...................................................................................7.0V

All inputs and outputs w.r.t. VSS ............... -0.6V to VCC +1.0V

Storage temperature .....................................-65°C to +150°C

Ambient temp. with power applied ................ - 65°C to +125°C

Soldering temperature of leads (10 seconds).............+300°C

ESD protection on all pins..... ........................ .....................≥ 4 kV

*Notice: Stresses above those listed under “Maximum Ratings”

may cause permanent damage to the device. This is a stress rat-

ing only and functional operation of the device at those or any

other conditions above those indicated in the operational listings

of this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect dev ice reliability.

TABLE 1-1: PIN FUNCTION TABLE

Name Function

A0,A1,A2 User Configurable Chip Selects

VSS Ground

SDA Serial A ddress/Data I/O

SCL Serial Clock

WP Write Protect Input

VCC +1.8V to 6.0V Power Supply

TABLE 1-2: DC CHARACTERISTICS

FIGURE 1-1: BUS TIMING START/STOP

Vcc = +1.8V to 6.0V

Commercial (C) Tamb = 0°C to +70°C

Parameter Symbol Min Typ Max Units Conditions

A0, A1, A2, SCL , SDA and WP

pins:

High level input voltage VIH .7 VCC —V

Low level input voltage VIL1

VIL2—

—.3 Vcc

.2 VCC V

VVcc ≥ 2.5V

Vcc < 2.5V

Hysteresis of Schmitt Trigger

inputs VHYS .05

VCC —V(Note)

Low level output voltag e VOL —.40VIOL = 3.0 mA

Input leakage current ILI -10 10 µAVIN = .1V to VCC

Output leakage current ILO -10 10 µAVOUT = .1V to VCC

Pin capacitance

(all inputs /ou tpu ts) CIN,COUT —10pFVCC = 5.0V (Note)

Tamb = 25°C, Fc = 1 MHz

Operating current ICC Write — 3 mA VCC = 6.0V

ICC Read — 0.5 mA VCC = 6.0V, SCL = 400kHz

Standby current ICCS — 1 5 µA SCL = SDA = VCC = 5.5V

ICCS 1µAVCC = 1.8V (Note)

WP = VSS, A0, A1, A2 = VSS

Note: This parameter is periodically sampled and not 100% tested.

SCL

SDA

TSU:STA THD:STA TSU:STO

VHYS

START STOP

 1999 Microchip Technology Inc. DS21162D-page 3

24AA32A

TABLE 1-3: AC CHARACTERISTICS

FIGURE 1-2: BUS TIMING DATA

Parameter Symbol Vcc = 1.8-6.0V

STD . MODE Vcc = 4. 5-6.0V

FAST MODE Units Remarks

Min Max Min Max

Clock frequency FCLK — 100 — 400 kHz

Clock high time THIGH 4000 — 600 — ns

Clock low time TLOW 4700 — 1300 — ns

SDA and SCL rise time TR— 1000 — 300 ns (Note 1)

SDA and SCL fall time TF— 300 — 300 ns (Note 1)

START condition hold time THD:STA 4000 — 600 — ns After this period the first

clock pulse is generated

START condition setup

time TSU:STA 4700 — 600 — ns Only rele vant for repe ate d

START condition

Data input hold time THD:DAT 0—0—ns

Data input setup time TSU:DAT 250 — 100 — ns

STOP condition setup time TSU:STO 4000 — 600 — ns

Output valid from clock TAA — 3500 — 900 ns (Note 2)

Bus free time TBUF 4700 — 1300 — ns Time the bus must be free

before a ne w tr a ns mi ss io n

can start

Output fall time from VIH

min to VIL max TOF — 250 20

+0.1CB250 ns (Note 1), CB ≤ 100 pF

Input filter spike suppres-

sion (SDA and SCL pins) TSP — 50 — 50 ns (Note 3)

Write cycl e time TWR — 5 — 5 ms Byte or Page Mode

Endurance — 1M — 1M — cycles 25°C, Vcc = 5.0V, Block

Mode (Note 4)

Note 1: Not 100% tested. CB = Total capacitance of one bus line in pF.

2: As a trasmitter, the device must provide an internal minimum delay time to bridge the undefined region (min-

imum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.

3: The combined TSP and VHYS specifications are due to Sch m itt trigger inputs which provide improved noise

and spike suppression. This eliminates the need for a Ti specification for standard operation.

4: This application is n ot tested b u t g uaranteed by charac terizat ion . For endura nce e sti ma tes i n a specific app li-

cation, please consult the Total Enduranc e Model which can be obtained on our website.

SCL

SDA

OUT

THD:STA

TSU:STA

TFTHIGH

TSU:STOTSU:DATTHD:DAT

TBUFTAA

THD:STA

TAA

TSP

TLOW

24AA32A

DS21162D-page 4  1999 Microchip Technology Inc.

2.0 FUNCTIONAL DESCRIPTION

The 24AA32A supports a Bi-directional two-wire bus

and data transmission protocol. A device that sends

data onto the bus is defined as transmitter, and a

de vice receiving data as receiver . The bus must be con-

trolled by a master device which generates the Serial

Clock (SCL), controls the bus access, and generates

the START and STOP conditions, while the 24AA32A

works as slave. Both master and slave can operate as

transmitter or receiver but the master device deter-

mines which mode is activated.

3.0 BUS CHARACTERISTICS

The follow ing bus protocol has been defined:

• Data transfer may be initiated only w hen the bus

is no t busy.

• During data transfer, the data line must remain

stable whenever the clock line is HIGH. Changes

in th e d ata line while the clock li ne is H IG H will be

interpreted as a START or STOP condition.

Accordingly, the following bus conditions have been

defined (Figu re 3-1).

3.1 Bus not Busy (A)

Both data and clock lines remain HIGH.

3.2 Start Data Transfer (B)

A HIGH to LOW transition of the SDA line while the

cloc k (SCL) is HIGH d etermines a STAR T condi tion. All

commands must be preceded by a START condition.

3.3 Stop Data Transfer (C)

A LOW to HIGH transition of the SDA line while the

clock (S CL) i s HI GH de termi n es a STOP con dit i on . A ll

operations must be ended with a STOP condition.

3.4 Data Valid (D)

The state of the data line represents valid data when,

after a START condition, the data line is stable for the

duration of the HIGH period of the clock signal.

The data on the line must be changed during the LOW

period of the clock signal. There is one clock pulse per

bit of data.

Each data transfer is initiated with a START condition

and terminated with a STOP condition. The number of

the data bytes transferred between the START and

STOP conditions is determi ned by the master device.

3.5 Acknowledge

Each receiving device, when addressed, is obliged to

generate an acknowledge signal after the reception of

each byte. The master device must generate an extra

clock pulse which is associated with this acknowledge

bit.

A device that acknowledges must pull down the SDA

line during the acknowledge clock pulse in such a way

that the SD A l ine is stable LO W du ring the HI GH period

of the acknowledge related clock pulse. Of course,

setup and hold times must be taken into account. Dur-

ing reads, a master must signal an end of data to the

slave by NO T generating an acknowledge bit on the last

by te that has been cloc ked out of the slave. In thi s case ,

the slave (24AA32A) will leave the data line HIGH to

enable the master to generate the STOP condition.

Note: The 24AA32A does not generate any

acknowledge bits if an internal program-

ming cyc le is in prog r ess.

FIGURE 3-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS

SCL

SDA

(A) (B) (D) (D) (A)(C)

START

CONDITION ADDRESS OR

ACKNOWLEDGE

VALID

DATA

ALLOWED

TO CHANGE

STOP

CONDITION

 1999 Microchip Technology Inc. DS21162D-page 5

24AA32A

3.6 Device Addressing

A control byte is the first byte received following the

start conditio n from th e master device. T he control by te

consists of a 4-bit control code; for the 24AA32A this is

set as 101 0 binary for read and write (R/W) oper ations.

The next three bits of the control byte are the device

select bits (A2, A1, A0). They are used by the master

device to select which of the eight devices are to be

acces sed. These bit s are in eff ect the three m ost signif-

icant b its of the w ord add ress. The last bi t of the co ntrol

byte def ines th e operati on to be performe d. When set

to a one a read operation is selected, and when set to

a zero a w rite ope rati on is selected. The next two b ytes

received define the address of the first data byte

(Figure 3-3). Because only A11...A0 are used, the

upper f our ad dress bi ts must be zeros . The m ost signif-

icant bit of the most significant byte of the address is

transferred first.

FIGURE 3-2: CONTROL BYTE

ALLOCATION

R/W A

1 0 1 0 A2 A1 A0

READ/WRITE

START

SLAVE ADDRESS

Following the start condition, the 24AA32A monitors

the SDA bus checking the device type identifier being

tran smit ted. Upon re ceivi ng a 1010 code an d approp ri-

ate device select bits, the slave device outputs an

ac know ledge sig nal on the SD A lin e. Dep ending on th e

stat e of the R/W bit, the 24AA32A will select a read or

write operation.

Operation Control

Code Device Select R/W

Read 1010 Device Address 1

Write 1010 Device Address 0

FIGURE 3-3: ADDRESS SEQUENCE BIT ASSIGNMENTS

1010A

0R/W 0000A

11 A

10 A

8•• ••••

SLAVE

ADDRESS DEVICE

SELECT

BUS

CONTROL BYTE ADDRESS BYTE 1 ADDRESS BYTE 0

24AA32A

DS21162D-page 6  1999 Microchip Technology Inc.

4.0 WRITE OPERATION

4.1 Byte Write

Following the start condition from the master, the con-

trol code (four bits), the dev ice select (three bits), and

the R/W bit which is a logic lo w are clocked onto the b us

by the master transmitter. This indicates to the

addressed slave receiver that a byte with a word

address will follow after it has generated an acknowl-

edge bit during the ninth clock cycle. Therefore, the

next byte transmitted by the master is the high-order

byte of the word address and will be written into the

address pointer of the 24AA32A. The next byte is the

least significant address byte. After receiving another

acknowledge signal from the 24AA32A the master

device will transmit the data word to be written into the

addressed memory location.

The 24AA32A acknowledges again and the master

generates a stop condition. This initiates the internal

write cycle, and during this time the 24AA32A will not

generate acknowledge signals (Figure 4-1).

4.2 Page Write

The write control byte, word address and the first data

byte are transmitted to the 24AA32A in the same way

as in a by te write. But ins tead of gener ating a stop con-

dition, the master transmits up to 32 bytes which are

tempor arily stored in the on-chip page b uffer an d will be

written into memory after the master has transmitted a

stop co ndition. After re ceipt of each word, the fiv e lo wer

address poin ter bits are int ernally inc rem en ted by one.

If the master should transmit more than 32 bytes prior

to generating the stop condition, the address counter

will roll over and the previously received data will be

overwritten. As with the byte write operation, once the

stop condition is received, an internal write cycle will

begin. (Figure 4-2).

Note: P age write operations are limited to writing

by tes within a single physical page, regard-

less of the number of bytes actually being

written. Physical page boundaries start at

addresses that are integer multiples of the

page b uff e r siz e (or ‘pa ge siz e’) and end at

addresses that are integer multiples of

[page size - 1]. If a page write command

attempts to write across a physical page

boundary, the result is that the data wraps

around to the beginning o f the current page

(overwriting data previously stored there),

inst ead of b eing writte n to the ne xt page as

might be expected. It is therefore neces-

sary for the applic at ion softw are to pre v e nt

page write operations that would attempt

to cross a page boundary.

FIGURE 4-1: BYTE WRITE

FIGURE 4-2: PAGE WRITE

0000

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE ADDRESS

HIGH BYTE ADDRESS

LO W BYTE DATA

0000

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

TCONTROL

BYTE ADDRESS

HIGH BYTE ADDRESS

LOW BYTE DATA BYTE 0

DATA BYTE 31

S P

 1999 Microchip Technology Inc. DS21162D-page 7

24AA32A

5.0 ACKNOWLEDGE POLLING

Since the device will not acknowledge during a write

cycle, this can be used to determine when the cycle is

complete (this feature can be used to maximize bus

throughput). Once the stop condition for a write com-

mand has been issued from the master, the device ini-

tiates the internally timed write cycle. Acknowledge

Polling (ACK) can be initiated immediately. This

involves the master sending a start condition followed

by the control byte for a write command (R/W = 0). If the

device is still busy with the write cycle, then no A CK will

be returned. If the cycle is complete, then the device

will return the ACK and the master can then proceed

with the next read or write command. See Figure 5-1

for flow diagram.

FIGURE 5-1: ACKNOWLEDGE POLLING

FLOW

Send

Write Command

Send Stop

Condition to

Initiate Write Cycle

Send Start

Send Control Byte

with R/W = 0

Did Device

Acknowledge

(ACK = 0)?

Operation

YES

6.0 READ OPERATION

Read operations are initiated in the same way as write

operations with the exception that the R/W bit of the

sla ve addr ess is set to one . There are th ree basic type s

of read o perat ions: cu rrent address read, ra ndom rea d,

and sequential read.

6.1 Current Address Read

The 24AA32A contains an address counter that main-

tains the address of the last wo rd ac cessed, internally

inc rement ed by one. T herefore, i f the p revious ac cess

(either a rea d or write ope rati on) wa s to addre ss n (n i s

any legal add ress), the next current addres s read op er-

ation would access data from address n + 1. Upon

receipt of the sla ve ad dress with R/W bit s et to one, the

24AA32A issues an acknowledge and transmits the

eight bit data word. The master will not acknowledge

the tr ansf e r but does gene rate a s top con dition and the

24AA32A discontinues transmission (Figure 6-1).

6.2 Random Read

Random read operations allow the master to access

any memory location in a random manner. To perfor m

this type of read operation, first the word address must

be set. This is don e by sending the word address t o the

24AA32A as part of a write operation (R/W bit set to

zero). After the word address is sent, the master gen-

era tes a start conditi on fo llowin g the ac know ledge. This

terminates the write operation, but not before the inter-

nal address pointer is set. Then the master issues the

control b yte again b ut with the R/W bit set to a one. The

24AA32A will then issue an acknowledge and transmit

the 8-bit data word. The master will not acknowledge

the transfer but does generate a stop condition which

causes the 24AA32A to discontinue transmission

(Figure 6-2).

FIGURE 6-1: CURRE NT ADDRESS READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

TCONTROL BYTE DATA BYTE

24AA32A

DS21162D-page 8  1999 Microchip Technology Inc.

6.3 Contiguous Addressing Across

Multiple Devices

The device select bits A2, A1, A0 can be used to

expand the contiguous address space for up to 256K

bits by adding up to eight 24 AA32A’s on t he sa me bus.

In this case, software can use A0 of the co ntrol byte as

address bit A12, A1 as address bit A13, and A2 as

address bit A14.

6.4 Sequential Read

Sequenti al reads ar e initiat ed in the same w ay as a ra n-

dom read except that after the 24AA32A transmits the

first data byte, the master issues an acknowledge as

oppos ed to the stop co nditi on us ed in a rand om re ad.

This acknowledge directs the 24AA32A to transmit the

next sequentially addressed 8-bit word (Figure 6-3).

Following the final byte transmitted to the master, the

master w ill NO T generate an ac know ledge b ut w ill gen-

erate a stop condition.

To pr ovide seq uent ial read s the 2 4AA32A contai ns an

internal ad dress pointe r which is inc remented b y one at

the com ple tio n of each operat ion . Thi s a ddress pointer

allows the entire memory contents to be serially read

during one operation. The internal address pointer will

automatically roll over from address 0FFF to address

000 if the master acknowled ges the byte rec eived from

the array address 0FFF.

FIGURE 6-2: RANDOM READ

FIGURE 6-3: SE QUEN TIAL READ

0000

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL S

BYTE ADDRESS

HIGH BYTE ADDRESS

LOW BYTE CONTROL

BYTE DATA

BYTE

SSP

BUS A CTIVIT Y

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA n DATA n + 1 DATA n + 2 DATA n + x

 1999 Microchip Technology Inc. DS21162D-page 9

24AA32A

7.0 PIN DESCRIPTIONS

7.1 A0, A1, A2 Chip Address Inputs

The A0..A2 inpu ts are used by the 24AA32A for multi-

ple device operation and conform to the 2-wire bus

standard. The levels applied to these pins define the

address block occupied by the device in the address

map. A particular device is selected by transmitting the

corresponding bits (A2, A1, A0) in the control byte

(Figure 3-3).

7.2 SD A Serial Address/Data Input/Output

This is a Bi-directional pin used to transfer addresses

and data into and data out of the device. It is an open

drain te rminal, th erefore the SDA bus requ ires a pu llup

resistor to VCC (typical 10KΩ for 100 kHz, 2 KΩ for

400 kHz)

F or normal data tr ansf er SDA is allow ed to chan ge only

during SCL low. Changes during SCL HIGH are

reserved for indicating the START and STOP condi-

tions.

7.3 SCL Serial Clock

This in put is used to sync hroniz e the data tr ansf e r from

and to the device.

7.4 WP

This pin must be connected to either VSS or VCC.

If tied to VSS, normal memory operation is enabled

(read/write the entire memory 000-FFF).

If tied to VCC, WRITE operations are inhibited. The

entir e memory will be writ e-protected . Read oper ation s

are not affect ed.

8.0 NOISE PROTECTION

The SCL and SD A inputs have filter circuits which sup-

press noise spikes to ensure proper device operation

even on a noisy bus. All I/O lines incorporate Schmitt

triggers for 400 kHz (Fast Mode) compatibility.

9.0 POWER MANAGEMENT

This design incorporates a power standby mode when

the device is not in use and automatically powers off

after the normal termination of any operation when a

stop bit is received and all internal functions are com-

plete. This includes any error conditions, i.e., not

receiving an acknowledge or stop condition per the 2-

wire bus specification. The device also incorporates

VDD monitor circuitry to prevent inadvertent writes

(data corruption) during low-voltage conditions. The

VDD monitor circuitry is powered off when the device is

in standby mode in order to further reduce power con-

sumption.

24AA32A

DS21162D-page 10  1999 Microchip Technology Inc.

NOTES:

24AA32A

24AA32A Product Identification System

To order or to obtain information, e.g., on pricing or deliver y, please use the listed part numbers, and refer to the factory or the listed

sales offices.

Sales and Support

Data Sheets

Products supported by a preliminary Data Sheet may have an errata sheet descr ibing minor operational differ ences and recom -

mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:

1. Your local Microchip sales office

2. The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277

3. The Microchip Worldwide Site (www.microchip.com)

Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.

New Customer Notification System

Package: P = Plastic DIP (300 mil Body), 8-lead

SN = Plastic SOIC (150 mil Body, EIAJ standard), 8-lead

SM = Plastic SOIC (207 mil Body, EIAJ standard), 8-lead

Temperature Blank = 0°C to +70°C

Range:

Device: 24AA32A 32K I2C Serial EEPROM (100 kHz, 400 kHz)

24AA32AT 32K I2C Serial EEPROM (Tape and Reel)

24AA32A – /P

 1999 Microchip Technology Inc. DS21162D-page 11

 2002 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is intended through sug gestion only

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

No representation or warranty is given and no liability is

assumed by Microc hip Technology Incorporated with respect

to the accuracy or use of such inf orm ation, or inf ringement of

patents or other intellectual property rights arising from such

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ponents in life support systems is not authorized except with

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Trademarks

The Microchip name and logo, the Microchip logo, FilterLab,

KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER,

PICSTART, PRO MATE, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip Tech-

nology Incorporated in the U.S.A. and other countries.

dsPIC, ECONOMONITOR, FanSense, FlexRO M, fuzzyLAB,

In-Circuit Serial Programming, ICSP, ICEPIC, microPort,

Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM,

MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode

and Total Endurance are trademarks of Microchip Technology

Incorporated in the U.S.A.

Serialized Quick Turn Programming (SQTP) is a service mark

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All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

Microchip received QS-9000 quality system

certification for its worldwide headquarters,

design and wafer fabrication facilities in

Chandler and T empe, Arizona in July 1999. The

Company’s quality system processes and

procedures are QS-9000 compliant for its

PICmicro® 8-bit MCUs, KEELOQ® code ho pp in g

devices, Serial EEPROMs and microperipheral

products. In addition, Microchip’s quality

system for the design and manufacture of

development systems is ISO 9001 certified.

Note the following details of the code protection feature on PICmicro® MCUs.

•The PICmicro family meets the specifications contained in the Microchip Data Sheet.

•Microchip believes that its family of PICmicro microcontrollers is one of the most secure product s of its kind on the market today,

when used in the intended manner and under normal conditions.

•There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowl-

edge, require using the PICmicro microcontroller in a manner outside the operating specifications contained in the data sheet.

The person doing so may be engaged in theft of intellectual property.

•Microchip is willing to work with the customer who is concerned about the integrity of their code.

•Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable”.

•Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of

our product.

If you have any further questions about this matter, please contact the local sales office nearest to you.

 2002 Microchip Technology Inc.

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150 Motor Parkway, Suite 202

Hauppauge, NY 11788

Tel: 631 -2 73- 530 5 Fax: 631- 273 -53 35

San Jose

Microchip Technology Inc.

2107 North First Street, Suite 590

San Jose, CA 95131

Tel: 408 -4 36- 795 0 Fax: 408- 436 -79 55

Toronto

6285 Northam Drive, Suite 108

Mississ aug a, Ontario L4V 1X5, C ana da

Tel: 905-673-0699 Fax: 905-673-6509

ASIA/PACIFIC

Australia

Microchip Technology Australia Pty Ltd

Suite 22, 41 Rawson Street

Epping 212 1, NSW

Australia

Tel: 61-2-9868-6733 Fax: 61-2-9868-6755

China - Be ij ing

Microchip Technology Consulting (Shanghai)

Co., Ltd., Beijing Liaison Office

Unit 915

Bei Hai Wa n Tai Bldg.

No. 6 Chaoyangmen Beidajie

Beijing, 100027, No. China

Tel: 86-10-85282100 Fax: 86-10-85282104

China - Chengdu

Microchip Technology Consulting (Shanghai)

Co., Ltd., Chengdu Liaison Office

Rm. 2401, 24th Floor,

Ming Xing Financial Tower

No. 88 TIDU Street

Cheng du 610 016 , Chi na

Tel: 86-28-6766200 Fax: 86-28-6766599

China - Fuzhou

Microchip Technology Consulting (Shanghai)

Co., Ltd., Fuzhou Liaison Office

Unit 28F, World Trade Plaza

No. 71 Wusi Road

Fuzhou 350001, China

Tel: 86-591-7503506 Fax: 86-591-7503521

China - Shanghai

Microchip Technology Consulting (Shanghai)

Co., Ltd.

Room 701, Bldg. B

Far East In ternational Plaza

No. 317 Xian Xia Road

Shanghai, 200051

Tel: 86-21-6275-5700 Fax: 86-21-6275-5060

China - Shenzhen

Microchip Technology Consulting (Shanghai)

Co., Ltd., Shenzhen Liaison Office

Rm. 1315, 13/F, Shenzhen Kerry Centre,

Renminnan Lu

Shenzhen 518001, China

Tel: 86-755-2350361 Fax: 86-755-2366086

Hong Kong

Microchip Technology Hongkong Ltd.

Unit 901-6, Tower 2, Metroplaza

223 Hing Fong Road

Kwai Fong, N.T., Hong Kong

Tel: 852-2401-1200 Fax: 852-2401-3431

India

Microchip Technology Inc.

India Liaiso n Office

Divyasree Chambers

1 Floor, Wing A (A3/A4)

No. 11, O’Shaugnessey Road

Bangalore, 560 025, India

Tel: 91-80-2290061 Fax: 91-80-2290062

Japan

Microchip Technology Japan K.K.

Benex S-1 6F

3-18-20, Shinyokohama

Kohoku-K u, Yokohama- shi

Kanagawa, 222-0033, Japan

Tel: 81-45-471- 6166 Fax: 81-45-471-6122

Korea

Microc hip Technolo gy Korea

168-1, You ng bo Bld g. 3 Floor

Samsung-Dong, Kangnam-Ku

Seoul, Ko re a 135- 88 2

Tel: 82-2-554-7200 Fax: 82-2-558-5934

Singapore

Microchip Technology Singapore Pte Ltd.

200 Midd le Ro ad

#07-02 Prime Centre

Singapore, 188980

Tel: 65-6334-8870 Fax: 65-6334-8850

Taiwan

Microc hip Technolo gy Tai wan

11F-3, No. 207

Tung Hua North Road

Taipei, 105, Taiwan

Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

EUROPE

Denmark

Microchip Technology Nordic ApS

Regus Business Centre

Lautrup hoj 1-3

Ballerup DK-2750 Denmark

Tel: 45 4420 9895 Fax: 45 4420 9910

France

Microc hip Technolo gy SARL

Parc d’Activite du Moulin de Massy

43 Rue du Saule Trapu

Batiment A - ler Et age

91300 Massy, France

Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Germany

Microc hip Technolo gy GmbH

Gustav-Heinemann Ring 125

D-81739 Munich, Germany

Tel: 49-89-627-144 0 Fax: 49-89-627-144-44

Italy

Microc hip Technolo gy SRL

Centro Direzionale Colleoni

Palazzo Taurus 1 V. Le Colleoni 1

20041 Agrate Brianza

Milan, Italy

Tel: 39-039-65791-1 Fax: 39-039-6899883

United Kingdom

Arizona Microchip Technology Ltd.

505 Eskdale Road

Winnersh Triangle

Wokingham

Berksh ire, E ngla nd RG 41 5TU

Tel: 44 118 921 5869 Fax: 44-118 921-5820

03/01/02

WORLDWIDE SALES AND SERVICE