REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
a
Low Power Mixer
3 V Receiver IF Subsystem
AD607
FEATURES
Complete Receiver-on-a-Chip: Monoceiver® Mixer
–15 dBm 1 dB Compression Point
–8 dBm Input Third Order Intercept
500 MHz RF and LO Bandwidths
Linear IF Amplifier
Linear-in-dB Gain Control
Manual Gain Control
Quadrature Demodulator
On-Board Phase-Locked Quadrature Oscillator
Demodulates IFs from 400 kHz to 12 MHz
Can Also Demodulate AM, CW, SSB
Low Power
25 mW at 3 V
CMOS Compatible Power-Down
Interfaces to AD7013 and AD7015 Baseband Converters
APPLICATIONS
GSM, CDMA, TDMA, and TETRA Receivers
Satellite Terminals
Battery-Powered Communications Receivers
PIN CONFIGURATION
20-Lead SSOP
(RS Suffix)
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD607
FDIN
QOUT
IOUT
FLTR
VPS1
COM1
PRUP
LOIP
IFOP
DMIP
VPS2
RFLO
RFHI
GREF
MXOP
VMID
IFHI IFLO
GAIN
COM2
GENERAL DESCRIPTION
The AD607 is a 3 V low power receiver IF subsystem for opera-
tion at input frequencies as high as 500 MHz and IFs from
400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and
Q demodulators, a phase-locked quadrature oscillator, and a
biasing system with external power-down.
The AD607’s low noise, high intercept mixer is a doubly
balanced Gilbert cell type. It has a nominal –15 dBm input
referred 1 dB compression point and a –8 dBm input referred
third order intercept. The mixer section of the AD607 also
includes a local oscillator (LO) preamplifier, which lowers the
required LO drive to –16 dBm.
In MGC operation, the AD607 accepts an external gain-control
voltage input from an external AGC detector or a DAC.
The I and Q demodulators provide in-phase and quadrature
baseband outputs to interface with Analog Devices’ AD7013
(IS54, TETRA, MSAT) and AD7015 (GSM) baseband con-
verters. A quadrature VCO phase-locked to the IF drives the I
and Q demodulators. The I and Q demodulators can also
demodulate AM; when the AD607’s quadrature VCO is phase-
locked to the received signal, the in-phase demodulator becomes
a synchronous product detector for AM. The VCO can also be
phase-locked to an external beat-frequency oscillator (BFO),
and the demodulator serves as a product detector for CW or
SSB reception. Finally, the AD607 can be used to demodulate
BPSK using an external Costas Loop for carrier recovery.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2002
Monoceiver is a registered trademark of Analog Devices, Inc.
AD607–SPECIFICATIONS
REV. C
–2–
(@ T
A
= 25ⴗC, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted.)
AD607ARS
Model Conditions Min Typ Max Unit
DYNAMIC PERFORMANCE
MIXER
Maximum RF and LO Frequency Range For Conversion Gain > 20 dB 500 MHz
Maximum Mixer Input Voltage For Linear Operation; Between RFHI and RFLO ±54 mV
Input 1 dB Compression Point RF Input Terminated in 50 Ω–15 dBm
Input Third-Order Intercept RF Input Terminated in 50 Ω–5 dBm
Noise Figure Matched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz 14 dB
Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz 12 dB
Maximum Output Voltage at MXOP Z
IF
= 165 Ω, at Input Compression ±1.3 V
Mixer Output Bandwidth at MXOP –3 dB, Z
IF
= 165 Ω45 MHz
LO Drive Level Mixer LO Input Terminated in 50 Ω–16 dBm
LO Input Impedance LOIP to VMID 1 kΩ
Isolation, RF to IF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 30 dB
Isolation, LO to IF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 20 dB
Isolation, LO to RF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 40 dB
Isolation, IF to RF RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz 70 dB
IF AMPLIFIERS
Noise Figure Max Gain, f = 10.7 MHz 17 dB
Input 1 dB Compression Point IF = 10.7 MHz –15 dBm
Output Third-Order Intercept IF = 10.7 MHz 18 dBm
Maximum IF Output Voltage at IFOP Z
IF
= 600 Ω±560 mV
Output Resistance at IFOP From IFOP to VMID 15 Ω
Bandwidth –3 dB at IFOP, Max Gain 45 MHz
GAIN CONTROL (See Figures 23 and 24)
Gain Control Range Mixer + IF Section, GREF to 1.5 V 90 dB
Gain Scaling GREF to 1.5 V 20 mV/dB
GREF to General Reference Voltage V
R
75/V
R
dB/V
Gain Scaling Accuracy GREF to 1.5 V, 80 dB Span ±1dB
Bias Current at GAIN 5µA
Bias Current at GREF 1µA
Input Resistance at GAIN, GREF 1MΩ
I AND Q DEMODULATORS
Required DC Bias at DMIP VPOS/2 V dc
Input Resistance at DMIP From DMIP to VMID 50 kΩ
Input Bias Current at DMIP 2µA
Maximum Input Voltage IF > 3 MHz ±150 mV
IF ≤ 3 MHz ±75 mV
Amplitude Balance IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz ±0.2 dB
Quadrature Error IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz –1.2 Degrees
Phase Noise in Degrees IF = 10.7 MHz, F = 10 kHz –100 dBc/Hz
Demodulation Gain Sine Wave Input, Baseband Output 18 dB
Maximum Output Voltage R
L
≥ 20 kΩ±1.23 V
Output Offset Voltage Measured from I
OUT
, Q
OUT
to VMID –150 +10 +150 mV
Output Bandwidth Sine Wave Input, Baseband Output 1.5 MHz
PLL
Required DC Bias at FDIN VPOS/2 V dc
Input Resistance at FDIN From FDIN to VMID 50 kΩ
Input Bias Current at FDIN 200 nA
Frequency Range 0.4 to 12 MHz
Required Input Drive Level Sine Wave Input at Pin 1 400 mV
Acquisition Time to ±3°IF = 10.7 MHz 16.5 µs
POWER-DOWN INTERFACE
Logical Threshold For Power Up on Logical High 2 V dc
Input Current for Logical High 75 µA
Turn-On Response Time To PLL Locked 16.5 µs
Standby Current 550 µA
POWER SUPPLY
Supply Range 2.92 5.5 V
Supply Current Midgain, IF = 10.7 MHz 8.5 mA
OPERATING TEMPERATURE
T
MIN
to T
MAX
Operation to 2.92 V Minimum Supply Voltage –25 +85 °C
Operation to 4.5 V Minimum Supply Voltage –40 +85 °C
Specifications subject to change without notice.
REV. C –3–
AD607
ORDERING GUIDE
Temperature Package Package
Model Range Description Option
AD607ARS –25°C to +85°C20-Lead Plastic RS-20
for 2.92 V to 5.5 V SSOP
Operation; –40°C
to +85°C for 4.5 V
to 5.5 V Operation
ABSOLUTE MAXIMUM RATINGS
1
Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . . . 5.5 V
Internal Power Dissipation
2
. . . . . . . . . . . . . . . . . . . . 600 mW
2.92 V to 5.5 V Operating Temperature Range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°Cto+85°C
4.5 V to 5.5 V Operating Temperature Range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
NOTES
1
Stresses above those listed under Absolute Maximum Rating may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Thermal Characteristics: 20-lead SSOP Package: θ
JA
= 126°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD607 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. C
–4–
AD607
PIN FUNCTION DESCRIPTIONS
Pin Mnemonic Reads Function
1FDIN Frequency Detector Input PLL Input for I/Q Demodulator Quadrature Oscillator, ±400 mV
Drive Required from External Oscillator. Must be biased at V
P
/2.
2COM1 Common #1 Supply Common for RF Front End and Main Bias
3PRUP Power-Up Input 3 V/5 V CMOS compatible power-up control; logical high =
powered-up; max input level = VPS1 = VPS2.
4LOIP Local Oscillator Input LO input, ac-coupled ±54 mV LO input is required (–16 dBm for
50 Ω input termination).
5RFLO RF “Low” Input Usually Connected to AC Ground
6RFHI RF “High” Input AC-Coupled, ±56 mV, Max RF Input for Linear Operation
7GREF Gain Reference Input High Impedance Input, typically 1.5 V, sets gain scaling.
8MXOP Mixer Output High Impedance, Single-Sided Current Output, ±1.3 V Max
Voltage Output (±6 mA Max Current Output)
9VMID Midsupply Bias Voltage Output of the Midsupply Bias Generator (VMID = VPOS/2)
10 IFHI IF “High” Input AC-Coupled IF Input, ±56 mV Max Input for Linear Operation
11 IFLO IF “Low” Input Reference Node for IF Input; Auto-Offset Null
12 GAIN Gain Control Input High Impedance Input, 0 V–2 V Using 3 V Supply, Max Gain at
V = 0
13 COM2 Common #2 Supply Common for IF Stages and Demodulator
14 IFOP IF Output Low Impedance, Single-Sided Voltage Output, 5 dBm
(±560 mV) Max
15 DMIP Demodulator Input Signal input to I and Q demodulators has a ±150 mV max input
at IF > 3 MHz for linear operation; ±75 mV max input at IF < 3 MHz
for linear operation. Must be biased at V
P
/2.
16 VPS2 VPOS Supply #2 Supply to High Level IF, PLL, and Demodulators
17 QOUT Quadrature Output Low Impedance Q Baseband Output; ±1.23 V Full Scale in 20 kΩ
Min Load; AC-Coupled
18 IOUT In-Phase Output Low Impedance I Baseband Output; ±1.23 V Full Scale in 20 kΩ
Min Load; AC-Coupled
19 FLTR PLL Loop Filter Series RC PLL Loop Filter, Connected to Ground
20 VPS1 VPOS Supply #1 Supply to Mixer, Low Level IF, PLL, and Gain Control
PIN CONNECTION
20-Lead SSOP (RS-20)
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
AD607
FDIN
QOUT
IOUT
FLTR
VPS1
COM1
PRUP
LOIP
IFOP
DMIP
VPS2
RFLO
RFHI
GREF
MXOP
VMID
IFHI IFLO
GAIN
COM2
HP8656B
IEEE RF_OUT
SYNTHESIZER
HP8656B
IEEE RF_OUT
SYNTHESIZER
HP8656B
IEEE RF_OUT
SYNTHESIZER
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
HP34401A
CPIB
HI
LO
I
DMM
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
V
REF
HP8764B
0
0
1
1
S0
S1
V
50⍀
50⍀
MXOP
RFHI
LOIP
L
RX
IFOPIFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
HP8764B
0
0
1
1
S0
S1
V
50⍀
50⍀
HP8594E
RF_IN IEEE
SPEC AN
HP8765B
0
1C
S0 S1V
R5
1k⍀
CHARACTERIZATION
BOARD
HP8765B
0
1C
S0 S1V
P6205
X10 OUT
FET PROBE
TEK1105
IN1 OUT1
IN2 OUT2
PROBE
SUPPLY
Figure 1. Mixer/Amplifier Test Set
HP346B
28V NOISE
NOISE SOURCE
HP8656B
IEEE RF_OUT
SYNTHESIZER
MXOP
RFHI
LOIP
L
RX
IFOPIFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
HP8765B 0
1
C
S0
S1 V
50⍀
CHARACTERIZATION
BOARD
HP8765B
0
1C
S0 S1
V
HP8720C
IEEE_488
PORT_1
PORT_2
NETWORK AN
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
V
REF
HP8970A
RF_IN 28V_OUT
NOISE FIGURE METER
Figure 2. Mixer Noise Figure Test Set
AD607
REV. C –5–
REV. C
–6–
AD607
HP346B
28V NOISE
NOISE SOURCE
MXOP
RFHI
LOIP
L
RX
IFOPIFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
V
REF
HP8970A
RF_IN 28V_OUT
NOISE FIGURE METER
P6205
X10 OUT
FET PROBE
TEK1103
IN1 OUT1
IN2 OUT2
PROBE SUPPLY
Figure 3. IF Amp Noise Figure Test Set
MXOP
RFHI
LOIP
L
RX
IFOPIFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
HP8764B
0
0
1
1
S0
S1
V
50⍀
50⍀
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
VREF
HP3326A
IEEE
OUTPUT_1
OUTPUT_2
DUAL SYNTHESIZER
DCFM
HP8656B
IEEE RF_OUT
SYNTHESIZER
P6205
X10
FET PROBE
P6205
X10
FET PROBE
OUT
OUT
1103
OUT1
OUT2
PROBE
SUPPLY
HP8765B 0
1
C
S0S1 V
HP8765B
0
1C
S0 S1V
HP8694E
RF_IN IEEE
SPEC AN
HP54120
CH1
DIGITAL
OSCILLOSCOPE
CH2
CH3
CH4
TRIG IEEE_488
IN1
IN2
Figure 4. PLL/Demodulator Test Set
REV. C –7–
AD607
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
V
REF
HP34401A
GPIB
HI
LO
I
DMM
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
R1
499k
⍀
MXOPRFHI
LOIP
L
RX
IFOP
IFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
Figure 5. GAIN Pin Bias Test Set
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
V
REF
HP34401A
GPIB
HI
LO
I
DMM
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
R1
499k⍀
MXOP
RFHI
LOIP
L
RX
IFOP
IFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
Figure 6. Demodulator Bias Test Set
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
HP34401A
GPIB
HI
LO
I
DMM
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
R1
10k⍀
HP3325B
IEEE RF_OUT
SYNTHESIZER
HP8594E
RF_IN IEEE
SPEC AN
MXOP
RFHI
LOIP
L
RX
IFOP
IFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
Figure 7. Power-Up Threshold Test Set
REV. C
–8–
AD607
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
FL6082A
RF_OUT
IEEE
MOD_OUT
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
V
REF
HP8112
PULSE_OUT
IEEE
PULSE GENERATOR
HP54120
CH1
CH2
CH3
CH4
TRIG IEEE_488
P6205
X10 OUT
FET PROBE
1103
IN1 OUT1
IN2 OUT2
PROBE SUPPLY
P6205
X10 OUT
FET PROBE
50⍀
DIGITAL
OSCILLOSCOPE
NOTE: MUST BE 3 RESISTOR POWER DIVIDER
MXOP
RFHI
LOIP
L
RX
IFOP
IFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
Figure 8. Power-Up Test Set
HP8594E
RF_IN IEEE
SPEC AN
P6205
X10 OUT
FET PROBE
1103
IN1 OUT1
IN2 OUT2
PROBE SUPPLY
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
HP8656B
RF_OUTIEEE
SYNTHESIZER
R1
1k⍀
MXOPRFHI
LOIP
L
RX
IFOP
IFHI
PLL
IOUT
QOUT
DMIP
FDIN
BIAS
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
Figure 9. IF Output Impedance Test Set
REV. C –9–
AD607
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
V
REF
P6205
X10
FET PROBE
P6205
X10
FET PROBE
OUT
OUT
1103
OUT1
OUT2
PROBE SUPPLY
HP54120
CH1
DIGITAL
OSCILLOSCOPE
CH2
CH3
CH4
TRIG IEEE_488
IN1
IN2
FL6082A
IEEE RF_OUT
MOD_OUT
20⍀
dB
MXOPRFHI
LOIP
L
RX
IFOP
IFHI
PLL
IOUT
QOUT
DMIP
FDIN
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
BIAS
Figure 10. PLL Settling Time Test Set
HP6633A
IEEE
VPOS
VNEG
SPOS
SNEG
DCPS
DP8200
IEEE
VPOS
VNEG
SPOS
SNEG
VREF
HP3326
IEEE
OUTPUT_1
OUTPUT_2
DUAL SYNTHESIZER
DCFM
HP3325B
IEEE RF_OUT
SYNTHESIZER
P6205
X10
FET PROBE
P6205
X10
FET PROBE
OUT
OUT
1103
OUT1
OUT2
PROBE SUPPLY
HP8765B
0
1C
S0 S1
V
HP8694E
RF_IN IEEE
SPEC AN
IN1
IN2
MXOP
RFHI
LOIP
L
RX
IFOP
IFHI
PLL
IOUT
QOUT
DMIP
FDIN
VPOS
PRUP
GAIN
CHARACTERIZATION
BOARD
BIAS
Figure 11. Quadrature Accuracy Test Set
REV. C
–10–
AD607
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5AD607
FDIN
QOUT
IOUT
FLTR
VPS1
COM1
PRUP
LOIP
IFOP
DMIP
VPS2
RFLO
RFHI
GREF
MXOP
VMID
IFHI IFLO
GAIN
COM2
0.1␮F
C13
C15
0.1␮F
IOUT
*
QOUT
*
IFOP
*
GAIN
*
DMIP
*
0.1␮F
C1
C3
10nF
R1
1k⍀
R2
316⍀
C6
0.1␮F
C8
0.1␮F
C5
1nF
4.99k⍀
R10
R8
51.1⍀
C11
10nF
R7
51.1⍀
C10
1nF
R6
51.1⍀
C9
1nF
R14
54.9⍀
R13
301⍀
R5
332⍀
0.1␮F
VPOS
GND
FDIN
PRUP
LOIP
RFHI
MXOP
*
IFHI
0⍀
R12
C16
1nF
C7
1nF
0.1␮F
C2
*CONNECTIONS ARE DC-COUPLED.
R9
51.1⍀
Figure 12. Characterization Board
REV. C –11–
Typical Performance Characteristics–AD607
RF FREQUENCY – MHz
SSB NF – dB
20
18
1050 25070 90 110 130 150 170 190 210 230
16
14
12
19
17
15
13
11
VPOS = 5V, IF = 20MHz
VPOS = 3V, IF = 20MHz
VPOS = 5V, IF = 10MHz VPOS = 3V, IF = 10MHz
TPC 1. Mixer Noise Figure vs. Frequency
4500
3000
0
5002500
2500
2000
3500
4000
FREQUENCY – MHz
1500
1000
500
50 100 150 200 300 350 400 450
RESISTANCE – ⍀
R SHUNT COMPONENT
C SHUNT COMPONENT
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
CAPACITANCE –
p
F
TPC 2. Mixer Input Impedance vs. Frequency,
VPOS = 3 V, V GAIN = 0.8 V
30
20
–20
6003000
25
10
15
0
5
RADIO FREQUENCY – MHz
–5
–15
–10
50 100 150 200 250 350 400 450 500 550
CONVERSION GAIN – dB
V
GAIN
= 0.00V
V
GAIN
= 0.54V
V
GAIN
= 1.08V
V
GAIN
= 1.62V
V
GAIN
= 2.16V
TPC 3. Mixer Conversion Gain vs. Frequency,
T = 25
°
C, VPOS = 2.92 V, VREF = 1.35 V, IF = 10.7 MHz
30
20
1000.1
25
10
15
0
5
INTERMEDIATE FREQUENCY – MHz
–5
–10 110
CONVERSION GAIN – dB
VGAIN = 0.3V
VGAIN = 0.6V
VGAIN = 1.8V
VGAIN = 1.2V
VGAIN = 2.4V
TPC 4. Mixer Conversion Gain vs. IF, T = 25
°
C,
VPOS = 3 V, VREF = 1.5 V
80
60
130–50
70
40
50
20
30
TEMPERATURE – ⴗC
10
–20
70
0
–10
–30 –10 10 20 30 40 50 60 80 90 100 110 120–40 –20 0
GAIN – dB
CUBIC FIT OF CONV_GAIN (TEMP)
CUBIC FIT OF IF_GAIN (TEMP)
IF AMP GAIN
MIXER CG
TPC 5. Mixer Conversion Gain and IF Amplifier Gain vs.
Temperature, VPOS = 3 V, VGAIN = 0.3 V, VREF = 1.5 V, IF =
10.7 MHz, RF = 250 MHz
80
60
62.4
70
40
50
20
30
SUPPLY – V
10
4.8
GAIN – dB
2.8 3.2 3.6 3.8 4 4.2 4.4 4.6 5 5.2 5.4 5.6 5.82.6 3 3.4
CUBIC FIT OF CONV_GAIN (V
POS
)
CUBIC FIT OF IF_GAIN (V
POS
)
IF AMP GAIN
MIXER CG
TPC 6. Mixer Conversion Gain and IF Amplifier Gain vs.
Supply Voltage, T = 25
°
C, VGAIN = 0.3 V, VREF = 1.5 V, IF =
10.7 MHz, RF = 250 MHz
REV. C
–12–
AD607
70
50
1000.1
60
30
40
10
20
INTERMEDIATE FREQUENCY – MHz
0
–10
110
IF AMPLIFIER GAIN – dB
VGAIN = 0.3V
VGAIN = 0.6V
VGAIN = 1.8V
VGAIN = 1.2V
VGAIN = 2.4V
80
TPC 7. IF Amplifier Gain vs. Frequency,
T = 25
°
C, VPOS = 3 V, VREF = 1.5 V
8
4
30
6
0
2
–4
–2
GAIN VOLTAGE – V
–6
–10
12
ERROR – dB
10
–8
0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8
IF AMP
MIXER
TPC 8. Gain Error vs. Gain Control Voltage,
Representative Part
996.200␮s1.00870ms 1.02120ms
TRIGGER ON EXTERNAL AT POS. EDGE AT 134.0mV
TIMEBASE
MEMORY 1
TIMEBASE
MEMORY 2
TIMEBASE
DELTA T
START
= 2.5␮s/DIV
= 100.0mV/DIV
= 2.50␮s/DIV
= 20.00mV/DIV
= 2.50␮s/DIV
= 16.5199␮s
= 1.00048ms
DELAY
OFFSET
DELAY
OFFSET
DELAY
STOP
= 1.00870ms
= 127.3mV
= 1.00870ms
= 155.2mV
= 1.00870ms
= 1.01700ms
TPC 9. PLL Acquisition Time
1.00E+071.00E+02
–110.00
–100.00
–130.00
–120.00
CARRIER FREQUENCY OFFSET
,
f
(
fm
)
– Hz
–140.00
–150.00
1.00E+03 1.00E+05
–90.00
1.00E+04 1.00E+06
PHASE NOISE – dBc
TPC 10. PLL Phase Noise L (F) vs. Frequency,
VPOS = 3 V, C3 = 0.1
µ
F, IF = 10.7 MHz
1000.1
2
PLL FREQUENCY – MHz
1.5
110
FLTR PIN VOLTAGE
2.5
TPC 11. PLL Loop Voltage at FLTR (K
VCO
) vs. Frequency
8
5
9485
7
3
4
1
2
QUADRATURE ANGLE – Degrees
0
9186 87 88 89 90 92 93
6
95
COUNT
TPC 12. Demodulator Quadrature Angle, Histogram,
T = 25
°
C, VPOS = 3 V, IF = 10.7 MHz
REV. C –13–
AD607
30
20
–2
25
10
15
5
IQ GAIN BALANCE – dB
0
COUNT
–1 0 1 2
TPC 13. Demodulator Gain Balance, Histogram,
T = 25
°
C, VPOS = 3 V, IF = 10.7 MHz
20
18
0
19
16
17
15
BASEBAND FREQUENCY – MHz
10 0.2 0.4 0.6 0.8
14
12
13
11
1.0 1.2 1.4 1.6 1.8 2.0
IGAIN – dB
QUADRATIC FIT OF I_GAIN_CORR (IFF)
I_GAIN_CORR
TPC 14. Demodulator Gain vs. Frequency
20
18
–50
19
16
17
15
TEMPERATURE – ⴗC
10
–40 –30 –20 –10
14
12
13
11
01020304050
IGAIN – dB
CUBIC FIT OF I_GAIN_CORR (TEMP)
I_GAIN_CORR
60 70 80 90 100 110 120 130
TPC 15. Demodulator Gain vs. Temperature
20
18
2.5
19
16
17
15
SUPPLY – V
10
3
14
12
13
11
3.5 4 4.5
IGAIN – dB
CUBIC FIT OF I_GAIN_CORR (TEMP)
I_GAIN_CORR
55.5 6
TPC 16. Demodulator Gain vs. Supply Voltage
40
25
17
35
15
20
10
DEMODULATOR GAIN – dB
0
17.2
5
17.4 17.6 17.8 18 18.2 18.4
COUNT
18.6 18.8
30
TPC 17. Demodulator Gain Histogram,
T = 25
°
C, VPOS = 3 V, IF = 10.7 MHz
REV. C
–14–
AD607
PRODUCT OVERVIEW
The AD607 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero-
dyne receiver, or most of a double-conversion receiver, at input
frequencies up to 500 MHz, and an IF from 400 kHz to 12 MHz.
The internal I/Q demodulators and their associated phase-
locked loop, which can provide carrier recovery from the IF,
support a wide variety of modulation modes, including
n-PSK, n-QAM, and AM. A single positive supply voltage of 3 V
is required (2.92 V minimum, 5.5 V maximum) at a typical
supply current of 8.5 mA at midgain. In the following discus-
sion, V
P
will be used to denote the power supply voltage, which
will be assumed to be 3 V.
Figure 13 shows the main sections of the AD607. It consists of a
variable gain UHF mixer and linear four-stage IF strip, which
together provide a voltage controlled gain range of more than
90 dB; dual demodulators, each comprising a multiplier fol-
lowed by a two-pole, 2 MHz low-pass filter; and a phase-locked
loop providing the inphase and quadrature clocks. A biasing
system with CMOS compatible power-down completes the
AD607.
Mixer
The UHF mixer is an improved Gilbert cell design, and can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 500 MHz. The dynamic range at the input of the
mixer is determined at the upper end by the maximum input
signal level of ±56 mV between RFHI and RFLO up to which the
mixer remains linear, and at the lower end by the noise level. It is
customary to define the linearity of a mixer in terms of the 1 dB
gain-compression point and third order intercept, which for the
AD607 are –15 dBm and –8 dBm, respectively, in a 50 Ω system.
RFHI
RFLO
IFLO
BPF
LOIP
MXOP
MIDPOINT
BIAS
GENERATOR
VMID
IFHI
BIAS
GENERATOR
VPS1
VPS2
PRUP
COM1 COM2
VMID
PTAT
VOLTAGE
IFOP BPF OR
LPF
DMIP
IOUT
FDIN
FLTR
QOUT
GAIN
AD607
GREF
VQFO
Figure 13. Functional Block Diagram
40.2127ms 40.2377ms 40.2627ms
TRIGGER ON EXTERNAL AT POS. EDGE AT 40.0mV
TIMEBASE
MEMORY 1
TIMEBASE
MEMORY 2
TIMEBASE
DELTA T
START
= 500␮s/DIV
= 100.0mV/DIV
= 5.00␮s/DIV
= 60.00mV/DIV
= 5.00␮s/DIV
= 15.7990␮s
= 40.2327ms
DELAY
OFFSET
DELAY
OFFSET
DELAY
STOP
= 40.2377ms
= 154.0mV
= 40.2377ms
= 209.0mV
= 40.2377ms
= 40.2485ms
TPC 18. Power-Up Response Time to PLL Stable
0
GAIN VOLTAGE – V
5
0.5 1.5 2
10
1
15
2.5
SUPPLY CURRENT – mA
TPC 19. Power Supply Current vs. Gain Control Voltage,
GREF = 1.5 V
REV. C –15–
AD607
The mixer’s RF input port is differential, that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased; we will generally assume that RFLO is decoupled to ac
ground. The RF port can be modeled as a parallel RC circuit as
shown in Figure 14.
R
IN
C
IN
C2
C1
C3
L1
RFHI
RFLO
AD607
C1, C2, L1: OPTIONAL MATCHING CIRCUIT
C3: COUPLES RFLO TO AC GROUND
Figure 14. Mixer Port Modeled as a Parallel RC Network;
an Optional Matching Network Is also Shown
The local oscillator (LO) input is internally biased at V
P
/2 via a
nominal 1000 Ω resistor internally connected from pin LOIP to
VMID. The LO interface includes a preamplifier that minimizes
the drive requirements, thus simplifying the oscillator design
and reducing LO leakage from the RF port. Internally, this
single-sided input is actually differential; the noninverting input
is referenced to Pin VMID. The LO requires a single-sided
drive of ±50 mV, or –16 dBm in a 50 Ω system.
The mixer’s output passes through both a low-pass filter and a
buffer, which provides an internal differential to single-ended
signal conversion with a bandwidth of approximately 45 MHz.
Its output at Pin MXOP is in the form of a single-ended cur-
rent. This approach eliminates the 6 dB voltage loss of the usual
series termination by replacing it with shunt terminations at
both the input and the output of the filter. The nominal conver-
sion gain is specified for operation into a total IF band-pass
filter (BPF) load of 165 Ω, that is, a 330 Ω filter doubly-termi-
nated as shown in Figure 14. Note that these loads are con-
nected to bias point VMID, which is always at the midpoint of
the supply (that is, V
P
/2).
The conversion gain is measured between the mixer input and
the input of this filter, and varies between 1.5 dB and 26.5 dB
for a 165 Ω load impedance. Using filters of higher impedance,
the conversion gain can always be maintained at its specified
value or made even higher; for filters of lower impedance, of say
Z
O
, the conversion gain will be lowered by 10 log
10
(165/Z
O
).
Thus, the use of a 50 Ω filter will result in a conversion gain that
is 5.2 dB lower. Figure 15 shows filter matching networks and
Table I lists resistor values.
IFLO
BPF
MXOP
VMID
IFHI
10
11
8
9
1nF
100nF
R3
100nF
R1
R2
Figure 15. Suggested IF Filter Matching Network. The
Values of R1 and R2 Are Selected to Keep the Impedance
at Pin MXOP at 165
Ω
Table I. Filter Termination Resistor Values for
Common IFs
Filter Filter Termination Resistor
IF Impedance Values
*
for 24 dB of Mixer Gain
R1 R2 R3
450 kHz 1500 Ω174 Ω1330 Ω1500 Ω
455 kHz 1500 Ω174 Ω1330 Ω1500 Ω
6.5 MHz 1000 Ω215 Ω787 Ω1000 Ω
10.7 MHz 330 Ω330 Ω0 Ω330 Ω
*Resistor values were calculated such that R1+ R2 = Z
FILTER
and
R1储 (R2 + Z
FILTER
) = 165 Ω.
The maximum permissible signal level at MXOP is determined
by both voltage and current limitations. Using a 3 V supply and
VMID at 1.5 V, the maximum swing is about ±1.3 V. To attain
a voltage swing of ±1 V in the standard IF filter load of 165 Ω
requires a peak drive current of about ±6 mA, which is well
within the linear capability of the mixer. However, these upper
limits for voltage and current should not be confused with issues
related to the mixer gain, already discussed. In an operational
system, the AGC voltage will determine the mixer gain, and
hence the signal level at the IF input Pin IFHI; it will always be
less than ±56 mV (–15 dBm into 50 Ω), which is the limit of the
IF amplifier’s linear range.
IF Amplifier
Most of the gain in the AD607 arises in the IF amplifier strip,
which comprises four stages. The first three are fully differential
and each has a gain span of 25 dB for the nominal AGC voltage
range. Thus, in conjunction with the mixer’s variable gain, the
total gain exceeds 90 dB. The final IF stage has a fixed gain of
20 dB, and it also provides differential to single-ended conversion.
The IF input is differential, at IFHI (noninverting relative to the
output IFOP) and IFLO (inverting). Figure 16 shows a simpli-
fied schematic of the IF interface. The offset voltage of this
stage would cause a large dc output error at high gain, so it is
nulled by a low pass feedback path from the IF output, also
shown in TPC 13. Unlike the mixer output, the signal at IFOP
is a low-impedance single-sided voltage, centered at V
P
/2 by the
dc feedback loop. It may be loaded by a resistance as low as
50 Ω, which will normally be connected to VMID.
10k⍀
10k⍀
VMID
AD607
IFHI
IFLO
OFFSET FEEDBACK
LOOP
IFOP
Figure 16. Simplified Schematic of the IF Interface
REV. C
–16–
AD607
The IF’s small-signal bandwidth is approximately 45 MHz from
IFHI and IFLO through IFOP. The peak output at IFOP is
±560 mV at V
P
= 3 V and ±400 mV at the minimum V
P
of
2.92 V. This allows some headroom at the demodulator inputs
(Pin DMIP), which accept a maximum input of ±150 mV for
IFs > 3 MHz and ±75 mV for IFs ≤ 3 MHz (at IFs ≤ 3 MHz,
the drive to the demodulators must be reduced to avoid saturat-
ing the output amplifiers with higher order mixing products that
are no longer removed by the on-board low pass filters).
Since there is no band-limiting in the IF strip, the output-
referred noise can be quite high; in a typical application and
at a gain of 75 dB, it is about 100 mV rms, making post-IF filtering
desirable. IFOP may be also used as an IF output for driving
an A/D converter, external demodulator, or external AGC
detector. Figure 17 shows methods of matching the optional
second IF filter.
AD607
BPF
IFOP
DMIP
RT
2RT
2RT
VPOS
a. Biasing DMIP from Power Supply (Assumes BPF
AC-Coupled Internally)
AD607
BPF
IFOP
DMIP
RT
VMID
RT
CBYPASS
b. Biasing DMIP from VMID (Assumes BPF AC-Coupled
Internally)
Figure 17. Input and Output Matching of the Optional
Second IF Filter
Gain Scaling and RSSI
The AD607’s overall gain, expressed in decibels, is linear-in-dB
with respect to the AGC voltage V
G
at Pin GAIN. The gain of
all sections is maximum when V
G
is zero, and reduces progres-
sively up to V
G
= 2.2 V (for V
P
= 3 V; in general, up to a limit
V
P
– 0.8 V). The gain of all stages changes in parallel. The AD607
features temperature compensation of the gain scaling. The gain
control scaling is proportional to the reference voltage applied to
the Pin GREF. When this pin is tied to the midpoint of the
supply (VMID), the scale is nominally 20 mV/dB (50 dB/V) for
V
P
= 3 V. Under these conditions, the lower 80 dB of gain range
(mixer plus IF) corresponds to a control voltage of 0.4 V ≤
V
G
≤ 2.0 V. The final centering of this 1.6 V range depends on
the insertion losses of the IF filters used. More generally, the gain
scaling using these connections is V
P
/150 (volts per dB), so scale
becomes 33.3 mV/dB (30 dB/V) using a 5 V supply, with a
proportional change in the AGC range, to 0.33 V ≤ V
G
≤ 3 V.
Table II lists gain control voltages and scale factors for power
supply voltages from 2.92 V to 5.5 V
Alternatively, Pin GREF can be tied to an external voltage
reference (V
R
) from, for example, an AD1582 (2.5 V) or
AD1580 (1.21 V) voltage reference, to provide supply-
independent gain scaling of V
R
/75 (volts per dB). When using
the Analog Devices’ AD7013 and AD7015 baseband converters,
the external reference may also be provided by the reference
output of the baseband converter (Figure 18). For example, the
AD7015 baseband converter provides a V
R
of 1.23 V; when
connected to GREF, the gain scaling is 16.4 mV/dB (60 dB/V).
An auxiliary DAC in the AD7015 can be used to generate the
MGC voltage. Since it uses the same reference voltage, the
numerical input to this DAC provides an accurate RSSI value
in digital form, no longer requiring the reference voltage to have
high absolute accuracy.
AD607
IOUT
R
QOUT
R
C
C
VMID
GREF
10nF
GAIN
1nF
AD7013 OR
AD7015
IADC
QADC
IADC
QADC
REFOUT
BYPASS
(AD7015)
(AD7013)
AUX DAC
Figure 18. Interfacing the AD607 to the AD7013 or AD7015
Baseband Converters
I/Q Demodulators
Both demodulators (I and Q) receive their inputs at Pin DMIP.
Internally, this single-sided input is actually differential; the
noninverting input is referenced to Pin VMID. Each demodula-
tor comprises a full-wave synchronous detector followed by a
2 MHz, two-pole low-pass filter, producing single-sided outputs
at pins IOUT and QOUT. Using the I and Q demodulators for
IFs above 12 MHz is precluded by the 400 kHz to 12 MHz
response of the PLL used in the demodulator section. Pin DMIP
requires an external bias source at V
P
/2; Figure 19 shows
suggested methods.
Outputs IOUT and QOUT are centered at V
P
/2 and can swing
up to ±1.23 V even at the low supply voltage of 2.92 V. They can
therefore directly drive the RX ADCs in the AD7015 baseband
converter, which require an amplitude of 1.23 V to fully load
them when driven by a single-sided signal. The conversion gain of
the I and Q demodulators is 18 dB (X8), requiring a maxi-
mum input amplitude at DMIP of ±150 mV for IFs > 3 MHz.
REV. C –17–
AD607
AD607
BPF
IFOP
DMIP
R
T
2R
T
2R
T
VPOS
a. Biasing DMIP from Power Supply (Assumes BPF
AC-Coupled Internally)
AD607
BPF
IFOP
DMIP
RT
VMID
RT
CBYPASS
b. Biasing DMIP from VMID (Assumes BPF
AC-Coupled Internally)
Figure 19. Suggested Methods for Biasing Pin DMIP
at V
P
/2
For IFs < 3 MHz, the on-chip low-pass filters (2 MHz cutoff)
do not attenuate the IF or feedthrough products. Thus, the
maximum input voltage at DMIP must be limited to ±75 mV
to allow sufficient headroom at the I and Q outputs for not only
the desired baseband signal, but also the unattenuated higher-
order demodulation products. These products can be removed
by an external low-pass filter. In the case of IS54 applications
using a 455 kHz IF and the AD7013 baseband converter, a simple
one-pole RC filter with its corner above the modulation band-
width is sufficient to attenuate undesired outputs.
Phase-Locked Loop
The demodulators are driven by quadrature signals that are
provided by a variable frequency quadrature oscillator (VFQO),
phase-locked to a reference signal applied to Pin FDIN. When
this signal is at the IF, in-phase and quadrature baseband outputs
Table II. AD607 Gain and Manual Gain Control Voltage vs. Power Supply Voltage
Power Supply GREF Gain Control
Voltage (= VMID) Scale Factor Scale Factor Voltage Input Range
(V) (V) (dB/V) (mV/dB) (V)
3.0 1.5 50.00 20.00 0.400–2.000
3.5 1.75 42.86 23.33 0.467–2.333
4.0 2.0 37.50 26.67 0.533–2.667
4.5 2.25 33.33 30.00 0.600–3.000
5.0 2.5 30.00 33.33 0.667–3.333
5.5 2.75 27.27 36.67 0.733–3.667
Maximum gain occurs for gain control voltage = 0 V.
The reference signal may be provided from an external source
in the form of a high level clock, typically a low level signal
(±400 mV) since there is an input amplifier between FDIN and
the loop’s phase detector. For example, the IF output itself can
be used by connecting DMIP to FDIN, which will then provide
automatic carrier recover for synchronous AM detection and
take advantage of any post-IF filtering. Pin FDIN must be
biased at V
P
/2; Figure 22 shows suggested methods.
The VFQO operates from 400 kHz to 12 MHz and is controlled
by the voltage between VPOS and FLTR. In normal operation,
a series RC network forming the PLL loop filter is connected
from FLTR to ground. The use of an integral sample-hold
system ensures that the frequency-control voltage on Pin FLTR
remains held during power-down, so reacquisition of the carrier
typically occurs in 16.5 µs.
In practice, the probability of a phase mismatch at power-up is
high, so the worst-case linear settling period to full lock needs
to be considered in making filter choices. This is typically 16.5 µs
at an IF of 10.7 MHz for a ±100 mV signal at DMIP and FDIN.
are generated at IOUT and QOUT, respectively. The quadra-
ture accuracy of this VFQO is typically –1.2°C at 10.7 MHz. The
PLL uses a sequential-phase detector that comprises low power
emitter-coupled logic and a charge pump (Figure 20).
SEQUENTIAL
PHASE
DETECTOR
VARIABLE-
FREQUENCY
QUADRATURE
OSCILLATOR 90ⴗ
Q-CLOCK
(ECL OUTPUTS)
I-CLOCK
REFERENCE CARRIER
(FDIN AFTER LIMITING)
U
D
I
U
~
40␮A
C
R
V
F
F
R
I
D
~
40␮A
Figure 20. Simplified Schematic of the PLL and
Quadrature VCO
REV. C
–18–
AD607
Bias System
The AD607 operates from a single supply, V
P
, usually of 3 V, at
a typical supply current of 8.5 mA at midgain and T = 27°C,
corresponding to a power consumption of 25 mW. Any voltage
from 2.92 V to 5.5 V may be used.
The bias system includes a fast-acting active-high CMOS-
compatible power-up switch, allowing the part to idle at 550 µA
when disabled. Biasing is proportional-to-absolute temperature
(PTAT) to ensure stable gain with temperature.
An independent regulator generates a voltage at the midpoint
of the supply (V
P
/2) that appears at the VMID pin at a low
impedance. This voltage does not shut down, ensuring that the
major signal interfaces (e.g., mixer-to-IF and IF-to-demodulators)
remain biased at all times, thus minimizing transient disturbances
at power-up and allowing the use of substantial decoupling
capacitors on this node. The quiescent consumption of this
regulator is included in the idling current.
AD607
FDIN
50k⍀
50k⍀
VPOS
EXTERNAL
FREQUENCY
REFERENCE
a. Biasing FDIN from Supply when Using
External Frequency Reference
AD607
FDIN
50k⍀
C
BYPASS
EXTERNAL
FREQUENCY
REFERENCE
VMID
b. Biasing FDIN from VMID when Using
External Frequency Reference
Figure 21. Suggested Methods for Biasing Pin FDIN at V
P
/2
USING THE AD607
In this section, we will focus on a few areas of special impor-
tance and include a few general application tips. As is true of
any wideband high gain component, great care is needed in PC
board layout. The location of the particular grounding points
must be considered with due regard to the possibility of unwanted
signal coupling, particularly from IFOP to RFHI or IFHI or both.
The high sensitivity of the AD607 leads to the possibility that
unwanted local EM signals may have an effect on the perfor-
mance. During system development, carefully-shielded test
assemblies should be used. The best solution is to use a fully-
enclosed box enclosing all components, with the minimum
number of needed signal connectors (RF, LO, I, and Q outputs)
in miniature coax form.
The I and Q output leads can include small series resistors
(about 100 Ω) inside the shielded box without significant loss
of performance, provided the external loading during testing
is light (that is, a resistive load of more than 20 kΩ and capaci-
tances of a few picofarads). These help to keep unwanted RF
emanations out of the interior.
The power supply should be connected via a through-hole
capacitor with a ferrite bead on both inside and outside leads.
Close to the IC pins, two capacitors of different value should be
used to decouple the main supply (V
P
) and the midpoint supply
pin, VMID. Guidance on these matters is also generally included
in applications schematics.
Gain Distribution
As in all receivers, the most critical decisions in effectively using
the AD607 relate to the partitioning of gain between the various
subsections (Mixer, IF Amplifier, Demodulators) and the place-
ment of filters so as to achieve the highest overall signal-to-noise
ratio and lowest intermodulation distortion.
Figure 22 shows the main RF/IF signal path at maximum and
minimum signal levels.
IOUT
QOUT
I
Q
RFHI
LOIP
MXOP IFHI DMIPIFOP
IF BPF IF BPF
(VMID)
330⍀330⍀
(TYPICAL
IMPEDANCE)
(LOCATION OF OPTIONAL
SECOND IF FILTER)
CONSTANT
–16dBm
(ⴞ50mV)
ⴞ54mV
MAX INPUT
ⴞ1.3V
MAX OUTPUT
ⴞ54mV
MAX INPUT
ⴞ560mV
MAX OUTPUT
ⴞ154mV
MAX INPUT
ⴞ1.23V
MAX OUTPUT
Figure 22. Signal Levels for Minimum and Maximum Gain
REV. C –19–
AD607
As noted earlier, the gain in dB is reduced linearly with the voltage
V
G
on the GAIN pin. Figure 23 shows how the mixer and IF strip
gains vary with V
G
when GREF is connected to VMID (1.5 V) and
a supply voltage of 3 V is used. Figure 24 shows how these vary
when GREF is connected to a 1.23 V reference.
VG
(7.5dB)
(1.5dB)
01V2V
0.4V 1.8V 2.2V
(67.5dB)
(21.5dB)
IF GAIN
MIXER GAIN
90dB
80dB
70dB
60dB
50dB
40dB
30dB
20dB
10dB
0dB
NORMAL OPERATING RANGE
Figure 23. Gain Distribution for GREF = 1.5 V
(7.5dB)
(1.5dB)
01V2V
(67.5dB)
(21.5dB)
IF GAIN
MIXER GAIN
90dB
80dB
70dB
60dB
50dB
40dB
30dB
20dB
10dB
0dB
0.328V 1.64V
VG
NORMAL OPERATING RANGE
Figure 24. Gain Distribution for GREF = 1.23 V
Using the AD607 with a Fast PRUP Control Signal
If the AD607 is used in a system in which the PRUP signal
(Pin 3) is applied with a rise time less than 35 µs, anomalous
behavior occasionally occurs. The problem is intermittent, so it
will not occur every time the part is powered up under these
conditions. It does not occur for any other normal operating condi-
tions when the PRUP signal has a rise time slower than 35 µs.
Symptoms of operation with too fast a PRUP signal include low
gain, oscillations at the I or Q outputs of the device, or no valid
data occurring at the output of the AD607. The problem causes
no permanent damage to the AD607, so it will often operate
normally when reset.
Fortunately, there is a very simple solution to the fast PRUP
problem. If the PRUP signal (Pin 3) is slowed down so that
the rise time of the signal edge is greater than 35 µs, the
anomalous behavior will not occur. This can be realized by a
simple RC circuit connected to the PRUP pin, where R = 4.7 kΩ
and C = 1.5 nF. This circuit is shown in Figure 25.
AD607
PRUP
4.7k⍀
1.5nF
FROM PRUP
CONTROL SIGNAL
Figure 25. Proper Configuration of AD607 PRUP Signal
All designs incorporating the AD607 should include this circuitry.
Note that connecting the PRUP pin to the supply voltage will
not eliminate the problem, since the supply voltage may have a
rise time faster than 35 µs. With this configuration, the 4.7 kΩ
series R and 1.5 nF shunt C should be placed between the
supply and the PRUP pin as shown in Figure 25.
AD607 EVALUATION BOARD
The AD607 evaluation board (Figures 26 and 27) consists of an
AD607, ground plane, I/O connectors, and a 10.7 MHz band-
pass filter. The RF and LO ports are terminated in 50 Ω to
provide a broadband match to external signal generators to
allow a choice of RF and LO input frequencies. The IF filter is
at 10.7 MHz and has 330 Ω input and output terminations; the
board is laid out to allow the user to substitute other filters for
other IFs.
The board provides SMA connectors for the RF and LO port
inputs, the demodulated I and Q outputs, the manual gain con-
trol (MGC) input, the PLL input, and the power-up input. In
addition, the IF output is also available at an SMA connector;
this may be connected to the PLL input for carrier recovery to
realize synchronous AM and FM detection via the I and Q
demodulators, respectively. Table III lists the AD607 Evalua-
tion Board’s I/O Connectors and their functions.
REV. C
–20–
AD607
VPS1
AD607
C12
0.1␮F
C5
1nF
C6
0.1␮F
C8
0.1␮F
GAIN
IF
Q
I
C1
0.1␮F
C3 10nF
R1
1k⍀
C2 0.1␮FC4
47pF
R2
316⍀
C15
0.1␮FJUMPER
JUMPER
C16 1nF
R10
4.99k⍀
R11
OPEN
C11
10nF
R8
51.1⍀
C13 0
C14 0
R7
51.1⍀
R6
51.1⍀
C10
1nF
C9
1nF
R5
332⍀
R3
332⍀
R4
OPEN
C7
1nF
VPOS
GND
FDIN
PRUP
LO
RF
R13
50k⍀
R15
50k⍀
VPOS
FDIN
R12
OPEN
VMID
C17
10nF
C18
SHORT
R14
51.1⍀
FDIN
MOD FOR LARGE MAGNITUDE
AC-COUPLED INPUT
AD607 EVALUATION BOARD
(AS RECEIVED)
R18
OPEN
R17
OPEN
VPOS
FDIN
R16
OPEN
VMID
C20
SHORT
C19
ANYTHING
R19
RSOURCE
FDIN
MOD FOR DC-COUPLED INPUT
FDIN
COM1
PRUP
LOIP
RFLO
RFHI
GREF
MXOP
VMID
IFHI
FLTR
IOUT
QOUT
VPS2
DMIP
IFOP
COM2
GAIN
IFLO
C17
1.5nF
R12
4.7k⍀
Figure 26. Evaluation Board
Figure 27a. Evaluation Board Layout, Topside
REV. C –21–
AD607
Table III. AD607 Evaluation Board Input and Output Connections
Reference Connector Approximate
Designation Type Description Coupling Signal Level Comments
J1 SMA Frequency DC ±400 mV This pin needs to be biased at VMID
Detector Input and ac-coupled when driven by an
external signal generator.
J2 SMA Power-Up DC CMOS Logic Tied to Positive Supply by Jumper J10
Level Input
J3 SMA LO Input AC –16 dBm Input is terminated in 50 Ω.
(±50 mV)
J4 SMA RF Input AC –15 dBm max Input is terminated in 50 Ω.
(±54 mV)
J5 SMA MGC Input DC 0.4 V to 2.0 V Jumper is set for manual gain control
(3 V Supply) input; see Table I for control voltage
(GREF = VMID) values.
J6 SMA IF Output AC NA This signal level depends on the
AD607’s gain setting.
J7 SMA Q Output AC NA This signal level depends on the
AD607’s gain setting.
J8 SMA I Output AC NA This signal level depends on the
AD607’s gain setting.
J9 Jumper Ties GREF NA NA Sets gain-control scale factor (SF);
to VMID SF = 75/VMID in dB/V, where
VMID = VPOS/2.
J10 Jumper Ties Power-Up NA NA Remove to test power-up/-down.
to Positive
Supply
T1 Terminal Pin Power Supply DC DC 2.92 V to 5.5 V
Positive Input Draws 8.5 mA at midgain connection.
(VPS1, VPS2)
T2 Terminal Pin Power Supply DC 0 V
Return (GND)
Figure 27b. Evaluation Board Layout, Bottom Side
REV. C
–22–
AD607
HP 6632A
PROGRAMMABLE
POWER SUPPLY
2.92V–6V
HP 3326
SYNTHESIZED
SIGNAL GENERATOR
10.710MHz
FLUKE 6082A
SYNTHESIZED
SIGNAL GENERATOR
240MHz
HP 8656A
SYNTHESIZED
SIGNAL GENERATOR
240.02MHz
AD607
EVALUATION
BOARD
TEKTRONIX
11402A
OSCILLOSCOPE
WITH 11A32
PLUGIN
HP 8656A
SYNTHESIZED
SIGNAL GENERATOR
229.3MHz
DATA PRECISION
DVC8200
PROGRAMMABLE
VOLTAGE SOURCE
HP 9920
IEEE CONTROLLER
HP9121
DISK DRIVE
MCL
ZFSC–2–1
COMBINER
IEEE–488 BUS
VPOS FDIN
I OUTPUT
Q OUTPUT
MGC
LO
RF
Figure 28. Evaluation Board Test Setup
In operation (Figure 28), the AD607 evaluation board draws
about 8.5 mA at midgain (59 dB). Use high impedance probes
to monitor signals from the demodulated I and Q outputs and
the IF output. The MGC voltage should be set such that the
signal level at DMIP does not exceed ±150 mV; signal levels
above this will overload the I and Q demodulators. The insertion
loss between IFOP and DMIP is typically 3 dB if a simple low-pass
filter (R8 and C2) is used, and higher if a reverse-terminated
band-pass filter is used.
REV. C –23–
AD607
OUTLINE DIMENSIONS
20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
COPLANARITY
0.10
0.05 MIN
1.85
1.75
1.65
0.65
BSC
0.25
0.09
0.95
0.75
0.55
8ⴗ
4ⴗ
0ⴗ
2.00 MAX
0.38
0.22 SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-150AE
C00543–0–11/02(C)
PRINTED IN U.S.A.
Revision History
Location Page
11/02—Data Sheet changed from REV. B to REV. C.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Edits to PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Edits to IF Amplifier section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Edits to Gain Scaling and RSSI section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Edits to I/Q Demodulators section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Edits to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Edits to Bias System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Edits to Figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
OUTLINE DIMENSIONS Updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
REV. C
AD607
–24–